Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
3569 |
0 |
0 |
T40 |
10173 |
2 |
0 |
0 |
T109 |
4647 |
50 |
0 |
0 |
T110 |
5546 |
15 |
0 |
0 |
T111 |
4213 |
46 |
0 |
0 |
T112 |
8429 |
128 |
0 |
0 |
T116 |
52912 |
2 |
0 |
0 |
T117 |
88245 |
6 |
0 |
0 |
T120 |
12356 |
8 |
0 |
0 |
T121 |
6612 |
276 |
0 |
0 |
T133 |
5267 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1881 |
0 |
0 |
T117 |
88245 |
82 |
0 |
0 |
T133 |
5267 |
7 |
0 |
0 |
T134 |
30688 |
20 |
0 |
0 |
T151 |
18730 |
95 |
0 |
0 |
T152 |
10602 |
29 |
0 |
0 |
T154 |
12559 |
37 |
0 |
0 |
T160 |
156761 |
325 |
0 |
0 |
T161 |
7426 |
40 |
0 |
0 |
T162 |
7241 |
12 |
0 |
0 |
T163 |
101991 |
95 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1771 |
0 |
0 |
T117 |
88245 |
42 |
0 |
0 |
T133 |
5267 |
4 |
0 |
0 |
T134 |
30688 |
9 |
0 |
0 |
T151 |
18730 |
76 |
0 |
0 |
T152 |
10602 |
23 |
0 |
0 |
T154 |
12559 |
19 |
0 |
0 |
T160 |
156761 |
278 |
0 |
0 |
T161 |
7426 |
20 |
0 |
0 |
T163 |
101991 |
123 |
0 |
0 |
T164 |
69209 |
95 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2162 |
0 |
0 |
T117 |
88245 |
122 |
0 |
0 |
T133 |
5267 |
4 |
0 |
0 |
T134 |
30688 |
48 |
0 |
0 |
T151 |
18730 |
77 |
0 |
0 |
T152 |
10602 |
37 |
0 |
0 |
T154 |
12559 |
40 |
0 |
0 |
T160 |
156761 |
240 |
0 |
0 |
T161 |
7426 |
8 |
0 |
0 |
T162 |
7241 |
15 |
0 |
0 |
T163 |
101991 |
176 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
8021 |
0 |
0 |
T117 |
88245 |
1125 |
0 |
0 |
T133 |
5267 |
9 |
0 |
0 |
T134 |
30688 |
195 |
0 |
0 |
T151 |
18730 |
99 |
0 |
0 |
T152 |
10602 |
18 |
0 |
0 |
T154 |
12559 |
21 |
0 |
0 |
T160 |
156761 |
280 |
0 |
0 |
T161 |
7426 |
18 |
0 |
0 |
T162 |
7241 |
15 |
0 |
0 |
T163 |
101991 |
1525 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
7470 |
0 |
0 |
T117 |
88245 |
647 |
0 |
0 |
T133 |
5267 |
113 |
0 |
0 |
T134 |
30688 |
415 |
0 |
0 |
T151 |
18730 |
58 |
0 |
0 |
T152 |
10602 |
27 |
0 |
0 |
T154 |
12559 |
26 |
0 |
0 |
T160 |
156761 |
277 |
0 |
0 |
T161 |
7426 |
10 |
0 |
0 |
T162 |
7241 |
11 |
0 |
0 |
T163 |
101991 |
1212 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
8113 |
0 |
0 |
T117 |
88245 |
985 |
0 |
0 |
T133 |
5267 |
90 |
0 |
0 |
T134 |
30688 |
241 |
0 |
0 |
T151 |
18730 |
70 |
0 |
0 |
T152 |
10602 |
30 |
0 |
0 |
T154 |
12559 |
54 |
0 |
0 |
T160 |
156761 |
295 |
0 |
0 |
T161 |
7426 |
47 |
0 |
0 |
T162 |
7241 |
3 |
0 |
0 |
T163 |
101991 |
1601 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
7483 |
0 |
0 |
T117 |
88245 |
804 |
0 |
0 |
T133 |
5267 |
111 |
0 |
0 |
T134 |
30688 |
345 |
0 |
0 |
T151 |
18730 |
86 |
0 |
0 |
T152 |
10602 |
18 |
0 |
0 |
T154 |
12559 |
30 |
0 |
0 |
T160 |
156761 |
256 |
0 |
0 |
T161 |
7426 |
28 |
0 |
0 |
T162 |
7241 |
25 |
0 |
0 |
T163 |
101991 |
1467 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
9125 |
0 |
0 |
T117 |
88245 |
837 |
0 |
0 |
T133 |
5267 |
14 |
0 |
0 |
T134 |
30688 |
365 |
0 |
0 |
T151 |
18730 |
74 |
0 |
0 |
T152 |
10602 |
32 |
0 |
0 |
T154 |
12559 |
31 |
0 |
0 |
T160 |
156761 |
197 |
0 |
0 |
T161 |
7426 |
34 |
0 |
0 |
T162 |
7241 |
11 |
0 |
0 |
T163 |
101991 |
2316 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
8049 |
0 |
0 |
T117 |
88245 |
903 |
0 |
0 |
T133 |
5267 |
119 |
0 |
0 |
T134 |
30688 |
428 |
0 |
0 |
T151 |
18730 |
91 |
0 |
0 |
T152 |
10602 |
31 |
0 |
0 |
T154 |
12559 |
22 |
0 |
0 |
T160 |
156761 |
293 |
0 |
0 |
T161 |
7426 |
48 |
0 |
0 |
T163 |
101991 |
1638 |
0 |
0 |
T164 |
69209 |
1012 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
8127 |
0 |
0 |
T117 |
88245 |
854 |
0 |
0 |
T133 |
5267 |
88 |
0 |
0 |
T134 |
30688 |
552 |
0 |
0 |
T151 |
18730 |
45 |
0 |
0 |
T152 |
10602 |
8 |
0 |
0 |
T154 |
12559 |
32 |
0 |
0 |
T160 |
156761 |
257 |
0 |
0 |
T161 |
7426 |
19 |
0 |
0 |
T162 |
7241 |
17 |
0 |
0 |
T163 |
101991 |
1698 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
8221 |
0 |
0 |
T117 |
88245 |
914 |
0 |
0 |
T133 |
5267 |
10 |
0 |
0 |
T134 |
30688 |
367 |
0 |
0 |
T151 |
18730 |
15 |
0 |
0 |
T152 |
10602 |
16 |
0 |
0 |
T154 |
12559 |
21 |
0 |
0 |
T160 |
156761 |
240 |
0 |
0 |
T161 |
7426 |
17 |
0 |
0 |
T162 |
7241 |
31 |
0 |
0 |
T163 |
101991 |
1538 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4529 |
0 |
0 |
T117 |
88245 |
644 |
0 |
0 |
T133 |
5267 |
14 |
0 |
0 |
T134 |
30688 |
101 |
0 |
0 |
T151 |
18730 |
25 |
0 |
0 |
T152 |
10602 |
28 |
0 |
0 |
T154 |
12559 |
16 |
0 |
0 |
T160 |
156761 |
291 |
0 |
0 |
T162 |
7241 |
14 |
0 |
0 |
T163 |
101991 |
777 |
0 |
0 |
T164 |
69209 |
529 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4491 |
0 |
0 |
T117 |
88245 |
462 |
0 |
0 |
T133 |
5267 |
2 |
0 |
0 |
T134 |
30688 |
100 |
0 |
0 |
T151 |
18730 |
49 |
0 |
0 |
T152 |
10602 |
30 |
0 |
0 |
T154 |
12559 |
23 |
0 |
0 |
T160 |
156761 |
262 |
0 |
0 |
T161 |
7426 |
22 |
0 |
0 |
T162 |
7241 |
19 |
0 |
0 |
T163 |
101991 |
916 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
3790 |
0 |
0 |
T117 |
88245 |
317 |
0 |
0 |
T133 |
5267 |
2 |
0 |
0 |
T134 |
30688 |
102 |
0 |
0 |
T151 |
18730 |
23 |
0 |
0 |
T152 |
10602 |
10 |
0 |
0 |
T154 |
12559 |
18 |
0 |
0 |
T160 |
156761 |
233 |
0 |
0 |
T161 |
7426 |
33 |
0 |
0 |
T162 |
7241 |
22 |
0 |
0 |
T163 |
101991 |
666 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4261 |
0 |
0 |
T117 |
88245 |
387 |
0 |
0 |
T133 |
5267 |
7 |
0 |
0 |
T134 |
30688 |
102 |
0 |
0 |
T151 |
18730 |
51 |
0 |
0 |
T152 |
10602 |
8 |
0 |
0 |
T154 |
12559 |
23 |
0 |
0 |
T160 |
156761 |
231 |
0 |
0 |
T161 |
7426 |
3 |
0 |
0 |
T162 |
7241 |
2 |
0 |
0 |
T163 |
101991 |
830 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4890 |
0 |
0 |
T117 |
88245 |
446 |
0 |
0 |
T133 |
5267 |
9 |
0 |
0 |
T134 |
30688 |
141 |
0 |
0 |
T151 |
18730 |
103 |
0 |
0 |
T152 |
10602 |
5 |
0 |
0 |
T154 |
12559 |
12 |
0 |
0 |
T160 |
156761 |
307 |
0 |
0 |
T161 |
7426 |
15 |
0 |
0 |
T162 |
7241 |
10 |
0 |
0 |
T163 |
101991 |
1043 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4107 |
0 |
0 |
T117 |
88245 |
472 |
0 |
0 |
T133 |
5267 |
71 |
0 |
0 |
T134 |
30688 |
128 |
0 |
0 |
T151 |
18730 |
51 |
0 |
0 |
T154 |
12559 |
22 |
0 |
0 |
T160 |
156761 |
277 |
0 |
0 |
T161 |
7426 |
29 |
0 |
0 |
T162 |
7241 |
11 |
0 |
0 |
T163 |
101991 |
688 |
0 |
0 |
T164 |
69209 |
469 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4323 |
0 |
0 |
T117 |
88245 |
548 |
0 |
0 |
T133 |
5267 |
42 |
0 |
0 |
T134 |
30688 |
103 |
0 |
0 |
T151 |
18730 |
83 |
0 |
0 |
T152 |
10602 |
7 |
0 |
0 |
T154 |
12559 |
28 |
0 |
0 |
T160 |
156761 |
241 |
0 |
0 |
T161 |
7426 |
4 |
0 |
0 |
T162 |
7241 |
10 |
0 |
0 |
T163 |
101991 |
996 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4021 |
0 |
0 |
T117 |
88245 |
324 |
0 |
0 |
T133 |
5267 |
8 |
0 |
0 |
T134 |
30688 |
97 |
0 |
0 |
T151 |
18730 |
31 |
0 |
0 |
T152 |
10602 |
26 |
0 |
0 |
T154 |
12559 |
8 |
0 |
0 |
T160 |
156761 |
251 |
0 |
0 |
T161 |
7426 |
41 |
0 |
0 |
T162 |
7241 |
12 |
0 |
0 |
T163 |
101991 |
711 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4275 |
0 |
0 |
T117 |
88245 |
615 |
0 |
0 |
T133 |
5267 |
28 |
0 |
0 |
T134 |
30688 |
123 |
0 |
0 |
T151 |
18730 |
61 |
0 |
0 |
T152 |
10602 |
30 |
0 |
0 |
T154 |
12559 |
24 |
0 |
0 |
T160 |
156761 |
261 |
0 |
0 |
T161 |
7426 |
18 |
0 |
0 |
T162 |
7241 |
27 |
0 |
0 |
T163 |
101991 |
855 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4041 |
0 |
0 |
T117 |
88245 |
366 |
0 |
0 |
T133 |
5267 |
56 |
0 |
0 |
T134 |
30688 |
188 |
0 |
0 |
T151 |
18730 |
14 |
0 |
0 |
T152 |
10602 |
26 |
0 |
0 |
T154 |
12559 |
13 |
0 |
0 |
T160 |
156761 |
324 |
0 |
0 |
T161 |
7426 |
33 |
0 |
0 |
T162 |
7241 |
25 |
0 |
0 |
T163 |
101991 |
615 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4660 |
0 |
0 |
T117 |
88245 |
412 |
0 |
0 |
T133 |
5267 |
64 |
0 |
0 |
T134 |
30688 |
168 |
0 |
0 |
T151 |
18730 |
80 |
0 |
0 |
T152 |
10602 |
28 |
0 |
0 |
T154 |
12559 |
3 |
0 |
0 |
T160 |
156761 |
209 |
0 |
0 |
T161 |
7426 |
23 |
0 |
0 |
T162 |
7241 |
7 |
0 |
0 |
T163 |
101991 |
942 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4271 |
0 |
0 |
T117 |
88245 |
470 |
0 |
0 |
T133 |
5267 |
56 |
0 |
0 |
T134 |
30688 |
107 |
0 |
0 |
T151 |
18730 |
57 |
0 |
0 |
T152 |
10602 |
21 |
0 |
0 |
T154 |
12559 |
9 |
0 |
0 |
T160 |
156761 |
239 |
0 |
0 |
T161 |
7426 |
2 |
0 |
0 |
T163 |
101991 |
636 |
0 |
0 |
T164 |
69209 |
657 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4620 |
0 |
0 |
T117 |
88245 |
477 |
0 |
0 |
T133 |
5267 |
10 |
0 |
0 |
T134 |
30688 |
205 |
0 |
0 |
T151 |
18730 |
49 |
0 |
0 |
T154 |
12559 |
4 |
0 |
0 |
T160 |
156761 |
327 |
0 |
0 |
T161 |
7426 |
17 |
0 |
0 |
T162 |
7241 |
1 |
0 |
0 |
T163 |
101991 |
777 |
0 |
0 |
T164 |
69209 |
513 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4183 |
0 |
0 |
T117 |
88245 |
500 |
0 |
0 |
T133 |
5267 |
45 |
0 |
0 |
T134 |
30688 |
139 |
0 |
0 |
T151 |
18730 |
10 |
0 |
0 |
T152 |
10602 |
16 |
0 |
0 |
T154 |
12559 |
16 |
0 |
0 |
T160 |
156761 |
289 |
0 |
0 |
T162 |
7241 |
18 |
0 |
0 |
T163 |
101991 |
591 |
0 |
0 |
T164 |
69209 |
537 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4591 |
0 |
0 |
T117 |
88245 |
592 |
0 |
0 |
T133 |
5267 |
52 |
0 |
0 |
T134 |
30688 |
170 |
0 |
0 |
T151 |
18730 |
51 |
0 |
0 |
T152 |
10602 |
1 |
0 |
0 |
T154 |
12559 |
34 |
0 |
0 |
T160 |
156761 |
244 |
0 |
0 |
T161 |
7426 |
7 |
0 |
0 |
T162 |
7241 |
6 |
0 |
0 |
T163 |
101991 |
650 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4067 |
0 |
0 |
T117 |
88245 |
330 |
0 |
0 |
T133 |
5267 |
12 |
0 |
0 |
T134 |
30688 |
140 |
0 |
0 |
T151 |
18730 |
33 |
0 |
0 |
T152 |
10602 |
19 |
0 |
0 |
T154 |
12559 |
35 |
0 |
0 |
T160 |
156761 |
278 |
0 |
0 |
T161 |
7426 |
29 |
0 |
0 |
T162 |
7241 |
2 |
0 |
0 |
T163 |
101991 |
782 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4410 |
0 |
0 |
T117 |
88245 |
415 |
0 |
0 |
T133 |
5267 |
1 |
0 |
0 |
T134 |
30688 |
184 |
0 |
0 |
T151 |
18730 |
107 |
0 |
0 |
T152 |
10602 |
25 |
0 |
0 |
T154 |
12559 |
26 |
0 |
0 |
T160 |
156761 |
293 |
0 |
0 |
T161 |
7426 |
23 |
0 |
0 |
T162 |
7241 |
13 |
0 |
0 |
T163 |
101991 |
861 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4596 |
0 |
0 |
T117 |
88245 |
562 |
0 |
0 |
T133 |
5267 |
57 |
0 |
0 |
T134 |
30688 |
151 |
0 |
0 |
T151 |
18730 |
87 |
0 |
0 |
T152 |
10602 |
26 |
0 |
0 |
T160 |
156761 |
294 |
0 |
0 |
T161 |
7426 |
35 |
0 |
0 |
T162 |
7241 |
27 |
0 |
0 |
T163 |
101991 |
996 |
0 |
0 |
T164 |
69209 |
406 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4104 |
0 |
0 |
T117 |
88245 |
429 |
0 |
0 |
T133 |
5267 |
8 |
0 |
0 |
T134 |
30688 |
163 |
0 |
0 |
T151 |
18730 |
105 |
0 |
0 |
T152 |
10602 |
20 |
0 |
0 |
T154 |
12559 |
51 |
0 |
0 |
T160 |
156761 |
280 |
0 |
0 |
T161 |
7426 |
39 |
0 |
0 |
T162 |
7241 |
14 |
0 |
0 |
T163 |
101991 |
668 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4284 |
0 |
0 |
T117 |
88245 |
238 |
0 |
0 |
T133 |
5267 |
10 |
0 |
0 |
T134 |
30688 |
155 |
0 |
0 |
T151 |
18730 |
62 |
0 |
0 |
T152 |
10602 |
26 |
0 |
0 |
T154 |
12559 |
14 |
0 |
0 |
T160 |
156761 |
209 |
0 |
0 |
T162 |
7241 |
12 |
0 |
0 |
T163 |
101991 |
995 |
0 |
0 |
T164 |
69209 |
635 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4356 |
0 |
0 |
T117 |
88245 |
486 |
0 |
0 |
T133 |
5267 |
10 |
0 |
0 |
T134 |
30688 |
137 |
0 |
0 |
T151 |
18730 |
53 |
0 |
0 |
T152 |
10602 |
20 |
0 |
0 |
T154 |
12559 |
21 |
0 |
0 |
T160 |
156761 |
238 |
0 |
0 |
T161 |
7426 |
14 |
0 |
0 |
T163 |
101991 |
743 |
0 |
0 |
T164 |
69209 |
583 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4469 |
0 |
0 |
T117 |
88245 |
508 |
0 |
0 |
T133 |
5267 |
51 |
0 |
0 |
T134 |
30688 |
132 |
0 |
0 |
T151 |
18730 |
60 |
0 |
0 |
T152 |
10602 |
23 |
0 |
0 |
T154 |
12559 |
13 |
0 |
0 |
T160 |
156761 |
350 |
0 |
0 |
T161 |
7426 |
19 |
0 |
0 |
T162 |
7241 |
10 |
0 |
0 |
T163 |
101991 |
776 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4564 |
0 |
0 |
T117 |
88245 |
452 |
0 |
0 |
T133 |
5267 |
45 |
0 |
0 |
T134 |
30688 |
133 |
0 |
0 |
T151 |
18730 |
56 |
0 |
0 |
T152 |
10602 |
13 |
0 |
0 |
T154 |
12559 |
11 |
0 |
0 |
T160 |
156761 |
230 |
0 |
0 |
T161 |
7426 |
13 |
0 |
0 |
T162 |
7241 |
20 |
0 |
0 |
T163 |
101991 |
875 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
4523 |
0 |
0 |
T117 |
88245 |
466 |
0 |
0 |
T133 |
5267 |
51 |
0 |
0 |
T134 |
30688 |
186 |
0 |
0 |
T151 |
18730 |
37 |
0 |
0 |
T152 |
10602 |
18 |
0 |
0 |
T154 |
12559 |
30 |
0 |
0 |
T160 |
156761 |
196 |
0 |
0 |
T161 |
7426 |
27 |
0 |
0 |
T162 |
7241 |
16 |
0 |
0 |
T163 |
101991 |
804 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1873 |
0 |
0 |
T117 |
88245 |
109 |
0 |
0 |
T133 |
5267 |
5 |
0 |
0 |
T134 |
30688 |
33 |
0 |
0 |
T151 |
18730 |
63 |
0 |
0 |
T152 |
10602 |
9 |
0 |
0 |
T154 |
12559 |
36 |
0 |
0 |
T160 |
156761 |
257 |
0 |
0 |
T161 |
7426 |
26 |
0 |
0 |
T162 |
7241 |
17 |
0 |
0 |
T163 |
101991 |
134 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1963 |
0 |
0 |
T117 |
88245 |
74 |
0 |
0 |
T133 |
5267 |
6 |
0 |
0 |
T134 |
30688 |
44 |
0 |
0 |
T151 |
18730 |
45 |
0 |
0 |
T152 |
10602 |
10 |
0 |
0 |
T154 |
12559 |
16 |
0 |
0 |
T160 |
156761 |
252 |
0 |
0 |
T161 |
7426 |
22 |
0 |
0 |
T162 |
7241 |
1 |
0 |
0 |
T163 |
101991 |
216 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1851 |
0 |
0 |
T117 |
88245 |
86 |
0 |
0 |
T133 |
5267 |
14 |
0 |
0 |
T134 |
30688 |
59 |
0 |
0 |
T151 |
18730 |
39 |
0 |
0 |
T152 |
10602 |
7 |
0 |
0 |
T154 |
12559 |
45 |
0 |
0 |
T160 |
156761 |
254 |
0 |
0 |
T162 |
7241 |
21 |
0 |
0 |
T163 |
101991 |
146 |
0 |
0 |
T164 |
69209 |
144 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2098 |
0 |
0 |
T117 |
88245 |
89 |
0 |
0 |
T133 |
5267 |
10 |
0 |
0 |
T134 |
30688 |
19 |
0 |
0 |
T151 |
18730 |
69 |
0 |
0 |
T152 |
10602 |
17 |
0 |
0 |
T154 |
12559 |
21 |
0 |
0 |
T160 |
156761 |
342 |
0 |
0 |
T162 |
7241 |
30 |
0 |
0 |
T163 |
101991 |
151 |
0 |
0 |
T164 |
69209 |
138 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2429 |
0 |
0 |
T117 |
88245 |
132 |
0 |
0 |
T133 |
5267 |
9 |
0 |
0 |
T134 |
30688 |
44 |
0 |
0 |
T151 |
18730 |
64 |
0 |
0 |
T152 |
10602 |
37 |
0 |
0 |
T154 |
12559 |
26 |
0 |
0 |
T160 |
156761 |
286 |
0 |
0 |
T161 |
7426 |
13 |
0 |
0 |
T162 |
7241 |
4 |
0 |
0 |
T163 |
101991 |
328 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
3838 |
0 |
0 |
T27 |
54693 |
0 |
0 |
0 |
T42 |
7379 |
52 |
0 |
0 |
T43 |
0 |
22 |
0 |
0 |
T44 |
0 |
49 |
0 |
0 |
T117 |
0 |
234 |
0 |
0 |
T133 |
0 |
12 |
0 |
0 |
T134 |
0 |
83 |
0 |
0 |
T151 |
0 |
51 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T160 |
0 |
318 |
0 |
0 |
T165 |
0 |
24 |
0 |
0 |
T166 |
181836 |
0 |
0 |
0 |
T167 |
2823 |
0 |
0 |
0 |
T168 |
23086 |
0 |
0 |
0 |
T169 |
61882 |
0 |
0 |
0 |
T170 |
12907 |
0 |
0 |
0 |
T171 |
64953 |
0 |
0 |
0 |
T172 |
54270 |
0 |
0 |
0 |
T173 |
1905 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2009 |
0 |
0 |
T117 |
88245 |
85 |
0 |
0 |
T133 |
5267 |
8 |
0 |
0 |
T134 |
30688 |
32 |
0 |
0 |
T151 |
18730 |
89 |
0 |
0 |
T152 |
10602 |
18 |
0 |
0 |
T154 |
12559 |
24 |
0 |
0 |
T160 |
156761 |
282 |
0 |
0 |
T161 |
7426 |
34 |
0 |
0 |
T163 |
101991 |
149 |
0 |
0 |
T164 |
69209 |
118 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1922 |
0 |
0 |
T117 |
88245 |
94 |
0 |
0 |
T133 |
5267 |
14 |
0 |
0 |
T134 |
30688 |
34 |
0 |
0 |
T151 |
18730 |
28 |
0 |
0 |
T152 |
10602 |
11 |
0 |
0 |
T154 |
12559 |
27 |
0 |
0 |
T160 |
156761 |
260 |
0 |
0 |
T161 |
7426 |
31 |
0 |
0 |
T163 |
101991 |
143 |
0 |
0 |
T164 |
69209 |
103 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1912 |
0 |
0 |
T117 |
88245 |
48 |
0 |
0 |
T133 |
5267 |
11 |
0 |
0 |
T134 |
30688 |
20 |
0 |
0 |
T151 |
18730 |
113 |
0 |
0 |
T152 |
10602 |
38 |
0 |
0 |
T154 |
12559 |
23 |
0 |
0 |
T160 |
156761 |
236 |
0 |
0 |
T161 |
7426 |
11 |
0 |
0 |
T162 |
7241 |
36 |
0 |
0 |
T163 |
101991 |
88 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1724 |
0 |
0 |
T117 |
88245 |
71 |
0 |
0 |
T133 |
5267 |
5 |
0 |
0 |
T134 |
30688 |
31 |
0 |
0 |
T151 |
18730 |
53 |
0 |
0 |
T152 |
10602 |
9 |
0 |
0 |
T154 |
12559 |
18 |
0 |
0 |
T160 |
156761 |
292 |
0 |
0 |
T161 |
7426 |
17 |
0 |
0 |
T162 |
7241 |
6 |
0 |
0 |
T163 |
101991 |
96 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1730 |
0 |
0 |
T117 |
88245 |
56 |
0 |
0 |
T133 |
5267 |
9 |
0 |
0 |
T134 |
30688 |
28 |
0 |
0 |
T151 |
18730 |
55 |
0 |
0 |
T152 |
10602 |
18 |
0 |
0 |
T154 |
12559 |
19 |
0 |
0 |
T160 |
156761 |
226 |
0 |
0 |
T161 |
7426 |
2 |
0 |
0 |
T162 |
7241 |
14 |
0 |
0 |
T163 |
101991 |
141 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1799 |
0 |
0 |
T117 |
88245 |
68 |
0 |
0 |
T133 |
5267 |
12 |
0 |
0 |
T134 |
30688 |
29 |
0 |
0 |
T151 |
18730 |
63 |
0 |
0 |
T152 |
10602 |
10 |
0 |
0 |
T154 |
12559 |
23 |
0 |
0 |
T160 |
156761 |
270 |
0 |
0 |
T161 |
7426 |
21 |
0 |
0 |
T162 |
7241 |
2 |
0 |
0 |
T163 |
101991 |
106 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2249 |
0 |
0 |
T117 |
88245 |
115 |
0 |
0 |
T133 |
5267 |
1 |
0 |
0 |
T134 |
30688 |
40 |
0 |
0 |
T151 |
18730 |
46 |
0 |
0 |
T152 |
10602 |
22 |
0 |
0 |
T154 |
12559 |
15 |
0 |
0 |
T160 |
156761 |
249 |
0 |
0 |
T161 |
7426 |
12 |
0 |
0 |
T162 |
7241 |
3 |
0 |
0 |
T163 |
101991 |
285 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1853 |
0 |
0 |
T117 |
88245 |
61 |
0 |
0 |
T133 |
5267 |
9 |
0 |
0 |
T134 |
30688 |
33 |
0 |
0 |
T151 |
18730 |
88 |
0 |
0 |
T152 |
10602 |
5 |
0 |
0 |
T154 |
12559 |
40 |
0 |
0 |
T160 |
156761 |
243 |
0 |
0 |
T161 |
7426 |
3 |
0 |
0 |
T162 |
7241 |
10 |
0 |
0 |
T163 |
101991 |
115 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2749 |
0 |
0 |
T117 |
88245 |
212 |
0 |
0 |
T134 |
30688 |
51 |
0 |
0 |
T151 |
18730 |
44 |
0 |
0 |
T152 |
10602 |
17 |
0 |
0 |
T154 |
12559 |
33 |
0 |
0 |
T160 |
156761 |
231 |
0 |
0 |
T161 |
7426 |
4 |
0 |
0 |
T162 |
7241 |
13 |
0 |
0 |
T163 |
101991 |
393 |
0 |
0 |
T164 |
69209 |
219 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
2063 |
0 |
0 |
T117 |
88245 |
103 |
0 |
0 |
T133 |
5267 |
10 |
0 |
0 |
T134 |
30688 |
24 |
0 |
0 |
T151 |
18730 |
84 |
0 |
0 |
T152 |
10602 |
31 |
0 |
0 |
T154 |
12559 |
29 |
0 |
0 |
T160 |
156761 |
195 |
0 |
0 |
T161 |
7426 |
32 |
0 |
0 |
T162 |
7241 |
9 |
0 |
0 |
T163 |
101991 |
209 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1711 |
0 |
0 |
T117 |
88245 |
51 |
0 |
0 |
T133 |
5267 |
13 |
0 |
0 |
T134 |
30688 |
9 |
0 |
0 |
T151 |
18730 |
57 |
0 |
0 |
T152 |
10602 |
49 |
0 |
0 |
T154 |
12559 |
21 |
0 |
0 |
T160 |
156761 |
252 |
0 |
0 |
T162 |
7241 |
5 |
0 |
0 |
T163 |
101991 |
77 |
0 |
0 |
T164 |
69209 |
98 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1793 |
0 |
0 |
T117 |
88245 |
65 |
0 |
0 |
T133 |
5267 |
9 |
0 |
0 |
T134 |
30688 |
12 |
0 |
0 |
T151 |
18730 |
40 |
0 |
0 |
T152 |
10602 |
14 |
0 |
0 |
T154 |
12559 |
14 |
0 |
0 |
T160 |
156761 |
335 |
0 |
0 |
T161 |
7426 |
6 |
0 |
0 |
T162 |
7241 |
10 |
0 |
0 |
T163 |
101991 |
117 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1886 |
0 |
0 |
T117 |
88245 |
67 |
0 |
0 |
T133 |
5267 |
2 |
0 |
0 |
T134 |
30688 |
29 |
0 |
0 |
T151 |
18730 |
86 |
0 |
0 |
T152 |
10602 |
12 |
0 |
0 |
T154 |
12559 |
50 |
0 |
0 |
T160 |
156761 |
281 |
0 |
0 |
T161 |
7426 |
8 |
0 |
0 |
T162 |
7241 |
16 |
0 |
0 |
T163 |
101991 |
98 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1610 |
0 |
0 |
T117 |
88245 |
54 |
0 |
0 |
T133 |
5267 |
14 |
0 |
0 |
T134 |
30688 |
11 |
0 |
0 |
T151 |
18730 |
25 |
0 |
0 |
T152 |
10602 |
3 |
0 |
0 |
T154 |
12559 |
9 |
0 |
0 |
T160 |
156761 |
262 |
0 |
0 |
T161 |
7426 |
23 |
0 |
0 |
T162 |
7241 |
5 |
0 |
0 |
T163 |
101991 |
77 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1851 |
0 |
0 |
T117 |
88245 |
80 |
0 |
0 |
T133 |
5267 |
7 |
0 |
0 |
T134 |
30688 |
11 |
0 |
0 |
T151 |
18730 |
119 |
0 |
0 |
T152 |
10602 |
31 |
0 |
0 |
T154 |
12559 |
29 |
0 |
0 |
T160 |
156761 |
287 |
0 |
0 |
T161 |
7426 |
25 |
0 |
0 |
T162 |
7241 |
10 |
0 |
0 |
T163 |
101991 |
118 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112783176 |
1784 |
0 |
0 |
T117 |
88245 |
48 |
0 |
0 |
T133 |
5267 |
12 |
0 |
0 |
T134 |
30688 |
32 |
0 |
0 |
T151 |
18730 |
54 |
0 |
0 |
T152 |
10602 |
2 |
0 |
0 |
T154 |
12559 |
15 |
0 |
0 |
T160 |
156761 |
250 |
0 |
0 |
T161 |
7426 |
11 |
0 |
0 |
T162 |
7241 |
21 |
0 |
0 |
T163 |
101991 |
108 |
0 |
0 |