Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3433615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3823212

1

T1

874

T2

22904

T3

134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4180237	1			T1	2		T2	40760		T3	122
values[0x0]	1537038	1			T1	444		T2	11968		T3	71
values[0x1]	1539552	1			T1	431		T2	11871		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2445757	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4811070

1

T1

874

T2

36038

T3

165

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25613	1			T1	1		T2	250		T3	1
valid_sources[0x01]	25270	1			T1	6		T2	232		T4	5
valid_sources[0x02]	32553	1			T1	2		T2	273		T4	10
valid_sources[0x03]	25740	1			T1	4		T2	276		T3	1
valid_sources[0x04]	25556	1			T1	2		T2	263		T4	3
valid_sources[0x05]	28246	1			T1	4		T2	256		T3	1
valid_sources[0x06]	26065	1			T1	3		T2	243		T3	1
valid_sources[0x07]	46589	1			T1	3		T2	230		T4	3
valid_sources[0x08]	25650	1			T1	1		T2	272		T3	2
valid_sources[0x09]	26146	1			T1	1		T2	251		T3	1
valid_sources[0x0a]	27649	1			T1	1		T2	255		T3	1
valid_sources[0x0b]	24383	1			T1	4		T2	249		T3	2
valid_sources[0x0c]	25011	1			T1	2		T2	264		T4	2
valid_sources[0x0d]	25769	1			T1	5		T2	283		T3	1
valid_sources[0x0e]	30795	1			T1	7		T2	264		T4	2
valid_sources[0x0f]	25472	1			T1	4		T2	251		T3	2
valid_sources[0x10]	24901	1			T1	3		T2	273		T3	1
valid_sources[0x11]	29880	1			T1	2		T2	276		T3	1
valid_sources[0x12]	27261	1			T1	5		T2	225		T3	1
valid_sources[0x13]	25426	1			T1	1		T2	249		T3	1
valid_sources[0x14]	26967	1			T1	8		T2	252		T3	1
valid_sources[0x15]	24844	1			T1	6		T2	236		T4	6
valid_sources[0x16]	27439	1			T1	6		T2	248		T3	1
valid_sources[0x17]	29538	1			T1	4		T2	245		T3	2
valid_sources[0x18]	29012	1			T1	1		T2	246		T4	2
valid_sources[0x19]	27401	1			T1	1		T2	229		T3	1
valid_sources[0x1a]	28315	1			T1	6		T2	250		T4	5
valid_sources[0x1b]	33358	1			T1	3		T2	240		T3	1
valid_sources[0x1c]	23937	1			T1	4		T2	263		T4	7
valid_sources[0x1d]	27868	1			T1	1		T2	276		T5	6
valid_sources[0x1e]	24120	1			T1	5		T2	261		T3	1
valid_sources[0x1f]	23742	1			T1	2		T2	240		T3	2
valid_sources[0x20]	25682	1			T1	2		T2	256		T4	2
valid_sources[0x21]	28155	1			T1	4		T2	249		T3	1
valid_sources[0x22]	24941	1			T1	2		T2	238		T5	7
valid_sources[0x23]	24455	1			T1	6		T2	223		T4	11
valid_sources[0x24]	36145	1			T1	3		T2	237		T3	1
valid_sources[0x25]	25964	1			T1	1		T2	238		T4	6
valid_sources[0x26]	32525	1			T1	2		T2	270		T3	1
valid_sources[0x27]	30757	1			T2	271		T3	2		T4	9
valid_sources[0x28]	28448	1			T1	6		T2	251		T4	10
valid_sources[0x29]	28037	1			T1	3		T2	257		T4	15
valid_sources[0x2a]	26056	1			T1	4		T2	258		T3	1
valid_sources[0x2b]	27079	1			T1	1		T2	270		T3	2
valid_sources[0x2c]	27608	1			T1	1		T2	231		T3	3
valid_sources[0x2d]	30065	1			T1	3		T2	247		T3	2
valid_sources[0x2e]	25700	1			T1	4		T2	253		T3	1
valid_sources[0x2f]	28097	1			T1	4		T2	244		T4	4
valid_sources[0x30]	71464	1			T1	14		T2	229		T4	3
valid_sources[0x31]	26217	1			T1	1		T2	267		T3	1
valid_sources[0x32]	24976	1			T1	5		T2	256		T3	2
valid_sources[0x33]	24696	1			T1	3		T2	280		T4	6
valid_sources[0x34]	27568	1			T1	3		T2	248		T3	3
valid_sources[0x35]	26275	1			T1	3		T2	266		T3	2
valid_sources[0x36]	32789	1			T1	3		T2	242		T3	1
valid_sources[0x37]	26540	1			T1	6		T2	245		T3	3
valid_sources[0x38]	26596	1			T1	3		T2	264		T3	4
valid_sources[0x39]	23274	1			T1	3		T2	264		T4	3
valid_sources[0x3a]	27511	1			T1	2		T2	215		T3	1
valid_sources[0x3b]	23933	1			T1	3		T2	234		T4	2
valid_sources[0x3c]	35418	1			T1	3		T2	254		T4	10
valid_sources[0x3d]	24955	1			T1	2		T2	263		T3	1
valid_sources[0x3e]	24568	1			T1	2		T2	287		T4	13
valid_sources[0x3f]	27781	1			T2	261		T4	7		T5	4
valid_sources[0x40]	28473	1			T1	2		T2	256		T4	6
valid_sources[0x41]	27548	1			T1	3		T2	241		T3	1
valid_sources[0x42]	27128	1			T1	2		T2	255		T4	3
valid_sources[0x43]	24567	1			T1	4		T2	249		T4	4
valid_sources[0x44]	26098	1			T1	4		T2	267		T3	1
valid_sources[0x45]	24278	1			T1	2		T2	247		T3	1
valid_sources[0x46]	26293	1			T1	2		T2	253		T4	3
valid_sources[0x47]	25048	1			T1	2		T2	253		T4	5
valid_sources[0x48]	25967	1			T1	2		T2	236		T3	2
valid_sources[0x49]	31066	1			T1	5		T2	247		T3	2
valid_sources[0x4a]	26633	1			T1	3		T2	257		T4	6
valid_sources[0x4b]	25345	1			T1	8		T2	252		T3	2
valid_sources[0x4c]	26774	1			T1	1		T2	257		T3	4
valid_sources[0x4d]	27677	1			T1	4		T2	207		T3	1
valid_sources[0x4e]	25854	1			T1	4		T2	267		T4	8
valid_sources[0x4f]	23499	1			T1	3		T2	249		T3	1
valid_sources[0x50]	25836	1			T1	2		T2	254		T4	2
valid_sources[0x51]	25027	1			T1	1		T2	238		T4	13
valid_sources[0x52]	28011	1			T1	2		T2	272		T4	19
valid_sources[0x53]	25808	1			T1	5		T2	238		T4	5
valid_sources[0x54]	26845	1			T1	6		T2	270		T3	2
valid_sources[0x55]	29290	1			T1	3		T2	248		T3	2
valid_sources[0x56]	25730	1			T1	2		T2	251		T3	1
valid_sources[0x57]	25472	1			T1	2		T2	266		T4	4
valid_sources[0x58]	24011	1			T1	3		T2	270		T4	1
valid_sources[0x59]	30169	1			T1	3		T2	304		T3	1
valid_sources[0x5a]	29365	1			T1	3		T2	223		T3	2
valid_sources[0x5b]	26442	1			T1	6		T2	225		T3	2
valid_sources[0x5c]	25793	1			T2	258		T3	1		T4	1
valid_sources[0x5d]	24543	1			T1	3		T2	257		T4	1
valid_sources[0x5e]	37373	1			T1	4		T2	250		T3	1
valid_sources[0x5f]	26356	1			T1	2		T2	248		T4	6
valid_sources[0x60]	29389	1			T1	2		T2	257		T3	2
valid_sources[0x61]	25680	1			T1	2		T2	264		T4	7
valid_sources[0x62]	40106	1			T1	5		T2	239		T3	1
valid_sources[0x63]	28889	1			T2	263		T3	2		T4	5
valid_sources[0x64]	27935	1			T1	1		T2	228		T4	5
valid_sources[0x65]	27960	1			T1	4		T2	250		T3	1
valid_sources[0x66]	25575	1			T1	2		T2	240		T4	4
valid_sources[0x67]	31132	1			T1	5		T2	236		T4	8
valid_sources[0x68]	31954	1			T1	8		T2	222		T3	1
valid_sources[0x69]	26572	1			T1	4		T2	265		T3	1
valid_sources[0x6a]	26048	1			T1	8		T2	230		T3	1
valid_sources[0x6b]	29085	1			T1	3		T2	250		T4	11
valid_sources[0x6c]	24999	1			T1	3		T2	286		T4	9
valid_sources[0x6d]	26012	1			T1	4		T2	246		T4	9
valid_sources[0x6e]	26438	1			T1	5		T2	287		T3	1
valid_sources[0x6f]	25047	1			T1	4		T2	233		T4	7
valid_sources[0x70]	26831	1			T1	4		T2	253		T3	4
valid_sources[0x71]	24196	1			T1	2		T2	259		T3	1
valid_sources[0x72]	24989	1			T1	6		T2	241		T3	1
valid_sources[0x73]	25784	1			T1	5		T2	249		T5	9
valid_sources[0x74]	35011	1			T1	6		T2	248		T4	10
valid_sources[0x75]	25007	1			T1	7		T2	263		T4	4
valid_sources[0x76]	24576	1			T1	4		T2	242		T3	2
valid_sources[0x77]	28404	1			T1	5		T2	245		T3	2
valid_sources[0x78]	25175	1			T1	4		T2	251		T3	1
valid_sources[0x79]	25046	1			T1	2		T2	256		T4	5
valid_sources[0x7a]	25240	1			T1	6		T2	229		T3	2
valid_sources[0x7b]	25696	1			T1	2		T2	237		T3	1
valid_sources[0x7c]	25824	1			T1	4		T2	228		T4	5
valid_sources[0x7d]	26247	1			T1	3		T2	257		T4	2
valid_sources[0x7e]	25323	1			T1	6		T2	268		T4	19
valid_sources[0x7f]	24953	1			T1	1		T2	270		T5	9
valid_sources[0x80]	51800	1			T1	4		T2	258		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1054538

1

T1

1

T2

2997

T3

54

values[0x0]

all_enables

biggest_size

1394771

1

T1

444

T2

10041

T3

49

values[0x1]

all_enables

biggest_size

1373903

1

T1

429

T2

9866

T3

31