Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3454398

1

T1

3

T2

41695

T3

113

full_word

3822331

1

T1

874

T2

22904

T3

134

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7276349	1			T1	877		T2	64599		T3	247
auto[TlIntgErrCmd]	133	1			T97	6		T99	12		T100	4
auto[TlIntgErrData]	118	1			T97	10		T99	9		T100	2
auto[TlIntgErrBoth]	129	1			T97	14		T99	9		T100	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4182300

1

T1

2

T2

40760

T3

122

auto[1]

3094429

1

T1

875

T2

23839

T3

125

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3127477	1			T1	1		T2	37763		T3	68
auto[TlIntgErrNone]	partial	auto[1]	326570	1			T1	2		T2	3932		T3	45
auto[TlIntgErrNone]	full_word	auto[0]	1054648	1			T1	1		T2	2997		T3	54
auto[TlIntgErrNone]	full_word	auto[1]	2767654	1			T1	873		T2	19907		T3	80
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T97	1		T99	8		T100	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T97	5		T99	4		T100	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T260	1		T152	1		T262	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T259	2		T152	1		T263	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T97	7		T99	3		T100	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T97	2		T99	6		T100	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T264	1		T262	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T97	1		T259	1		T260	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T97	6		T99	3		T100	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T97	6		T99	5		T259	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T97	2		T100	1		T259	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T99	1		T265	1		T266	1