Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405156956	5922119	0	0
DepthKnown_A	405156956	405027185	0	0
RvalidKnown_A	405156956	405027185	0	0
WreadyKnown_A	405156956	405027185	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	5922119	0	0
T1	34921	45	0	0
T2	335593	62812	0	0
T3	3815	199	0	0
T4	404901	633	0	0
T5	48516	1066	0	0
T6	116269	1718	0	0
T7	825447	1970	0	0
T8	69292	69	0	0
T9	1191	19	0	0
T10	252502	1130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	405027185	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	405027185	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	405027185	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	405156956	11395116	0	0
DepthKnown_A	405156956	405027185	0	0
RvalidKnown_A	405156956	405027185	0	0
WreadyKnown_A	405156956	405027185	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	11395116	0	0
T1	34921	206	0	0
T2	335593	184421	0	0
T3	3815	900	0	0
T4	404901	2560	0	0
T5	48516	4658	0	0
T6	116269	7405	0	0
T7	825447	8528	0	0
T8	69292	69	0	0
T9	1191	19	0	0
T10	252502	1124	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	405027185	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	405027185	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405156956	405027185	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0