Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T13
1	0	Covered	T2,T3,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Unreachable
1	1	Covered	T2,T3,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T10
1	0	Covered	T2,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T2,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	654954689	527798548	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	654954689	2956630	0	0
GntImpliesValid_A	654954689	2956630	0	0
GrantKnown_A	654954689	527798548	0	0
IdxKnown_A	654954689	527798548	0	0
IndexIsCorrect_A	654954689	2956630	0	0
LockArbDecision_A	654954689	0	0	0
NoReadyValidNoGrant_A	654954689	0	0	0
ReadyAndValidImplyGrant_A	654954689	2956630	0	0
ReqAndReadyImplyGrant_A	654954689	2956630	0	0
ReqImpliesValid_A	654954689	2956630	0	0
ReqStaysHighUntilGranted0_M	654954689	0	0	0
RoundRobin_A	654954689	3	0	926
ValidKnown_A	654954689	527798548	0	0
gen_data_port_assertion.DataFlow_A	654954689	2956630	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	527798548	0	0
T1	39033	38941	0	0
T2	1298697	812016	0	0
T3	18791	11215	0	0
T4	565329	483928	0	0
T5	85114	66312	0	0
T6	447025	281357	0	0
T7	1552617	1186082	0	0
T8	463368	265810	0	0
T9	1191	1111	0	0
T10	1695638	970922	0	0
T11	80734	39738	0	0
T12	19525	19525	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	527798548	0	0
T1	39033	38941	0	0
T2	1298697	812016	0	0
T3	18791	11215	0	0
T4	565329	483928	0	0
T5	85114	66312	0	0
T6	447025	281357	0	0
T7	1552617	1186082	0	0
T8	463368	265810	0	0
T9	1191	1111	0	0
T10	1695638	970922	0	0
T11	80734	39738	0	0
T12	19525	19525	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	527798548	0	0
T1	39033	38941	0	0
T2	1298697	812016	0	0
T3	18791	11215	0	0
T4	565329	483928	0	0
T5	85114	66312	0	0
T6	447025	281357	0	0
T7	1552617	1186082	0	0
T8	463368	265810	0	0
T9	1191	1111	0	0
T10	1695638	970922	0	0
T11	80734	39738	0	0
T12	19525	19525	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	3	0	926
T43	897752	1	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	171463	0	0	1
T47	113715	0	0	1
T48	157483	0	0	1
T49	11559	0	0	1
T50	157728	0	0	1
T51	19193	0	0	1
T52	299910	0	0	1
T53	1556	0	0	1
T54	33056	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	527798548	0	0
T1	39033	38941	0	0
T2	1298697	812016	0	0
T3	18791	11215	0	0
T4	565329	483928	0	0
T5	85114	66312	0	0
T6	447025	281357	0	0
T7	1552617	1186082	0	0
T8	463368	265810	0	0
T9	1191	1111	0	0
T10	1695638	970922	0	0
T11	80734	39738	0	0
T12	19525	19525	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	654954689	2956630	0	0
T1	34921	832	0	0
T2	1298697	10425	0	0
T3	18791	366	0	0
T4	565329	832	0	0
T5	85114	832	0	0
T6	447025	832	0	0
T7	1552617	11053	0	0
T8	463368	832	0	0
T9	1191	0	0	0
T10	1695638	13211	0	0
T11	80734	1600	0	0
T12	39050	0	0	0
T13	0	8690	0	0
T15	0	3507	0	0
T19	0	7502	0	0
T20	0	1322	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T31	0	408	0	0
T32	0	3684	0	0
T36	0	2	0	0
T41	0	3311	0	0
T42	0	1206	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T13
1	0	Covered	T2,T3,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T13
1	0	Unreachable
1	1	Covered	T2,T3,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125892913	27556535	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	125892913	580748	0	0
GntImpliesValid_A	125892913	580748	0	0
GrantKnown_A	125892913	27556535	0	0
IdxKnown_A	125892913	27556535	0	0
IndexIsCorrect_A	125892913	580748	0	0
LockArbDecision_A	125892913	0	0	0
NoReadyValidNoGrant_A	125892913	0	0	0
ReadyAndValidImplyGrant_A	125892913	580748	0	0
ReqAndReadyImplyGrant_A	125892913	580748	0	0
ReqImpliesValid_A	125892913	580748	0	0
ReqStaysHighUntilGranted0_M	125892913	0	0	0
RoundRobin_A	125892913	0	0	0
ValidKnown_A	125892913	27556535	0	0
gen_data_port_assertion.DataFlow_A	125892913	580748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	27556535	0	0
T2	481552	97264	0	0
T3	7488	7488	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	27556535	0	0
T2	481552	97264	0	0
T3	7488	7488	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	27556535	0	0
T2	481552	97264	0	0
T3	7488	7488	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	27556535	0	0
T2	481552	97264	0	0
T3	7488	7488	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	159200	0	0
T15	0	75400	0	0
T17	0	88808	0	0
T19	0	122800	0	0
T20	0	107848	0	0
T31	0	11336	0	0
T32	0	107232	0	0
T41	0	75192	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	580748	0	0
T2	481552	3935	0	0
T3	7488	255	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	0	0	0
T8	197038	0	0	0
T10	721568	0	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	1404	0	0
T15	0	3507	0	0
T19	0	1035	0	0
T20	0	1322	0	0
T31	0	408	0	0
T32	0	3684	0	0
T41	0	3311	0	0
T42	0	1206	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T10
1	0	Covered	T2,T7,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T2,T7,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T10
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125892913	97159449	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	125892913	494628	0	0
GntImpliesValid_A	125892913	494628	0	0
GrantKnown_A	125892913	97159449	0	0
IdxKnown_A	125892913	97159449	0	0
IndexIsCorrect_A	125892913	494628	0	0
LockArbDecision_A	125892913	0	0	0
NoReadyValidNoGrant_A	125892913	0	0	0
ReadyAndValidImplyGrant_A	125892913	494628	0	0
ReqAndReadyImplyGrant_A	125892913	494628	0	0
ReqImpliesValid_A	125892913	494628	0	0
ReqStaysHighUntilGranted0_M	125892913	0	0	0
RoundRobin_A	125892913	0	0	0
ValidKnown_A	125892913	97159449	0	0
gen_data_port_assertion.DataFlow_A	125892913	494628	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	97159449	0	0
T1	4112	4112	0	0
T2	481552	379165	0	0
T3	7488	0	0	0
T4	80214	79106	0	0
T5	18299	17872	0	0
T6	165378	165094	0	0
T7	363585	360733	0	0
T8	197038	196568	0	0
T10	721568	718490	0	0
T11	40367	39738	0	0
T12	0	19525	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	97159449	0	0
T1	4112	4112	0	0
T2	481552	379165	0	0
T3	7488	0	0	0
T4	80214	79106	0	0
T5	18299	17872	0	0
T6	165378	165094	0	0
T7	363585	360733	0	0
T8	197038	196568	0	0
T10	721568	718490	0	0
T11	40367	39738	0	0
T12	0	19525	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	97159449	0	0
T1	4112	4112	0	0
T2	481552	379165	0	0
T3	7488	0	0	0
T4	80214	79106	0	0
T5	18299	17872	0	0
T6	165378	165094	0	0
T7	363585	360733	0	0
T8	197038	196568	0	0
T10	721568	718490	0	0
T11	40367	39738	0	0
T12	0	19525	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	97159449	0	0
T1	4112	4112	0	0
T2	481552	379165	0	0
T3	7488	0	0	0
T4	80214	79106	0	0
T5	18299	17872	0	0
T6	165378	165094	0	0
T7	363585	360733	0	0
T8	197038	196568	0	0
T10	721568	718490	0	0
T11	40367	39738	0	0
T12	0	19525	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125892913	494628	0	0
T2	481552	397	0	0
T3	7488	0	0	0
T4	80214	0	0	0
T5	18299	0	0	0
T6	165378	0	0	0
T7	363585	1737	0	0
T8	197038	0	0	0
T10	721568	3713	0	0
T11	40367	0	0	0
T12	19525	0	0	0
T13	0	7286	0	0
T19	0	6467	0	0
T27	0	3007	0	0
T28	0	7172	0	0
T36	0	2	0	0
T40	0	2361	0	0
T55	0	3354	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	403168863	403082564	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	403168863	1881254	0	0
GntImpliesValid_A	403168863	1881254	0	0
GrantKnown_A	403168863	403082564	0	0
IdxKnown_A	403168863	403082564	0	0
IndexIsCorrect_A	403168863	1881254	0	0
LockArbDecision_A	403168863	0	0	0
NoReadyValidNoGrant_A	403168863	0	0	0
ReadyAndValidImplyGrant_A	403168863	1881254	0	0
ReqAndReadyImplyGrant_A	403168863	1881254	0	0
ReqImpliesValid_A	403168863	1881254	0	0
ReqStaysHighUntilGranted0_M	403168863	0	0	0
RoundRobin_A	403168863	3	0	926
ValidKnown_A	403168863	403082564	0	0
gen_data_port_assertion.DataFlow_A	403168863	1881254	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	403082564	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	403082564	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	403082564	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	3	0	926
T43	897752	1	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	171463	0	0	1
T47	113715	0	0	1
T48	157483	0	0	1
T49	11559	0	0	1
T50	157728	0	0	1
T51	19193	0	0	1
T52	299910	0	0	1
T53	1556	0	0	1
T54	33056	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	403082564	0	0
T1	34921	34829	0	0
T2	335593	335587	0	0
T3	3815	3727	0	0
T4	404901	404822	0	0
T5	48516	48440	0	0
T6	116269	116263	0	0
T7	825447	825349	0	0
T8	69292	69242	0	0
T9	1191	1111	0	0
T10	252502	252432	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403168863	1881254	0	0
T1	34921	832	0	0
T2	335593	6093	0	0
T3	3815	111	0	0
T4	404901	832	0	0
T5	48516	832	0	0
T6	116269	832	0	0
T7	825447	9316	0	0
T8	69292	832	0	0
T9	1191	0	0	0
T10	252502	9498	0	0
T11	0	1600	0	0