Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3840 |
0 |
0 |
T94 |
5380 |
2 |
0 |
0 |
T95 |
4928 |
10 |
0 |
0 |
T96 |
2330 |
3 |
0 |
0 |
T97 |
98715 |
2 |
0 |
0 |
T98 |
5387 |
72 |
0 |
0 |
T99 |
29333 |
1 |
0 |
0 |
T101 |
2448 |
29 |
0 |
0 |
T111 |
5782 |
2 |
0 |
0 |
T112 |
2660 |
8 |
0 |
0 |
T113 |
2514 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
835 |
0 |
0 |
T81 |
4072 |
14 |
0 |
0 |
T94 |
5380 |
11 |
0 |
0 |
T97 |
98715 |
39 |
0 |
0 |
T100 |
34655 |
49 |
0 |
0 |
T111 |
5782 |
2 |
0 |
0 |
T116 |
4137 |
5 |
0 |
0 |
T144 |
4792 |
7 |
0 |
0 |
T151 |
5082 |
3 |
0 |
0 |
T152 |
63603 |
28 |
0 |
0 |
T153 |
7661 |
14 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
955 |
0 |
0 |
T81 |
4072 |
4 |
0 |
0 |
T94 |
5380 |
16 |
0 |
0 |
T97 |
98715 |
48 |
0 |
0 |
T100 |
34655 |
28 |
0 |
0 |
T111 |
5782 |
9 |
0 |
0 |
T144 |
4792 |
5 |
0 |
0 |
T151 |
5082 |
15 |
0 |
0 |
T152 |
63603 |
51 |
0 |
0 |
T153 |
7661 |
28 |
0 |
0 |
T154 |
19270 |
27 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1448 |
0 |
0 |
T94 |
5380 |
20 |
0 |
0 |
T97 |
98715 |
110 |
0 |
0 |
T100 |
34655 |
43 |
0 |
0 |
T111 |
5782 |
7 |
0 |
0 |
T116 |
4137 |
10 |
0 |
0 |
T144 |
4792 |
10 |
0 |
0 |
T151 |
5082 |
13 |
0 |
0 |
T152 |
63603 |
106 |
0 |
0 |
T153 |
7661 |
20 |
0 |
0 |
T154 |
19270 |
43 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
8160 |
0 |
0 |
T81 |
4072 |
5 |
0 |
0 |
T94 |
5380 |
123 |
0 |
0 |
T97 |
98715 |
1155 |
0 |
0 |
T100 |
34655 |
272 |
0 |
0 |
T111 |
5782 |
7 |
0 |
0 |
T116 |
4137 |
7 |
0 |
0 |
T144 |
4792 |
6 |
0 |
0 |
T151 |
5082 |
124 |
0 |
0 |
T152 |
63603 |
873 |
0 |
0 |
T153 |
7661 |
10 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
9015 |
0 |
0 |
T81 |
4072 |
2 |
0 |
0 |
T94 |
5380 |
11 |
0 |
0 |
T97 |
98715 |
900 |
0 |
0 |
T100 |
34655 |
1022 |
0 |
0 |
T111 |
5782 |
17 |
0 |
0 |
T116 |
4137 |
5 |
0 |
0 |
T144 |
4792 |
114 |
0 |
0 |
T151 |
5082 |
83 |
0 |
0 |
T152 |
63603 |
726 |
0 |
0 |
T153 |
7661 |
33 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
9257 |
0 |
0 |
T81 |
4072 |
7 |
0 |
0 |
T94 |
5380 |
144 |
0 |
0 |
T97 |
98715 |
1077 |
0 |
0 |
T100 |
34655 |
755 |
0 |
0 |
T103 |
16781 |
4 |
0 |
0 |
T111 |
5782 |
160 |
0 |
0 |
T144 |
4792 |
148 |
0 |
0 |
T151 |
5082 |
104 |
0 |
0 |
T152 |
63603 |
894 |
0 |
0 |
T153 |
7661 |
21 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
9382 |
0 |
0 |
T81 |
4072 |
5 |
0 |
0 |
T94 |
5380 |
13 |
0 |
0 |
T97 |
98715 |
1058 |
0 |
0 |
T100 |
34655 |
930 |
0 |
0 |
T111 |
5782 |
98 |
0 |
0 |
T116 |
4137 |
136 |
0 |
0 |
T144 |
4792 |
92 |
0 |
0 |
T151 |
5082 |
5 |
0 |
0 |
T152 |
63603 |
997 |
0 |
0 |
T153 |
7661 |
15 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
8435 |
0 |
0 |
T81 |
4072 |
2 |
0 |
0 |
T94 |
5380 |
7 |
0 |
0 |
T97 |
98715 |
1193 |
0 |
0 |
T100 |
34655 |
528 |
0 |
0 |
T111 |
5782 |
6 |
0 |
0 |
T116 |
4137 |
108 |
0 |
0 |
T144 |
4792 |
129 |
0 |
0 |
T151 |
5082 |
9 |
0 |
0 |
T152 |
63603 |
840 |
0 |
0 |
T153 |
7661 |
3 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
8029 |
0 |
0 |
T81 |
4072 |
6 |
0 |
0 |
T94 |
5380 |
5 |
0 |
0 |
T97 |
98715 |
1162 |
0 |
0 |
T100 |
34655 |
273 |
0 |
0 |
T111 |
5782 |
10 |
0 |
0 |
T116 |
4137 |
86 |
0 |
0 |
T144 |
4792 |
80 |
0 |
0 |
T151 |
5082 |
7 |
0 |
0 |
T152 |
63603 |
709 |
0 |
0 |
T153 |
7661 |
29 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
8355 |
0 |
0 |
T81 |
4072 |
3 |
0 |
0 |
T94 |
5380 |
108 |
0 |
0 |
T97 |
98715 |
1167 |
0 |
0 |
T100 |
34655 |
268 |
0 |
0 |
T111 |
5782 |
141 |
0 |
0 |
T116 |
4137 |
6 |
0 |
0 |
T144 |
4792 |
6 |
0 |
0 |
T151 |
5082 |
128 |
0 |
0 |
T152 |
63603 |
619 |
0 |
0 |
T153 |
7661 |
17 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
8850 |
0 |
0 |
T81 |
4072 |
7 |
0 |
0 |
T94 |
5380 |
10 |
0 |
0 |
T97 |
98715 |
921 |
0 |
0 |
T100 |
34655 |
783 |
0 |
0 |
T111 |
5782 |
7 |
0 |
0 |
T116 |
4137 |
9 |
0 |
0 |
T144 |
4792 |
2 |
0 |
0 |
T151 |
5082 |
3 |
0 |
0 |
T152 |
63603 |
768 |
0 |
0 |
T153 |
7661 |
13 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3688 |
0 |
0 |
T81 |
4072 |
3 |
0 |
0 |
T94 |
5380 |
54 |
0 |
0 |
T97 |
98715 |
384 |
0 |
0 |
T100 |
34655 |
256 |
0 |
0 |
T111 |
5782 |
52 |
0 |
0 |
T116 |
4137 |
7 |
0 |
0 |
T144 |
4792 |
2 |
0 |
0 |
T151 |
5082 |
3 |
0 |
0 |
T152 |
63603 |
257 |
0 |
0 |
T153 |
7661 |
18 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
4528 |
0 |
0 |
T81 |
4072 |
7 |
0 |
0 |
T94 |
5380 |
3 |
0 |
0 |
T97 |
98715 |
467 |
0 |
0 |
T100 |
34655 |
384 |
0 |
0 |
T111 |
5782 |
73 |
0 |
0 |
T116 |
4137 |
5 |
0 |
0 |
T144 |
4792 |
7 |
0 |
0 |
T151 |
5082 |
1 |
0 |
0 |
T152 |
63603 |
292 |
0 |
0 |
T153 |
7661 |
36 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3405 |
0 |
0 |
T81 |
4072 |
15 |
0 |
0 |
T94 |
5380 |
59 |
0 |
0 |
T97 |
98715 |
451 |
0 |
0 |
T100 |
34655 |
273 |
0 |
0 |
T111 |
5782 |
67 |
0 |
0 |
T116 |
4137 |
1 |
0 |
0 |
T144 |
4792 |
44 |
0 |
0 |
T151 |
5082 |
10 |
0 |
0 |
T152 |
63603 |
339 |
0 |
0 |
T153 |
7661 |
18 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3707 |
0 |
0 |
T81 |
4072 |
4 |
0 |
0 |
T94 |
5380 |
46 |
0 |
0 |
T97 |
98715 |
563 |
0 |
0 |
T100 |
34655 |
145 |
0 |
0 |
T111 |
5782 |
57 |
0 |
0 |
T116 |
4137 |
6 |
0 |
0 |
T144 |
4792 |
55 |
0 |
0 |
T151 |
5082 |
28 |
0 |
0 |
T152 |
63603 |
386 |
0 |
0 |
T153 |
7661 |
29 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3882 |
0 |
0 |
T81 |
4072 |
13 |
0 |
0 |
T94 |
5380 |
38 |
0 |
0 |
T97 |
98715 |
449 |
0 |
0 |
T100 |
34655 |
227 |
0 |
0 |
T111 |
5782 |
15 |
0 |
0 |
T144 |
4792 |
55 |
0 |
0 |
T151 |
5082 |
47 |
0 |
0 |
T152 |
63603 |
253 |
0 |
0 |
T153 |
7661 |
15 |
0 |
0 |
T154 |
19270 |
26 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3762 |
0 |
0 |
T81 |
4072 |
4 |
0 |
0 |
T94 |
5380 |
4 |
0 |
0 |
T97 |
98715 |
420 |
0 |
0 |
T100 |
34655 |
246 |
0 |
0 |
T110 |
6178 |
3 |
0 |
0 |
T111 |
5782 |
73 |
0 |
0 |
T116 |
4137 |
2 |
0 |
0 |
T144 |
4792 |
62 |
0 |
0 |
T151 |
5082 |
48 |
0 |
0 |
T152 |
63603 |
328 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3407 |
0 |
0 |
T94 |
5380 |
43 |
0 |
0 |
T97 |
98715 |
243 |
0 |
0 |
T100 |
34655 |
265 |
0 |
0 |
T103 |
16781 |
6 |
0 |
0 |
T111 |
5782 |
71 |
0 |
0 |
T116 |
4137 |
35 |
0 |
0 |
T144 |
4792 |
6 |
0 |
0 |
T151 |
5082 |
13 |
0 |
0 |
T152 |
63603 |
228 |
0 |
0 |
T153 |
7661 |
33 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
4075 |
0 |
0 |
T81 |
4072 |
6 |
0 |
0 |
T94 |
5380 |
29 |
0 |
0 |
T97 |
98715 |
397 |
0 |
0 |
T100 |
34655 |
255 |
0 |
0 |
T111 |
5782 |
4 |
0 |
0 |
T116 |
4137 |
60 |
0 |
0 |
T144 |
4792 |
51 |
0 |
0 |
T151 |
5082 |
41 |
0 |
0 |
T152 |
63603 |
342 |
0 |
0 |
T153 |
7661 |
41 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3445 |
0 |
0 |
T81 |
4072 |
10 |
0 |
0 |
T94 |
5380 |
3 |
0 |
0 |
T97 |
98715 |
471 |
0 |
0 |
T100 |
34655 |
299 |
0 |
0 |
T111 |
5782 |
7 |
0 |
0 |
T144 |
4792 |
55 |
0 |
0 |
T151 |
5082 |
60 |
0 |
0 |
T152 |
63603 |
416 |
0 |
0 |
T153 |
7661 |
24 |
0 |
0 |
T154 |
19270 |
27 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
4056 |
0 |
0 |
T81 |
4072 |
11 |
0 |
0 |
T94 |
5380 |
11 |
0 |
0 |
T97 |
98715 |
500 |
0 |
0 |
T100 |
34655 |
347 |
0 |
0 |
T111 |
5782 |
52 |
0 |
0 |
T116 |
4137 |
40 |
0 |
0 |
T144 |
4792 |
50 |
0 |
0 |
T151 |
5082 |
38 |
0 |
0 |
T152 |
63603 |
226 |
0 |
0 |
T153 |
7661 |
14 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3935 |
0 |
0 |
T81 |
4072 |
21 |
0 |
0 |
T94 |
5380 |
9 |
0 |
0 |
T97 |
98715 |
517 |
0 |
0 |
T100 |
34655 |
322 |
0 |
0 |
T111 |
5782 |
6 |
0 |
0 |
T116 |
4137 |
1 |
0 |
0 |
T144 |
4792 |
9 |
0 |
0 |
T151 |
5082 |
54 |
0 |
0 |
T152 |
63603 |
449 |
0 |
0 |
T153 |
7661 |
9 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3981 |
0 |
0 |
T81 |
4072 |
15 |
0 |
0 |
T94 |
5380 |
8 |
0 |
0 |
T97 |
98715 |
464 |
0 |
0 |
T100 |
34655 |
206 |
0 |
0 |
T111 |
5782 |
10 |
0 |
0 |
T116 |
4137 |
60 |
0 |
0 |
T144 |
4792 |
8 |
0 |
0 |
T151 |
5082 |
38 |
0 |
0 |
T152 |
63603 |
287 |
0 |
0 |
T153 |
7661 |
8 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
4076 |
0 |
0 |
T81 |
4072 |
4 |
0 |
0 |
T94 |
5380 |
45 |
0 |
0 |
T97 |
98715 |
476 |
0 |
0 |
T100 |
34655 |
398 |
0 |
0 |
T111 |
5782 |
74 |
0 |
0 |
T116 |
4137 |
47 |
0 |
0 |
T144 |
4792 |
5 |
0 |
0 |
T151 |
5082 |
37 |
0 |
0 |
T152 |
63603 |
375 |
0 |
0 |
T153 |
7661 |
53 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3602 |
0 |
0 |
T94 |
5380 |
50 |
0 |
0 |
T97 |
98715 |
404 |
0 |
0 |
T100 |
34655 |
333 |
0 |
0 |
T111 |
5782 |
12 |
0 |
0 |
T116 |
4137 |
39 |
0 |
0 |
T144 |
4792 |
3 |
0 |
0 |
T151 |
5082 |
7 |
0 |
0 |
T152 |
63603 |
276 |
0 |
0 |
T153 |
7661 |
22 |
0 |
0 |
T154 |
19270 |
14 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
4329 |
0 |
0 |
T81 |
4072 |
5 |
0 |
0 |
T94 |
5380 |
7 |
0 |
0 |
T97 |
98715 |
388 |
0 |
0 |
T100 |
34655 |
169 |
0 |
0 |
T111 |
5782 |
7 |
0 |
0 |
T116 |
4137 |
2 |
0 |
0 |
T144 |
4792 |
61 |
0 |
0 |
T151 |
5082 |
8 |
0 |
0 |
T152 |
63603 |
312 |
0 |
0 |
T153 |
7661 |
24 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3960 |
0 |
0 |
T81 |
4072 |
6 |
0 |
0 |
T94 |
5380 |
2 |
0 |
0 |
T97 |
98715 |
542 |
0 |
0 |
T100 |
34655 |
307 |
0 |
0 |
T111 |
5782 |
59 |
0 |
0 |
T116 |
4137 |
29 |
0 |
0 |
T144 |
4792 |
42 |
0 |
0 |
T151 |
5082 |
45 |
0 |
0 |
T152 |
63603 |
245 |
0 |
0 |
T153 |
7661 |
2 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3940 |
0 |
0 |
T81 |
4072 |
1 |
0 |
0 |
T94 |
5380 |
47 |
0 |
0 |
T97 |
98715 |
447 |
0 |
0 |
T100 |
34655 |
367 |
0 |
0 |
T111 |
5782 |
3 |
0 |
0 |
T116 |
4137 |
44 |
0 |
0 |
T144 |
4792 |
38 |
0 |
0 |
T151 |
5082 |
3 |
0 |
0 |
T152 |
63603 |
282 |
0 |
0 |
T153 |
7661 |
40 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3589 |
0 |
0 |
T81 |
4072 |
11 |
0 |
0 |
T94 |
5380 |
11 |
0 |
0 |
T97 |
98715 |
294 |
0 |
0 |
T100 |
34655 |
241 |
0 |
0 |
T111 |
5782 |
13 |
0 |
0 |
T116 |
4137 |
2 |
0 |
0 |
T144 |
4792 |
6 |
0 |
0 |
T151 |
5082 |
12 |
0 |
0 |
T152 |
63603 |
274 |
0 |
0 |
T153 |
7661 |
7 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
4145 |
0 |
0 |
T94 |
5380 |
56 |
0 |
0 |
T97 |
98715 |
499 |
0 |
0 |
T100 |
34655 |
324 |
0 |
0 |
T111 |
5782 |
72 |
0 |
0 |
T116 |
4137 |
54 |
0 |
0 |
T144 |
4792 |
52 |
0 |
0 |
T151 |
5082 |
63 |
0 |
0 |
T152 |
63603 |
424 |
0 |
0 |
T153 |
7661 |
54 |
0 |
0 |
T154 |
19270 |
78 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3813 |
0 |
0 |
T81 |
4072 |
8 |
0 |
0 |
T94 |
5380 |
10 |
0 |
0 |
T97 |
98715 |
415 |
0 |
0 |
T100 |
34655 |
280 |
0 |
0 |
T111 |
5782 |
72 |
0 |
0 |
T116 |
4137 |
6 |
0 |
0 |
T144 |
4792 |
47 |
0 |
0 |
T151 |
5082 |
47 |
0 |
0 |
T152 |
63603 |
264 |
0 |
0 |
T153 |
7661 |
4 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3706 |
0 |
0 |
T94 |
5380 |
6 |
0 |
0 |
T97 |
98715 |
269 |
0 |
0 |
T100 |
34655 |
354 |
0 |
0 |
T111 |
5782 |
2 |
0 |
0 |
T116 |
4137 |
65 |
0 |
0 |
T144 |
4792 |
3 |
0 |
0 |
T151 |
5082 |
9 |
0 |
0 |
T152 |
63603 |
248 |
0 |
0 |
T153 |
7661 |
3 |
0 |
0 |
T154 |
19270 |
54 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3951 |
0 |
0 |
T94 |
5380 |
2 |
0 |
0 |
T97 |
98715 |
406 |
0 |
0 |
T100 |
34655 |
479 |
0 |
0 |
T111 |
5782 |
63 |
0 |
0 |
T116 |
4137 |
8 |
0 |
0 |
T144 |
4792 |
37 |
0 |
0 |
T151 |
5082 |
6 |
0 |
0 |
T152 |
63603 |
286 |
0 |
0 |
T153 |
7661 |
25 |
0 |
0 |
T154 |
19270 |
29 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3830 |
0 |
0 |
T81 |
4072 |
3 |
0 |
0 |
T94 |
5380 |
5 |
0 |
0 |
T97 |
98715 |
385 |
0 |
0 |
T100 |
34655 |
437 |
0 |
0 |
T111 |
5782 |
53 |
0 |
0 |
T116 |
4137 |
58 |
0 |
0 |
T151 |
5082 |
11 |
0 |
0 |
T152 |
63603 |
236 |
0 |
0 |
T153 |
7661 |
7 |
0 |
0 |
T154 |
19270 |
23 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3945 |
0 |
0 |
T81 |
4072 |
10 |
0 |
0 |
T94 |
5380 |
41 |
0 |
0 |
T97 |
98715 |
388 |
0 |
0 |
T100 |
34655 |
345 |
0 |
0 |
T111 |
5782 |
53 |
0 |
0 |
T116 |
4137 |
9 |
0 |
0 |
T144 |
4792 |
2 |
0 |
0 |
T151 |
5082 |
14 |
0 |
0 |
T152 |
63603 |
357 |
0 |
0 |
T153 |
7661 |
7 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1182 |
0 |
0 |
T81 |
4072 |
4 |
0 |
0 |
T94 |
5380 |
10 |
0 |
0 |
T97 |
98715 |
110 |
0 |
0 |
T100 |
34655 |
77 |
0 |
0 |
T111 |
5782 |
7 |
0 |
0 |
T116 |
4137 |
8 |
0 |
0 |
T144 |
4792 |
10 |
0 |
0 |
T151 |
5082 |
14 |
0 |
0 |
T152 |
63603 |
56 |
0 |
0 |
T153 |
7661 |
22 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1136 |
0 |
0 |
T81 |
4072 |
19 |
0 |
0 |
T94 |
5380 |
8 |
0 |
0 |
T97 |
98715 |
60 |
0 |
0 |
T100 |
34655 |
55 |
0 |
0 |
T111 |
5782 |
14 |
0 |
0 |
T116 |
4137 |
7 |
0 |
0 |
T144 |
4792 |
4 |
0 |
0 |
T151 |
5082 |
6 |
0 |
0 |
T152 |
63603 |
81 |
0 |
0 |
T153 |
7661 |
9 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1258 |
0 |
0 |
T81 |
4072 |
9 |
0 |
0 |
T94 |
5380 |
13 |
0 |
0 |
T97 |
98715 |
110 |
0 |
0 |
T100 |
34655 |
58 |
0 |
0 |
T111 |
5782 |
11 |
0 |
0 |
T116 |
4137 |
16 |
0 |
0 |
T144 |
4792 |
17 |
0 |
0 |
T151 |
5082 |
6 |
0 |
0 |
T152 |
63603 |
42 |
0 |
0 |
T153 |
7661 |
27 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1170 |
0 |
0 |
T81 |
4072 |
5 |
0 |
0 |
T94 |
5380 |
11 |
0 |
0 |
T97 |
98715 |
127 |
0 |
0 |
T100 |
34655 |
72 |
0 |
0 |
T111 |
5782 |
9 |
0 |
0 |
T116 |
4137 |
2 |
0 |
0 |
T144 |
4792 |
1 |
0 |
0 |
T151 |
5082 |
10 |
0 |
0 |
T152 |
63603 |
42 |
0 |
0 |
T153 |
7661 |
35 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1639 |
0 |
0 |
T94 |
5380 |
6 |
0 |
0 |
T97 |
98715 |
222 |
0 |
0 |
T100 |
34655 |
99 |
0 |
0 |
T111 |
5782 |
8 |
0 |
0 |
T116 |
4137 |
2 |
0 |
0 |
T144 |
4792 |
12 |
0 |
0 |
T151 |
5082 |
7 |
0 |
0 |
T152 |
63603 |
108 |
0 |
0 |
T153 |
7661 |
7 |
0 |
0 |
T154 |
19270 |
16 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
3197 |
0 |
0 |
T19 |
226245 |
15 |
0 |
0 |
T20 |
235722 |
0 |
0 |
0 |
T29 |
149806 |
0 |
0 |
0 |
T40 |
195866 |
0 |
0 |
0 |
T41 |
176686 |
0 |
0 |
0 |
T55 |
113905 |
0 |
0 |
0 |
T59 |
0 |
16 |
0 |
0 |
T60 |
0 |
28 |
0 |
0 |
T146 |
112954 |
0 |
0 |
0 |
T147 |
121208 |
0 |
0 |
0 |
T155 |
0 |
32 |
0 |
0 |
T156 |
0 |
7 |
0 |
0 |
T157 |
0 |
45 |
0 |
0 |
T158 |
0 |
39 |
0 |
0 |
T159 |
0 |
45 |
0 |
0 |
T160 |
0 |
40 |
0 |
0 |
T161 |
0 |
39 |
0 |
0 |
T162 |
19179 |
0 |
0 |
0 |
T163 |
37896 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1071 |
0 |
0 |
T94 |
5380 |
6 |
0 |
0 |
T97 |
98715 |
105 |
0 |
0 |
T100 |
34655 |
57 |
0 |
0 |
T111 |
5782 |
3 |
0 |
0 |
T116 |
4137 |
4 |
0 |
0 |
T144 |
4792 |
3 |
0 |
0 |
T151 |
5082 |
5 |
0 |
0 |
T152 |
63603 |
73 |
0 |
0 |
T154 |
19270 |
17 |
0 |
0 |
T164 |
4745 |
12 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1123 |
0 |
0 |
T81 |
4072 |
5 |
0 |
0 |
T94 |
5380 |
21 |
0 |
0 |
T97 |
98715 |
62 |
0 |
0 |
T100 |
34655 |
70 |
0 |
0 |
T111 |
5782 |
8 |
0 |
0 |
T116 |
4137 |
2 |
0 |
0 |
T144 |
4792 |
16 |
0 |
0 |
T151 |
5082 |
11 |
0 |
0 |
T152 |
63603 |
83 |
0 |
0 |
T153 |
7661 |
46 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
838 |
0 |
0 |
T81 |
4072 |
9 |
0 |
0 |
T94 |
5380 |
7 |
0 |
0 |
T97 |
98715 |
79 |
0 |
0 |
T100 |
34655 |
37 |
0 |
0 |
T111 |
5782 |
8 |
0 |
0 |
T116 |
4137 |
4 |
0 |
0 |
T144 |
4792 |
9 |
0 |
0 |
T151 |
5082 |
2 |
0 |
0 |
T152 |
63603 |
33 |
0 |
0 |
T153 |
7661 |
20 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
934 |
0 |
0 |
T81 |
4072 |
2 |
0 |
0 |
T94 |
5380 |
8 |
0 |
0 |
T97 |
98715 |
35 |
0 |
0 |
T100 |
34655 |
38 |
0 |
0 |
T111 |
5782 |
9 |
0 |
0 |
T116 |
4137 |
6 |
0 |
0 |
T144 |
4792 |
4 |
0 |
0 |
T151 |
5082 |
12 |
0 |
0 |
T152 |
63603 |
45 |
0 |
0 |
T153 |
7661 |
35 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
823 |
0 |
0 |
T81 |
4072 |
9 |
0 |
0 |
T94 |
5380 |
8 |
0 |
0 |
T97 |
98715 |
49 |
0 |
0 |
T100 |
34655 |
38 |
0 |
0 |
T111 |
5782 |
4 |
0 |
0 |
T116 |
4137 |
1 |
0 |
0 |
T144 |
4792 |
1 |
0 |
0 |
T151 |
5082 |
11 |
0 |
0 |
T152 |
63603 |
62 |
0 |
0 |
T153 |
7661 |
27 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
862 |
0 |
0 |
T81 |
4072 |
7 |
0 |
0 |
T94 |
5380 |
12 |
0 |
0 |
T97 |
98715 |
70 |
0 |
0 |
T100 |
34655 |
23 |
0 |
0 |
T111 |
5782 |
14 |
0 |
0 |
T116 |
4137 |
1 |
0 |
0 |
T144 |
4792 |
4 |
0 |
0 |
T151 |
5082 |
11 |
0 |
0 |
T152 |
63603 |
47 |
0 |
0 |
T153 |
7661 |
12 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1654 |
0 |
0 |
T81 |
4072 |
15 |
0 |
0 |
T94 |
5380 |
7 |
0 |
0 |
T97 |
98715 |
131 |
0 |
0 |
T100 |
34655 |
81 |
0 |
0 |
T111 |
5782 |
16 |
0 |
0 |
T116 |
4137 |
10 |
0 |
0 |
T144 |
4792 |
10 |
0 |
0 |
T151 |
5082 |
20 |
0 |
0 |
T152 |
63603 |
123 |
0 |
0 |
T153 |
7661 |
30 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
935 |
0 |
0 |
T81 |
4072 |
5 |
0 |
0 |
T94 |
5380 |
10 |
0 |
0 |
T97 |
98715 |
78 |
0 |
0 |
T100 |
34655 |
40 |
0 |
0 |
T111 |
5782 |
6 |
0 |
0 |
T116 |
4137 |
9 |
0 |
0 |
T144 |
4792 |
2 |
0 |
0 |
T152 |
63603 |
38 |
0 |
0 |
T153 |
7661 |
20 |
0 |
0 |
T154 |
19270 |
32 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1946 |
0 |
0 |
T81 |
4072 |
2 |
0 |
0 |
T94 |
5380 |
12 |
0 |
0 |
T97 |
98715 |
175 |
0 |
0 |
T100 |
34655 |
94 |
0 |
0 |
T111 |
5782 |
8 |
0 |
0 |
T116 |
4137 |
14 |
0 |
0 |
T144 |
4792 |
19 |
0 |
0 |
T151 |
5082 |
3 |
0 |
0 |
T152 |
63603 |
91 |
0 |
0 |
T153 |
7661 |
18 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
1256 |
0 |
0 |
T81 |
4072 |
8 |
0 |
0 |
T94 |
5380 |
6 |
0 |
0 |
T97 |
98715 |
99 |
0 |
0 |
T100 |
34655 |
66 |
0 |
0 |
T111 |
5782 |
10 |
0 |
0 |
T116 |
4137 |
4 |
0 |
0 |
T144 |
4792 |
9 |
0 |
0 |
T151 |
5082 |
20 |
0 |
0 |
T152 |
63603 |
51 |
0 |
0 |
T153 |
7661 |
30 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
974 |
0 |
0 |
T81 |
4072 |
9 |
0 |
0 |
T94 |
5380 |
14 |
0 |
0 |
T97 |
98715 |
50 |
0 |
0 |
T100 |
34655 |
34 |
0 |
0 |
T110 |
6178 |
10 |
0 |
0 |
T111 |
5782 |
11 |
0 |
0 |
T116 |
4137 |
3 |
0 |
0 |
T144 |
4792 |
7 |
0 |
0 |
T151 |
5082 |
8 |
0 |
0 |
T152 |
63603 |
32 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
942 |
0 |
0 |
T81 |
4072 |
14 |
0 |
0 |
T94 |
5380 |
11 |
0 |
0 |
T97 |
98715 |
43 |
0 |
0 |
T100 |
34655 |
52 |
0 |
0 |
T111 |
5782 |
6 |
0 |
0 |
T116 |
4137 |
8 |
0 |
0 |
T144 |
4792 |
4 |
0 |
0 |
T151 |
5082 |
7 |
0 |
0 |
T152 |
63603 |
43 |
0 |
0 |
T153 |
7661 |
61 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
970 |
0 |
0 |
T94 |
5380 |
2 |
0 |
0 |
T97 |
98715 |
33 |
0 |
0 |
T100 |
34655 |
26 |
0 |
0 |
T111 |
5782 |
13 |
0 |
0 |
T116 |
4137 |
7 |
0 |
0 |
T144 |
4792 |
7 |
0 |
0 |
T151 |
5082 |
17 |
0 |
0 |
T152 |
63603 |
60 |
0 |
0 |
T153 |
7661 |
28 |
0 |
0 |
T154 |
19270 |
48 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
880 |
0 |
0 |
T81 |
4072 |
2 |
0 |
0 |
T94 |
5380 |
4 |
0 |
0 |
T97 |
98715 |
49 |
0 |
0 |
T100 |
34655 |
53 |
0 |
0 |
T116 |
4137 |
7 |
0 |
0 |
T144 |
4792 |
6 |
0 |
0 |
T151 |
5082 |
6 |
0 |
0 |
T152 |
63603 |
44 |
0 |
0 |
T153 |
7661 |
14 |
0 |
0 |
T154 |
19270 |
58 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
913 |
0 |
0 |
T81 |
4072 |
6 |
0 |
0 |
T94 |
5380 |
10 |
0 |
0 |
T97 |
98715 |
38 |
0 |
0 |
T100 |
34655 |
53 |
0 |
0 |
T111 |
5782 |
13 |
0 |
0 |
T116 |
4137 |
1 |
0 |
0 |
T144 |
4792 |
7 |
0 |
0 |
T151 |
5082 |
1 |
0 |
0 |
T152 |
63603 |
43 |
0 |
0 |
T153 |
7661 |
25 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
405156956 |
987 |
0 |
0 |
T94 |
5380 |
3 |
0 |
0 |
T97 |
98715 |
64 |
0 |
0 |
T100 |
34655 |
40 |
0 |
0 |
T111 |
5782 |
8 |
0 |
0 |
T116 |
4137 |
7 |
0 |
0 |
T144 |
4792 |
3 |
0 |
0 |
T152 |
63603 |
53 |
0 |
0 |
T153 |
7661 |
23 |
0 |
0 |
T154 |
19270 |
56 |
0 |
0 |
T165 |
65089 |
34 |
0 |
0 |