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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.94 98.35 94.21 98.61 89.36 97.14 95.81 98.12


Total test records in report: 1101
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T1020 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3176690720 May 09 01:07:25 PM PDT 24 May 09 01:07:28 PM PDT 24 23943555 ps
T1021 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1154465178 May 09 01:06:27 PM PDT 24 May 09 01:06:29 PM PDT 24 14064244 ps
T1022 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2490569580 May 09 01:07:12 PM PDT 24 May 09 01:07:14 PM PDT 24 65743318 ps
T1023 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1499016843 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 48919104 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1715275057 May 09 01:06:29 PM PDT 24 May 09 01:06:35 PM PDT 24 254808341 ps
T107 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.979140855 May 09 01:06:40 PM PDT 24 May 09 01:06:45 PM PDT 24 680991880 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4258572790 May 09 01:06:26 PM PDT 24 May 09 01:06:29 PM PDT 24 60496383 ps
T153 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.123794574 May 09 01:06:49 PM PDT 24 May 09 01:06:52 PM PDT 24 80658537 ps
T1025 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4025445472 May 09 01:06:42 PM PDT 24 May 09 01:06:46 PM PDT 24 239207231 ps
T1026 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1387112124 May 09 01:07:12 PM PDT 24 May 09 01:07:14 PM PDT 24 14528733 ps
T1027 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4063833305 May 09 01:07:12 PM PDT 24 May 09 01:07:15 PM PDT 24 12933287 ps
T1028 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2107830622 May 09 01:06:48 PM PDT 24 May 09 01:06:51 PM PDT 24 82817770 ps
T1029 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.309437769 May 09 01:06:42 PM PDT 24 May 09 01:06:46 PM PDT 24 328342478 ps
T154 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1315923694 May 09 01:06:38 PM PDT 24 May 09 01:06:44 PM PDT 24 1284857266 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2477738396 May 09 01:06:43 PM PDT 24 May 09 01:06:47 PM PDT 24 246595027 ps
T1030 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2745927714 May 09 01:06:41 PM PDT 24 May 09 01:06:43 PM PDT 24 34142624 ps
T1031 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4281329207 May 09 01:06:46 PM PDT 24 May 09 01:06:50 PM PDT 24 30531295 ps
T125 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2924751059 May 09 01:07:12 PM PDT 24 May 09 01:07:16 PM PDT 24 317382873 ps
T1032 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1731394684 May 09 01:06:39 PM PDT 24 May 09 01:06:41 PM PDT 24 41045288 ps
T126 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.912849911 May 09 01:07:01 PM PDT 24 May 09 01:07:04 PM PDT 24 184403811 ps
T164 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4056543260 May 09 01:06:37 PM PDT 24 May 09 01:06:39 PM PDT 24 49971094 ps
T1033 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.472083785 May 09 01:06:30 PM PDT 24 May 09 01:06:34 PM PDT 24 94975493 ps
T1034 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.148871008 May 09 01:07:11 PM PDT 24 May 09 01:07:13 PM PDT 24 28847027 ps
T1035 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3634946223 May 09 01:07:02 PM PDT 24 May 09 01:07:05 PM PDT 24 26571011 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1728646860 May 09 01:06:39 PM PDT 24 May 09 01:06:55 PM PDT 24 215050530 ps
T165 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2979251248 May 09 01:06:41 PM PDT 24 May 09 01:06:57 PM PDT 24 692438425 ps
T1037 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3626801336 May 09 01:07:11 PM PDT 24 May 09 01:07:12 PM PDT 24 25006881 ps
T1038 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.592911678 May 09 01:06:39 PM PDT 24 May 09 01:06:44 PM PDT 24 652476562 ps
T1039 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3290181612 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 25997669 ps
T263 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2298128438 May 09 01:06:45 PM PDT 24 May 09 01:07:02 PM PDT 24 3471968826 ps
T1040 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1678643019 May 09 01:06:41 PM PDT 24 May 09 01:06:44 PM PDT 24 203406397 ps
T1041 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3514105399 May 09 01:06:48 PM PDT 24 May 09 01:06:52 PM PDT 24 992812612 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1625887882 May 09 01:06:46 PM PDT 24 May 09 01:06:49 PM PDT 24 23141704 ps
T128 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3098163328 May 09 01:06:28 PM PDT 24 May 09 01:06:32 PM PDT 24 139765462 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2955391046 May 09 01:06:50 PM PDT 24 May 09 01:06:54 PM PDT 24 138117245 ps
T1044 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2761068176 May 09 01:06:58 PM PDT 24 May 09 01:07:00 PM PDT 24 231798514 ps
T1045 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1530668358 May 09 01:07:25 PM PDT 24 May 09 01:07:29 PM PDT 24 23075511 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2435207840 May 09 01:07:02 PM PDT 24 May 09 01:07:09 PM PDT 24 308400410 ps
T1046 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3617104549 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 74484081 ps
T1047 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1479719145 May 09 01:07:11 PM PDT 24 May 09 01:07:14 PM PDT 24 13995092 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4079458151 May 09 01:06:46 PM PDT 24 May 09 01:06:54 PM PDT 24 105339059 ps
T1049 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2080299822 May 09 01:06:58 PM PDT 24 May 09 01:07:03 PM PDT 24 1717253804 ps
T264 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366847420 May 09 01:06:26 PM PDT 24 May 09 01:06:34 PM PDT 24 427469689 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1193925177 May 09 01:06:17 PM PDT 24 May 09 01:06:22 PM PDT 24 274171086 ps
T129 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3206055355 May 09 01:06:50 PM PDT 24 May 09 01:06:53 PM PDT 24 145473262 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2713220731 May 09 01:06:28 PM PDT 24 May 09 01:06:31 PM PDT 24 79558057 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1512397052 May 09 01:06:44 PM PDT 24 May 09 01:06:46 PM PDT 24 71122327 ps
T262 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.812353948 May 09 01:06:57 PM PDT 24 May 09 01:07:14 PM PDT 24 2411866102 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.751882046 May 09 01:06:28 PM PDT 24 May 09 01:06:30 PM PDT 24 66138170 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.997942554 May 09 01:06:30 PM PDT 24 May 09 01:06:39 PM PDT 24 110584544 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2220003802 May 09 01:06:15 PM PDT 24 May 09 01:06:24 PM PDT 24 915691505 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1757760205 May 09 01:06:46 PM PDT 24 May 09 01:06:52 PM PDT 24 405897419 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1374840069 May 09 01:06:27 PM PDT 24 May 09 01:06:29 PM PDT 24 120429906 ps
T1058 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.539995666 May 09 01:07:00 PM PDT 24 May 09 01:07:03 PM PDT 24 34581977 ps
T261 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2011788083 May 09 01:06:58 PM PDT 24 May 09 01:07:11 PM PDT 24 800466536 ps
T1059 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.694113288 May 09 01:07:02 PM PDT 24 May 09 01:07:07 PM PDT 24 1453501152 ps
T1060 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2287377789 May 09 01:06:45 PM PDT 24 May 09 01:06:49 PM PDT 24 94541317 ps
T1061 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3119068295 May 09 01:06:39 PM PDT 24 May 09 01:06:48 PM PDT 24 1084876055 ps
T1062 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2217283611 May 09 01:07:12 PM PDT 24 May 09 01:07:15 PM PDT 24 16555411 ps
T1063 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.877617496 May 09 01:06:48 PM PDT 24 May 09 01:06:57 PM PDT 24 328601994 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1321320566 May 09 01:06:28 PM PDT 24 May 09 01:06:43 PM PDT 24 379841584 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3472320166 May 09 01:06:16 PM PDT 24 May 09 01:06:18 PM PDT 24 11474055 ps
T1066 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2221606273 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 85143832 ps
T1067 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1119672088 May 09 01:07:03 PM PDT 24 May 09 01:07:07 PM PDT 24 266797623 ps
T1068 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3887087815 May 09 01:06:38 PM PDT 24 May 09 01:06:40 PM PDT 24 47653604 ps
T1069 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2910756715 May 09 01:07:03 PM PDT 24 May 09 01:07:06 PM PDT 24 131509436 ps
T1070 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4202362594 May 09 01:07:06 PM PDT 24 May 09 01:07:08 PM PDT 24 43865704 ps
T1071 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1923361570 May 09 01:06:38 PM PDT 24 May 09 01:06:41 PM PDT 24 244816229 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1538396456 May 09 01:06:32 PM PDT 24 May 09 01:06:35 PM PDT 24 12927784 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.688609498 May 09 01:06:45 PM PDT 24 May 09 01:06:49 PM PDT 24 99717888 ps
T1074 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.256806953 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 14492775 ps
T1075 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2503897373 May 09 01:07:03 PM PDT 24 May 09 01:07:19 PM PDT 24 1789274046 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2327124689 May 09 01:06:58 PM PDT 24 May 09 01:07:02 PM PDT 24 161757194 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3078127288 May 09 01:06:40 PM PDT 24 May 09 01:06:44 PM PDT 24 177770215 ps
T1078 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.332722106 May 09 01:07:14 PM PDT 24 May 09 01:07:17 PM PDT 24 18957841 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4176660079 May 09 01:06:29 PM PDT 24 May 09 01:06:31 PM PDT 24 18611766 ps
T265 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.353584014 May 09 01:06:53 PM PDT 24 May 09 01:07:06 PM PDT 24 407845686 ps
T1080 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1621114204 May 09 01:07:03 PM PDT 24 May 09 01:07:07 PM PDT 24 100543768 ps
T1081 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3347114416 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 20203092 ps
T1082 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1983355452 May 09 01:06:41 PM PDT 24 May 09 01:06:44 PM PDT 24 84815040 ps
T266 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3668749371 May 09 01:06:30 PM PDT 24 May 09 01:06:44 PM PDT 24 305240956 ps
T83 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.423994482 May 09 01:06:16 PM PDT 24 May 09 01:06:18 PM PDT 24 54859897 ps
T1083 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1940568851 May 09 01:07:01 PM PDT 24 May 09 01:07:03 PM PDT 24 36259917 ps
T1084 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2638226662 May 09 01:07:01 PM PDT 24 May 09 01:07:04 PM PDT 24 205898821 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.907141688 May 09 01:06:40 PM PDT 24 May 09 01:06:45 PM PDT 24 58820778 ps
T1086 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2364178665 May 09 01:06:50 PM PDT 24 May 09 01:06:54 PM PDT 24 37582547 ps
T1087 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1091926802 May 09 01:07:10 PM PDT 24 May 09 01:07:12 PM PDT 24 51676790 ps
T1088 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3798600407 May 09 01:06:57 PM PDT 24 May 09 01:07:01 PM PDT 24 467834087 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2223353513 May 09 01:06:39 PM PDT 24 May 09 01:06:41 PM PDT 24 12396052 ps
T1090 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4072809775 May 09 01:07:02 PM PDT 24 May 09 01:07:04 PM PDT 24 29855025 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2690435475 May 09 01:06:16 PM PDT 24 May 09 01:06:34 PM PDT 24 1851742702 ps
T1092 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1861522055 May 09 01:07:01 PM PDT 24 May 09 01:07:24 PM PDT 24 1669663351 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4053160441 May 09 01:07:03 PM PDT 24 May 09 01:07:07 PM PDT 24 81699140 ps
T1094 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1099445004 May 09 01:07:12 PM PDT 24 May 09 01:07:15 PM PDT 24 11562786 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3361645867 May 09 01:06:42 PM PDT 24 May 09 01:06:45 PM PDT 24 54375594 ps
T1096 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4032201073 May 09 01:07:13 PM PDT 24 May 09 01:07:16 PM PDT 24 12142808 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1343984600 May 09 01:06:31 PM PDT 24 May 09 01:06:35 PM PDT 24 73827823 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.10255651 May 09 01:06:39 PM PDT 24 May 09 01:06:44 PM PDT 24 1007672744 ps
T1099 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.507258894 May 09 01:06:49 PM PDT 24 May 09 01:06:54 PM PDT 24 771325005 ps
T1100 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1084055229 May 09 01:06:46 PM PDT 24 May 09 01:06:53 PM PDT 24 884817085 ps
T1101 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4293550509 May 09 01:07:12 PM PDT 24 May 09 01:07:15 PM PDT 24 16581514 ps

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3136192407
Short name T2
Test name
Test status
Simulation time 139831860244 ps
CPU time 310.98 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:16:24 PM PDT 24
Peak memory 241440 kb
Host smart-13660919-b4c0-4b31-853c-ef4a7b8da5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136192407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3136192407
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3642447412
Short name T13
Test name
Test status
Simulation time 3755792475 ps
CPU time 90.84 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:13:10 PM PDT 24
Peak memory 264980 kb
Host smart-ea3c623f-ec7c-49c1-9b43-618a568ce5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642447412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3642447412
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3772745305
Short name T62
Test name
Test status
Simulation time 175293742689 ps
CPU time 177.64 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:11:46 PM PDT 24
Peak memory 252324 kb
Host smart-b3ab541c-6424-42ad-848c-aac47dbc1933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772745305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3772745305
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2452495262
Short name T97
Test name
Test status
Simulation time 997136841 ps
CPU time 19.92 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:22 PM PDT 24
Peak memory 215836 kb
Host smart-0daddd48-1f13-4219-b561-7a930ea1ca0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452495262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2452495262
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2182582646
Short name T23
Test name
Test status
Simulation time 711912851168 ps
CPU time 1759.76 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:39:16 PM PDT 24
Peak memory 316376 kb
Host smart-84a0e682-bcbe-4642-8c6c-b22a83271765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182582646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2182582646
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2930016034
Short name T41
Test name
Test status
Simulation time 73619934872 ps
CPU time 159.62 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:13:21 PM PDT 24
Peak memory 254432 kb
Host smart-d66358c5-cbe3-444f-b205-8fec11d48a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930016034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2930016034
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1391669810
Short name T63
Test name
Test status
Simulation time 16311232 ps
CPU time 0.73 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:05 PM PDT 24
Peak memory 216216 kb
Host smart-f878b2b0-fadc-4f3b-b475-419f1711e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391669810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1391669810
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1725075107
Short name T185
Test name
Test status
Simulation time 84073231177 ps
CPU time 645.33 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:20:22 PM PDT 24
Peak memory 265816 kb
Host smart-dea0159c-b0a8-459f-92ac-46149307c923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725075107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1725075107
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1034018760
Short name T32
Test name
Test status
Simulation time 35061215512 ps
CPU time 252.22 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:15:50 PM PDT 24
Peak memory 262056 kb
Host smart-a3d408fe-e7ab-486a-bdb4-6a68fdc103ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034018760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1034018760
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.118022229
Short name T59
Test name
Test status
Simulation time 17147652786 ps
CPU time 209.84 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 254536 kb
Host smart-e9f20161-769d-4710-bba9-afa441660011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118022229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.118022229
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3919688538
Short name T11
Test name
Test status
Simulation time 336154813 ps
CPU time 10.7 seconds
Started May 09 01:08:21 PM PDT 24
Finished May 09 01:08:33 PM PDT 24
Peak memory 233352 kb
Host smart-b18b2956-d6e7-4a8e-95ec-af7f292896eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919688538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3919688538
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1336692649
Short name T79
Test name
Test status
Simulation time 30099949319 ps
CPU time 218.4 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:15:05 PM PDT 24
Peak memory 273336 kb
Host smart-e03afb60-657f-4cb8-9b91-f386bf91b17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336692649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1336692649
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2633031136
Short name T102
Test name
Test status
Simulation time 685704122 ps
CPU time 4.59 seconds
Started May 09 01:06:49 PM PDT 24
Finished May 09 01:06:55 PM PDT 24
Peak memory 215964 kb
Host smart-098dc82e-3805-4d10-a469-e9e48c15df94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633031136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2633031136
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3601029567
Short name T64
Test name
Test status
Simulation time 78610523 ps
CPU time 1.09 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:14 PM PDT 24
Peak memory 235112 kb
Host smart-8e053cea-fcab-4f59-96ca-12b88fb30eaf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601029567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3601029567
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2589310740
Short name T43
Test name
Test status
Simulation time 183213338205 ps
CPU time 863.51 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:23:25 PM PDT 24
Peak memory 253812 kb
Host smart-27714f62-61f9-4639-877e-f3404a37acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589310740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2589310740
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4117715276
Short name T118
Test name
Test status
Simulation time 233936932 ps
CPU time 1.81 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:34 PM PDT 24
Peak memory 215772 kb
Host smart-99b8c51a-403a-475f-b42c-c2481756a114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117715276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
117715276
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1907142839
Short name T180
Test name
Test status
Simulation time 247861720005 ps
CPU time 455.24 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:19:04 PM PDT 24
Peak memory 251052 kb
Host smart-df591d91-345d-4ad3-bb86-f23181e79b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907142839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1907142839
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.619177865
Short name T61
Test name
Test status
Simulation time 6053794281 ps
CPU time 66.82 seconds
Started May 09 01:08:55 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 253360 kb
Host smart-0ac0557e-db29-4287-90d0-577db770b64b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619177865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.619177865
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1007700520
Short name T10
Test name
Test status
Simulation time 10100132301 ps
CPU time 64.44 seconds
Started May 09 01:08:39 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 254836 kb
Host smart-3a009c93-1cae-4fab-b907-2abf79efdedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007700520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1007700520
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1212370031
Short name T420
Test name
Test status
Simulation time 43278651 ps
CPU time 1.09 seconds
Started May 09 01:08:00 PM PDT 24
Finished May 09 01:08:03 PM PDT 24
Peak memory 216684 kb
Host smart-111d5731-6f05-4e00-8738-1f2186afabc5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212370031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1212370031
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1527764
Short name T27
Test name
Test status
Simulation time 9595164839 ps
CPU time 44.83 seconds
Started May 09 01:10:00 PM PDT 24
Finished May 09 01:10:46 PM PDT 24
Peak memory 252692 kb
Host smart-b656f26c-5e52-4a37-92ce-d29a867f1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.1527764
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2294828128
Short name T130
Test name
Test status
Simulation time 364325065546 ps
CPU time 910.09 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:24:09 PM PDT 24
Peak memory 270456 kb
Host smart-d98a6f61-436e-4315-89a4-c4e6b345560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294828128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2294828128
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2253287299
Short name T177
Test name
Test status
Simulation time 14484747458 ps
CPU time 143.42 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:11:47 PM PDT 24
Peak memory 257580 kb
Host smart-02d77188-78c1-4b4d-8fcf-da867e46f32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253287299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2253287299
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2141238383
Short name T30
Test name
Test status
Simulation time 62694037976 ps
CPU time 439.59 seconds
Started May 09 01:09:05 PM PDT 24
Finished May 09 01:16:25 PM PDT 24
Peak memory 250292 kb
Host smart-2c6d848d-df3f-4e8c-9c4a-d69c3159a676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141238383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2141238383
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1339272530
Short name T21
Test name
Test status
Simulation time 460973259688 ps
CPU time 364.61 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:17:17 PM PDT 24
Peak memory 253420 kb
Host smart-f31e7310-6944-472a-9491-bcd33457ae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339272530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1339272530
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.462693912
Short name T362
Test name
Test status
Simulation time 30604542 ps
CPU time 0.8 seconds
Started May 09 01:09:26 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 204772 kb
Host smart-8379e5c2-33e3-4df9-b8f6-07eede6167a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462693912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.462693912
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.306905188
Short name T140
Test name
Test status
Simulation time 44158931404 ps
CPU time 172.11 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:14:20 PM PDT 24
Peak memory 264256 kb
Host smart-d0968585-edcc-415f-b9a3-deb9af3da59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306905188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.306905188
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2654228714
Short name T241
Test name
Test status
Simulation time 4184114820 ps
CPU time 38.19 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:51 PM PDT 24
Peak memory 249408 kb
Host smart-1361736d-11b1-431e-b3e2-5820a6957a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654228714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2654228714
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3141557197
Short name T235
Test name
Test status
Simulation time 18771825724 ps
CPU time 174.68 seconds
Started May 09 01:10:53 PM PDT 24
Finished May 09 01:13:49 PM PDT 24
Peak memory 257400 kb
Host smart-3a33d820-1738-40e9-888b-6da1beb96056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141557197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3141557197
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3317239832
Short name T105
Test name
Test status
Simulation time 230205368 ps
CPU time 6.67 seconds
Started May 09 01:06:44 PM PDT 24
Finished May 09 01:06:52 PM PDT 24
Peak memory 215984 kb
Host smart-c1290af7-f2a1-4e30-982a-32d305f561fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317239832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
317239832
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3730346421
Short name T152
Test name
Test status
Simulation time 2544180128 ps
CPU time 15.41 seconds
Started May 09 01:06:43 PM PDT 24
Finished May 09 01:06:59 PM PDT 24
Peak memory 216412 kb
Host smart-c7209dda-48ad-4aa1-8c0e-1d6a8c6653b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730346421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3730346421
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1832850991
Short name T157
Test name
Test status
Simulation time 6661813512 ps
CPU time 22.22 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:49 PM PDT 24
Peak memory 224776 kb
Host smart-bfe193ed-f106-47ef-bc5c-e0177b2851cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832850991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1832850991
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.461891864
Short name T213
Test name
Test status
Simulation time 11608055504 ps
CPU time 42.95 seconds
Started May 09 01:10:03 PM PDT 24
Finished May 09 01:10:47 PM PDT 24
Peak memory 233728 kb
Host smart-211a4588-7136-46f7-8ee6-868f5d7d46b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461891864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.461891864
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1656678232
Short name T732
Test name
Test status
Simulation time 10492293959 ps
CPU time 36.63 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 241000 kb
Host smart-88bd8ec4-b779-4f90-b5dd-5d6062400393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656678232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1656678232
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1035995021
Short name T90
Test name
Test status
Simulation time 2599980657 ps
CPU time 7.64 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 218764 kb
Host smart-78d75c4d-6417-4ba3-9bbb-b10654af0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035995021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1035995021
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.728660361
Short name T175
Test name
Test status
Simulation time 54762659221 ps
CPU time 300.01 seconds
Started May 09 01:08:51 PM PDT 24
Finished May 09 01:13:52 PM PDT 24
Peak memory 271476 kb
Host smart-5ba403b6-1a88-4d85-a86e-91ec88b9efb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728660361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.728660361
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.104354425
Short name T231
Test name
Test status
Simulation time 117251660036 ps
CPU time 390.74 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:17:00 PM PDT 24
Peak memory 254896 kb
Host smart-2c4bd609-a965-4888-822c-d513b2a012bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104354425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.104354425
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.537319426
Short name T219
Test name
Test status
Simulation time 24871666806 ps
CPU time 174.98 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:14:23 PM PDT 24
Peak memory 270560 kb
Host smart-438043ac-df8f-4cce-a606-cbbc4cd35130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537319426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.537319426
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4281802941
Short name T308
Test name
Test status
Simulation time 114779596 ps
CPU time 5.32 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:43 PM PDT 24
Peak memory 232664 kb
Host smart-11211259-a585-4b96-b811-4632fac11004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281802941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4281802941
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.681661554
Short name T99
Test name
Test status
Simulation time 1173417084 ps
CPU time 18.1 seconds
Started May 09 01:06:50 PM PDT 24
Finished May 09 01:07:10 PM PDT 24
Peak memory 223892 kb
Host smart-f2ccc93b-6a73-49f3-98f3-0065452e4369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681661554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.681661554
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.812353948
Short name T262
Test name
Test status
Simulation time 2411866102 ps
CPU time 15.89 seconds
Started May 09 01:06:57 PM PDT 24
Finished May 09 01:07:14 PM PDT 24
Peak memory 215972 kb
Host smart-c9dc9365-e905-4264-a103-82fc79611481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812353948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.812353948
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.46671655
Short name T31
Test name
Test status
Simulation time 50188780000 ps
CPU time 234.98 seconds
Started May 09 01:09:04 PM PDT 24
Finished May 09 01:13:00 PM PDT 24
Peak memory 257552 kb
Host smart-34902758-5520-4dc1-bdf6-b1288ebe786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46671655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.46671655
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2892399340
Short name T239
Test name
Test status
Simulation time 2494422261 ps
CPU time 56.71 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 254472 kb
Host smart-c2a299cc-43a9-4f78-8801-9e2b04a4f38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892399340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2892399340
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3345668930
Short name T226
Test name
Test status
Simulation time 5435128022 ps
CPU time 15.33 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:55 PM PDT 24
Peak memory 218052 kb
Host smart-b462e9b3-588a-4929-a82c-8f275d80712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345668930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3345668930
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2270698337
Short name T202
Test name
Test status
Simulation time 230654843726 ps
CPU time 336.96 seconds
Started May 09 01:08:18 PM PDT 24
Finished May 09 01:13:56 PM PDT 24
Peak memory 264992 kb
Host smart-63575ba3-59e4-44b8-a7b9-85b9f469bc8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270698337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2270698337
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.401840971
Short name T192
Test name
Test status
Simulation time 26195856919 ps
CPU time 199.15 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:13:49 PM PDT 24
Peak memory 265108 kb
Host smart-69886175-a569-4312-970e-492db7e2e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401840971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.401840971
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.22729270
Short name T161
Test name
Test status
Simulation time 166674482214 ps
CPU time 289.75 seconds
Started May 09 01:10:43 PM PDT 24
Finished May 09 01:15:35 PM PDT 24
Peak memory 253452 kb
Host smart-e6ed22c7-47da-435f-a727-a1f7d13b3d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress
_all.22729270
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3600328026
Short name T93
Test name
Test status
Simulation time 667209508 ps
CPU time 6.98 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:18 PM PDT 24
Peak memory 237336 kb
Host smart-6f644547-f1c5-4aec-a9a8-c982818a6e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600328026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3600328026
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3332287547
Short name T82
Test name
Test status
Simulation time 20808055 ps
CPU time 1.18 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 216680 kb
Host smart-4deb57dd-7e24-40b3-80f4-316224bbdd0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332287547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3332287547
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3753454375
Short name T95
Test name
Test status
Simulation time 114648994 ps
CPU time 3.79 seconds
Started May 09 01:06:36 PM PDT 24
Finished May 09 01:06:40 PM PDT 24
Peak memory 217744 kb
Host smart-04c7d49c-4753-4394-b42b-97f535bdfe35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753454375 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3753454375
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2220003802
Short name T1055
Test name
Test status
Simulation time 915691505 ps
CPU time 7.8 seconds
Started May 09 01:06:15 PM PDT 24
Finished May 09 01:06:24 PM PDT 24
Peak memory 207556 kb
Host smart-362939a7-9215-44c2-96c8-3b5fe2ba8227
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220003802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2220003802
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2690435475
Short name T1091
Test name
Test status
Simulation time 1851742702 ps
CPU time 15.47 seconds
Started May 09 01:06:16 PM PDT 24
Finished May 09 01:06:34 PM PDT 24
Peak memory 207608 kb
Host smart-e5d7a08c-e866-4ec4-8cd3-532c6d896619
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690435475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2690435475
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.423994482
Short name T83
Test name
Test status
Simulation time 54859897 ps
CPU time 1.01 seconds
Started May 09 01:06:16 PM PDT 24
Finished May 09 01:06:18 PM PDT 24
Peak memory 207324 kb
Host smart-906b7cac-7949-4410-b733-a4eaae48e3c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423994482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.423994482
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2977574714
Short name T151
Test name
Test status
Simulation time 188253085 ps
CPU time 1.77 seconds
Started May 09 01:06:27 PM PDT 24
Finished May 09 01:06:30 PM PDT 24
Peak memory 215736 kb
Host smart-c1c10652-5a7b-4c27-82eb-6d4dfb48dd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977574714 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2977574714
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.525406991
Short name T120
Test name
Test status
Simulation time 103748361 ps
CPU time 2.75 seconds
Started May 09 01:06:15 PM PDT 24
Finished May 09 01:06:18 PM PDT 24
Peak memory 215772 kb
Host smart-1ff9a78f-7cd0-4938-a031-d9ab90f96bff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525406991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.525406991
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.751642719
Short name T994
Test name
Test status
Simulation time 16647277 ps
CPU time 0.76 seconds
Started May 09 01:06:16 PM PDT 24
Finished May 09 01:06:18 PM PDT 24
Peak memory 203936 kb
Host smart-69671142-d0fc-41c7-a85e-ff78af08e399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751642719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.751642719
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4283934532
Short name T123
Test name
Test status
Simulation time 81947723 ps
CPU time 1.66 seconds
Started May 09 01:06:17 PM PDT 24
Finished May 09 01:06:21 PM PDT 24
Peak memory 215760 kb
Host smart-a57beb70-8e8b-4b08-9370-f564394fb903
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283934532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4283934532
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3472320166
Short name T1065
Test name
Test status
Simulation time 11474055 ps
CPU time 0.69 seconds
Started May 09 01:06:16 PM PDT 24
Finished May 09 01:06:18 PM PDT 24
Peak memory 203924 kb
Host smart-8ea5e8e3-883b-4ef9-80bc-891f77a99045
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472320166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3472320166
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1810301502
Short name T1015
Test name
Test status
Simulation time 44296720 ps
CPU time 1.77 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:31 PM PDT 24
Peak memory 215728 kb
Host smart-0b4d1d78-97d5-4827-9d10-f9f16bf62a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810301502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1810301502
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1193925177
Short name T1050
Test name
Test status
Simulation time 274171086 ps
CPU time 2.25 seconds
Started May 09 01:06:17 PM PDT 24
Finished May 09 01:06:22 PM PDT 24
Peak memory 215916 kb
Host smart-0b4de244-8db9-4110-8bd3-445d506e497a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193925177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
193925177
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1347375451
Short name T259
Test name
Test status
Simulation time 952583600 ps
CPU time 12.38 seconds
Started May 09 01:06:18 PM PDT 24
Finished May 09 01:06:32 PM PDT 24
Peak memory 215844 kb
Host smart-95c562f6-2747-4097-bb59-b21a13c26b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347375451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1347375451
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3428169061
Short name T1012
Test name
Test status
Simulation time 220832305 ps
CPU time 7.09 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:36 PM PDT 24
Peak memory 207516 kb
Host smart-6df67680-39a7-421b-a4c2-1db9e48eafa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428169061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3428169061
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2969967821
Short name T117
Test name
Test status
Simulation time 543913274 ps
CPU time 33.08 seconds
Started May 09 01:06:27 PM PDT 24
Finished May 09 01:07:02 PM PDT 24
Peak memory 207520 kb
Host smart-1c6a35cc-38f9-43d7-ba44-2a34b0fd6a09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969967821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2969967821
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4258572790
Short name T124
Test name
Test status
Simulation time 60496383 ps
CPU time 1.95 seconds
Started May 09 01:06:26 PM PDT 24
Finished May 09 01:06:29 PM PDT 24
Peak memory 215756 kb
Host smart-a7ee1f45-4c92-4592-a8f6-273abbe2de91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258572790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
258572790
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.751882046
Short name T1053
Test name
Test status
Simulation time 66138170 ps
CPU time 0.74 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:30 PM PDT 24
Peak memory 203996 kb
Host smart-8981fb49-98a6-42ca-8341-508176fe2775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751882046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.751882046
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.909951373
Short name T121
Test name
Test status
Simulation time 35474902 ps
CPU time 1.3 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 215668 kb
Host smart-394407de-e0dd-417a-8604-7f4f265b99ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909951373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.909951373
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4176660079
Short name T1079
Test name
Test status
Simulation time 18611766 ps
CPU time 0.67 seconds
Started May 09 01:06:29 PM PDT 24
Finished May 09 01:06:31 PM PDT 24
Peak memory 203948 kb
Host smart-b4e84287-69a4-48ff-93be-eb7d647e6768
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176660079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4176660079
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2713220731
Short name T1051
Test name
Test status
Simulation time 79558057 ps
CPU time 1.96 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:31 PM PDT 24
Peak memory 215772 kb
Host smart-4cb84a18-6257-4575-99b0-3f5a993f4e38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713220731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2713220731
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.873772684
Short name T109
Test name
Test status
Simulation time 264338065 ps
CPU time 4.86 seconds
Started May 09 01:06:32 PM PDT 24
Finished May 09 01:06:39 PM PDT 24
Peak memory 215772 kb
Host smart-8b120f21-7c12-40ad-b21a-4d71ff8ec565
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873772684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.873772684
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.997942554
Short name T1054
Test name
Test status
Simulation time 110584544 ps
CPU time 6.56 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:39 PM PDT 24
Peak memory 216180 kb
Host smart-be168d28-ca6b-490d-bc22-7e9fd6eac460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997942554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.997942554
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.128042636
Short name T112
Test name
Test status
Simulation time 55434993 ps
CPU time 2.07 seconds
Started May 09 01:06:45 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 216880 kb
Host smart-3da47f7f-2478-403a-9e52-8f897a9f45f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128042636 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.128042636
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3078127288
Short name T1077
Test name
Test status
Simulation time 177770215 ps
CPU time 2.38 seconds
Started May 09 01:06:40 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 215828 kb
Host smart-479b7c2c-3f9e-4cb9-a65f-2f343db55430
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078127288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3078127288
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.22543090
Short name T991
Test name
Test status
Simulation time 56099822 ps
CPU time 0.73 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 203956 kb
Host smart-28a0a327-7fe1-4923-bc52-723334840575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22543090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.22543090
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2287377789
Short name T1060
Test name
Test status
Simulation time 94541317 ps
CPU time 1.84 seconds
Started May 09 01:06:45 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 207592 kb
Host smart-a43dc4ae-1487-4ce0-a6e7-d37b31362c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287377789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2287377789
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.979140855
Short name T107
Test name
Test status
Simulation time 680991880 ps
CPU time 4.1 seconds
Started May 09 01:06:40 PM PDT 24
Finished May 09 01:06:45 PM PDT 24
Peak memory 216832 kb
Host smart-6f967d32-9981-4b44-96f1-a5be755b96d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979140855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.979140855
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2298128438
Short name T263
Test name
Test status
Simulation time 3471968826 ps
CPU time 14.73 seconds
Started May 09 01:06:45 PM PDT 24
Finished May 09 01:07:02 PM PDT 24
Peak memory 216044 kb
Host smart-19d99236-ca07-40cd-99c2-b68e644ee610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298128438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2298128438
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.688609498
Short name T1073
Test name
Test status
Simulation time 99717888 ps
CPU time 1.92 seconds
Started May 09 01:06:45 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 215820 kb
Host smart-74c4e354-de84-414e-a22c-79e4ed7ed1aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688609498 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.688609498
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3361645867
Short name T1095
Test name
Test status
Simulation time 54375594 ps
CPU time 1.28 seconds
Started May 09 01:06:42 PM PDT 24
Finished May 09 01:06:45 PM PDT 24
Peak memory 215744 kb
Host smart-6dd72c6f-746c-4c1c-8681-f0997136afc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361645867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3361645867
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2745927714
Short name T1030
Test name
Test status
Simulation time 34142624 ps
CPU time 0.76 seconds
Started May 09 01:06:41 PM PDT 24
Finished May 09 01:06:43 PM PDT 24
Peak memory 204012 kb
Host smart-488e29a2-964a-47b0-82a9-544d3099dec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745927714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2745927714
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.907141688
Short name T1085
Test name
Test status
Simulation time 58820778 ps
CPU time 3.8 seconds
Started May 09 01:06:40 PM PDT 24
Finished May 09 01:06:45 PM PDT 24
Peak memory 215800 kb
Host smart-dd5aeb93-9ee5-44c1-8e57-20fa7c2bdea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907141688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.907141688
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.488949709
Short name T110
Test name
Test status
Simulation time 128720370 ps
CPU time 1.82 seconds
Started May 09 01:06:41 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 215920 kb
Host smart-d7a72659-0d08-4b8f-8a27-0476757c8936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488949709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.488949709
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4245976558
Short name T100
Test name
Test status
Simulation time 361031529 ps
CPU time 8.19 seconds
Started May 09 01:06:43 PM PDT 24
Finished May 09 01:06:52 PM PDT 24
Peak memory 216196 kb
Host smart-c2729b13-3a20-4498-af79-16fb15682509
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245976558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4245976558
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3798600407
Short name T1088
Test name
Test status
Simulation time 467834087 ps
CPU time 2.65 seconds
Started May 09 01:06:57 PM PDT 24
Finished May 09 01:07:01 PM PDT 24
Peak memory 216976 kb
Host smart-4342e1b8-acb5-47cb-a939-ff62508bd80f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798600407 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3798600407
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2364178665
Short name T1086
Test name
Test status
Simulation time 37582547 ps
CPU time 2.34 seconds
Started May 09 01:06:50 PM PDT 24
Finished May 09 01:06:54 PM PDT 24
Peak memory 207752 kb
Host smart-e903688e-d868-4c6a-b464-245ea77e6e08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364178665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2364178665
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2107830622
Short name T1028
Test name
Test status
Simulation time 82817770 ps
CPU time 0.78 seconds
Started May 09 01:06:48 PM PDT 24
Finished May 09 01:06:51 PM PDT 24
Peak memory 203984 kb
Host smart-5f309f9a-f26b-4004-824c-1176e6682f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107830622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2107830622
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3514105399
Short name T1041
Test name
Test status
Simulation time 992812612 ps
CPU time 2.97 seconds
Started May 09 01:06:48 PM PDT 24
Finished May 09 01:06:52 PM PDT 24
Peak memory 215780 kb
Host smart-21bf2d31-4578-41bb-8f9e-bcd6b07d5f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514105399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3514105399
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1527251584
Short name T1006
Test name
Test status
Simulation time 3568089639 ps
CPU time 5.08 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:52 PM PDT 24
Peak memory 215960 kb
Host smart-8dbf1426-bbac-4d99-839b-e25b75a2ccf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527251584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1527251584
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1813087181
Short name T111
Test name
Test status
Simulation time 57847119 ps
CPU time 1.74 seconds
Started May 09 01:06:50 PM PDT 24
Finished May 09 01:06:53 PM PDT 24
Peak memory 215740 kb
Host smart-d9b25d51-7497-4e4d-a679-4ff178706562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813087181 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1813087181
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3206055355
Short name T129
Test name
Test status
Simulation time 145473262 ps
CPU time 2.19 seconds
Started May 09 01:06:50 PM PDT 24
Finished May 09 01:06:53 PM PDT 24
Peak memory 207472 kb
Host smart-2774caef-5c7d-4e48-8b29-32bc008796f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206055355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3206055355
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3152733451
Short name T1002
Test name
Test status
Simulation time 51566989 ps
CPU time 0.69 seconds
Started May 09 01:06:52 PM PDT 24
Finished May 09 01:06:54 PM PDT 24
Peak memory 204280 kb
Host smart-8a0169a3-3d97-477e-935d-85de06875495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152733451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3152733451
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.123794574
Short name T153
Test name
Test status
Simulation time 80658537 ps
CPU time 1.98 seconds
Started May 09 01:06:49 PM PDT 24
Finished May 09 01:06:52 PM PDT 24
Peak memory 215768 kb
Host smart-309d6538-9e29-41bd-aa9d-75340f129ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123794574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.123794574
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.877617496
Short name T1063
Test name
Test status
Simulation time 328601994 ps
CPU time 7.76 seconds
Started May 09 01:06:48 PM PDT 24
Finished May 09 01:06:57 PM PDT 24
Peak memory 215800 kb
Host smart-8fbd7009-25b8-4e63-9d3b-f276926a26b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877617496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.877617496
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2080299822
Short name T1049
Test name
Test status
Simulation time 1717253804 ps
CPU time 3.71 seconds
Started May 09 01:06:58 PM PDT 24
Finished May 09 01:07:03 PM PDT 24
Peak memory 217512 kb
Host smart-971c908d-90ae-4550-9b51-0fdf7b8c8b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080299822 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2080299822
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2955391046
Short name T1043
Test name
Test status
Simulation time 138117245 ps
CPU time 2.57 seconds
Started May 09 01:06:50 PM PDT 24
Finished May 09 01:06:54 PM PDT 24
Peak memory 215768 kb
Host smart-4f5fa0a1-7344-4b3d-a03f-28a1595740d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955391046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2955391046
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.895704967
Short name T1010
Test name
Test status
Simulation time 49073793 ps
CPU time 0.71 seconds
Started May 09 01:06:50 PM PDT 24
Finished May 09 01:06:51 PM PDT 24
Peak memory 204240 kb
Host smart-0ec9f9c0-3437-404a-9d15-7e4735452cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895704967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.895704967
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2327124689
Short name T1076
Test name
Test status
Simulation time 161757194 ps
CPU time 2.67 seconds
Started May 09 01:06:58 PM PDT 24
Finished May 09 01:07:02 PM PDT 24
Peak memory 215800 kb
Host smart-ea4f1298-d083-417d-a7a1-2f344c173e9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327124689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2327124689
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.507258894
Short name T1099
Test name
Test status
Simulation time 771325005 ps
CPU time 3.62 seconds
Started May 09 01:06:49 PM PDT 24
Finished May 09 01:06:54 PM PDT 24
Peak memory 216848 kb
Host smart-3b27d836-c101-42a2-9eef-28a3ed1af57c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507258894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.507258894
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2011788083
Short name T261
Test name
Test status
Simulation time 800466536 ps
CPU time 12.14 seconds
Started May 09 01:06:58 PM PDT 24
Finished May 09 01:07:11 PM PDT 24
Peak memory 215676 kb
Host smart-4963450e-b7ec-4afa-bb2d-d7c3fb7f2b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011788083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2011788083
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3634946223
Short name T1035
Test name
Test status
Simulation time 26571011 ps
CPU time 1.8 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:05 PM PDT 24
Peak memory 215792 kb
Host smart-6d17c920-5736-4a8d-a7bf-f846d9f330cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634946223 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3634946223
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4202362594
Short name T1070
Test name
Test status
Simulation time 43865704 ps
CPU time 1.52 seconds
Started May 09 01:07:06 PM PDT 24
Finished May 09 01:07:08 PM PDT 24
Peak memory 207512 kb
Host smart-6e102e24-2d74-4e1e-9099-1571d5d5c67a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202362594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4202362594
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3236234028
Short name T986
Test name
Test status
Simulation time 18499419 ps
CPU time 0.71 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:04 PM PDT 24
Peak memory 203840 kb
Host smart-86a31192-2ab2-4734-a395-32a0c903c4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236234028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3236234028
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.694113288
Short name T1059
Test name
Test status
Simulation time 1453501152 ps
CPU time 3.09 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:07 PM PDT 24
Peak memory 215804 kb
Host smart-4511c19f-9445-4f57-9a15-642cf376162e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694113288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.694113288
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2761068176
Short name T1044
Test name
Test status
Simulation time 231798514 ps
CPU time 1.55 seconds
Started May 09 01:06:58 PM PDT 24
Finished May 09 01:07:00 PM PDT 24
Peak memory 215308 kb
Host smart-420deec7-99f3-4a7d-becd-8b5338d0cbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761068176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2761068176
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.587938023
Short name T113
Test name
Test status
Simulation time 104796620 ps
CPU time 1.8 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:06 PM PDT 24
Peak memory 215968 kb
Host smart-c9fba744-e29f-4b3e-9975-ea08ffb89830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587938023 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.587938023
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.268198767
Short name T116
Test name
Test status
Simulation time 43128053 ps
CPU time 1.23 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:06 PM PDT 24
Peak memory 207440 kb
Host smart-91ad122d-9db9-43d4-9489-697fdac57caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268198767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.268198767
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4255380105
Short name T987
Test name
Test status
Simulation time 29200816 ps
CPU time 0.77 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:03 PM PDT 24
Peak memory 204264 kb
Host smart-ae56c95a-cf3b-4c5e-99e9-e46c53a30c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255380105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4255380105
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3878318999
Short name T145
Test name
Test status
Simulation time 179827017 ps
CPU time 2.91 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:05 PM PDT 24
Peak memory 215772 kb
Host smart-dddc6bdd-98f4-4160-9091-222d96ec19a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878318999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3878318999
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1119672088
Short name T1067
Test name
Test status
Simulation time 266797623 ps
CPU time 2.82 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:07 PM PDT 24
Peak memory 215996 kb
Host smart-3f7ec5d7-3ec1-4b87-ba77-d192f521f55d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119672088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1119672088
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1861522055
Short name T1092
Test name
Test status
Simulation time 1669663351 ps
CPU time 21.87 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:24 PM PDT 24
Peak memory 215668 kb
Host smart-6e6712cf-d3a9-40b6-a65a-8fce649640da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861522055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1861522055
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2638226662
Short name T1084
Test name
Test status
Simulation time 205898821 ps
CPU time 1.68 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:04 PM PDT 24
Peak memory 215748 kb
Host smart-aaabcf6c-486b-4eaa-988b-63f950574e94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638226662 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2638226662
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.912849911
Short name T126
Test name
Test status
Simulation time 184403811 ps
CPU time 1.9 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:04 PM PDT 24
Peak memory 215664 kb
Host smart-d242e23d-2151-4a79-a055-1fd29a5ee0de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912849911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.912849911
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.561928071
Short name T997
Test name
Test status
Simulation time 42903911 ps
CPU time 0.73 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:05 PM PDT 24
Peak memory 204244 kb
Host smart-36822806-c84a-493e-92a3-103d2c1be7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561928071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.561928071
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1621114204
Short name T1080
Test name
Test status
Simulation time 100543768 ps
CPU time 2.86 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:07 PM PDT 24
Peak memory 215832 kb
Host smart-5a32050e-700c-4160-bae5-62726e011bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621114204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1621114204
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2435207840
Short name T108
Test name
Test status
Simulation time 308400410 ps
CPU time 6.21 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:09 PM PDT 24
Peak memory 215912 kb
Host smart-9e3d2aa0-763d-4097-af41-dd03e7fe6201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435207840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2435207840
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2503897373
Short name T1075
Test name
Test status
Simulation time 1789274046 ps
CPU time 14.65 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:19 PM PDT 24
Peak memory 215784 kb
Host smart-8ccb55a6-a7c1-4ad1-9138-12930b4102fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503897373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2503897373
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2786216782
Short name T96
Test name
Test status
Simulation time 86303785 ps
CPU time 1.78 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:05 PM PDT 24
Peak memory 215736 kb
Host smart-7fe6fc94-ae8d-4967-964b-05b1f9d094e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786216782 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2786216782
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2910756715
Short name T1069
Test name
Test status
Simulation time 131509436 ps
CPU time 1.53 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:06 PM PDT 24
Peak memory 215744 kb
Host smart-3ffd203d-860f-43e2-a66d-0c15309c3c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910756715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2910756715
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4072809775
Short name T1090
Test name
Test status
Simulation time 29855025 ps
CPU time 0.76 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:04 PM PDT 24
Peak memory 203924 kb
Host smart-35023989-0d87-42b1-9b74-2e5c7cf66381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072809775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4072809775
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4053160441
Short name T1093
Test name
Test status
Simulation time 81699140 ps
CPU time 2.86 seconds
Started May 09 01:07:03 PM PDT 24
Finished May 09 01:07:07 PM PDT 24
Peak memory 215992 kb
Host smart-1b32670e-7e38-4558-b2ba-b29ffe41bb4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053160441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4053160441
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1888810310
Short name T98
Test name
Test status
Simulation time 224522816 ps
CPU time 1.88 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:05 PM PDT 24
Peak memory 216888 kb
Host smart-781552b5-8112-431e-b6a1-dd4013f8582c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888810310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1888810310
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.930585387
Short name T1004
Test name
Test status
Simulation time 2167964288 ps
CPU time 15.95 seconds
Started May 09 01:07:02 PM PDT 24
Finished May 09 01:07:20 PM PDT 24
Peak memory 215920 kb
Host smart-8aa9da92-9b6a-45a8-8f57-be729ca37789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930585387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.930585387
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2942776808
Short name T1005
Test name
Test status
Simulation time 155398910 ps
CPU time 3.11 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:18 PM PDT 24
Peak memory 217380 kb
Host smart-3d4bc420-dc2b-4687-8fec-afcdf3371bc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942776808 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2942776808
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2924751059
Short name T125
Test name
Test status
Simulation time 317382873 ps
CPU time 1.44 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 215864 kb
Host smart-0f6de84e-6a3e-40db-b7c3-234441b62c01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924751059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2924751059
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1940568851
Short name T1083
Test name
Test status
Simulation time 36259917 ps
CPU time 0.76 seconds
Started May 09 01:07:01 PM PDT 24
Finished May 09 01:07:03 PM PDT 24
Peak memory 204280 kb
Host smart-d9e6624e-d4e6-4707-9ed5-1e328b397f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940568851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1940568851
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2198045042
Short name T142
Test name
Test status
Simulation time 81239834 ps
CPU time 1.72 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 207820 kb
Host smart-94f2b2bb-3f75-42f4-bd0c-4aee0144c381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198045042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2198045042
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.539995666
Short name T1058
Test name
Test status
Simulation time 34581977 ps
CPU time 2.14 seconds
Started May 09 01:07:00 PM PDT 24
Finished May 09 01:07:03 PM PDT 24
Peak memory 215876 kb
Host smart-811d0c34-e402-4ae3-b587-5f13e084108d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539995666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.539995666
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1173876046
Short name T1011
Test name
Test status
Simulation time 627821803 ps
CPU time 8.51 seconds
Started May 09 01:06:29 PM PDT 24
Finished May 09 01:06:39 PM PDT 24
Peak memory 207368 kb
Host smart-11f3d971-a536-421d-886d-2dbbf450d10f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173876046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1173876046
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.777356152
Short name T1014
Test name
Test status
Simulation time 786757633 ps
CPU time 13.36 seconds
Started May 09 01:06:26 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 207608 kb
Host smart-7ea493b8-5222-410a-ae85-5bf0cb2162ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777356152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.777356152
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1569476211
Short name T80
Test name
Test status
Simulation time 20874513 ps
CPU time 1.15 seconds
Started May 09 01:06:32 PM PDT 24
Finished May 09 01:06:35 PM PDT 24
Peak memory 207112 kb
Host smart-1f63ecda-c72d-4b58-9e1f-14ed65ccabd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569476211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1569476211
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2988146612
Short name T1018
Test name
Test status
Simulation time 378713175 ps
CPU time 1.68 seconds
Started May 09 01:06:31 PM PDT 24
Finished May 09 01:06:35 PM PDT 24
Peak memory 215748 kb
Host smart-358f606a-0426-42c5-94cb-dafbad841d69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988146612 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2988146612
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1343984600
Short name T1097
Test name
Test status
Simulation time 73827823 ps
CPU time 1.44 seconds
Started May 09 01:06:31 PM PDT 24
Finished May 09 01:06:35 PM PDT 24
Peak memory 215764 kb
Host smart-eb30356a-121c-4e13-b4ff-37ff5c07974c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343984600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
343984600
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1154465178
Short name T1021
Test name
Test status
Simulation time 14064244 ps
CPU time 0.73 seconds
Started May 09 01:06:27 PM PDT 24
Finished May 09 01:06:29 PM PDT 24
Peak memory 204104 kb
Host smart-42d54c1b-effe-40ad-80ed-890cf39ef696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154465178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
154465178
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1779174249
Short name T122
Test name
Test status
Simulation time 31944894 ps
CPU time 1.28 seconds
Started May 09 01:06:29 PM PDT 24
Finished May 09 01:06:31 PM PDT 24
Peak memory 215792 kb
Host smart-25b0fa73-318d-467d-b44b-45b757923fee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779174249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1779174249
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1538396456
Short name T1072
Test name
Test status
Simulation time 12927784 ps
CPU time 0.68 seconds
Started May 09 01:06:32 PM PDT 24
Finished May 09 01:06:35 PM PDT 24
Peak memory 203804 kb
Host smart-9a9a53e9-54dc-4c46-8d58-fa1d691d6818
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538396456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1538396456
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.472083785
Short name T1033
Test name
Test status
Simulation time 94975493 ps
CPU time 1.69 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:34 PM PDT 24
Peak memory 215704 kb
Host smart-0e431d5e-abfa-4746-9b95-b365ddf6fa4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472083785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.472083785
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1715275057
Short name T1024
Test name
Test status
Simulation time 254808341 ps
CPU time 3.64 seconds
Started May 09 01:06:29 PM PDT 24
Finished May 09 01:06:35 PM PDT 24
Peak memory 215924 kb
Host smart-7557a2f1-1fb8-42eb-85a7-48e7a2567944
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715275057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
715275057
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3668749371
Short name T266
Test name
Test status
Simulation time 305240956 ps
CPU time 12.64 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 216004 kb
Host smart-59c3836f-39e0-4f21-90ca-bda3ed09b4e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668749371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3668749371
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.224283345
Short name T988
Test name
Test status
Simulation time 11876099 ps
CPU time 0.72 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:15 PM PDT 24
Peak memory 203860 kb
Host smart-d2369761-8680-41f8-ac4b-92033b0185fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224283345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.224283345
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3626801336
Short name T1037
Test name
Test status
Simulation time 25006881 ps
CPU time 0.72 seconds
Started May 09 01:07:11 PM PDT 24
Finished May 09 01:07:12 PM PDT 24
Peak memory 204224 kb
Host smart-1ca41b1a-71eb-45b4-9f0c-d8e74c0b8fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626801336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3626801336
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1099445004
Short name T1094
Test name
Test status
Simulation time 11562786 ps
CPU time 0.75 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:15 PM PDT 24
Peak memory 203852 kb
Host smart-75c54021-20b0-445b-b87e-92a155311d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099445004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1099445004
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2490569580
Short name T1022
Test name
Test status
Simulation time 65743318 ps
CPU time 0.78 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:14 PM PDT 24
Peak memory 203964 kb
Host smart-b36c4b3f-fc27-4780-9117-8877cf7bbbb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490569580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2490569580
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.256806953
Short name T1074
Test name
Test status
Simulation time 14492775 ps
CPU time 0.73 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 203932 kb
Host smart-f56a1721-77dc-4599-99b8-3292c38f9915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256806953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.256806953
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2221606273
Short name T1066
Test name
Test status
Simulation time 85143832 ps
CPU time 0.73 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 204012 kb
Host smart-e689bf51-c5d2-41b9-a99c-59789ff15a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221606273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2221606273
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1479719145
Short name T1047
Test name
Test status
Simulation time 13995092 ps
CPU time 0.73 seconds
Started May 09 01:07:11 PM PDT 24
Finished May 09 01:07:14 PM PDT 24
Peak memory 204020 kb
Host smart-285dbf69-e4cf-4943-9b39-e28777340991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479719145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1479719145
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1790894290
Short name T982
Test name
Test status
Simulation time 158933024 ps
CPU time 0.77 seconds
Started May 09 01:07:16 PM PDT 24
Finished May 09 01:07:18 PM PDT 24
Peak memory 204016 kb
Host smart-780cb7ff-3510-4392-953c-e7a4b3f1a9bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790894290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1790894290
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1387112124
Short name T1026
Test name
Test status
Simulation time 14528733 ps
CPU time 0.77 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:14 PM PDT 24
Peak memory 203968 kb
Host smart-a8ecd1d8-9cdc-4765-86b1-3ed5b690988c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387112124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1387112124
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3290181612
Short name T1039
Test name
Test status
Simulation time 25997669 ps
CPU time 0.71 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 204028 kb
Host smart-a4d9c037-3119-4ad4-9e76-1c05d38722a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290181612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3290181612
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4103404660
Short name T996
Test name
Test status
Simulation time 2522776062 ps
CPU time 15.51 seconds
Started May 09 01:06:31 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 215876 kb
Host smart-e60b2d71-50d5-47b0-b5fe-cc2b31ea8952
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103404660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4103404660
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1321320566
Short name T1064
Test name
Test status
Simulation time 379841584 ps
CPU time 12.88 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:43 PM PDT 24
Peak memory 215740 kb
Host smart-6bfc7ea8-4b0f-42e0-bbe0-ecf38b9323b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321320566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1321320566
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2542029509
Short name T81
Test name
Test status
Simulation time 79890672 ps
CPU time 1.37 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 216804 kb
Host smart-c7e85e45-1914-4237-9a63-0b83a95a573b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542029509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2542029509
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3225826229
Short name T1013
Test name
Test status
Simulation time 486625064 ps
CPU time 3.86 seconds
Started May 09 01:06:31 PM PDT 24
Finished May 09 01:06:37 PM PDT 24
Peak memory 218032 kb
Host smart-ffb8c9a0-3586-4bf6-b2aa-d11cbababd7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225826229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3225826229
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.546062201
Short name T995
Test name
Test status
Simulation time 12338710 ps
CPU time 0.69 seconds
Started May 09 01:06:30 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 203880 kb
Host smart-41954be6-b173-4fcc-a321-a248ca5b9158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546062201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.546062201
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3098163328
Short name T128
Test name
Test status
Simulation time 139765462 ps
CPU time 2.18 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:32 PM PDT 24
Peak memory 215768 kb
Host smart-786e5c42-faf4-45cd-8b6d-629f18987d1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098163328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3098163328
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1374840069
Short name T1057
Test name
Test status
Simulation time 120429906 ps
CPU time 0.65 seconds
Started May 09 01:06:27 PM PDT 24
Finished May 09 01:06:29 PM PDT 24
Peak memory 203900 kb
Host smart-8c65aded-3297-453c-94be-d685e9b07f40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374840069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1374840069
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.242903881
Short name T143
Test name
Test status
Simulation time 54353789 ps
CPU time 2.83 seconds
Started May 09 01:06:28 PM PDT 24
Finished May 09 01:06:32 PM PDT 24
Peak memory 215784 kb
Host smart-548bffc5-2b9b-4fa7-ab59-40838d2f6e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242903881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.242903881
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3751595811
Short name T103
Test name
Test status
Simulation time 174840887 ps
CPU time 4.09 seconds
Started May 09 01:06:31 PM PDT 24
Finished May 09 01:06:37 PM PDT 24
Peak memory 215836 kb
Host smart-b7b848aa-4c6a-4b06-8070-d4c06e14c5d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751595811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
751595811
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2366847420
Short name T264
Test name
Test status
Simulation time 427469689 ps
CPU time 6.64 seconds
Started May 09 01:06:26 PM PDT 24
Finished May 09 01:06:34 PM PDT 24
Peak memory 216412 kb
Host smart-bf541bde-b8b5-44e9-9c09-59cb93505a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366847420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2366847420
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2217283611
Short name T1062
Test name
Test status
Simulation time 16555411 ps
CPU time 0.77 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:15 PM PDT 24
Peak memory 203928 kb
Host smart-a6c706ce-e870-458f-9293-297256258693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217283611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2217283611
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.332722106
Short name T1078
Test name
Test status
Simulation time 18957841 ps
CPU time 0.72 seconds
Started May 09 01:07:14 PM PDT 24
Finished May 09 01:07:17 PM PDT 24
Peak memory 204020 kb
Host smart-bf5387c9-a83e-41ce-b86e-b580188bfb93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332722106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.332722106
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.148871008
Short name T1034
Test name
Test status
Simulation time 28847027 ps
CPU time 0.79 seconds
Started May 09 01:07:11 PM PDT 24
Finished May 09 01:07:13 PM PDT 24
Peak memory 203980 kb
Host smart-7599beeb-e7ba-4e9b-8d61-7a9c19bb7723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148871008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.148871008
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4252180721
Short name T989
Test name
Test status
Simulation time 85089555 ps
CPU time 0.72 seconds
Started May 09 01:07:14 PM PDT 24
Finished May 09 01:07:17 PM PDT 24
Peak memory 203944 kb
Host smart-e117d032-7004-4139-98ce-3cfe98dcd894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252180721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4252180721
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4027053076
Short name T1001
Test name
Test status
Simulation time 18182497 ps
CPU time 0.8 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:15 PM PDT 24
Peak memory 204236 kb
Host smart-86791b64-c177-4a9c-82d5-afe63994984d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027053076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4027053076
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3167796498
Short name T1019
Test name
Test status
Simulation time 46966315 ps
CPU time 0.74 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 203932 kb
Host smart-c6118254-c344-41f1-8d16-78533b3739ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167796498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3167796498
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3617104549
Short name T1046
Test name
Test status
Simulation time 74484081 ps
CPU time 0.71 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 203912 kb
Host smart-796fe816-54e1-4024-b752-18470b022dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617104549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3617104549
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4032201073
Short name T1096
Test name
Test status
Simulation time 12142808 ps
CPU time 0.69 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 203948 kb
Host smart-e8c84b2a-32bc-4b93-ab8f-5a541c297b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032201073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4032201073
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.814130153
Short name T1008
Test name
Test status
Simulation time 71096440 ps
CPU time 0.73 seconds
Started May 09 01:07:11 PM PDT 24
Finished May 09 01:07:13 PM PDT 24
Peak memory 203924 kb
Host smart-e8954bd5-0aae-4951-9d21-8e746ce0ad59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814130153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.814130153
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1091926802
Short name T1087
Test name
Test status
Simulation time 51676790 ps
CPU time 0.73 seconds
Started May 09 01:07:10 PM PDT 24
Finished May 09 01:07:12 PM PDT 24
Peak memory 204004 kb
Host smart-554a913f-7d0f-4f77-9bd0-a01e714709a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091926802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1091926802
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1728646860
Short name T1036
Test name
Test status
Simulation time 215050530 ps
CPU time 15.06 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:55 PM PDT 24
Peak memory 215820 kb
Host smart-65dd9314-d0d8-4406-bf63-b15d89ec31ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728646860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1728646860
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2425435179
Short name T1007
Test name
Test status
Simulation time 1886226110 ps
CPU time 36.82 seconds
Started May 09 01:06:45 PM PDT 24
Finished May 09 01:07:24 PM PDT 24
Peak memory 207568 kb
Host smart-0f24b9dd-6a89-4bb2-9ba9-603c3dc58297
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425435179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2425435179
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1625887882
Short name T1042
Test name
Test status
Simulation time 23141704 ps
CPU time 0.97 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 207376 kb
Host smart-3007846e-460a-4516-bbef-c85f6942ea7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625887882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1625887882
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.10255651
Short name T1098
Test name
Test status
Simulation time 1007672744 ps
CPU time 3.58 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 217476 kb
Host smart-5d78e8b9-5e6e-4f7f-a7a8-0adbdfc325ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10255651 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.10255651
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.428104208
Short name T119
Test name
Test status
Simulation time 177696037 ps
CPU time 2.68 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:42 PM PDT 24
Peak memory 215808 kb
Host smart-be609d41-7844-4041-8dc9-99242b12a503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428104208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.428104208
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3887087815
Short name T1068
Test name
Test status
Simulation time 47653604 ps
CPU time 0.75 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:40 PM PDT 24
Peak memory 204004 kb
Host smart-56786a69-243d-4874-b50e-4daafe013076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887087815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
887087815
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2477738396
Short name T127
Test name
Test status
Simulation time 246595027 ps
CPU time 2.14 seconds
Started May 09 01:06:43 PM PDT 24
Finished May 09 01:06:47 PM PDT 24
Peak memory 215836 kb
Host smart-c7f65767-af97-4757-a89d-680670c8afd0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477738396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2477738396
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1330764477
Short name T990
Test name
Test status
Simulation time 10782085 ps
CPU time 0.69 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:40 PM PDT 24
Peak memory 204220 kb
Host smart-4a92c453-d882-4562-966d-12ac895969d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330764477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1330764477
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4281329207
Short name T1031
Test name
Test status
Simulation time 30531295 ps
CPU time 1.78 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:50 PM PDT 24
Peak memory 215836 kb
Host smart-d6b7487c-fe85-444d-baba-38125dbca574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281329207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4281329207
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1390468554
Short name T1000
Test name
Test status
Simulation time 146761589 ps
CPU time 2.23 seconds
Started May 09 01:06:29 PM PDT 24
Finished May 09 01:06:33 PM PDT 24
Peak memory 215928 kb
Host smart-dad766ad-d2c6-4369-abd6-545f0b3b08f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390468554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
390468554
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2979251248
Short name T165
Test name
Test status
Simulation time 692438425 ps
CPU time 15.39 seconds
Started May 09 01:06:41 PM PDT 24
Finished May 09 01:06:57 PM PDT 24
Peak memory 215796 kb
Host smart-5122bf96-2278-45df-a7bd-99dcb4cc42dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979251248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2979251248
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2710934607
Short name T998
Test name
Test status
Simulation time 74700371 ps
CPU time 0.76 seconds
Started May 09 01:07:11 PM PDT 24
Finished May 09 01:07:14 PM PDT 24
Peak memory 204252 kb
Host smart-4d44778f-654f-4685-ac94-0fadc75a545c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710934607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2710934607
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1499016843
Short name T1023
Test name
Test status
Simulation time 48919104 ps
CPU time 0.7 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 204192 kb
Host smart-3ca08fa1-08d0-4246-84c4-583c63550854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499016843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1499016843
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2909546252
Short name T983
Test name
Test status
Simulation time 14453858 ps
CPU time 0.71 seconds
Started May 09 01:07:14 PM PDT 24
Finished May 09 01:07:17 PM PDT 24
Peak memory 203864 kb
Host smart-7e582282-4a94-405e-aa62-081a73e5edb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909546252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2909546252
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3254856687
Short name T1016
Test name
Test status
Simulation time 55231403 ps
CPU time 0.75 seconds
Started May 09 01:07:14 PM PDT 24
Finished May 09 01:07:17 PM PDT 24
Peak memory 203972 kb
Host smart-e1c30347-6047-48bd-9070-40c0e176d69d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254856687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3254856687
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4293550509
Short name T1101
Test name
Test status
Simulation time 16581514 ps
CPU time 0.79 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:15 PM PDT 24
Peak memory 203984 kb
Host smart-ab7af148-d588-4f0e-9668-7e2d5b2b0adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293550509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4293550509
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3347114416
Short name T1081
Test name
Test status
Simulation time 20203092 ps
CPU time 0.75 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:16 PM PDT 24
Peak memory 203912 kb
Host smart-530d3fc3-2a29-42e9-9a87-e61ca1fd244b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347114416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3347114416
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4063833305
Short name T1027
Test name
Test status
Simulation time 12933287 ps
CPU time 0.74 seconds
Started May 09 01:07:12 PM PDT 24
Finished May 09 01:07:15 PM PDT 24
Peak memory 203848 kb
Host smart-e9fd0851-a3a8-4cb3-80a0-221b53bc5f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063833305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4063833305
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2903975282
Short name T993
Test name
Test status
Simulation time 21865576 ps
CPU time 0.75 seconds
Started May 09 01:07:13 PM PDT 24
Finished May 09 01:07:17 PM PDT 24
Peak memory 204232 kb
Host smart-75e715a3-6b14-46a8-912a-04811a6c2136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903975282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2903975282
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1530668358
Short name T1045
Test name
Test status
Simulation time 23075511 ps
CPU time 0.76 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:29 PM PDT 24
Peak memory 204028 kb
Host smart-d00e5ef5-296d-4c1f-aaef-6dba50fe08f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530668358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1530668358
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3176690720
Short name T1020
Test name
Test status
Simulation time 23943555 ps
CPU time 0.75 seconds
Started May 09 01:07:25 PM PDT 24
Finished May 09 01:07:28 PM PDT 24
Peak memory 203936 kb
Host smart-1990078b-1b47-4d8d-86c9-0895cd49a38f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176690720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3176690720
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1923361570
Short name T1071
Test name
Test status
Simulation time 244816229 ps
CPU time 1.9 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 216856 kb
Host smart-6ab55591-b4c5-4683-9909-25475c48a4fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923361570 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1923361570
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1678643019
Short name T1040
Test name
Test status
Simulation time 203406397 ps
CPU time 1.8 seconds
Started May 09 01:06:41 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 215764 kb
Host smart-2875842f-acea-437c-aa28-7024b6f91ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678643019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
678643019
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3315240591
Short name T985
Test name
Test status
Simulation time 20974176 ps
CPU time 0.7 seconds
Started May 09 01:06:42 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 203852 kb
Host smart-267e3edc-5e1a-4211-90a4-184fac43222e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315240591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
315240591
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1547901211
Short name T1017
Test name
Test status
Simulation time 86530124 ps
CPU time 2.94 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:42 PM PDT 24
Peak memory 215720 kb
Host smart-d1d0481e-a526-48f0-be8f-139e9f9e5570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547901211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1547901211
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3119068295
Short name T1061
Test name
Test status
Simulation time 1084876055 ps
CPU time 7.56 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:48 PM PDT 24
Peak memory 215856 kb
Host smart-65096fdf-122d-4406-a32f-5496a7a15fa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119068295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3119068295
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4025445472
Short name T1025
Test name
Test status
Simulation time 239207231 ps
CPU time 2.97 seconds
Started May 09 01:06:42 PM PDT 24
Finished May 09 01:06:46 PM PDT 24
Peak memory 218496 kb
Host smart-7a36d772-ab23-4867-ae2d-25af4fa74a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025445472 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4025445472
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1122691188
Short name T1009
Test name
Test status
Simulation time 144319518 ps
CPU time 1.37 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 207504 kb
Host smart-4090229f-d78c-46d2-8e9f-53edd1692f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122691188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
122691188
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1512397052
Short name T1052
Test name
Test status
Simulation time 71122327 ps
CPU time 0.76 seconds
Started May 09 01:06:44 PM PDT 24
Finished May 09 01:06:46 PM PDT 24
Peak memory 203960 kb
Host smart-1676a06d-dc30-4c5e-8a9d-3413fae7f564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512397052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
512397052
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2664189546
Short name T1003
Test name
Test status
Simulation time 151033904 ps
CPU time 3.82 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:51 PM PDT 24
Peak memory 215832 kb
Host smart-cb9648b3-75b7-441e-ae2a-b4e24a24ece5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664189546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2664189546
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.592911678
Short name T1038
Test name
Test status
Simulation time 652476562 ps
CPU time 3.82 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 215824 kb
Host smart-fbc3f81b-2d01-472c-b427-5a5053c9de01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592911678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.592911678
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.353584014
Short name T265
Test name
Test status
Simulation time 407845686 ps
CPU time 12.96 seconds
Started May 09 01:06:53 PM PDT 24
Finished May 09 01:07:06 PM PDT 24
Peak memory 216108 kb
Host smart-89326364-27d6-48f5-b5a2-46e19b134c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353584014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.353584014
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.271965205
Short name T94
Test name
Test status
Simulation time 56069507 ps
CPU time 1.79 seconds
Started May 09 01:06:45 PM PDT 24
Finished May 09 01:06:49 PM PDT 24
Peak memory 215748 kb
Host smart-14fba1c8-437b-4992-ab27-b93bfce32e7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271965205 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.271965205
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2140005720
Short name T144
Test name
Test status
Simulation time 266361335 ps
CPU time 1.51 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:42 PM PDT 24
Peak memory 215792 kb
Host smart-394553aa-43d3-47da-91d5-09e2d35a1aba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140005720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
140005720
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2138667287
Short name T984
Test name
Test status
Simulation time 39416352 ps
CPU time 0.8 seconds
Started May 09 01:06:43 PM PDT 24
Finished May 09 01:06:45 PM PDT 24
Peak memory 204004 kb
Host smart-f29d46b2-cb2d-4a47-b75d-8e146e2538fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138667287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
138667287
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.458521712
Short name T992
Test name
Test status
Simulation time 228773110 ps
CPU time 3.61 seconds
Started May 09 01:06:42 PM PDT 24
Finished May 09 01:06:47 PM PDT 24
Peak memory 215816 kb
Host smart-f0b09a61-83d7-401e-8342-7c3a7d17ad29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458521712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.458521712
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.680444260
Short name T101
Test name
Test status
Simulation time 25789219 ps
CPU time 1.48 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 215964 kb
Host smart-417a7be1-4299-4b58-91eb-1d077ea3b0cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680444260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.680444260
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4079458151
Short name T1048
Test name
Test status
Simulation time 105339059 ps
CPU time 6.42 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:54 PM PDT 24
Peak memory 215772 kb
Host smart-8c6ac622-a9ed-4d6b-b59b-64bf658b592e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079458151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4079458151
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.309437769
Short name T1029
Test name
Test status
Simulation time 328342478 ps
CPU time 2.87 seconds
Started May 09 01:06:42 PM PDT 24
Finished May 09 01:06:46 PM PDT 24
Peak memory 218368 kb
Host smart-73abf440-70ad-4be3-8917-b9e188de0ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309437769 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.309437769
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4056543260
Short name T164
Test name
Test status
Simulation time 49971094 ps
CPU time 1.52 seconds
Started May 09 01:06:37 PM PDT 24
Finished May 09 01:06:39 PM PDT 24
Peak memory 207600 kb
Host smart-f417a4ac-9f0c-4887-b1b7-8083fabe0c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056543260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
056543260
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1731394684
Short name T1032
Test name
Test status
Simulation time 41045288 ps
CPU time 0.69 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 203940 kb
Host smart-666e9d96-6b99-4353-9680-68af34ab0ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731394684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
731394684
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1084055229
Short name T1100
Test name
Test status
Simulation time 884817085 ps
CPU time 4.62 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:53 PM PDT 24
Peak memory 215756 kb
Host smart-4818acc4-45cb-42af-abf1-afb6ab2ed5d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084055229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1084055229
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1757760205
Short name T1056
Test name
Test status
Simulation time 405897419 ps
CPU time 4.03 seconds
Started May 09 01:06:46 PM PDT 24
Finished May 09 01:06:52 PM PDT 24
Peak memory 215904 kb
Host smart-db2c8a50-911a-4b9a-876f-4c95578eecf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757760205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
757760205
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1983355452
Short name T1082
Test name
Test status
Simulation time 84815040 ps
CPU time 1.72 seconds
Started May 09 01:06:41 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 215844 kb
Host smart-0f92a998-ca2a-458f-9a97-d375e89caa81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983355452 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1983355452
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1947551770
Short name T999
Test name
Test status
Simulation time 20521462 ps
CPU time 1.24 seconds
Started May 09 01:06:42 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 207504 kb
Host smart-5231263f-51e2-4c4c-999c-208da7045929
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947551770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
947551770
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2223353513
Short name T1089
Test name
Test status
Simulation time 12396052 ps
CPU time 0.7 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:41 PM PDT 24
Peak memory 203936 kb
Host smart-94ab52f3-0b1a-4db4-8449-435c8ec7008c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223353513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
223353513
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1315923694
Short name T154
Test name
Test status
Simulation time 1284857266 ps
CPU time 4.34 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:44 PM PDT 24
Peak memory 215808 kb
Host smart-656795ba-faa3-458a-bd2a-ae694261df31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315923694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1315923694
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4097305654
Short name T106
Test name
Test status
Simulation time 307701126 ps
CPU time 4.21 seconds
Started May 09 01:06:39 PM PDT 24
Finished May 09 01:06:45 PM PDT 24
Peak memory 215868 kb
Host smart-63438997-d4d1-4f0f-bc74-1527d2a1b94b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097305654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
097305654
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3538699248
Short name T260
Test name
Test status
Simulation time 296269836 ps
CPU time 19.23 seconds
Started May 09 01:06:38 PM PDT 24
Finished May 09 01:06:59 PM PDT 24
Peak memory 215644 kb
Host smart-fc8c4537-ab27-4054-b0a8-4062ec321dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538699248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3538699248
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1241217147
Short name T679
Test name
Test status
Simulation time 225871685 ps
CPU time 0.75 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:08:17 PM PDT 24
Peak memory 205408 kb
Host smart-e7e7d35d-514f-4894-a2f8-6ecd47d02696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241217147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
241217147
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1769741818
Short name T653
Test name
Test status
Simulation time 298746081 ps
CPU time 3.28 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:14 PM PDT 24
Peak memory 219420 kb
Host smart-4e2166df-34eb-4128-83eb-b7b0ae6c5233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769741818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1769741818
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2004059326
Short name T592
Test name
Test status
Simulation time 61531075 ps
CPU time 0.8 seconds
Started May 09 01:08:05 PM PDT 24
Finished May 09 01:08:07 PM PDT 24
Peak memory 206452 kb
Host smart-a555acf1-d8d6-4199-8688-885bfb30cc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004059326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2004059326
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1009658395
Short name T228
Test name
Test status
Simulation time 172809139322 ps
CPU time 320.73 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:13:32 PM PDT 24
Peak memory 254556 kb
Host smart-806fcfe0-633e-499f-baf6-181a8d9f83a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009658395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1009658395
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.287436155
Short name T328
Test name
Test status
Simulation time 2129160357 ps
CPU time 15 seconds
Started May 09 01:08:15 PM PDT 24
Finished May 09 01:08:32 PM PDT 24
Peak memory 235036 kb
Host smart-1ac6afed-f0cc-4f51-bfe2-a5c95b527b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287436155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.287436155
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3616929310
Short name T348
Test name
Test status
Simulation time 15668575509 ps
CPU time 50.89 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 232844 kb
Host smart-e7f60d73-4758-4049-adca-3c488b8c51c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616929310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3616929310
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.607518272
Short name T497
Test name
Test status
Simulation time 941029695 ps
CPU time 20.92 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:31 PM PDT 24
Peak memory 256552 kb
Host smart-9949aa68-c159-4baa-8341-707f2a9593ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607518272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.607518272
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2983627139
Short name T519
Test name
Test status
Simulation time 3568866133 ps
CPU time 11.86 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:22 PM PDT 24
Peak memory 233396 kb
Host smart-1f7e1110-0c62-411e-b15b-43a313287f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983627139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2983627139
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3334138485
Short name T794
Test name
Test status
Simulation time 33530684972 ps
CPU time 27.78 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 218828 kb
Host smart-a48aa27d-a46a-497a-8f92-e601498aab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334138485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3334138485
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3763286719
Short name T419
Test name
Test status
Simulation time 83883933 ps
CPU time 3.87 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:15 PM PDT 24
Peak memory 223040 kb
Host smart-07f61887-2661-490e-9006-8d7a11772d58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763286719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3763286719
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2891162258
Short name T66
Test name
Test status
Simulation time 90341336 ps
CPU time 1.25 seconds
Started May 09 01:08:08 PM PDT 24
Finished May 09 01:08:11 PM PDT 24
Peak memory 236764 kb
Host smart-93b5cd04-2697-42b8-9e2b-29bd406fd39d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891162258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2891162258
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3877720847
Short name T60
Test name
Test status
Simulation time 33406622541 ps
CPU time 253.84 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:12:25 PM PDT 24
Peak memory 249364 kb
Host smart-c0f2164f-364f-45aa-94c6-e4c4cd7b1b41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877720847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3877720847
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2110606051
Short name T545
Test name
Test status
Simulation time 331623346 ps
CPU time 6.47 seconds
Started May 09 01:08:03 PM PDT 24
Finished May 09 01:08:12 PM PDT 24
Peak memory 216564 kb
Host smart-165955e1-1652-4e10-ad10-907631dcc4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110606051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2110606051
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2771451513
Short name T520
Test name
Test status
Simulation time 806884195 ps
CPU time 3.29 seconds
Started May 09 01:08:02 PM PDT 24
Finished May 09 01:08:08 PM PDT 24
Peak memory 216200 kb
Host smart-c8062b95-d274-4cb3-a356-f2d628e19162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771451513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2771451513
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1743815328
Short name T396
Test name
Test status
Simulation time 35154960 ps
CPU time 0.73 seconds
Started May 09 01:08:13 PM PDT 24
Finished May 09 01:08:16 PM PDT 24
Peak memory 205768 kb
Host smart-b3e8ed92-6060-4a63-830c-be75d589d28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743815328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1743815328
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2964915588
Short name T633
Test name
Test status
Simulation time 769025055 ps
CPU time 0.83 seconds
Started May 09 01:08:16 PM PDT 24
Finished May 09 01:08:18 PM PDT 24
Peak memory 205728 kb
Host smart-ad6b38d8-4be5-4de1-a759-d1b22f2a4312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964915588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2964915588
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4281750126
Short name T494
Test name
Test status
Simulation time 695302343 ps
CPU time 5.7 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:08:21 PM PDT 24
Peak memory 228060 kb
Host smart-01eb2758-ec8e-41b4-b72a-4496ac128265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281750126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4281750126
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2828304994
Short name T959
Test name
Test status
Simulation time 12908506 ps
CPU time 0.74 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:14 PM PDT 24
Peak memory 204400 kb
Host smart-d411b26c-075f-4ec4-bf3e-0be3de63849d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828304994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
828304994
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.600112580
Short name T482
Test name
Test status
Simulation time 910191303 ps
CPU time 11.05 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:08:27 PM PDT 24
Peak memory 232820 kb
Host smart-3bb79124-fb7b-4a5e-9aea-eb90d15de600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600112580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.600112580
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1592188426
Short name T937
Test name
Test status
Simulation time 42208297 ps
CPU time 0.85 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:11 PM PDT 24
Peak memory 206832 kb
Host smart-4201f346-3662-4ce0-ac56-efd35ec87fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592188426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1592188426
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3769248798
Short name T170
Test name
Test status
Simulation time 11335459456 ps
CPU time 60.09 seconds
Started May 09 01:08:13 PM PDT 24
Finished May 09 01:09:15 PM PDT 24
Peak memory 249284 kb
Host smart-7ba1c593-58ee-471d-80ae-d25a017a3b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769248798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3769248798
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2005313138
Short name T837
Test name
Test status
Simulation time 20479948617 ps
CPU time 228.89 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:12:01 PM PDT 24
Peak memory 265792 kb
Host smart-0e2e035b-7f77-4bb0-bd0b-f7a65a0558ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005313138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2005313138
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3662613815
Short name T863
Test name
Test status
Simulation time 36433037178 ps
CPU time 147.41 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:10:43 PM PDT 24
Peak memory 249400 kb
Host smart-fbe6dfe1-4bfd-4f89-af38-7f47820790ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662613815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3662613815
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.853848929
Short name T598
Test name
Test status
Simulation time 5403475990 ps
CPU time 49.53 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 234012 kb
Host smart-e04f282a-8d41-43fe-b600-f971cb1a5e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853848929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.853848929
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2895084970
Short name T212
Test name
Test status
Simulation time 813516030 ps
CPU time 4.22 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:08:17 PM PDT 24
Peak memory 224536 kb
Host smart-6bc71bdb-24ab-4b5a-9559-82303b1df21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895084970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2895084970
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.214880556
Short name T869
Test name
Test status
Simulation time 39117430051 ps
CPU time 131.3 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:10:23 PM PDT 24
Peak memory 236984 kb
Host smart-1fe9fe85-3a04-4ab4-8dbe-7bc57c3d202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214880556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.214880556
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2115120808
Short name T659
Test name
Test status
Simulation time 35557543 ps
CPU time 1.09 seconds
Started May 09 01:08:17 PM PDT 24
Finished May 09 01:08:19 PM PDT 24
Peak memory 216700 kb
Host smart-39a7b40a-2589-43c2-aaff-33b75f8ff960
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115120808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2115120808
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3777654467
Short name T69
Test name
Test status
Simulation time 4151359261 ps
CPU time 12.22 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:25 PM PDT 24
Peak memory 218644 kb
Host smart-03ee8101-c1bd-4a60-baba-d44fa1120cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777654467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3777654467
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3278943775
Short name T1
Test name
Test status
Simulation time 712679027 ps
CPU time 3.09 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:16 PM PDT 24
Peak memory 218588 kb
Host smart-8bb150d2-4d1a-4ed0-8670-60d6f589a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278943775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3278943775
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3235124902
Short name T363
Test name
Test status
Simulation time 2120886910 ps
CPU time 7.27 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:08:23 PM PDT 24
Peak memory 220776 kb
Host smart-a5c71063-b6e7-47da-9471-3c159718bd8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3235124902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3235124902
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1114062224
Short name T67
Test name
Test status
Simulation time 89334019 ps
CPU time 1.18 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:14 PM PDT 24
Peak memory 236744 kb
Host smart-ac9e0200-89dc-46f6-a292-d633bfe5d384
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114062224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1114062224
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2993986885
Short name T870
Test name
Test status
Simulation time 30285329779 ps
CPU time 182.76 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:11:16 PM PDT 24
Peak memory 253732 kb
Host smart-6636f51a-42d0-4f6d-8e49-82a5fed8ce58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993986885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2993986885
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3838194438
Short name T798
Test name
Test status
Simulation time 8958241523 ps
CPU time 10.86 seconds
Started May 09 01:08:12 PM PDT 24
Finished May 09 01:08:25 PM PDT 24
Peak memory 216492 kb
Host smart-624ab281-c7bf-4f94-a47e-50651f4628ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838194438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3838194438
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3271548676
Short name T913
Test name
Test status
Simulation time 10258077100 ps
CPU time 13.86 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:27 PM PDT 24
Peak memory 216516 kb
Host smart-b677455b-c16e-460d-bfc7-06b82b86b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271548676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3271548676
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.242995606
Short name T589
Test name
Test status
Simulation time 24954212 ps
CPU time 1.44 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:13 PM PDT 24
Peak memory 216320 kb
Host smart-cae8df2f-e019-4cc3-a8ea-3d63abb0516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242995606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.242995606
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2344249998
Short name T410
Test name
Test status
Simulation time 29151519 ps
CPU time 0.85 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:12 PM PDT 24
Peak memory 205808 kb
Host smart-0b72d895-875a-4b7e-adfb-3fa265e6b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344249998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2344249998
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1982271043
Short name T836
Test name
Test status
Simulation time 262855913 ps
CPU time 4.08 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:15 PM PDT 24
Peak memory 233980 kb
Host smart-2413342e-f603-4f12-acdf-fa24b2e07ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982271043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1982271043
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3088291320
Short name T139
Test name
Test status
Simulation time 24714905 ps
CPU time 0.73 seconds
Started May 09 01:08:51 PM PDT 24
Finished May 09 01:08:53 PM PDT 24
Peak memory 205268 kb
Host smart-617b9996-b05e-4316-b1b5-5eb4e6214f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088291320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3088291320
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2186877537
Short name T925
Test name
Test status
Simulation time 228661414 ps
CPU time 3.04 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:08:51 PM PDT 24
Peak memory 233780 kb
Host smart-caff923d-e944-4c9f-a20b-fc5714921ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186877537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2186877537
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1603576055
Short name T469
Test name
Test status
Simulation time 22145512 ps
CPU time 0.82 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:08:51 PM PDT 24
Peak memory 206452 kb
Host smart-457ff685-df40-44a1-a4e0-8f8e058e6059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603576055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1603576055
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.613762372
Short name T224
Test name
Test status
Simulation time 141254542049 ps
CPU time 113.14 seconds
Started May 09 01:08:51 PM PDT 24
Finished May 09 01:10:46 PM PDT 24
Peak memory 250092 kb
Host smart-edf4a60b-cae9-480c-814e-339be8f6abe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613762372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.613762372
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.938402048
Short name T172
Test name
Test status
Simulation time 470851148704 ps
CPU time 446.92 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:16:22 PM PDT 24
Peak memory 267816 kb
Host smart-70022526-ccc0-4203-8095-9285894d272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938402048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.938402048
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.4243153714
Short name T173
Test name
Test status
Simulation time 34880277623 ps
CPU time 78.9 seconds
Started May 09 01:08:44 PM PDT 24
Finished May 09 01:10:04 PM PDT 24
Peak memory 249436 kb
Host smart-4c599e32-51c4-4cf5-ad22-20e6bd871cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243153714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.4243153714
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1861013486
Short name T429
Test name
Test status
Simulation time 1113526066 ps
CPU time 9.58 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:09:00 PM PDT 24
Peak memory 232712 kb
Host smart-ad47a86a-78eb-427a-b880-b9a8e305935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861013486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1861013486
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3251680387
Short name T441
Test name
Test status
Simulation time 29241328 ps
CPU time 1.99 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:08:52 PM PDT 24
Peak memory 216056 kb
Host smart-c010e17d-556d-4e41-8b49-47a0e9fda62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251680387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3251680387
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3092435132
Short name T435
Test name
Test status
Simulation time 5695202270 ps
CPU time 41.65 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:09:31 PM PDT 24
Peak memory 232836 kb
Host smart-d085450a-d73e-464d-8e40-03825c48d755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092435132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3092435132
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3712238626
Short name T25
Test name
Test status
Simulation time 110966984 ps
CPU time 1.12 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:08:49 PM PDT 24
Peak memory 218004 kb
Host smart-7776aa57-1532-4c12-9ae8-08725ff50806
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712238626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3712238626
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2529213588
Short name T369
Test name
Test status
Simulation time 4081944164 ps
CPU time 12.22 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:09:00 PM PDT 24
Peak memory 224548 kb
Host smart-d0fdb1e8-43cd-4ed8-b82c-0e16bd529b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529213588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2529213588
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3708269735
Short name T299
Test name
Test status
Simulation time 3058741671 ps
CPU time 12.13 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:07 PM PDT 24
Peak memory 236272 kb
Host smart-c65781f4-bc90-40f3-8dca-7bd31148668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708269735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3708269735
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1191983316
Short name T906
Test name
Test status
Simulation time 409797258 ps
CPU time 7 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 221592 kb
Host smart-96423b4d-2725-41fa-bd1b-36c1c6c7ad52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1191983316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1191983316
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1354605608
Short name T529
Test name
Test status
Simulation time 2013756812 ps
CPU time 13.39 seconds
Started May 09 01:08:55 PM PDT 24
Finished May 09 01:09:09 PM PDT 24
Peak memory 216396 kb
Host smart-edfc2f4e-6998-42c7-91bf-d144180776e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354605608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1354605608
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1748239545
Short name T476
Test name
Test status
Simulation time 1133918359 ps
CPU time 3.76 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:08:54 PM PDT 24
Peak memory 216344 kb
Host smart-162479c4-329c-465f-801a-18afb6bc1fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748239545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1748239545
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.190827757
Short name T960
Test name
Test status
Simulation time 255056348 ps
CPU time 1.17 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:50 PM PDT 24
Peak memory 216468 kb
Host smart-7f3efa62-23a9-4a91-b6c1-11c5c39b5e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190827757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.190827757
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.590689305
Short name T725
Test name
Test status
Simulation time 270259045 ps
CPU time 1.05 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:50 PM PDT 24
Peak memory 206800 kb
Host smart-ea3a6803-e4f6-4b88-b1ff-378d94780601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590689305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.590689305
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3529010836
Short name T200
Test name
Test status
Simulation time 3014187500 ps
CPU time 6.17 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 233720 kb
Host smart-c490a650-62ba-43e7-afc5-97a27d708d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529010836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3529010836
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.622687889
Short name T617
Test name
Test status
Simulation time 13952412 ps
CPU time 0.78 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:00 PM PDT 24
Peak memory 205332 kb
Host smart-84ddd510-8cec-4dbc-bc3d-f7c058d1b5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622687889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.622687889
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4244403331
Short name T968
Test name
Test status
Simulation time 220204082 ps
CPU time 3.26 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:52 PM PDT 24
Peak memory 233472 kb
Host smart-124dd309-dae9-48b4-8d69-d62a8105264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244403331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4244403331
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3219695077
Short name T544
Test name
Test status
Simulation time 16402233 ps
CPU time 0.77 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:08:56 PM PDT 24
Peak memory 206448 kb
Host smart-56538066-656f-41d9-9985-46fdf9d276f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219695077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3219695077
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3093486469
Short name T171
Test name
Test status
Simulation time 77819418260 ps
CPU time 262.84 seconds
Started May 09 01:08:51 PM PDT 24
Finished May 09 01:13:15 PM PDT 24
Peak memory 253772 kb
Host smart-aec78933-d744-4530-ab98-3a3369ef9d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093486469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3093486469
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.590028825
Short name T499
Test name
Test status
Simulation time 2966150355 ps
CPU time 61.15 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 254544 kb
Host smart-bd80b423-462c-42de-b13e-0ab5c862be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590028825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.590028825
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3226590773
Short name T842
Test name
Test status
Simulation time 767335654 ps
CPU time 4.43 seconds
Started May 09 01:08:51 PM PDT 24
Finished May 09 01:08:56 PM PDT 24
Peak memory 232772 kb
Host smart-b602cbf4-eb48-47ef-86be-f0bc09fd2a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226590773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3226590773
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.875460795
Short name T666
Test name
Test status
Simulation time 844142432 ps
CPU time 5.89 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:08:56 PM PDT 24
Peak memory 233232 kb
Host smart-10e68981-fa27-41f3-9914-8c4a173d0934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875460795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.875460795
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.874158013
Short name T643
Test name
Test status
Simulation time 8913334558 ps
CPU time 25.95 seconds
Started May 09 01:08:53 PM PDT 24
Finished May 09 01:09:20 PM PDT 24
Peak memory 234488 kb
Host smart-4ad2afd6-3dcf-417c-99c6-39f10eb5e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874158013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.874158013
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.4067427607
Short name T448
Test name
Test status
Simulation time 83408920 ps
CPU time 1.04 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:08:56 PM PDT 24
Peak memory 216756 kb
Host smart-9a25d637-dcd4-45ba-a52c-1091bb4525e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067427607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.4067427607
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3823320856
Short name T823
Test name
Test status
Simulation time 2509849436 ps
CPU time 8.28 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:08:59 PM PDT 24
Peak memory 224692 kb
Host smart-2b057361-c8d6-483b-824b-964680898dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823320856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3823320856
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.10417068
Short name T748
Test name
Test status
Simulation time 5959950237 ps
CPU time 6.67 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 232860 kb
Host smart-ebb0c001-5911-4d34-84ff-6fb87929d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10417068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.10417068
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2705714500
Short name T5
Test name
Test status
Simulation time 1010753232 ps
CPU time 5.98 seconds
Started May 09 01:08:51 PM PDT 24
Finished May 09 01:08:58 PM PDT 24
Peak memory 220128 kb
Host smart-3672f279-47b2-4b5f-8526-061dba3f1cdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2705714500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2705714500
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2263014252
Short name T840
Test name
Test status
Simulation time 51983167 ps
CPU time 1.13 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 207104 kb
Host smart-54237b29-947e-439c-bc07-9e21cbc12714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263014252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2263014252
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.785133356
Short name T313
Test name
Test status
Simulation time 2580317624 ps
CPU time 12.18 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 216532 kb
Host smart-d042e3ad-4f5f-4d35-ab3f-25c1f3c9e6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785133356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.785133356
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1976630491
Short name T747
Test name
Test status
Simulation time 36046019 ps
CPU time 0.72 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:08:48 PM PDT 24
Peak memory 205500 kb
Host smart-a8e3038d-6bd7-4dbc-b573-8ae19bac156c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976630491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1976630491
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.721734401
Short name T767
Test name
Test status
Simulation time 859205263 ps
CPU time 3.01 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:08:54 PM PDT 24
Peak memory 216380 kb
Host smart-6d3365cd-723e-4aad-b53c-db82a44b1fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721734401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.721734401
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3251953125
Short name T525
Test name
Test status
Simulation time 75458661 ps
CPU time 0.79 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:08:57 PM PDT 24
Peak memory 205836 kb
Host smart-6584616a-53cc-418b-99ef-84f15b344fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251953125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3251953125
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2356129687
Short name T504
Test name
Test status
Simulation time 3183524789 ps
CPU time 8.34 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:08:58 PM PDT 24
Peak memory 234904 kb
Host smart-32b1c54c-aea4-4c64-9e64-7d8ae5cd82b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356129687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2356129687
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4077350113
Short name T866
Test name
Test status
Simulation time 82924015 ps
CPU time 0.73 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 205696 kb
Host smart-eaed1746-d0e2-49dc-9df3-ffd17291dbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077350113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4077350113
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4116554332
Short name T671
Test name
Test status
Simulation time 1520097864 ps
CPU time 16.35 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:16 PM PDT 24
Peak memory 223048 kb
Host smart-001546bd-893d-47df-ac97-c1a6b83432cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116554332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4116554332
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3549865148
Short name T854
Test name
Test status
Simulation time 109056339 ps
CPU time 0.8 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:00 PM PDT 24
Peak memory 205740 kb
Host smart-619655af-48f1-4d6d-afd7-7f83de1f9d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549865148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3549865148
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2032109643
Short name T28
Test name
Test status
Simulation time 73864692031 ps
CPU time 187.98 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 254156 kb
Host smart-7d698f34-b960-465e-8b04-7ffe31cc676b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032109643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2032109643
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2607830667
Short name T821
Test name
Test status
Simulation time 7675883768 ps
CPU time 130.28 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:11:10 PM PDT 24
Peak memory 249400 kb
Host smart-e14e030d-aa0e-4174-ba2c-043ba725d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607830667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2607830667
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2533077457
Short name T759
Test name
Test status
Simulation time 144027271 ps
CPU time 4.35 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 224596 kb
Host smart-34c7dd09-8580-45d0-b2ae-8388412cc58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533077457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2533077457
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1932858424
Short name T946
Test name
Test status
Simulation time 465341487 ps
CPU time 6.5 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:07 PM PDT 24
Peak memory 219968 kb
Host smart-28ee5654-1f8c-475c-a7c9-2b25f741a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932858424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1932858424
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1023083773
Short name T919
Test name
Test status
Simulation time 28533502544 ps
CPU time 63.56 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:10:06 PM PDT 24
Peak memory 238464 kb
Host smart-3336fe8e-72c7-4590-9078-42537463ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023083773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1023083773
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2890792821
Short name T74
Test name
Test status
Simulation time 92825387 ps
CPU time 1.11 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:00 PM PDT 24
Peak memory 216732 kb
Host smart-bcb8fe27-cf8c-46e6-8fcb-c1d2873c4eb2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890792821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2890792821
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1224411865
Short name T304
Test name
Test status
Simulation time 4028390175 ps
CPU time 5.91 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:06 PM PDT 24
Peak memory 218792 kb
Host smart-a5111cd5-efb2-4007-82a5-31f45087e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224411865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1224411865
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1130033594
Short name T502
Test name
Test status
Simulation time 12528676739 ps
CPU time 7.36 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:09 PM PDT 24
Peak memory 233388 kb
Host smart-2ec56c35-a1b8-4d9b-980d-73a09023eb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130033594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1130033594
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3970039226
Short name T138
Test name
Test status
Simulation time 157790279 ps
CPU time 4.06 seconds
Started May 09 01:08:56 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 222328 kb
Host smart-37598f05-8858-4249-8b11-4729e93d4326
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3970039226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3970039226
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3890396027
Short name T876
Test name
Test status
Simulation time 76049135 ps
CPU time 0.98 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 207252 kb
Host smart-463dfdc5-b987-4137-b803-0ecb21063592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890396027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3890396027
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3844053887
Short name T850
Test name
Test status
Simulation time 16693819078 ps
CPU time 26.93 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 216888 kb
Host smart-aee2b6b1-7930-4dea-a5fb-cf5d16f8d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844053887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3844053887
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3238536067
Short name T350
Test name
Test status
Simulation time 11709786256 ps
CPU time 18.11 seconds
Started May 09 01:08:56 PM PDT 24
Finished May 09 01:09:15 PM PDT 24
Peak memory 216520 kb
Host smart-1587ea60-af85-4912-97d9-6198ac6ab0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238536067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3238536067
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1100665949
Short name T777
Test name
Test status
Simulation time 84731658 ps
CPU time 1.59 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 216676 kb
Host smart-3fc50b02-be74-43db-bedf-60dd6cc572e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100665949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1100665949
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2351551495
Short name T85
Test name
Test status
Simulation time 856701956 ps
CPU time 0.85 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 205740 kb
Host smart-3fad9286-9f53-4f8d-833c-296511000261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351551495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2351551495
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.285529292
Short name T217
Test name
Test status
Simulation time 1088943644 ps
CPU time 8.86 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:09:07 PM PDT 24
Peak memory 226844 kb
Host smart-41c38ab9-6528-4439-8822-fc2f23e5d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285529292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.285529292
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1276067144
Short name T601
Test name
Test status
Simulation time 20532755 ps
CPU time 0.71 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 205748 kb
Host smart-c4594026-1dc4-4ce5-8809-585c6f80b589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276067144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1276067144
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.387980420
Short name T886
Test name
Test status
Simulation time 338593865 ps
CPU time 4.99 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:05 PM PDT 24
Peak memory 235368 kb
Host smart-258813cf-8e5a-44ee-aa5b-a06f0b5fce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387980420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.387980420
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2392845043
Short name T458
Test name
Test status
Simulation time 46462012 ps
CPU time 0.77 seconds
Started May 09 01:09:01 PM PDT 24
Finished May 09 01:09:04 PM PDT 24
Peak memory 205796 kb
Host smart-39f468eb-4102-4013-81eb-57dd870602a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392845043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2392845043
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1317174679
Short name T831
Test name
Test status
Simulation time 2754463679 ps
CPU time 52.46 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:54 PM PDT 24
Peak memory 253428 kb
Host smart-9bd0e348-cc45-412e-9c3c-2c21def7f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317174679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1317174679
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3836452290
Short name T287
Test name
Test status
Simulation time 90176582 ps
CPU time 3.3 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:09:04 PM PDT 24
Peak memory 232676 kb
Host smart-1cb2ef74-96aa-4006-ac8a-5fffd4e136e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836452290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3836452290
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2557920244
Short name T945
Test name
Test status
Simulation time 274686124 ps
CPU time 2.32 seconds
Started May 09 01:09:04 PM PDT 24
Finished May 09 01:09:07 PM PDT 24
Peak memory 216168 kb
Host smart-c06c16b8-c0e7-4188-b7f5-d9a9fa3344eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557920244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2557920244
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2812749875
Short name T761
Test name
Test status
Simulation time 18706065238 ps
CPU time 86.29 seconds
Started May 09 01:08:58 PM PDT 24
Finished May 09 01:10:27 PM PDT 24
Peak memory 238552 kb
Host smart-03acef66-cf58-48aa-a671-a9018b6ee555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812749875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2812749875
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.309401310
Short name T780
Test name
Test status
Simulation time 35111356 ps
CPU time 1.14 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 216776 kb
Host smart-0efa36f9-53da-46b5-9db6-82042e2d2199
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309401310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.309401310
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.253476014
Short name T282
Test name
Test status
Simulation time 20278576423 ps
CPU time 15.39 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:09:14 PM PDT 24
Peak memory 245224 kb
Host smart-5d1b3f35-c84a-48af-b82a-9c03b5d2a181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253476014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.253476014
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3483199454
Short name T538
Test name
Test status
Simulation time 1549852448 ps
CPU time 4.77 seconds
Started May 09 01:08:55 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 233564 kb
Host smart-810fbd27-54fa-4efb-8d39-7b18e8b63ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483199454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3483199454
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2721378457
Short name T833
Test name
Test status
Simulation time 1403492683 ps
CPU time 4.54 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:06 PM PDT 24
Peak memory 219360 kb
Host smart-086aff6a-c5b9-4694-9463-125eb6f21e74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2721378457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2721378457
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1611348200
Short name T904
Test name
Test status
Simulation time 58319614859 ps
CPU time 293.63 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:13:56 PM PDT 24
Peak memory 262596 kb
Host smart-ac174d85-6723-4c9a-994b-91e73c6cab01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611348200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1611348200
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.91301390
Short name T450
Test name
Test status
Simulation time 3148677915 ps
CPU time 16.32 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:09:18 PM PDT 24
Peak memory 216468 kb
Host smart-eff2a93f-a258-4ee3-b1af-d9ca8b4a8872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91301390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.91301390
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.963987230
Short name T936
Test name
Test status
Simulation time 3225157339 ps
CPU time 4.83 seconds
Started May 09 01:09:02 PM PDT 24
Finished May 09 01:09:08 PM PDT 24
Peak memory 216556 kb
Host smart-9ea7f417-1e51-4923-b9e9-f840ac7e7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963987230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.963987230
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3952712774
Short name T357
Test name
Test status
Simulation time 136697650 ps
CPU time 1.18 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 207952 kb
Host smart-0b0c9e6d-e50d-4d65-b8fe-2717fb4c04a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952712774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3952712774
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1616516326
Short name T560
Test name
Test status
Simulation time 190823896 ps
CPU time 0.88 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 205848 kb
Host smart-2873c880-8f12-44f9-8684-85c2f57b44df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616516326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1616516326
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1283082726
Short name T335
Test name
Test status
Simulation time 168831957 ps
CPU time 4.8 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 226728 kb
Host smart-4ef1ea8b-27c2-4a9a-89be-b4357230b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283082726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1283082726
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3716830000
Short name T843
Test name
Test status
Simulation time 91378150 ps
CPU time 0.74 seconds
Started May 09 01:09:21 PM PDT 24
Finished May 09 01:09:23 PM PDT 24
Peak memory 205304 kb
Host smart-4306ddf6-3b6d-4bd7-b172-29b44b058252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716830000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3716830000
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3605134238
Short name T115
Test name
Test status
Simulation time 232193160 ps
CPU time 2.84 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:09:05 PM PDT 24
Peak memory 234056 kb
Host smart-fea1de89-8208-4d64-874d-1cc3d17f50a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605134238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3605134238
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.668520404
Short name T406
Test name
Test status
Simulation time 70843203 ps
CPU time 0.84 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 206516 kb
Host smart-28ab8285-1b99-4134-a655-ab020cb75a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668520404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.668520404
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4098633952
Short name T352
Test name
Test status
Simulation time 19056959 ps
CPU time 0.78 seconds
Started May 09 01:09:03 PM PDT 24
Finished May 09 01:09:05 PM PDT 24
Peak memory 215960 kb
Host smart-30716769-a89a-4366-9a26-341f1a3b91dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098633952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4098633952
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1557162118
Short name T883
Test name
Test status
Simulation time 13461727006 ps
CPU time 95.04 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:10:33 PM PDT 24
Peak memory 249272 kb
Host smart-057240e0-cdd9-40ad-b90c-5d8e7aafc207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557162118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1557162118
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4280970251
Short name T969
Test name
Test status
Simulation time 3378250486 ps
CPU time 11.64 seconds
Started May 09 01:09:04 PM PDT 24
Finished May 09 01:09:16 PM PDT 24
Peak memory 249148 kb
Host smart-4c12a011-883f-4618-9d2e-6e57bb365540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280970251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4280970251
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2494860726
Short name T176
Test name
Test status
Simulation time 2975021331 ps
CPU time 9.45 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:10 PM PDT 24
Peak memory 238100 kb
Host smart-8e0b60ae-1ca5-45aa-a665-7cb408cabcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494860726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2494860726
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2728858908
Short name T690
Test name
Test status
Simulation time 1927135549 ps
CPU time 12.82 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:09:15 PM PDT 24
Peak memory 231648 kb
Host smart-ca7d2cf6-30ff-402b-a3f0-1f28422a25c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728858908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2728858908
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3138739395
Short name T599
Test name
Test status
Simulation time 27339840 ps
CPU time 1 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:08:59 PM PDT 24
Peak memory 217992 kb
Host smart-7ba6abb4-8e7b-4a91-baea-0dc346018904
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138739395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3138739395
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.325379113
Short name T245
Test name
Test status
Simulation time 20170343404 ps
CPU time 28.64 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:30 PM PDT 24
Peak memory 240600 kb
Host smart-7b75f6d3-39d6-409f-8355-6feb12badefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325379113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.325379113
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.509691890
Short name T877
Test name
Test status
Simulation time 1854644942 ps
CPU time 6.93 seconds
Started May 09 01:09:04 PM PDT 24
Finished May 09 01:09:12 PM PDT 24
Peak memory 218908 kb
Host smart-39afa7e8-dfe1-4d78-a840-686face6bf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509691890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.509691890
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.158007254
Short name T880
Test name
Test status
Simulation time 486356546 ps
CPU time 7.1 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:09:04 PM PDT 24
Peak memory 220432 kb
Host smart-aa032892-91e2-4107-bb14-99ba31c134c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=158007254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.158007254
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.115960155
Short name T242
Test name
Test status
Simulation time 181977608566 ps
CPU time 310.66 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:14:34 PM PDT 24
Peak memory 256276 kb
Host smart-bffae68c-4264-43f7-862d-e38058f2149e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115960155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.115960155
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.461114439
Short name T409
Test name
Test status
Simulation time 434407913 ps
CPU time 4.64 seconds
Started May 09 01:09:02 PM PDT 24
Finished May 09 01:09:08 PM PDT 24
Peak memory 219356 kb
Host smart-6a730dbf-df08-4b6e-9a10-210ab01414cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461114439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.461114439
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3519722633
Short name T468
Test name
Test status
Simulation time 562283894 ps
CPU time 2.82 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:04 PM PDT 24
Peak memory 216392 kb
Host smart-f72e669f-f552-4d6b-8870-2fabb3f32fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519722633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3519722633
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2519761964
Short name T765
Test name
Test status
Simulation time 55849276 ps
CPU time 1.83 seconds
Started May 09 01:09:00 PM PDT 24
Finished May 09 01:09:04 PM PDT 24
Peak memory 216420 kb
Host smart-c780a65f-d3f6-4c33-ac2d-3fbfcfaeb392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519761964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2519761964
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4248437281
Short name T636
Test name
Test status
Simulation time 155378720 ps
CPU time 0.92 seconds
Started May 09 01:08:59 PM PDT 24
Finished May 09 01:09:02 PM PDT 24
Peak memory 205852 kb
Host smart-1d1aa17a-5540-4b72-88b7-4043c6362c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248437281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4248437281
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1132561140
Short name T215
Test name
Test status
Simulation time 911376409 ps
CPU time 3.92 seconds
Started May 09 01:08:57 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 232740 kb
Host smart-6680671a-9085-4ea1-bdf7-a6b94ab50050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132561140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1132561140
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1012189074
Short name T838
Test name
Test status
Simulation time 520642037 ps
CPU time 3.91 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:27 PM PDT 24
Peak memory 234336 kb
Host smart-dc63c90d-1ffb-47e0-869a-cdc2d89e4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012189074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1012189074
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4107383247
Short name T856
Test name
Test status
Simulation time 18059955 ps
CPU time 0.78 seconds
Started May 09 01:09:26 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 205348 kb
Host smart-ac0614b7-b4a5-4712-9d16-516da0bbb5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107383247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4107383247
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2214792461
Short name T660
Test name
Test status
Simulation time 19286262653 ps
CPU time 50.08 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:10:16 PM PDT 24
Peak memory 254752 kb
Host smart-e327fedc-fdaa-492c-a6c2-e7947e317289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214792461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2214792461
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2317032802
Short name T42
Test name
Test status
Simulation time 13602740229 ps
CPU time 58.2 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:10:26 PM PDT 24
Peak memory 249392 kb
Host smart-2a296151-391a-4c4b-b525-b5720bc76e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317032802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2317032802
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.912174428
Short name T509
Test name
Test status
Simulation time 77751681 ps
CPU time 2.46 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:27 PM PDT 24
Peak memory 224524 kb
Host smart-e84d2be7-bce6-43fc-8742-fd7c839a0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912174428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.912174428
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2769887691
Short name T807
Test name
Test status
Simulation time 30052192 ps
CPU time 2.19 seconds
Started May 09 01:09:21 PM PDT 24
Finished May 09 01:09:24 PM PDT 24
Peak memory 221476 kb
Host smart-02864975-703c-4ec4-b0ca-dfebf3957c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769887691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2769887691
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2645974282
Short name T929
Test name
Test status
Simulation time 174882486 ps
CPU time 4.89 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:31 PM PDT 24
Peak memory 218468 kb
Host smart-60b9793e-5ef9-4bcb-bb57-2dd8bc2014a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645974282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2645974282
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2144574728
Short name T431
Test name
Test status
Simulation time 117077861 ps
CPU time 1.09 seconds
Started May 09 01:09:21 PM PDT 24
Finished May 09 01:09:23 PM PDT 24
Peak memory 216752 kb
Host smart-b8fbf2b6-3a31-42b6-86de-73c97d933684
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144574728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2144574728
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.525981113
Short name T614
Test name
Test status
Simulation time 3263228771 ps
CPU time 13.39 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:41 PM PDT 24
Peak memory 233764 kb
Host smart-49e5ba29-89ee-49b7-a460-8d823a0a9a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525981113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.525981113
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3898181831
Short name T584
Test name
Test status
Simulation time 8740037255 ps
CPU time 8.38 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:35 PM PDT 24
Peak memory 234272 kb
Host smart-01698844-73d5-4ccb-bde7-83dcfcd8dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898181831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3898181831
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.860858518
Short name T147
Test name
Test status
Simulation time 2525144853 ps
CPU time 14.42 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:40 PM PDT 24
Peak memory 220044 kb
Host smart-1f61830c-8b6e-483d-aa8e-1063d24311b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=860858518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.860858518
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1855563572
Short name T19
Test name
Test status
Simulation time 7070193373 ps
CPU time 61.62 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 254728 kb
Host smart-09143b3f-8ff8-4f3a-86d2-fc72e05b1150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855563572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1855563572
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.960717795
Short name T317
Test name
Test status
Simulation time 5945110744 ps
CPU time 20.37 seconds
Started May 09 01:09:20 PM PDT 24
Finished May 09 01:09:41 PM PDT 24
Peak memory 216520 kb
Host smart-ea15a883-8896-48c6-93bf-a062a01046de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960717795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.960717795
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2126247215
Short name T373
Test name
Test status
Simulation time 1510657819 ps
CPU time 4.01 seconds
Started May 09 01:09:26 PM PDT 24
Finished May 09 01:09:32 PM PDT 24
Peak memory 216316 kb
Host smart-70d5f0c1-4ab8-46f4-b336-63de4287741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126247215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2126247215
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.305745878
Short name T580
Test name
Test status
Simulation time 639563340 ps
CPU time 2.1 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:27 PM PDT 24
Peak memory 216468 kb
Host smart-b1c7f445-c306-470d-bd0e-3288f2c14526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305745878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.305745878
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3625971845
Short name T624
Test name
Test status
Simulation time 109909179 ps
CPU time 0.91 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:28 PM PDT 24
Peak memory 205828 kb
Host smart-9f374126-6a97-44da-952d-84aeb406c6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625971845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3625971845
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.443519399
Short name T778
Test name
Test status
Simulation time 448435132 ps
CPU time 5.28 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 236732 kb
Host smart-13f614c8-2c8b-4267-9ac6-0ff65ce527f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443519399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.443519399
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2346505200
Short name T632
Test name
Test status
Simulation time 28015843 ps
CPU time 0.7 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:25 PM PDT 24
Peak memory 204792 kb
Host smart-09c8aebc-b4fe-40c9-83ac-eefa9df6b324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346505200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2346505200
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.241793105
Short name T908
Test name
Test status
Simulation time 98350971 ps
CPU time 3.17 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:28 PM PDT 24
Peak memory 218548 kb
Host smart-a356e345-5bf6-4ca3-b36b-523cf96fd933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241793105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.241793105
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1079559221
Short name T477
Test name
Test status
Simulation time 14092175 ps
CPU time 0.79 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:25 PM PDT 24
Peak memory 206460 kb
Host smart-308b19a3-0561-40bb-b2f4-f37596ba82c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079559221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1079559221
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.234355006
Short name T246
Test name
Test status
Simulation time 1459760765 ps
CPU time 14.47 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:40 PM PDT 24
Peak memory 232812 kb
Host smart-9a836612-0e82-42f1-8294-503786b36dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234355006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.234355006
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.34148487
Short name T232
Test name
Test status
Simulation time 66064404212 ps
CPU time 312.18 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:14:40 PM PDT 24
Peak memory 262224 kb
Host smart-811cb4ff-9939-4b1a-9e52-8b1b36e770ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34148487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.34148487
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2340362298
Short name T272
Test name
Test status
Simulation time 6053774147 ps
CPU time 120.55 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:11:25 PM PDT 24
Peak memory 255324 kb
Host smart-06411172-ad8d-44f3-9503-b9f0c575829f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340362298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2340362298
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1815723849
Short name T860
Test name
Test status
Simulation time 38584148637 ps
CPU time 29.63 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:58 PM PDT 24
Peak memory 238272 kb
Host smart-60d27f50-43b1-4aba-9b95-926bdcf7e166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815723849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1815723849
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4144283776
Short name T132
Test name
Test status
Simulation time 2417540627 ps
CPU time 8.75 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:35 PM PDT 24
Peak memory 220616 kb
Host smart-5e1d1cc2-2c11-4c4b-9a84-439707146c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144283776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4144283776
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.192339839
Short name T627
Test name
Test status
Simulation time 119957743 ps
CPU time 2.16 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 216084 kb
Host smart-f041d42b-1b23-442c-a980-d05814540f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192339839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.192339839
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2543999416
Short name T699
Test name
Test status
Simulation time 49133795 ps
CPU time 1.05 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 216720 kb
Host smart-15e2e1eb-31c6-43ae-98b1-83c558793846
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543999416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2543999416
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.126609567
Short name T332
Test name
Test status
Simulation time 75611947 ps
CPU time 2.32 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 216092 kb
Host smart-98b4c5fc-7a9e-4da5-8a20-027a43981a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126609567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.126609567
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3995781218
Short name T438
Test name
Test status
Simulation time 7300557382 ps
CPU time 6.74 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:34 PM PDT 24
Peak memory 218664 kb
Host smart-f42fa193-fe53-40e9-b365-c484818640a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995781218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3995781218
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1834356814
Short name T741
Test name
Test status
Simulation time 149602650 ps
CPU time 4.01 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:31 PM PDT 24
Peak memory 223052 kb
Host smart-b37616df-b8e3-4de5-8b89-2c417121a057
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1834356814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1834356814
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.381528885
Short name T708
Test name
Test status
Simulation time 3700344937 ps
CPU time 17.95 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 220064 kb
Host smart-a7115175-2434-4152-9823-5566e1384a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381528885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.381528885
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2730216078
Short name T955
Test name
Test status
Simulation time 13489056 ps
CPU time 0.77 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:27 PM PDT 24
Peak memory 205568 kb
Host smart-5d2ebef7-fd14-49a9-a8ea-f4e659527254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730216078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2730216078
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3672589274
Short name T327
Test name
Test status
Simulation time 190073191 ps
CPU time 1.27 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:27 PM PDT 24
Peak memory 216624 kb
Host smart-4bf860a3-9397-4008-8926-069c22113c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672589274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3672589274
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3011212486
Short name T422
Test name
Test status
Simulation time 244534251 ps
CPU time 0.93 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:25 PM PDT 24
Peak memory 205864 kb
Host smart-53f7248a-0fa0-4960-baec-627d6f871af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011212486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3011212486
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1287559309
Short name T781
Test name
Test status
Simulation time 44773283164 ps
CPU time 30.91 seconds
Started May 09 01:09:21 PM PDT 24
Finished May 09 01:09:53 PM PDT 24
Peak memory 235852 kb
Host smart-77726ba6-7053-43de-87ea-acd614650d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287559309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1287559309
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2682268028
Short name T665
Test name
Test status
Simulation time 13808635 ps
CPU time 0.74 seconds
Started May 09 01:09:26 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 204684 kb
Host smart-e4934c47-71e5-4c24-8e76-15d71e916839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682268028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2682268028
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.181999330
Short name T89
Test name
Test status
Simulation time 1180701157 ps
CPU time 3.92 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:30 PM PDT 24
Peak memory 234264 kb
Host smart-19cd3b42-7aac-41c8-aa3a-0df11b59d42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181999330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.181999330
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.415839790
Short name T479
Test name
Test status
Simulation time 135071183 ps
CPU time 0.8 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:28 PM PDT 24
Peak memory 206804 kb
Host smart-0da15225-c5aa-4462-b6e5-a74f3b6155f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415839790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.415839790
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1781546863
Short name T692
Test name
Test status
Simulation time 192267734 ps
CPU time 0.79 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:26 PM PDT 24
Peak memory 216180 kb
Host smart-d1f461ad-74c5-40e9-a156-c87eb0bc895e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781546863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1781546863
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3584334782
Short name T320
Test name
Test status
Simulation time 15398760251 ps
CPU time 162.08 seconds
Started May 09 01:09:26 PM PDT 24
Finished May 09 01:12:10 PM PDT 24
Peak memory 249448 kb
Host smart-25c75335-98fe-4f68-a65d-7c7355e0fcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584334782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3584334782
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2805678143
Short name T472
Test name
Test status
Simulation time 3326798215 ps
CPU time 39.01 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:10:05 PM PDT 24
Peak memory 222016 kb
Host smart-32cc2387-f927-4119-b6ea-ed2d0b00336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805678143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2805678143
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2210463483
Short name T654
Test name
Test status
Simulation time 446355378 ps
CPU time 8.62 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:36 PM PDT 24
Peak memory 233744 kb
Host smart-39e3f11b-d7ca-4672-aa21-ba2870e787f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210463483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2210463483
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.82848610
Short name T664
Test name
Test status
Simulation time 129193659 ps
CPU time 3.2 seconds
Started May 09 01:09:21 PM PDT 24
Finished May 09 01:09:25 PM PDT 24
Peak memory 217672 kb
Host smart-1636841b-918d-4d30-bbc5-e129c4e87887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82848610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.82848610
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3849199452
Short name T674
Test name
Test status
Simulation time 1791190481 ps
CPU time 5.7 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:33 PM PDT 24
Peak memory 232756 kb
Host smart-86493ed1-aa4b-4737-a731-cb555c4f8a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849199452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3849199452
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.917007464
Short name T881
Test name
Test status
Simulation time 83226192 ps
CPU time 1.15 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:28 PM PDT 24
Peak memory 216740 kb
Host smart-bd782fa2-a3e6-45f6-bbdd-f5f54e4e8cc1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917007464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.917007464
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2231702005
Short name T361
Test name
Test status
Simulation time 42056529 ps
CPU time 2.2 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 218756 kb
Host smart-460bf173-dade-4b36-9dfc-c21cf1dbebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231702005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2231702005
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1953441479
Short name T962
Test name
Test status
Simulation time 114533787 ps
CPU time 2.23 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 216216 kb
Host smart-03f8202b-39ce-42a4-8bcd-8408e56972a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953441479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1953441479
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1499459761
Short name T549
Test name
Test status
Simulation time 1188097828 ps
CPU time 12.9 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:40 PM PDT 24
Peak memory 219640 kb
Host smart-ab792355-4eeb-4e91-88ce-bab33608474a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1499459761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1499459761
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1004224808
Short name T417
Test name
Test status
Simulation time 25052383636 ps
CPU time 234.51 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:13:22 PM PDT 24
Peak memory 249460 kb
Host smart-60b7f971-c656-4433-9005-52f01180aa2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004224808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1004224808
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.499666107
Short name T321
Test name
Test status
Simulation time 2981980520 ps
CPU time 8.31 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:34 PM PDT 24
Peak memory 216480 kb
Host smart-020d4d4f-29ec-4c33-8a11-081a8ca357f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499666107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.499666107
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3067458396
Short name T385
Test name
Test status
Simulation time 18008638367 ps
CPU time 21.4 seconds
Started May 09 01:09:24 PM PDT 24
Finished May 09 01:09:48 PM PDT 24
Peak memory 216604 kb
Host smart-d9f12131-eda7-47be-bac8-96bad90b62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067458396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3067458396
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2796639872
Short name T872
Test name
Test status
Simulation time 154040098 ps
CPU time 3.59 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:31 PM PDT 24
Peak memory 216364 kb
Host smart-5b95063a-ebe0-42f9-81af-2fdfd3e08742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796639872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2796639872
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.971649885
Short name T630
Test name
Test status
Simulation time 660911161 ps
CPU time 0.86 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:27 PM PDT 24
Peak memory 205804 kb
Host smart-b408b5eb-765e-47b4-8163-5b2494580e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971649885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.971649885
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3402012259
Short name T387
Test name
Test status
Simulation time 1860664282 ps
CPU time 4.22 seconds
Started May 09 01:09:23 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 234380 kb
Host smart-37b17b2c-8dcc-4878-9bbf-62947f644d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402012259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3402012259
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1423754375
Short name T683
Test name
Test status
Simulation time 43136477 ps
CPU time 0.71 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 204668 kb
Host smart-41fb8174-549e-4309-9b6b-e7341487b836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423754375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1423754375
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.926758441
Short name T839
Test name
Test status
Simulation time 312623670 ps
CPU time 2.21 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:09:38 PM PDT 24
Peak memory 216212 kb
Host smart-cf65eb9e-57e8-4db8-a444-05faf63920d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926758441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.926758441
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3592531709
Short name T718
Test name
Test status
Simulation time 27997692 ps
CPU time 0.82 seconds
Started May 09 01:09:25 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 206468 kb
Host smart-47518b9d-4672-4ab8-931d-514579a8b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592531709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3592531709
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1445291499
Short name T506
Test name
Test status
Simulation time 14837772678 ps
CPU time 49.69 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:10:30 PM PDT 24
Peak memory 249276 kb
Host smart-24d83566-fe47-49ee-9ed9-ce169f72dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445291499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1445291499
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.863428141
Short name T966
Test name
Test status
Simulation time 2320472383 ps
CPU time 23.43 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:10:00 PM PDT 24
Peak memory 241196 kb
Host smart-1161f06e-f9a6-4e3f-bfe1-552b97667839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863428141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.863428141
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1717816090
Short name T878
Test name
Test status
Simulation time 1106194874 ps
CPU time 7.34 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 235332 kb
Host smart-1b9acda3-c82f-433f-a8c4-f90c168230a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717816090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1717816090
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2441133055
Short name T50
Test name
Test status
Simulation time 3218936688 ps
CPU time 17.68 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 224600 kb
Host smart-193db109-0ba3-411d-9495-ce6ace867bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441133055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2441133055
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.155065550
Short name T658
Test name
Test status
Simulation time 2526099631 ps
CPU time 3.44 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:09:44 PM PDT 24
Peak memory 217952 kb
Host smart-910d5af7-caf5-492b-9b6b-98a7f32fc2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155065550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.155065550
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1785932511
Short name T884
Test name
Test status
Simulation time 33746059 ps
CPU time 1.14 seconds
Started May 09 01:09:22 PM PDT 24
Finished May 09 01:09:24 PM PDT 24
Peak memory 216732 kb
Host smart-fb9ff1ff-f238-4e04-9de1-1945ad85371b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785932511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1785932511
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1390445942
Short name T8
Test name
Test status
Simulation time 3849716316 ps
CPU time 10.13 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:47 PM PDT 24
Peak memory 249076 kb
Host smart-d0813046-6e9b-42c6-b69b-cf9d5f2da49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390445942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1390445942
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.468977010
Short name T619
Test name
Test status
Simulation time 272361419 ps
CPU time 4.23 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:43 PM PDT 24
Peak memory 222480 kb
Host smart-1855b27a-0828-4bc8-8ecb-2bea13160820
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=468977010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.468977010
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.424678643
Short name T490
Test name
Test status
Simulation time 7521557114 ps
CPU time 18.88 seconds
Started May 09 01:09:40 PM PDT 24
Finished May 09 01:10:01 PM PDT 24
Peak memory 216588 kb
Host smart-52ee4e15-81fe-4e1a-87dd-b0584de6549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424678643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.424678643
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2152828338
Short name T618
Test name
Test status
Simulation time 10336253546 ps
CPU time 7.43 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:09:44 PM PDT 24
Peak memory 216416 kb
Host smart-8246d014-4e1f-442e-8b5e-adfa70b2887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152828338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2152828338
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1978242398
Short name T324
Test name
Test status
Simulation time 158413601 ps
CPU time 2.65 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:09:38 PM PDT 24
Peak memory 208148 kb
Host smart-e7b7eb46-400e-48a8-a09d-ac43cd29401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978242398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1978242398
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2744996053
Short name T924
Test name
Test status
Simulation time 222952666 ps
CPU time 0.8 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:09:35 PM PDT 24
Peak memory 205840 kb
Host smart-369ed10c-ff16-4232-90be-1bdd4f6803a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744996053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2744996053
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1332743424
Short name T292
Test name
Test status
Simulation time 807898066 ps
CPU time 7.49 seconds
Started May 09 01:09:41 PM PDT 24
Finished May 09 01:09:50 PM PDT 24
Peak memory 240824 kb
Host smart-6a771895-abf4-475e-9633-f1372740d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332743424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1332743424
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3691345476
Short name T815
Test name
Test status
Simulation time 179990069 ps
CPU time 0.77 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:09:35 PM PDT 24
Peak memory 204704 kb
Host smart-bd55f8ce-831f-4157-8e10-418a32a21325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691345476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3691345476
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1273439717
Short name T727
Test name
Test status
Simulation time 248715024 ps
CPU time 3.18 seconds
Started May 09 01:09:33 PM PDT 24
Finished May 09 01:09:38 PM PDT 24
Peak memory 234168 kb
Host smart-7ead9e46-c8fa-4547-b70c-9fb64387ac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273439717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1273439717
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2302177902
Short name T578
Test name
Test status
Simulation time 54459940 ps
CPU time 0.76 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:38 PM PDT 24
Peak memory 206424 kb
Host smart-5b51813e-1d30-4d28-a2c8-8456a2a38fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302177902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2302177902
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.583701779
Short name T183
Test name
Test status
Simulation time 31968072734 ps
CPU time 115.76 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:11:34 PM PDT 24
Peak memory 269764 kb
Host smart-e7320fd0-5844-491d-aa46-144d5035c8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583701779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.583701779
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1499094656
Short name T392
Test name
Test status
Simulation time 3792241685 ps
CPU time 30.97 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:10:06 PM PDT 24
Peak memory 238852 kb
Host smart-6dd91d28-22ef-44c3-92aa-2eecd1c88f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499094656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1499094656
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2928679001
Short name T603
Test name
Test status
Simulation time 7475306615 ps
CPU time 24.44 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:10:06 PM PDT 24
Peak memory 236980 kb
Host smart-58da6c37-c4a8-4eba-ae9e-8d8086c2d696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928679001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2928679001
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3201547768
Short name T447
Test name
Test status
Simulation time 81971945 ps
CPU time 2.91 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:41 PM PDT 24
Peak memory 232756 kb
Host smart-a64dbb63-1e51-4b5b-aefa-2de0394ed8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201547768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3201547768
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.61311098
Short name T92
Test name
Test status
Simulation time 7831902048 ps
CPU time 20.23 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:58 PM PDT 24
Peak memory 233972 kb
Host smart-884be720-656a-4e7b-a67a-b5fc9743cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61311098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.61311098
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2658374175
Short name T465
Test name
Test status
Simulation time 126650415514 ps
CPU time 77.87 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 218080 kb
Host smart-b6a6a6f6-dc67-4dc9-8c58-1bd37993b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658374175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2658374175
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3609640259
Short name T755
Test name
Test status
Simulation time 58051897 ps
CPU time 1.09 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:39 PM PDT 24
Peak memory 216764 kb
Host smart-1eb8f624-c632-4973-93af-3953fd84c287
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609640259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3609640259
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1727526228
Short name T250
Test name
Test status
Simulation time 4045071897 ps
CPU time 12.1 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:49 PM PDT 24
Peak memory 229212 kb
Host smart-1609bdc9-f023-445b-9a32-fe9802447f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727526228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1727526228
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2142156145
Short name T707
Test name
Test status
Simulation time 861700493 ps
CPU time 4.33 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 224524 kb
Host smart-566aa1c1-0940-4b41-bae0-f6e2c17561d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142156145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2142156145
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4071023162
Short name T491
Test name
Test status
Simulation time 1849974499 ps
CPU time 9.7 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 219280 kb
Host smart-2b8bed8c-7cd0-4367-9d60-cc13dd042803
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4071023162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4071023162
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2123979911
Short name T189
Test name
Test status
Simulation time 64773855875 ps
CPU time 247.69 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:13:46 PM PDT 24
Peak memory 249384 kb
Host smart-962da9c6-92f2-43c8-9e48-5cb6b95235fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123979911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2123979911
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.61390077
Short name T714
Test name
Test status
Simulation time 1237719370 ps
CPU time 13.35 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 219480 kb
Host smart-42d5264a-3666-4c8b-9c66-d6ae258f2f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61390077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.61390077
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2053154779
Short name T825
Test name
Test status
Simulation time 39804833571 ps
CPU time 19.46 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:10:00 PM PDT 24
Peak memory 216436 kb
Host smart-67a5801c-8412-45e8-a520-bbae86c20046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053154779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2053154779
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3092843247
Short name T382
Test name
Test status
Simulation time 201991903 ps
CPU time 0.99 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:38 PM PDT 24
Peak memory 206768 kb
Host smart-3983dbcb-c3e5-4b1e-8c42-6459bcf18795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092843247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3092843247
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2036939918
Short name T414
Test name
Test status
Simulation time 84773618 ps
CPU time 0.85 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:40 PM PDT 24
Peak memory 205892 kb
Host smart-e25f8f31-585f-4c2e-947b-0d01296ca1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036939918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2036939918
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3533614642
Short name T135
Test name
Test status
Simulation time 457463058 ps
CPU time 3.01 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:09:43 PM PDT 24
Peak memory 236112 kb
Host smart-557035e8-0bbd-4036-a612-9599b13e0e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533614642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3533614642
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2016958635
Short name T613
Test name
Test status
Simulation time 54517261 ps
CPU time 0.69 seconds
Started May 09 01:08:19 PM PDT 24
Finished May 09 01:08:20 PM PDT 24
Peak memory 204728 kb
Host smart-6d2374c1-bc67-4383-b03e-731206c46522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016958635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
016958635
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1975651854
Short name T595
Test name
Test status
Simulation time 438231120 ps
CPU time 4.65 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:17 PM PDT 24
Peak memory 219644 kb
Host smart-7f32feaf-faf2-47ba-904d-a6b3dca3bf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975651854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1975651854
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1593114602
Short name T738
Test name
Test status
Simulation time 24659357 ps
CPU time 0.77 seconds
Started May 09 01:08:16 PM PDT 24
Finished May 09 01:08:18 PM PDT 24
Peak memory 206368 kb
Host smart-03804ff1-06b8-49b5-aaff-0e5c79909e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593114602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1593114602
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1369652018
Short name T258
Test name
Test status
Simulation time 8405840732 ps
CPU time 112.56 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:10:05 PM PDT 24
Peak memory 252516 kb
Host smart-6960e606-8c18-456d-b76a-f4624d1531e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369652018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1369652018
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1359964029
Short name T408
Test name
Test status
Simulation time 9619395035 ps
CPU time 20.72 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:32 PM PDT 24
Peak memory 217432 kb
Host smart-936f203a-8850-4cc4-a970-6af34cd5b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359964029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1359964029
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.630241521
Short name T859
Test name
Test status
Simulation time 26001222550 ps
CPU time 137.55 seconds
Started May 09 01:08:13 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 254828 kb
Host smart-947ed22a-29fd-4970-a054-a0616fe46988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630241521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
630241521
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1038780274
Short name T772
Test name
Test status
Simulation time 1572198290 ps
CPU time 9.73 seconds
Started May 09 01:08:19 PM PDT 24
Finished May 09 01:08:30 PM PDT 24
Peak memory 224508 kb
Host smart-8720ee2d-03c8-4687-a7a1-b079df06f8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038780274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1038780274
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1099229228
Short name T483
Test name
Test status
Simulation time 2570375440 ps
CPU time 7.63 seconds
Started May 09 01:08:09 PM PDT 24
Finished May 09 01:08:19 PM PDT 24
Peak memory 217780 kb
Host smart-795b5fa6-1b26-477a-aea7-675cc7f443c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099229228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1099229228
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1939968595
Short name T703
Test name
Test status
Simulation time 1801565064 ps
CPU time 10.58 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:08:27 PM PDT 24
Peak memory 234428 kb
Host smart-60cb3a2e-37fb-449a-9e6b-aabce62b2eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939968595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1939968595
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2603809098
Short name T379
Test name
Test status
Simulation time 30805962 ps
CPU time 1.05 seconds
Started May 09 01:08:11 PM PDT 24
Finished May 09 01:08:14 PM PDT 24
Peak memory 216740 kb
Host smart-73d3b36e-3dd9-4130-a9bf-0112d18149b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603809098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2603809098
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4004029056
Short name T715
Test name
Test status
Simulation time 318029436 ps
CPU time 2.72 seconds
Started May 09 01:08:12 PM PDT 24
Finished May 09 01:08:17 PM PDT 24
Peak memory 232780 kb
Host smart-672749f6-b0cd-435b-9632-399232f761be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004029056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4004029056
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.162211292
Short name T912
Test name
Test status
Simulation time 4522332729 ps
CPU time 15.81 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:08:28 PM PDT 24
Peak memory 233664 kb
Host smart-90fd1e40-0c98-4a17-a6bb-37ff6211d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162211292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.162211292
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3717450374
Short name T818
Test name
Test status
Simulation time 147744632 ps
CPU time 3.4 seconds
Started May 09 01:08:16 PM PDT 24
Finished May 09 01:08:21 PM PDT 24
Peak memory 220000 kb
Host smart-5ef5c69a-b363-4d02-b630-2731c5b95840
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3717450374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3717450374
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.215558475
Short name T318
Test name
Test status
Simulation time 5189891632 ps
CPU time 22.64 seconds
Started May 09 01:08:14 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 216568 kb
Host smart-6ef0fcbd-047e-4db1-88c1-d3029f4b8ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215558475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.215558475
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2332991609
Short name T530
Test name
Test status
Simulation time 737143727 ps
CPU time 4.98 seconds
Started May 09 01:08:18 PM PDT 24
Finished May 09 01:08:24 PM PDT 24
Peak memory 216368 kb
Host smart-10dc2ed5-405e-485f-972b-7e24eb6f75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332991609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2332991609
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1763951925
Short name T814
Test name
Test status
Simulation time 757467176 ps
CPU time 5.51 seconds
Started May 09 01:08:13 PM PDT 24
Finished May 09 01:08:20 PM PDT 24
Peak memory 216416 kb
Host smart-95885411-bc24-4a6b-9a1c-7cecbf25ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763951925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1763951925
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2033443332
Short name T677
Test name
Test status
Simulation time 420167413 ps
CPU time 1.04 seconds
Started May 09 01:08:10 PM PDT 24
Finished May 09 01:08:13 PM PDT 24
Peak memory 206844 kb
Host smart-7dada2bd-954e-4f23-834b-76b7fec8b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033443332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2033443332
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1188022470
Short name T605
Test name
Test status
Simulation time 7777968773 ps
CPU time 27.41 seconds
Started May 09 01:08:13 PM PDT 24
Finished May 09 01:08:43 PM PDT 24
Peak memory 250640 kb
Host smart-687c6469-9170-4c57-9b13-ead6b4c5ea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188022470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1188022470
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3008548113
Short name T796
Test name
Test status
Simulation time 24666555 ps
CPU time 0.71 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 204696 kb
Host smart-531c9def-1889-4bc8-8e9d-1b1da50c9c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008548113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3008548113
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2460107330
Short name T873
Test name
Test status
Simulation time 198230411 ps
CPU time 4.01 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:43 PM PDT 24
Peak memory 218620 kb
Host smart-64d2f4e5-4cce-4dfb-9506-eff79e045e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460107330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2460107330
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.307865206
Short name T726
Test name
Test status
Simulation time 18463359 ps
CPU time 0.76 seconds
Started May 09 01:09:33 PM PDT 24
Finished May 09 01:09:34 PM PDT 24
Peak memory 205460 kb
Host smart-49bb2ee2-1a8b-4bb2-a0be-5bb27708008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307865206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.307865206
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2333337428
Short name T29
Test name
Test status
Simulation time 83226846537 ps
CPU time 106.71 seconds
Started May 09 01:09:40 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 232844 kb
Host smart-e9859803-a961-4982-a0eb-aaec6711226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333337428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2333337428
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1979171331
Short name T280
Test name
Test status
Simulation time 91005914588 ps
CPU time 607.85 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:19:45 PM PDT 24
Peak memory 264620 kb
Host smart-1ce30643-570f-430f-8004-b7a4dbb68ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979171331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1979171331
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3897384494
Short name T470
Test name
Test status
Simulation time 18219165482 ps
CPU time 92.74 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:11:10 PM PDT 24
Peak memory 250180 kb
Host smart-fbbd80a2-4d8b-4156-889b-c079f5ee47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897384494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3897384494
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2573613016
Short name T736
Test name
Test status
Simulation time 609139169 ps
CPU time 10.85 seconds
Started May 09 01:09:41 PM PDT 24
Finished May 09 01:09:53 PM PDT 24
Peak memory 240916 kb
Host smart-c2e6c2ec-ca92-4cb3-802d-d180bdc8d822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573613016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2573613016
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.740906712
Short name T163
Test name
Test status
Simulation time 394788988 ps
CPU time 6.15 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:44 PM PDT 24
Peak memory 235236 kb
Host smart-c861b4f6-e2ec-45cd-851f-91a45b15c04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740906712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.740906712
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.190143585
Short name T297
Test name
Test status
Simulation time 441736152 ps
CPU time 5.84 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:09:46 PM PDT 24
Peak memory 237096 kb
Host smart-b18d3e41-be4c-4411-b8ce-38222e06dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190143585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.190143585
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.862241482
Short name T51
Test name
Test status
Simulation time 799785994 ps
CPU time 3.08 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:43 PM PDT 24
Peak memory 233616 kb
Host smart-5a623eba-461c-4ee4-8367-5f689229fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862241482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.862241482
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2573127197
Short name T464
Test name
Test status
Simulation time 814273948 ps
CPU time 3.19 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:44 PM PDT 24
Peak memory 218772 kb
Host smart-62f01b77-e230-48b8-8770-0c0a672fe49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573127197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2573127197
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3565510762
Short name T923
Test name
Test status
Simulation time 1012027065 ps
CPU time 6.07 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 221996 kb
Host smart-462fcdae-5152-460f-8f67-9debc607b8d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3565510762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3565510762
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3175417609
Short name T713
Test name
Test status
Simulation time 103113016 ps
CPU time 1.13 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 206964 kb
Host smart-cd79aa2e-9df5-4a30-be1b-fea9255a852b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175417609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3175417609
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3929778325
Short name T861
Test name
Test status
Simulation time 4046649102 ps
CPU time 30.49 seconds
Started May 09 01:09:32 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 216472 kb
Host smart-e327360d-189a-4f96-b757-d1db3aa52a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929778325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3929778325
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4175411465
Short name T48
Test name
Test status
Simulation time 1640527123 ps
CPU time 9.43 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:47 PM PDT 24
Peak memory 216332 kb
Host smart-2c588238-84d4-4470-9712-a44e659add48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175411465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4175411465
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1505414859
Short name T565
Test name
Test status
Simulation time 23373993 ps
CPU time 0.97 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:39 PM PDT 24
Peak memory 207136 kb
Host smart-ca074fd4-e49d-4ae0-a219-cc64a4063e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505414859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1505414859
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1379908798
Short name T749
Test name
Test status
Simulation time 123144669 ps
CPU time 0.84 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 205772 kb
Host smart-83ab5e73-dff0-496f-9a8e-b631a4c5b22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379908798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1379908798
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3558754477
Short name T442
Test name
Test status
Simulation time 977639150 ps
CPU time 3.93 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 234100 kb
Host smart-0794c6da-d921-462d-8436-6154a0bb7ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558754477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3558754477
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2947612539
Short name T787
Test name
Test status
Simulation time 15021077 ps
CPU time 0.78 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 205368 kb
Host smart-b47aa492-e958-439d-9af5-e067cd1864e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947612539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2947612539
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1338498751
Short name T702
Test name
Test status
Simulation time 207971313 ps
CPU time 2.51 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:40 PM PDT 24
Peak memory 218524 kb
Host smart-5b1bf235-2e6a-446c-9ec9-a6c876d157ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338498751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1338498751
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1418512431
Short name T492
Test name
Test status
Simulation time 18981651 ps
CPU time 0.85 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:09:37 PM PDT 24
Peak memory 206732 kb
Host smart-27ac1253-3d91-400a-9035-4c64830fceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418512431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1418512431
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2603558545
Short name T203
Test name
Test status
Simulation time 19346840435 ps
CPU time 67.23 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:10:42 PM PDT 24
Peak memory 250308 kb
Host smart-181c584e-d079-44ec-a048-ae219b6e48fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603558545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2603558545
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3995207066
Short name T783
Test name
Test status
Simulation time 23806293296 ps
CPU time 198.91 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:12:58 PM PDT 24
Peak memory 249288 kb
Host smart-7b1a2ec8-db96-456e-acc6-4b286847177d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995207066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3995207066
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.247629733
Short name T788
Test name
Test status
Simulation time 26587620154 ps
CPU time 251.7 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:13:52 PM PDT 24
Peak memory 257472 kb
Host smart-95946c00-4755-4e57-8e0f-cd3e3784f43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247629733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.247629733
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.486534035
Short name T475
Test name
Test status
Simulation time 148129548 ps
CPU time 3.25 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 224584 kb
Host smart-57f7c9ab-104c-4a6b-96fd-873b046121c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486534035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.486534035
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.436249472
Short name T372
Test name
Test status
Simulation time 190027700 ps
CPU time 4.39 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 219356 kb
Host smart-89acc394-c85d-431d-b36f-897abd1ecbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436249472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.436249472
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1056110155
Short name T785
Test name
Test status
Simulation time 8782819603 ps
CPU time 94.54 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:11:15 PM PDT 24
Peak memory 227832 kb
Host smart-2230b883-12a7-4398-8323-96a7b70e3508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056110155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1056110155
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.17847315
Short name T251
Test name
Test status
Simulation time 343870947 ps
CPU time 3.39 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:09:39 PM PDT 24
Peak memory 218888 kb
Host smart-dffe923e-f603-4987-8033-7ac9bad6b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17847315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.17847315
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1684411884
Short name T389
Test name
Test status
Simulation time 884485717 ps
CPU time 4.15 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:09:39 PM PDT 24
Peak memory 233776 kb
Host smart-064df432-b042-4774-8dc2-6de90216cb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684411884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1684411884
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2244626723
Short name T457
Test name
Test status
Simulation time 119777774 ps
CPU time 4.7 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 222984 kb
Host smart-0c4ba870-3d32-4241-82c3-4bc4e50d9d70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2244626723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2244626723
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3020476605
Short name T167
Test name
Test status
Simulation time 342912750622 ps
CPU time 118.12 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:11:39 PM PDT 24
Peak memory 224704 kb
Host smart-970f6148-6c17-49af-aa4b-e4d0775a3b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020476605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3020476605
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.103449806
Short name T669
Test name
Test status
Simulation time 4477807435 ps
CPU time 11.5 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:53 PM PDT 24
Peak memory 216488 kb
Host smart-5ec5e249-9574-40e2-bbee-b71475aa6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103449806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.103449806
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2652814389
Short name T73
Test name
Test status
Simulation time 11162950321 ps
CPU time 9.59 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:48 PM PDT 24
Peak memory 216476 kb
Host smart-972e963e-28f8-42a7-90e1-95dd56d7caa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652814389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2652814389
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.157664351
Short name T416
Test name
Test status
Simulation time 513073498 ps
CPU time 2.61 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 216436 kb
Host smart-7b6b2f65-6679-4bae-a2cd-d6f976b17061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157664351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.157664351
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3930301113
Short name T916
Test name
Test status
Simulation time 104580778 ps
CPU time 1.02 seconds
Started May 09 01:09:36 PM PDT 24
Finished May 09 01:09:39 PM PDT 24
Peak memory 205900 kb
Host smart-cdfd309c-2f2e-4955-8c54-8f2317912d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930301113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3930301113
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3264175703
Short name T395
Test name
Test status
Simulation time 570590473 ps
CPU time 3.5 seconds
Started May 09 01:09:40 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 224592 kb
Host smart-ceda0cb3-add4-45df-bac8-bc09fa65531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264175703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3264175703
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3392665044
Short name T452
Test name
Test status
Simulation time 22873944 ps
CPU time 0.74 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:09:53 PM PDT 24
Peak memory 205736 kb
Host smart-cf419110-2009-4b2c-adfa-4a869e9ada6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392665044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3392665044
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1928478493
Short name T871
Test name
Test status
Simulation time 238483593 ps
CPU time 5.63 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 233912 kb
Host smart-f276762a-6e6e-4e6f-a3ea-906b6891769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928478493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1928478493
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1918746843
Short name T641
Test name
Test status
Simulation time 25017801 ps
CPU time 0.75 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:42 PM PDT 24
Peak memory 205424 kb
Host smart-0e1569b9-71e1-4e3c-be29-d19ecb66d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918746843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1918746843
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1170580459
Short name T517
Test name
Test status
Simulation time 119621659587 ps
CPU time 202.18 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:13:12 PM PDT 24
Peak memory 249328 kb
Host smart-de8ed912-7563-4ff4-8bcb-560316177430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170580459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1170580459
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2648093771
Short name T188
Test name
Test status
Simulation time 137657978676 ps
CPU time 317.42 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:15:08 PM PDT 24
Peak memory 265644 kb
Host smart-60797ed0-cd7d-4b18-b3f8-afe56bdd4a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648093771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2648093771
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.644686873
Short name T293
Test name
Test status
Simulation time 2875855281 ps
CPU time 63.48 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 249392 kb
Host smart-16c7452a-09f7-40a8-94c3-efde0fc9568b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644686873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.644686873
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1172450144
Short name T37
Test name
Test status
Simulation time 2319941600 ps
CPU time 7.77 seconds
Started May 09 01:09:37 PM PDT 24
Finished May 09 01:09:48 PM PDT 24
Peak memory 249328 kb
Host smart-a5cb65d4-3993-42c7-b1f3-94d48d5fc9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172450144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1172450144
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2878092057
Short name T39
Test name
Test status
Simulation time 537035068 ps
CPU time 8.04 seconds
Started May 09 01:09:41 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 218852 kb
Host smart-2aea7c71-7a6f-414d-958d-f1aec371d149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878092057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2878092057
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2495851435
Short name T460
Test name
Test status
Simulation time 1423974502 ps
CPU time 14.49 seconds
Started May 09 01:09:35 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 226096 kb
Host smart-e8649ec2-3704-45be-b851-5fe96d3e4116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495851435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2495851435
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2442606468
Short name T236
Test name
Test status
Simulation time 2916060769 ps
CPU time 4.44 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:09:45 PM PDT 24
Peak memory 233788 kb
Host smart-403215a2-402e-4335-b4d5-6d3349a50728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442606468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2442606468
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1919396777
Short name T587
Test name
Test status
Simulation time 4019351863 ps
CPU time 7.75 seconds
Started May 09 01:09:42 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 219348 kb
Host smart-5beec2bf-4989-4c7e-b24c-47e250cb5ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919396777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1919396777
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1583213174
Short name T849
Test name
Test status
Simulation time 4181419612 ps
CPU time 5.96 seconds
Started May 09 01:09:38 PM PDT 24
Finished May 09 01:09:47 PM PDT 24
Peak memory 223060 kb
Host smart-f859c262-bc35-437f-a70b-73616e4749dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1583213174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1583213174
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2713382752
Short name T141
Test name
Test status
Simulation time 208927516147 ps
CPU time 422.27 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:16:54 PM PDT 24
Peak memory 253704 kb
Host smart-2e7f4853-0b4e-41a2-abc7-93eaefb20b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713382752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2713382752
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2917781482
Short name T932
Test name
Test status
Simulation time 1171351768 ps
CPU time 7.79 seconds
Started May 09 01:09:42 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 216648 kb
Host smart-4252610e-a457-4e3b-95bd-b956ec14b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917781482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2917781482
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3800136197
Short name T903
Test name
Test status
Simulation time 731589184 ps
CPU time 2.68 seconds
Started May 09 01:09:39 PM PDT 24
Finished May 09 01:09:44 PM PDT 24
Peak memory 206988 kb
Host smart-ef106fd7-0f1d-40c3-af91-ce06dc5c41c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800136197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3800136197
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.72990758
Short name T701
Test name
Test status
Simulation time 396910336 ps
CPU time 5.11 seconds
Started May 09 01:09:42 PM PDT 24
Finished May 09 01:09:48 PM PDT 24
Peak memory 216712 kb
Host smart-764e3720-c586-4c18-ace0-c71103dcd40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72990758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.72990758
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.363287659
Short name T446
Test name
Test status
Simulation time 36908165 ps
CPU time 0.78 seconds
Started May 09 01:09:42 PM PDT 24
Finished May 09 01:09:44 PM PDT 24
Peak memory 206108 kb
Host smart-e5e082b1-4f4b-47de-91fa-e315bb4eb5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363287659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.363287659
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.612843609
Short name T893
Test name
Test status
Simulation time 15367348645 ps
CPU time 29.48 seconds
Started May 09 01:09:34 PM PDT 24
Finished May 09 01:10:04 PM PDT 24
Peak memory 239352 kb
Host smart-e06152bf-284b-4a54-b2ff-114fc304683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612843609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.612843609
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.332341723
Short name T571
Test name
Test status
Simulation time 62979275 ps
CPU time 0.69 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 205376 kb
Host smart-3cc42ca2-6240-45b4-a429-5ff6e80cd5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332341723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.332341723
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4251198308
Short name T54
Test name
Test status
Simulation time 330587965 ps
CPU time 7.8 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:10:02 PM PDT 24
Peak memory 233760 kb
Host smart-89755bd1-c5c2-4035-8afc-ebf40f91cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251198308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4251198308
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4081906237
Short name T655
Test name
Test status
Simulation time 21233088 ps
CPU time 0.82 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:09:51 PM PDT 24
Peak memory 206412 kb
Host smart-174cab47-f7c1-4484-bc50-dd09d93e7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081906237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4081906237
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.4158896344
Short name T227
Test name
Test status
Simulation time 121240761786 ps
CPU time 441.56 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:17:18 PM PDT 24
Peak memory 249284 kb
Host smart-6a97ad2e-bbbd-4d21-83d0-2005b8c893db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158896344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4158896344
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3397180424
Short name T271
Test name
Test status
Simulation time 7910839250 ps
CPU time 60.72 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 241272 kb
Host smart-45303a56-fa12-4ba4-abd0-1ec17486278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397180424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3397180424
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1365042502
Short name T486
Test name
Test status
Simulation time 5085712307 ps
CPU time 98.11 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 255948 kb
Host smart-9984dba2-166d-45f4-8418-0456b1e32259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365042502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1365042502
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2940303465
Short name T697
Test name
Test status
Simulation time 629710388 ps
CPU time 8.71 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:10:04 PM PDT 24
Peak memory 236520 kb
Host smart-06a59532-2503-4d6f-bfd5-fa44e0d2713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940303465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2940303465
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3674377944
Short name T279
Test name
Test status
Simulation time 5731071697 ps
CPU time 11.55 seconds
Started May 09 01:09:55 PM PDT 24
Finished May 09 01:10:08 PM PDT 24
Peak memory 219688 kb
Host smart-367c8179-bc5c-43db-b7bd-7bee868293d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674377944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3674377944
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2052451436
Short name T754
Test name
Test status
Simulation time 47549770760 ps
CPU time 90.88 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:11:25 PM PDT 24
Peak memory 219752 kb
Host smart-79d158ab-a68b-458e-a34c-695a9e1a0bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052451436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2052451436
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3792256131
Short name T647
Test name
Test status
Simulation time 166726367 ps
CPU time 2.97 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 233900 kb
Host smart-29d3f44e-5d15-457b-9482-b1f5c299e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792256131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3792256131
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2392699048
Short name T554
Test name
Test status
Simulation time 45222160 ps
CPU time 2.38 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 221616 kb
Host smart-ccbfd6ac-3440-405f-ad25-4cd1cb674e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392699048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2392699048
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1715966828
Short name T776
Test name
Test status
Simulation time 895019971 ps
CPU time 3.65 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:09:55 PM PDT 24
Peak memory 220416 kb
Host smart-5b4e1409-4d26-4710-ab5f-22133a893c1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1715966828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1715966828
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1708047794
Short name T289
Test name
Test status
Simulation time 23008577224 ps
CPU time 128.85 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:12:03 PM PDT 24
Peak memory 253772 kb
Host smart-6428c139-5cea-4208-8311-45c56cb91619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708047794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1708047794
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.882403289
Short name T322
Test name
Test status
Simulation time 6144711798 ps
CPU time 37.94 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 216536 kb
Host smart-793a511a-3b83-4744-9d99-039bc6996224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882403289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.882403289
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.753893654
Short name T444
Test name
Test status
Simulation time 5666605073 ps
CPU time 16.01 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:10:09 PM PDT 24
Peak memory 216520 kb
Host smart-2c4109d5-bd40-4328-a452-502f71f6242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753893654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.753893654
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.824398620
Short name T461
Test name
Test status
Simulation time 167762687 ps
CPU time 4.97 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 216320 kb
Host smart-0340ef4e-1c5b-4068-a3b4-92cbca9d4f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824398620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.824398620
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.279839837
Short name T331
Test name
Test status
Simulation time 100652633 ps
CPU time 0.75 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 205836 kb
Host smart-573aae69-991d-4872-8a6c-0890971533b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279839837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.279839837
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3480445956
Short name T199
Test name
Test status
Simulation time 10486449798 ps
CPU time 8.96 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:10:01 PM PDT 24
Peak memory 219144 kb
Host smart-6afd5f4e-2761-4d47-8dd9-b6cbebfcbca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480445956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3480445956
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2348783659
Short name T920
Test name
Test status
Simulation time 14432238 ps
CPU time 0.71 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:09:53 PM PDT 24
Peak memory 204716 kb
Host smart-7c693281-8c43-4a0b-98ec-1eeb6dbc47a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348783659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2348783659
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.915147769
Short name T49
Test name
Test status
Simulation time 462410668 ps
CPU time 3.66 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:09:55 PM PDT 24
Peak memory 234480 kb
Host smart-3401b01a-40b5-46fc-bbab-cdb756b362bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915147769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.915147769
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.405442014
Short name T487
Test name
Test status
Simulation time 56745969 ps
CPU time 0.77 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:09:54 PM PDT 24
Peak memory 205812 kb
Host smart-53d74225-0e7d-4d84-bdbe-1e4decf17f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405442014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.405442014
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.410730265
Short name T740
Test name
Test status
Simulation time 3954883121 ps
CPU time 44.09 seconds
Started May 09 01:09:55 PM PDT 24
Finished May 09 01:10:41 PM PDT 24
Peak memory 241352 kb
Host smart-431fe549-69b1-49f9-90e5-a2ab95c2aef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410730265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.410730265
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2690418013
Short name T723
Test name
Test status
Simulation time 21826150507 ps
CPU time 42.36 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:39 PM PDT 24
Peak memory 240824 kb
Host smart-0c6acc0e-96fd-4c53-9012-21ffcfde7c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690418013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2690418013
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1252709959
Short name T514
Test name
Test status
Simulation time 2031745297 ps
CPU time 9.26 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:09:59 PM PDT 24
Peak memory 234944 kb
Host smart-c9688532-2d7a-4e00-a3b4-99981ad74db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252709959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1252709959
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.119952870
Short name T462
Test name
Test status
Simulation time 48282769 ps
CPU time 3.07 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:09:54 PM PDT 24
Peak memory 232596 kb
Host smart-a564e760-4aec-4b18-a4f3-350e2a45d46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119952870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.119952870
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1240552733
Short name T182
Test name
Test status
Simulation time 1610185394 ps
CPU time 6.48 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 219532 kb
Host smart-17047743-3e00-426c-aac2-ca6c0da87e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240552733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1240552733
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2329612925
Short name T303
Test name
Test status
Simulation time 359547289 ps
CPU time 4.23 seconds
Started May 09 01:09:51 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 234028 kb
Host smart-2e0717a7-e9a6-4435-bcf2-b8c8917ed137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329612925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2329612925
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3489314057
Short name T248
Test name
Test status
Simulation time 1599849972 ps
CPU time 6.46 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:10:01 PM PDT 24
Peak memory 226980 kb
Host smart-d6916619-b8b8-455f-ab8f-7fe669121e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489314057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3489314057
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1981696657
Short name T786
Test name
Test status
Simulation time 3512839518 ps
CPU time 7.99 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:10:02 PM PDT 24
Peak memory 216900 kb
Host smart-811abaa1-88c0-4187-be42-28ac5796576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981696657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1981696657
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1663335217
Short name T629
Test name
Test status
Simulation time 350908670 ps
CPU time 3.92 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:00 PM PDT 24
Peak memory 222596 kb
Host smart-10ab81b8-87a9-433c-97f3-d158b06a5fb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1663335217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1663335217
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1929683666
Short name T436
Test name
Test status
Simulation time 11899080228 ps
CPU time 5.4 seconds
Started May 09 01:09:55 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 216772 kb
Host smart-52095f4f-b9c4-4be5-9da9-69d756608897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929683666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1929683666
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.684711750
Short name T784
Test name
Test status
Simulation time 504613308 ps
CPU time 2.37 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:09:54 PM PDT 24
Peak memory 216196 kb
Host smart-297d8d61-c80a-4926-b6ce-cb7d38741aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684711750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.684711750
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.718042682
Short name T576
Test name
Test status
Simulation time 110446669 ps
CPU time 2.77 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:09:53 PM PDT 24
Peak memory 216408 kb
Host smart-e5a0ac73-c24c-4254-ba2c-29cde10dc92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718042682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.718042682
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1013168390
Short name T637
Test name
Test status
Simulation time 25637325 ps
CPU time 0.73 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:54 PM PDT 24
Peak memory 205812 kb
Host smart-d841be82-9996-44fb-80b4-55bf1a3ce516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013168390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1013168390
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2725889493
Short name T685
Test name
Test status
Simulation time 5091122751 ps
CPU time 10.92 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:07 PM PDT 24
Peak memory 219204 kb
Host smart-631a49a6-53d5-4d58-9e39-4322f35253a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725889493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2725889493
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1670695770
Short name T359
Test name
Test status
Simulation time 36401854 ps
CPU time 0.73 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 204792 kb
Host smart-e94d3914-c902-4b92-8f87-02f7fa570531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670695770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1670695770
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1222602617
Short name T676
Test name
Test status
Simulation time 714464075 ps
CPU time 4.75 seconds
Started May 09 01:09:55 PM PDT 24
Finished May 09 01:10:02 PM PDT 24
Peak memory 234384 kb
Host smart-62487b9e-480c-4bf7-9f32-17a6f8a4f536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222602617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1222602617
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.231727372
Short name T16
Test name
Test status
Simulation time 64149719 ps
CPU time 0.78 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 206768 kb
Host smart-febcaab1-0a88-4c80-af49-29a11585dff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231727372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.231727372
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.706517334
Short name T513
Test name
Test status
Simulation time 53438101 ps
CPU time 0.93 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 216156 kb
Host smart-0b7609f9-c6cb-445b-8e9b-817def50d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706517334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.706517334
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4045968337
Short name T875
Test name
Test status
Simulation time 7855724204 ps
CPU time 58.25 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:10:53 PM PDT 24
Peak memory 249424 kb
Host smart-c33f33e9-0b2c-4e27-b0cc-6796573e541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045968337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4045968337
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2137112205
Short name T223
Test name
Test status
Simulation time 114409316446 ps
CPU time 105.14 seconds
Started May 09 01:09:49 PM PDT 24
Finished May 09 01:11:35 PM PDT 24
Peak memory 250172 kb
Host smart-6d5a5191-2de0-4053-b703-7eaf28b035f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137112205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2137112205
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1451959837
Short name T305
Test name
Test status
Simulation time 5295103675 ps
CPU time 48.17 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:10:40 PM PDT 24
Peak memory 232928 kb
Host smart-84beb723-8f49-4c4f-a368-148466100120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451959837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1451959837
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1927723324
Short name T976
Test name
Test status
Simulation time 1741456518 ps
CPU time 9.42 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:05 PM PDT 24
Peak memory 234036 kb
Host smart-d8197b5a-7c58-47cc-a20e-3a6c41eed583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927723324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1927723324
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1212114288
Short name T484
Test name
Test status
Simulation time 24970284034 ps
CPU time 65.68 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:11:01 PM PDT 24
Peak memory 233664 kb
Host smart-c84307b0-e38c-4e27-b26c-21d9400d1eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212114288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1212114288
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1604705582
Short name T394
Test name
Test status
Simulation time 31412359 ps
CPU time 2.54 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:09:54 PM PDT 24
Peak memory 221360 kb
Host smart-bc8f1b2e-3283-4a79-bd4f-4564bdec59d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604705582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1604705582
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.394125361
Short name T522
Test name
Test status
Simulation time 23596021403 ps
CPU time 10.04 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:10:02 PM PDT 24
Peak memory 229116 kb
Host smart-2b618cb9-d54b-488e-b52e-ed8d0b8a3ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394125361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.394125361
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3938234118
Short name T38
Test name
Test status
Simulation time 252212054 ps
CPU time 4.93 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:01 PM PDT 24
Peak memory 222900 kb
Host smart-e60dfed3-a7bc-40b5-b8ba-353c6329fbb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3938234118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3938234118
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1119248559
Short name T166
Test name
Test status
Simulation time 296849043 ps
CPU time 1.11 seconds
Started May 09 01:09:55 PM PDT 24
Finished May 09 01:09:59 PM PDT 24
Peak memory 207368 kb
Host smart-8a907f12-2238-4573-a689-9d43b7557071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119248559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1119248559
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2636306346
Short name T719
Test name
Test status
Simulation time 2448605889 ps
CPU time 15.4 seconds
Started May 09 01:09:54 PM PDT 24
Finished May 09 01:10:11 PM PDT 24
Peak memory 216520 kb
Host smart-3bc60331-0c2e-4e01-b654-1bef79db593e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636306346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2636306346
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3842269623
Short name T413
Test name
Test status
Simulation time 11172707653 ps
CPU time 17.08 seconds
Started May 09 01:09:50 PM PDT 24
Finished May 09 01:10:09 PM PDT 24
Peak memory 216444 kb
Host smart-5f4b1da7-e192-4056-a761-340f897cac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842269623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3842269623
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2987118762
Short name T455
Test name
Test status
Simulation time 20152260 ps
CPU time 0.83 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:55 PM PDT 24
Peak memory 205864 kb
Host smart-56273f21-e32f-4224-9df7-fb351584c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987118762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2987118762
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.849548672
Short name T330
Test name
Test status
Simulation time 385549717 ps
CPU time 0.76 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:55 PM PDT 24
Peak memory 205840 kb
Host smart-b777fd49-4041-4732-89e9-fc47d5272381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849548672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.849548672
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1020629333
Short name T782
Test name
Test status
Simulation time 1960789270 ps
CPU time 15.12 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:10:09 PM PDT 24
Peak memory 240948 kb
Host smart-e0bd9c5a-5d70-49d2-b691-0d0772df1656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020629333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1020629333
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1112206508
Short name T745
Test name
Test status
Simulation time 45303441 ps
CPU time 0.71 seconds
Started May 09 01:10:10 PM PDT 24
Finished May 09 01:10:11 PM PDT 24
Peak memory 205348 kb
Host smart-9bf23649-7198-479c-8dc1-be72b2326a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112206508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1112206508
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2412204279
Short name T77
Test name
Test status
Simulation time 67314755 ps
CPU time 2.41 seconds
Started May 09 01:10:09 PM PDT 24
Finished May 09 01:10:12 PM PDT 24
Peak memory 218552 kb
Host smart-e42492e7-1782-4ba8-b53b-bb2f8e327431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412204279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2412204279
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1797248487
Short name T478
Test name
Test status
Simulation time 26546798 ps
CPU time 0.73 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 206400 kb
Host smart-21799b7c-0f2f-4509-875f-9144388e4e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797248487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1797248487
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.275559365
Short name T753
Test name
Test status
Simulation time 1131287602 ps
CPU time 21.36 seconds
Started May 09 01:10:00 PM PDT 24
Finished May 09 01:10:22 PM PDT 24
Peak memory 239976 kb
Host smart-2e30cf81-d706-4e9d-80c7-13cd861f4ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275559365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.275559365
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1387618659
Short name T274
Test name
Test status
Simulation time 17617829772 ps
CPU time 150.7 seconds
Started May 09 01:09:59 PM PDT 24
Finished May 09 01:12:31 PM PDT 24
Peak memory 240980 kb
Host smart-bf789215-7857-48dd-ab36-54bfd4f8e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387618659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1387618659
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3435909966
Short name T505
Test name
Test status
Simulation time 9931577937 ps
CPU time 25.71 seconds
Started May 09 01:10:00 PM PDT 24
Finished May 09 01:10:27 PM PDT 24
Peak memory 241092 kb
Host smart-851f2db2-2830-45a1-a87b-1715f15f286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435909966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3435909966
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3893237123
Short name T268
Test name
Test status
Simulation time 504658123 ps
CPU time 7.96 seconds
Started May 09 01:10:05 PM PDT 24
Finished May 09 01:10:14 PM PDT 24
Peak memory 219632 kb
Host smart-fb91d0cb-612d-4e05-9c23-437089ea250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893237123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3893237123
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.244639441
Short name T208
Test name
Test status
Simulation time 548715763 ps
CPU time 6.45 seconds
Started May 09 01:10:03 PM PDT 24
Finished May 09 01:10:11 PM PDT 24
Peak memory 218552 kb
Host smart-96ae78b3-984b-4857-bb9d-969d718bcd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244639441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.244639441
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1265632611
Short name T257
Test name
Test status
Simulation time 460190763 ps
CPU time 5.93 seconds
Started May 09 01:10:04 PM PDT 24
Finished May 09 01:10:11 PM PDT 24
Peak memory 234308 kb
Host smart-3207967b-2741-43fe-89e1-383197f85d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265632611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1265632611
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3043164082
Short name T600
Test name
Test status
Simulation time 288462194 ps
CPU time 2.9 seconds
Started May 09 01:09:55 PM PDT 24
Finished May 09 01:10:00 PM PDT 24
Peak memory 218656 kb
Host smart-b0274458-8c2d-4a6f-bd6d-8febb8867274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043164082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3043164082
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2218577339
Short name T146
Test name
Test status
Simulation time 1176671042 ps
CPU time 15.35 seconds
Started May 09 01:10:10 PM PDT 24
Finished May 09 01:10:26 PM PDT 24
Peak memory 221788 kb
Host smart-1962c5a2-5637-4be2-9e41-4066152377d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2218577339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2218577339
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.212166839
Short name T155
Test name
Test status
Simulation time 404715019 ps
CPU time 1.04 seconds
Started May 09 01:10:02 PM PDT 24
Finished May 09 01:10:04 PM PDT 24
Peak memory 206656 kb
Host smart-2c6d1a7b-bcbe-4bc9-a043-fb14d6171b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212166839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.212166839
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1062156574
Short name T543
Test name
Test status
Simulation time 2422845422 ps
CPU time 6.19 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:09:59 PM PDT 24
Peak memory 216460 kb
Host smart-85811c23-2af3-4c8d-a151-91da59668a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062156574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1062156574
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.313699922
Short name T808
Test name
Test status
Simulation time 11390675683 ps
CPU time 9.44 seconds
Started May 09 01:09:52 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 216548 kb
Host smart-a553aada-e3fc-4989-b46b-0a2c61ff0928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313699922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.313699922
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2025001998
Short name T575
Test name
Test status
Simulation time 86896488 ps
CPU time 1.8 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 208156 kb
Host smart-2605c1f1-1d07-4a67-aeaf-179d7be82fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025001998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2025001998
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.505895420
Short name T368
Test name
Test status
Simulation time 29990873 ps
CPU time 0.76 seconds
Started May 09 01:09:53 PM PDT 24
Finished May 09 01:09:56 PM PDT 24
Peak memory 205832 kb
Host smart-f6442905-aa41-45b8-8a1b-2ac74dbbf54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505895420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.505895420
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2880151925
Short name T775
Test name
Test status
Simulation time 2357119513 ps
CPU time 5.53 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:10:08 PM PDT 24
Peak memory 224648 kb
Host smart-f3004541-09da-4755-8812-f37348bf3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880151925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2880151925
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1052704032
Short name T961
Test name
Test status
Simulation time 19817314 ps
CPU time 0.76 seconds
Started May 09 01:10:05 PM PDT 24
Finished May 09 01:10:07 PM PDT 24
Peak memory 204796 kb
Host smart-3b6619d9-747a-421c-8fe7-e1edc39f57ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052704032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1052704032
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3730333994
Short name T136
Test name
Test status
Simulation time 2174728127 ps
CPU time 30.37 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:10:33 PM PDT 24
Peak memory 224632 kb
Host smart-214297b1-f78a-4e4e-acb4-d4d4ade2d6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730333994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3730333994
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3494608616
Short name T546
Test name
Test status
Simulation time 49545621 ps
CPU time 0.84 seconds
Started May 09 01:10:00 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 206500 kb
Host smart-16831ed3-14d7-4137-80fc-3ca2a97e5bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494608616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3494608616
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2975136015
Short name T249
Test name
Test status
Simulation time 73741740977 ps
CPU time 534.42 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:18:57 PM PDT 24
Peak memory 264748 kb
Host smart-b280dfea-58fb-496e-bfba-8943dd04102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975136015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2975136015
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2455495954
Short name T230
Test name
Test status
Simulation time 28873039042 ps
CPU time 274.23 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:14:36 PM PDT 24
Peak memory 257492 kb
Host smart-6bf754cf-10af-4240-a33f-c149162b71eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455495954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2455495954
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.587436459
Short name T954
Test name
Test status
Simulation time 27277364637 ps
CPU time 137.79 seconds
Started May 09 01:10:02 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 251788 kb
Host smart-d8c72a9b-9603-4346-bf65-52c2729aa402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587436459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.587436459
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.757079851
Short name T498
Test name
Test status
Simulation time 11800713317 ps
CPU time 33.51 seconds
Started May 09 01:10:10 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 232860 kb
Host smart-cbb8510f-7a7e-4ae9-a119-40fba93daf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757079851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.757079851
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1693433753
Short name T803
Test name
Test status
Simulation time 1342343145 ps
CPU time 18.12 seconds
Started May 09 01:10:00 PM PDT 24
Finished May 09 01:10:19 PM PDT 24
Peak memory 219012 kb
Host smart-2f38f56e-75e0-4a34-8165-e12124566404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693433753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1693433753
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.546152280
Short name T277
Test name
Test status
Simulation time 7879405739 ps
CPU time 75.28 seconds
Started May 09 01:10:10 PM PDT 24
Finished May 09 01:11:26 PM PDT 24
Peak memory 240008 kb
Host smart-a14e11f1-b443-48f3-8c68-bac5ec6e3df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546152280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.546152280
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4103688333
Short name T811
Test name
Test status
Simulation time 1520583995 ps
CPU time 9.67 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:10:12 PM PDT 24
Peak memory 233640 kb
Host smart-a935d363-5db0-4d9d-974e-19be64688089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103688333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4103688333
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.694912936
Short name T590
Test name
Test status
Simulation time 1450299069 ps
CPU time 5.37 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:10:08 PM PDT 24
Peak memory 233864 kb
Host smart-b3200b74-6294-4fa9-ad3e-f3d2da85735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694912936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.694912936
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.288291303
Short name T523
Test name
Test status
Simulation time 995856662 ps
CPU time 12.57 seconds
Started May 09 01:10:00 PM PDT 24
Finished May 09 01:10:14 PM PDT 24
Peak memory 220616 kb
Host smart-5c3304e1-e735-4a75-9ccb-2dc16623fe01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=288291303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.288291303
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4201325106
Short name T555
Test name
Test status
Simulation time 1391983959 ps
CPU time 3.42 seconds
Started May 09 01:10:04 PM PDT 24
Finished May 09 01:10:09 PM PDT 24
Peak memory 219156 kb
Host smart-79da4408-be99-4bb1-a53e-99cf55be570b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201325106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4201325106
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4183898458
Short name T951
Test name
Test status
Simulation time 3220558382 ps
CPU time 5.97 seconds
Started May 09 01:10:10 PM PDT 24
Finished May 09 01:10:17 PM PDT 24
Peak memory 216472 kb
Host smart-ef6d926e-582b-4e27-aab1-543c518d5397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183898458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4183898458
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.802218292
Short name T689
Test name
Test status
Simulation time 20947847 ps
CPU time 0.71 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 205492 kb
Host smart-76782316-f71f-44cb-9e87-44811924ef84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802218292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.802218292
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2500208572
Short name T712
Test name
Test status
Simulation time 192401579 ps
CPU time 0.83 seconds
Started May 09 01:09:59 PM PDT 24
Finished May 09 01:10:01 PM PDT 24
Peak memory 205856 kb
Host smart-45651a8a-c102-4473-802b-ecf063768d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500208572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2500208572
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2710037827
Short name T194
Test name
Test status
Simulation time 34748316706 ps
CPU time 20.19 seconds
Started May 09 01:10:03 PM PDT 24
Finished May 09 01:10:24 PM PDT 24
Peak memory 234448 kb
Host smart-969cb476-accc-45ff-9fcf-72956c11e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710037827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2710037827
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1995605986
Short name T541
Test name
Test status
Simulation time 14019656 ps
CPU time 0.74 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 205348 kb
Host smart-12055c74-adce-4004-9f83-fe1012a28303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995605986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1995605986
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2442285597
Short name T596
Test name
Test status
Simulation time 517967001 ps
CPU time 2.63 seconds
Started May 09 01:10:11 PM PDT 24
Finished May 09 01:10:15 PM PDT 24
Peak memory 218604 kb
Host smart-bcd66519-bf5c-4831-b237-f920e2bc9745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442285597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2442285597
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.485607426
Short name T524
Test name
Test status
Simulation time 61245499 ps
CPU time 0.83 seconds
Started May 09 01:10:01 PM PDT 24
Finished May 09 01:10:03 PM PDT 24
Peak memory 206496 kb
Host smart-09f8c57f-af09-413c-8d4a-c564a6fca758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485607426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.485607426
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.380656584
Short name T667
Test name
Test status
Simulation time 16810622810 ps
CPU time 126.79 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:12:35 PM PDT 24
Peak memory 249664 kb
Host smart-ae7d9fbe-d90b-4bc6-8132-9da966c2d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380656584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.380656584
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.169420149
Short name T399
Test name
Test status
Simulation time 3270836117 ps
CPU time 20.66 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:49 PM PDT 24
Peak memory 232952 kb
Host smart-a49d41f3-b4f5-4b9c-b26d-7f65b89f3e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169420149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.169420149
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1130984385
Short name T948
Test name
Test status
Simulation time 12866398337 ps
CPU time 38.79 seconds
Started May 09 01:10:24 PM PDT 24
Finished May 09 01:11:04 PM PDT 24
Peak memory 249296 kb
Host smart-b40ec7d9-cf55-446c-99aa-63bcf933c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130984385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1130984385
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2872918289
Short name T309
Test name
Test status
Simulation time 4114913680 ps
CPU time 37.32 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 232852 kb
Host smart-b7390130-af69-45e1-80a4-5d5d1f699255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872918289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2872918289
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1894026290
Short name T281
Test name
Test status
Simulation time 1577001383 ps
CPU time 11.99 seconds
Started May 09 01:10:13 PM PDT 24
Finished May 09 01:10:26 PM PDT 24
Peak memory 234036 kb
Host smart-36bce9fe-9bf9-41d3-afe7-b0eeacd7bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894026290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1894026290
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.960983549
Short name T914
Test name
Test status
Simulation time 5237218925 ps
CPU time 12.42 seconds
Started May 09 01:10:14 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 227884 kb
Host smart-70046edf-eab0-4d0d-bc2e-3e3303bed7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960983549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.960983549
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3595733852
Short name T269
Test name
Test status
Simulation time 11944377198 ps
CPU time 9.2 seconds
Started May 09 01:10:11 PM PDT 24
Finished May 09 01:10:21 PM PDT 24
Peak memory 217096 kb
Host smart-d627c224-6df5-4e60-b92c-0372c6a90623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595733852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3595733852
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3837193729
Short name T943
Test name
Test status
Simulation time 21347536428 ps
CPU time 19.96 seconds
Started May 09 01:10:12 PM PDT 24
Finished May 09 01:10:34 PM PDT 24
Peak memory 232604 kb
Host smart-abe2d984-51b4-419e-b67c-96a8cfb5c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837193729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3837193729
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2837582015
Short name T337
Test name
Test status
Simulation time 923768822 ps
CPU time 12.46 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:41 PM PDT 24
Peak memory 219208 kb
Host smart-6285b61b-3591-4b5b-a253-645b00e5a501
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2837582015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2837582015
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4038789940
Short name T160
Test name
Test status
Simulation time 185281753719 ps
CPU time 586.49 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:20:16 PM PDT 24
Peak memory 249436 kb
Host smart-1a03ee0f-b3db-4cda-bdb2-128deabd42b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038789940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4038789940
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.374619813
Short name T717
Test name
Test status
Simulation time 14268559 ps
CPU time 0.77 seconds
Started May 09 01:10:13 PM PDT 24
Finished May 09 01:10:16 PM PDT 24
Peak memory 205608 kb
Host smart-2c92b849-0438-4d10-8435-301b24d30100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374619813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.374619813
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2116702567
Short name T591
Test name
Test status
Simulation time 76730443 ps
CPU time 1.39 seconds
Started May 09 01:10:02 PM PDT 24
Finished May 09 01:10:05 PM PDT 24
Peak memory 207992 kb
Host smart-1a07eb8c-ffd5-4023-9ba6-bd43b89a681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116702567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2116702567
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1718555146
Short name T980
Test name
Test status
Simulation time 92853541 ps
CPU time 1.48 seconds
Started May 09 01:10:12 PM PDT 24
Finished May 09 01:10:14 PM PDT 24
Peak memory 216408 kb
Host smart-363508b4-8b48-4243-a07a-c3c57b01d0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718555146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1718555146
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3054828844
Short name T639
Test name
Test status
Simulation time 92538229 ps
CPU time 0.72 seconds
Started May 09 01:10:13 PM PDT 24
Finished May 09 01:10:15 PM PDT 24
Peak memory 205752 kb
Host smart-6eb59e70-4a27-4afd-9b42-97e99973e2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054828844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3054828844
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3583944897
Short name T459
Test name
Test status
Simulation time 363146840 ps
CPU time 5.65 seconds
Started May 09 01:10:13 PM PDT 24
Finished May 09 01:10:20 PM PDT 24
Peak memory 230588 kb
Host smart-2816a3af-cd1d-4496-9337-a4f9ee11a290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583944897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3583944897
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2370248526
Short name T56
Test name
Test status
Simulation time 19389135 ps
CPU time 0.69 seconds
Started May 09 01:10:24 PM PDT 24
Finished May 09 01:10:26 PM PDT 24
Peak memory 205720 kb
Host smart-a55d13c8-8e2d-4ea8-97d0-24467feee780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370248526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2370248526
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1640704736
Short name T553
Test name
Test status
Simulation time 866341723 ps
CPU time 9.74 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:36 PM PDT 24
Peak memory 219488 kb
Host smart-42686d80-8dc3-474b-badc-b19db00f60fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640704736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1640704736
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3372717046
Short name T694
Test name
Test status
Simulation time 18444829 ps
CPU time 0.74 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 205652 kb
Host smart-ecce3658-ef9a-4856-b4c2-10b76ad19427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372717046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3372717046
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.993895953
Short name T275
Test name
Test status
Simulation time 47638380554 ps
CPU time 61.1 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 239488 kb
Host smart-48f5654b-4ec2-4443-a1cc-b4eff3a39e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993895953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.993895953
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.194037717
Short name T358
Test name
Test status
Simulation time 2605755124 ps
CPU time 6.89 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:36 PM PDT 24
Peak memory 217888 kb
Host smart-ffeba30d-51b7-4c26-ba62-d2f03934bcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194037717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.194037717
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1765982938
Short name T567
Test name
Test status
Simulation time 10631281213 ps
CPU time 83.19 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 257440 kb
Host smart-81cf2033-0bc3-4165-ab30-b2dd01b3bdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765982938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1765982938
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2584092216
Short name T608
Test name
Test status
Simulation time 953966017 ps
CPU time 14.44 seconds
Started May 09 01:10:28 PM PDT 24
Finished May 09 01:10:45 PM PDT 24
Peak memory 240984 kb
Host smart-4c19d6d7-16b4-4d49-9732-931452877b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584092216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2584092216
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1352736178
Short name T663
Test name
Test status
Simulation time 394183932 ps
CPU time 4.69 seconds
Started May 09 01:10:24 PM PDT 24
Finished May 09 01:10:30 PM PDT 24
Peak memory 233920 kb
Host smart-64abf999-e8e7-437c-a55c-0178fbf199d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352736178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1352736178
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.714877198
Short name T72
Test name
Test status
Simulation time 3905180835 ps
CPU time 20.14 seconds
Started May 09 01:10:28 PM PDT 24
Finished May 09 01:10:51 PM PDT 24
Peak memory 232848 kb
Host smart-ab609099-4e56-4f90-8219-62e50b7942ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714877198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.714877198
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1243117648
Short name T374
Test name
Test status
Simulation time 7714014075 ps
CPU time 9.04 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:35 PM PDT 24
Peak memory 219548 kb
Host smart-4917c9df-1855-4334-b8e3-873c059c81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243117648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1243117648
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2017316599
Short name T921
Test name
Test status
Simulation time 232362205 ps
CPU time 3.08 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 224508 kb
Host smart-eb6f29c2-23d2-499b-885e-f04a54506bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017316599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2017316599
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.30391390
Short name T570
Test name
Test status
Simulation time 2366046942 ps
CPU time 12.36 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:39 PM PDT 24
Peak memory 222600 kb
Host smart-02e28c68-0b3e-4ce7-b901-90ba5a4dc833
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=30391390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direc
t.30391390
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2362534997
Short name T252
Test name
Test status
Simulation time 13948273356 ps
CPU time 27.18 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 241044 kb
Host smart-fb2363cb-693d-4a66-bb97-b93cb209955a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362534997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2362534997
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.73367749
Short name T474
Test name
Test status
Simulation time 2188122922 ps
CPU time 12.2 seconds
Started May 09 01:10:24 PM PDT 24
Finished May 09 01:10:38 PM PDT 24
Peak memory 219188 kb
Host smart-a815d68f-dc65-458e-a49d-4717fe184cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73367749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.73367749
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1842301301
Short name T668
Test name
Test status
Simulation time 1481760627 ps
CPU time 4.9 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:33 PM PDT 24
Peak memory 216368 kb
Host smart-945a59c7-a21e-448c-abe2-b9159c3726f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842301301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1842301301
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3531575284
Short name T319
Test name
Test status
Simulation time 238693655 ps
CPU time 2.21 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 216448 kb
Host smart-57523867-fd78-4c0b-a563-2a7c254b5cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531575284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3531575284
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2782733995
Short name T844
Test name
Test status
Simulation time 25634043 ps
CPU time 0.78 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:27 PM PDT 24
Peak memory 205868 kb
Host smart-a549e5e9-1427-4ef2-a747-82660926ab3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782733995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2782733995
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3260023940
Short name T300
Test name
Test status
Simulation time 242308693 ps
CPU time 4.66 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:31 PM PDT 24
Peak memory 229592 kb
Host smart-050dbfac-449b-4250-b606-2936386baab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260023940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3260023940
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2030648887
Short name T621
Test name
Test status
Simulation time 41434819 ps
CPU time 0.76 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:35 PM PDT 24
Peak memory 205392 kb
Host smart-6d44e5e9-b7e9-4047-9a79-547cd8e117b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030648887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
030648887
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2215819180
Short name T351
Test name
Test status
Simulation time 147444926 ps
CPU time 3.35 seconds
Started May 09 01:08:21 PM PDT 24
Finished May 09 01:08:26 PM PDT 24
Peak memory 219736 kb
Host smart-b94985f0-b012-45a8-a94c-838c99e4d586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215819180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2215819180
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2605205704
Short name T675
Test name
Test status
Simulation time 16530139 ps
CPU time 0.82 seconds
Started May 09 01:08:23 PM PDT 24
Finished May 09 01:08:25 PM PDT 24
Peak memory 205772 kb
Host smart-c4703fc0-21d8-42fd-b959-5a6289085037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605205704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2605205704
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2674190956
Short name T52
Test name
Test status
Simulation time 3124194723 ps
CPU time 63.17 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:09:40 PM PDT 24
Peak memory 255040 kb
Host smart-70fd417a-efd7-4058-8264-468a546c80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674190956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2674190956
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3817693469
Short name T286
Test name
Test status
Simulation time 66012485235 ps
CPU time 327.15 seconds
Started May 09 01:08:38 PM PDT 24
Finished May 09 01:14:08 PM PDT 24
Peak memory 249408 kb
Host smart-4a1f1ace-3b46-4bac-a761-3756aa6b8ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817693469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3817693469
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2266292186
Short name T44
Test name
Test status
Simulation time 317031940596 ps
CPU time 752.8 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:21:10 PM PDT 24
Peak memory 273824 kb
Host smart-f07004a1-db34-4c08-9347-8ee0538c0491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266292186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2266292186
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3804109452
Short name T800
Test name
Test status
Simulation time 249299800 ps
CPU time 4.15 seconds
Started May 09 01:08:22 PM PDT 24
Finished May 09 01:08:28 PM PDT 24
Peak memory 218348 kb
Host smart-62cbe2f3-a698-4600-ab79-76b65846da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804109452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3804109452
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2448616983
Short name T193
Test name
Test status
Simulation time 6389733704 ps
CPU time 27.11 seconds
Started May 09 01:08:20 PM PDT 24
Finished May 09 01:08:48 PM PDT 24
Peak memory 233848 kb
Host smart-eeac1556-e05c-40ef-84ac-f7ca39793278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448616983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2448616983
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3818874116
Short name T853
Test name
Test status
Simulation time 95107935 ps
CPU time 1.16 seconds
Started May 09 01:08:20 PM PDT 24
Finished May 09 01:08:22 PM PDT 24
Peak memory 216780 kb
Host smart-ef3a2afb-165d-48c0-aa31-2d1d542a0580
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818874116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3818874116
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2986340117
Short name T255
Test name
Test status
Simulation time 4365496941 ps
CPU time 5.82 seconds
Started May 09 01:08:23 PM PDT 24
Finished May 09 01:08:30 PM PDT 24
Peak memory 240904 kb
Host smart-86266e2f-5f00-48e9-8a6c-67aa7608ca81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986340117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2986340117
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2847008407
Short name T162
Test name
Test status
Simulation time 199819325 ps
CPU time 2.56 seconds
Started May 09 01:08:21 PM PDT 24
Finished May 09 01:08:24 PM PDT 24
Peak memory 218936 kb
Host smart-8227940b-3cae-4d5f-b979-69a77ca1bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847008407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2847008407
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3365655023
Short name T376
Test name
Test status
Simulation time 848935269 ps
CPU time 9.92 seconds
Started May 09 01:08:21 PM PDT 24
Finished May 09 01:08:32 PM PDT 24
Peak memory 221740 kb
Host smart-0df413f3-4648-40f7-aaed-5f0cfab0ae28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3365655023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3365655023
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3096694464
Short name T65
Test name
Test status
Simulation time 157117962 ps
CPU time 1.32 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 236632 kb
Host smart-ff16fa40-3e96-4b1a-b896-6f224606c63d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096694464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3096694464
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2820597968
Short name T158
Test name
Test status
Simulation time 320915177281 ps
CPU time 702.1 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:20:17 PM PDT 24
Peak memory 273988 kb
Host smart-a7c1e11d-08ec-4150-aa53-8af900416729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820597968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2820597968
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3470065794
Short name T71
Test name
Test status
Simulation time 13557581082 ps
CPU time 18.93 seconds
Started May 09 01:08:22 PM PDT 24
Finished May 09 01:08:42 PM PDT 24
Peak memory 216516 kb
Host smart-587aeb93-38df-4393-8369-80f8b5c6ba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470065794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3470065794
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.148241140
Short name T817
Test name
Test status
Simulation time 990621838 ps
CPU time 5.55 seconds
Started May 09 01:08:24 PM PDT 24
Finished May 09 01:08:30 PM PDT 24
Peak memory 216452 kb
Host smart-b2cc1d34-7634-4eab-b079-b6595c869752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148241140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.148241140
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3496558740
Short name T415
Test name
Test status
Simulation time 103992210 ps
CPU time 2.02 seconds
Started May 09 01:08:23 PM PDT 24
Finished May 09 01:08:26 PM PDT 24
Peak memory 216364 kb
Host smart-27da58c3-ba05-44c0-80a9-db82abd7816a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496558740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3496558740
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.101591692
Short name T711
Test name
Test status
Simulation time 95423936 ps
CPU time 0.76 seconds
Started May 09 01:08:22 PM PDT 24
Finished May 09 01:08:24 PM PDT 24
Peak memory 205812 kb
Host smart-bb91f72b-d0c8-486e-bbcf-c562e48073bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101591692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.101591692
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2323827646
Short name T284
Test name
Test status
Simulation time 10619538571 ps
CPU time 12.68 seconds
Started May 09 01:08:22 PM PDT 24
Finished May 09 01:08:36 PM PDT 24
Peak memory 236364 kb
Host smart-f570875c-2024-4b0e-aa07-9fbd57f44c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323827646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2323827646
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.737744027
Short name T812
Test name
Test status
Simulation time 57573847 ps
CPU time 0.73 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:30 PM PDT 24
Peak memory 204792 kb
Host smart-fddb10d4-8e3e-46b2-b6f0-97e8773dd36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737744027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.737744027
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2260142082
Short name T454
Test name
Test status
Simulation time 222360698 ps
CPU time 4.7 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:33 PM PDT 24
Peak memory 234720 kb
Host smart-13af8d52-2e4f-4091-8336-94c8d141311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260142082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2260142082
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2629203715
Short name T557
Test name
Test status
Simulation time 18697013 ps
CPU time 0.8 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:29 PM PDT 24
Peak memory 205352 kb
Host smart-e1581a5b-a6d8-4b97-a999-83a4a18d3491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629203715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2629203715
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3588894680
Short name T568
Test name
Test status
Simulation time 13935306286 ps
CPU time 98.09 seconds
Started May 09 01:10:30 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 254168 kb
Host smart-da9fa367-ba9d-4a32-9962-5826a1405af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588894680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3588894680
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4126866873
Short name T926
Test name
Test status
Simulation time 85005886 ps
CPU time 5.16 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 232724 kb
Host smart-d9e144a4-285e-40e9-809b-1a3444e2054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126866873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4126866873
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1563257986
Short name T848
Test name
Test status
Simulation time 214785578 ps
CPU time 2.64 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 233716 kb
Host smart-b0941d27-be55-4702-8d6b-46c372f13da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563257986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1563257986
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1255509103
Short name T845
Test name
Test status
Simulation time 2666320213 ps
CPU time 28.2 seconds
Started May 09 01:10:28 PM PDT 24
Finished May 09 01:10:59 PM PDT 24
Peak memory 236396 kb
Host smart-8c6f84b6-2767-4880-b441-39345a798113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255509103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1255509103
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2808117674
Short name T979
Test name
Test status
Simulation time 35720663570 ps
CPU time 11.66 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:40 PM PDT 24
Peak memory 218584 kb
Host smart-37650c72-20c7-41cc-bd08-0336702c400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808117674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2808117674
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3561832938
Short name T902
Test name
Test status
Simulation time 9769495621 ps
CPU time 17.02 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:47 PM PDT 24
Peak memory 218208 kb
Host smart-b65c9af3-b44c-41ef-92b4-89205e17a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561832938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3561832938
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1760949434
Short name T550
Test name
Test status
Simulation time 190518809 ps
CPU time 4.57 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:10:34 PM PDT 24
Peak memory 223068 kb
Host smart-a6bacb28-f37c-478c-9133-8679bb22c023
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1760949434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1760949434
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4265172143
Short name T466
Test name
Test status
Simulation time 35175646 ps
CPU time 1.01 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 206796 kb
Host smart-79f8b9ba-c94c-4971-b78d-36aa21c9bfd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265172143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4265172143
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.809704230
Short name T76
Test name
Test status
Simulation time 15683097087 ps
CPU time 38.44 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:11:09 PM PDT 24
Peak memory 216504 kb
Host smart-33ac7412-9407-471e-b653-ad8048c8d8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809704230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.809704230
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3970731596
Short name T473
Test name
Test status
Simulation time 23565013563 ps
CPU time 10.24 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:38 PM PDT 24
Peak memory 216548 kb
Host smart-d814233b-c5a7-49d7-be31-da82cdcd24ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970731596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3970731596
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1282344523
Short name T734
Test name
Test status
Simulation time 57854082 ps
CPU time 0.96 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:10:31 PM PDT 24
Peak memory 206828 kb
Host smart-a00b353a-23b6-45da-b19e-3735956ccb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282344523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1282344523
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1209668927
Short name T899
Test name
Test status
Simulation time 53281952 ps
CPU time 0.79 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:30 PM PDT 24
Peak memory 205880 kb
Host smart-c02ce535-411f-40bc-bd0d-93fb81f37f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209668927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1209668927
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2169900119
Short name T941
Test name
Test status
Simulation time 145110097 ps
CPU time 2.4 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:30 PM PDT 24
Peak memory 216368 kb
Host smart-d7497245-14e2-48c1-bd76-c018ac947100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169900119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2169900119
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3524480928
Short name T709
Test name
Test status
Simulation time 25593488 ps
CPU time 0.78 seconds
Started May 09 01:10:36 PM PDT 24
Finished May 09 01:10:38 PM PDT 24
Peak memory 205352 kb
Host smart-61ac8e9c-f4ad-45d8-8d0e-2995aedb0f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524480928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3524480928
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4283829047
Short name T957
Test name
Test status
Simulation time 132810625 ps
CPU time 3.11 seconds
Started May 09 01:10:28 PM PDT 24
Finished May 09 01:10:34 PM PDT 24
Peak memory 218556 kb
Host smart-8a85dfc4-d7e2-4854-ae73-31a4d7293b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283829047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4283829047
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2476023150
Short name T18
Test name
Test status
Simulation time 134243381 ps
CPU time 0.78 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:30 PM PDT 24
Peak memory 206444 kb
Host smart-801226ee-56af-4c9b-a174-a942f84c673b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476023150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2476023150
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2073945236
Short name T253
Test name
Test status
Simulation time 74508082661 ps
CPU time 483.03 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:18:33 PM PDT 24
Peak memory 251532 kb
Host smart-d0214895-59e2-460a-b6c2-f634f2598bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073945236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2073945236
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2987167014
Short name T131
Test name
Test status
Simulation time 53617445298 ps
CPU time 563.04 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:19:53 PM PDT 24
Peak memory 255168 kb
Host smart-ff5d68ad-68e5-40b6-845b-62f4a2e3dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987167014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2987167014
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2481353403
Short name T534
Test name
Test status
Simulation time 81470636166 ps
CPU time 157.59 seconds
Started May 09 01:10:37 PM PDT 24
Finished May 09 01:13:15 PM PDT 24
Peak memory 232928 kb
Host smart-4e674821-18c9-4e92-83c4-b4e62d71981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481353403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2481353403
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1037481059
Short name T290
Test name
Test status
Simulation time 234819966 ps
CPU time 4.63 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:10:35 PM PDT 24
Peak memory 224556 kb
Host smart-42ee9fec-0f0b-4f1b-a541-07e07e757a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037481059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1037481059
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2107439528
Short name T298
Test name
Test status
Simulation time 155064007 ps
CPU time 4.84 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:10:35 PM PDT 24
Peak memory 233748 kb
Host smart-6be80179-3a25-4472-af04-547695b2199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107439528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2107439528
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3350826476
Short name T397
Test name
Test status
Simulation time 7682634095 ps
CPU time 13.28 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:41 PM PDT 24
Peak memory 232820 kb
Host smart-a01044d1-d857-4c02-b22f-22312c2f97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350826476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3350826476
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2461891440
Short name T593
Test name
Test status
Simulation time 15159635868 ps
CPU time 16.93 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:46 PM PDT 24
Peak memory 235136 kb
Host smart-59ff263e-8054-44f2-8b84-d80f3795fecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461891440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2461891440
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2113203323
Short name T169
Test name
Test status
Simulation time 124185046 ps
CPU time 2.56 seconds
Started May 09 01:10:29 PM PDT 24
Finished May 09 01:10:34 PM PDT 24
Peak memory 218792 kb
Host smart-2178a556-68d9-4fd8-99ad-a4ebf2402bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113203323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2113203323
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.596788419
Short name T467
Test name
Test status
Simulation time 73092018 ps
CPU time 3.69 seconds
Started May 09 01:10:28 PM PDT 24
Finished May 09 01:10:34 PM PDT 24
Peak memory 222056 kb
Host smart-416fd731-53a1-411f-bd0b-de1af51b2b04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=596788419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.596788419
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2704510151
Short name T156
Test name
Test status
Simulation time 408319893 ps
CPU time 6.73 seconds
Started May 09 01:10:37 PM PDT 24
Finished May 09 01:10:45 PM PDT 24
Peak memory 232748 kb
Host smart-1a927534-cd19-4a1f-a603-4332192d91e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704510151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2704510151
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4074757681
Short name T631
Test name
Test status
Simulation time 578640508 ps
CPU time 9.94 seconds
Started May 09 01:10:27 PM PDT 24
Finished May 09 01:10:40 PM PDT 24
Peak memory 216440 kb
Host smart-584b08c0-4688-470a-9d30-320aab84c5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074757681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4074757681
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2717278465
Short name T433
Test name
Test status
Simulation time 4630989242 ps
CPU time 6.83 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:37 PM PDT 24
Peak memory 216448 kb
Host smart-07b97221-e0eb-42f8-ac78-e33935c1f15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717278465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2717278465
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1733583352
Short name T532
Test name
Test status
Simulation time 71116361 ps
CPU time 1.05 seconds
Started May 09 01:10:24 PM PDT 24
Finished May 09 01:10:26 PM PDT 24
Peak memory 207692 kb
Host smart-d0e91de5-eb36-4c1d-80c4-d49b8b818e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733583352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1733583352
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.631630423
Short name T137
Test name
Test status
Simulation time 17505991 ps
CPU time 0.66 seconds
Started May 09 01:10:25 PM PDT 24
Finished May 09 01:10:27 PM PDT 24
Peak memory 205460 kb
Host smart-48f6e1dd-1493-4efe-ac38-2483d07d943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631630423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.631630423
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3917765435
Short name T114
Test name
Test status
Simulation time 708425339 ps
CPU time 2.54 seconds
Started May 09 01:10:26 PM PDT 24
Finished May 09 01:10:32 PM PDT 24
Peak memory 216228 kb
Host smart-e9c912ba-69e2-4746-966a-833b1e139d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917765435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3917765435
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.507952772
Short name T722
Test name
Test status
Simulation time 26138131 ps
CPU time 0.74 seconds
Started May 09 01:10:43 PM PDT 24
Finished May 09 01:10:46 PM PDT 24
Peak memory 205404 kb
Host smart-57e5120d-dc8e-48b7-90a3-febe072b8b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507952772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.507952772
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3477202157
Short name T918
Test name
Test status
Simulation time 398462970 ps
CPU time 6.1 seconds
Started May 09 01:10:42 PM PDT 24
Finished May 09 01:10:50 PM PDT 24
Peak memory 221288 kb
Host smart-68e8cb5d-11a0-4e49-8e54-6cc31b504eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477202157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3477202157
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3008163762
Short name T956
Test name
Test status
Simulation time 78620841 ps
CPU time 0.8 seconds
Started May 09 01:10:36 PM PDT 24
Finished May 09 01:10:38 PM PDT 24
Peak memory 206492 kb
Host smart-73313902-510d-4bd8-98b9-ed98af1f9f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008163762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3008163762
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1824858914
Short name T55
Test name
Test status
Simulation time 22781060744 ps
CPU time 83.49 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 232904 kb
Host smart-a2c85edb-5885-4cf6-92f2-4352f131b357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824858914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1824858914
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3868038612
Short name T294
Test name
Test status
Simulation time 38979584048 ps
CPU time 193.36 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:13:56 PM PDT 24
Peak memory 249340 kb
Host smart-986fed4d-57bd-4500-b65c-2ea57474d8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868038612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3868038612
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3748905430
Short name T316
Test name
Test status
Simulation time 5156524545 ps
CPU time 28.18 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:11:10 PM PDT 24
Peak memory 217608 kb
Host smart-ab4893aa-502c-4919-98c2-8fec2399f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748905430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3748905430
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2527308457
Short name T597
Test name
Test status
Simulation time 110797702 ps
CPU time 4.17 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 234428 kb
Host smart-62006afb-a8d6-46af-bac0-e567422ff887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527308457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2527308457
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1760810056
Short name T201
Test name
Test status
Simulation time 1256919713 ps
CPU time 6.34 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:47 PM PDT 24
Peak memory 234040 kb
Host smart-8d035fcd-5dd6-4dc9-9bf8-0781f122ee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760810056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1760810056
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.87293903
Short name T915
Test name
Test status
Simulation time 549283504 ps
CPU time 8.8 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:51 PM PDT 24
Peak memory 234716 kb
Host smart-f6184173-2103-49f5-be0c-f4497dea96d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87293903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.87293903
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1809764155
Short name T751
Test name
Test status
Simulation time 410328938 ps
CPU time 2.24 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:43 PM PDT 24
Peak memory 218600 kb
Host smart-6e74a9fa-7476-49d3-88a5-9d5439286bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809764155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1809764155
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3159551229
Short name T810
Test name
Test status
Simulation time 2429561051 ps
CPU time 10.36 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:53 PM PDT 24
Peak memory 235932 kb
Host smart-d6ba9721-2b75-481c-a915-9dee5ca46348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159551229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3159551229
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3497927265
Short name T793
Test name
Test status
Simulation time 768040160 ps
CPU time 9.82 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 222480 kb
Host smart-9ba2a85f-4196-4096-8eb7-0e677d314b7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3497927265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3497927265
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2448362252
Short name T471
Test name
Test status
Simulation time 63723615810 ps
CPU time 60.28 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 237188 kb
Host smart-0bcd9613-5106-4e8a-8dad-f221415977a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448362252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2448362252
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.302540170
Short name T577
Test name
Test status
Simulation time 487392419 ps
CPU time 3.7 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:47 PM PDT 24
Peak memory 216476 kb
Host smart-7b266dda-70e9-4819-90ed-09cfa756615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302540170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.302540170
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.775030511
Short name T706
Test name
Test status
Simulation time 6497384354 ps
CPU time 20.15 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:59 PM PDT 24
Peak memory 216412 kb
Host smart-ab53db4e-b931-4ad6-8ab1-b8a3a8b3b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775030511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.775030511
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.211104285
Short name T868
Test name
Test status
Simulation time 258271377 ps
CPU time 1.08 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:43 PM PDT 24
Peak memory 207168 kb
Host smart-b700564b-e65b-4269-bc78-7885193b8fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211104285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.211104285
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.223582717
Short name T615
Test name
Test status
Simulation time 54948214 ps
CPU time 0.79 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:42 PM PDT 24
Peak memory 205860 kb
Host smart-186b9bf5-9211-4867-b1e6-88d98c4e08f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223582717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.223582717
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2714213773
Short name T512
Test name
Test status
Simulation time 296264901 ps
CPU time 3.82 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:45 PM PDT 24
Peak memory 217320 kb
Host smart-03aa33b3-2735-46e6-b906-5b864b0de649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714213773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2714213773
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1269773113
Short name T57
Test name
Test status
Simulation time 16597767 ps
CPU time 0.72 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:42 PM PDT 24
Peak memory 204748 kb
Host smart-e870a618-6ab7-4519-b3b9-b7f9f98deb1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269773113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1269773113
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1795942930
Short name T87
Test name
Test status
Simulation time 294499294 ps
CPU time 4.46 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 234396 kb
Host smart-30b21dfa-c632-4f41-9c4d-a23551059157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795942930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1795942930
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.197501207
Short name T606
Test name
Test status
Simulation time 51133616 ps
CPU time 0.82 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:41 PM PDT 24
Peak memory 206812 kb
Host smart-8b3bdee1-2bcc-42b0-bb6d-ca79241e0cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197501207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.197501207
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2322483450
Short name T244
Test name
Test status
Simulation time 63121328474 ps
CPU time 48.79 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:11:31 PM PDT 24
Peak memory 224676 kb
Host smart-50e225eb-b3b6-4fc3-9d0d-5618d0b28ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322483450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2322483450
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3370369840
Short name T45
Test name
Test status
Simulation time 40540799542 ps
CPU time 159.5 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:13:21 PM PDT 24
Peak memory 256268 kb
Host smart-07693bb1-5b79-434c-9867-0b06468b98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370369840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3370369840
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1662035199
Short name T958
Test name
Test status
Simulation time 30087004315 ps
CPU time 31.82 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:11:12 PM PDT 24
Peak memory 224760 kb
Host smart-1af0c758-93d7-4fd3-8261-1e55e1555083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662035199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1662035199
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3018656867
Short name T635
Test name
Test status
Simulation time 3061552627 ps
CPU time 28.27 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:11:10 PM PDT 24
Peak memory 224744 kb
Host smart-1c901eef-13aa-4b07-a625-59a76b78fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018656867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3018656867
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3303261211
Short name T214
Test name
Test status
Simulation time 11565879419 ps
CPU time 9.58 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:49 PM PDT 24
Peak memory 224640 kb
Host smart-4c7ab7c9-fa6e-41af-b5a7-2af0d2427515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303261211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3303261211
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.326056783
Short name T898
Test name
Test status
Simulation time 29182156440 ps
CPU time 132.24 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:12:54 PM PDT 24
Peak memory 249004 kb
Host smart-9748c2b7-9a0c-4304-ac68-2ff5b762f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326056783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.326056783
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2579753795
Short name T400
Test name
Test status
Simulation time 913683922 ps
CPU time 7.79 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 233412 kb
Host smart-256d9239-2687-4e0b-89e4-35d5afe6ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579753795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2579753795
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2703672578
Short name T411
Test name
Test status
Simulation time 2602030373 ps
CPU time 10.7 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:53 PM PDT 24
Peak memory 217596 kb
Host smart-60b9d92c-0157-4c1d-908c-a6a8377d74ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703672578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2703672578
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3716391838
Short name T730
Test name
Test status
Simulation time 957185454 ps
CPU time 5.31 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 220204 kb
Host smart-f07685f9-f4ee-4d07-9560-57ad56de142e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3716391838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3716391838
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2639245899
Short name T760
Test name
Test status
Simulation time 114958321 ps
CPU time 0.97 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:41 PM PDT 24
Peak memory 206816 kb
Host smart-3f77795c-6cf0-49e1-82d5-18258bcf35cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639245899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2639245899
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.396533858
Short name T314
Test name
Test status
Simulation time 7567380085 ps
CPU time 21.37 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:11:01 PM PDT 24
Peak memory 216460 kb
Host smart-0707b067-e390-4915-bb37-51921d2f8e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396533858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.396533858
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1811242282
Short name T485
Test name
Test status
Simulation time 18241452608 ps
CPU time 10.13 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 216564 kb
Host smart-15a6221e-7feb-437b-9f61-b47236e00bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811242282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1811242282
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3442863831
Short name T768
Test name
Test status
Simulation time 32262105 ps
CPU time 1.2 seconds
Started May 09 01:10:37 PM PDT 24
Finished May 09 01:10:39 PM PDT 24
Peak memory 216420 kb
Host smart-51ae30c8-31d5-4d45-a410-9d3caaaca999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442863831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3442863831
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1308068302
Short name T841
Test name
Test status
Simulation time 220619219 ps
CPU time 0.96 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 206872 kb
Host smart-f1f6278d-5404-4e8e-8036-686525e11f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308068302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1308068302
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4186686148
Short name T495
Test name
Test status
Simulation time 6714295495 ps
CPU time 13.47 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:55 PM PDT 24
Peak memory 238648 kb
Host smart-02d55270-6b41-4a37-ab66-a106e930a1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186686148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4186686148
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2021697564
Short name T375
Test name
Test status
Simulation time 40850212 ps
CPU time 0.71 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:40 PM PDT 24
Peak memory 205680 kb
Host smart-88703d31-b27e-4567-a2b2-5d51e9f2bd4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021697564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2021697564
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3547028294
Short name T552
Test name
Test status
Simulation time 141246449 ps
CPU time 2.11 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 216256 kb
Host smart-a748b6b4-0368-4fdc-870d-f71ba4ee44f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547028294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3547028294
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2227880650
Short name T336
Test name
Test status
Simulation time 33226242 ps
CPU time 0.77 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:41 PM PDT 24
Peak memory 206744 kb
Host smart-a5cfc082-b4a5-4d40-a970-87788d962068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227880650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2227880650
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3162126606
Short name T218
Test name
Test status
Simulation time 8025218052 ps
CPU time 35.93 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:11:17 PM PDT 24
Peak memory 250292 kb
Host smart-b8a1cf4f-6d8d-44f8-8ca1-38d652ba9beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162126606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3162126606
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.968152521
Short name T889
Test name
Test status
Simulation time 5300379270 ps
CPU time 50.4 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:11:33 PM PDT 24
Peak memory 249800 kb
Host smart-46aefab2-b836-41cc-82bb-1cd746b52637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968152521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.968152521
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1965440706
Short name T432
Test name
Test status
Simulation time 2938844946 ps
CPU time 31.3 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:11:15 PM PDT 24
Peak memory 224692 kb
Host smart-a9ffb336-2e46-405b-81f3-c0e887440448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965440706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1965440706
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4145680654
Short name T640
Test name
Test status
Simulation time 1532383323 ps
CPU time 7.9 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:47 PM PDT 24
Peak memory 233132 kb
Host smart-4968428c-e84b-4a30-b0b3-3158ba61c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145680654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4145680654
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.621113595
Short name T537
Test name
Test status
Simulation time 17726595402 ps
CPU time 114.35 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:12:38 PM PDT 24
Peak memory 224620 kb
Host smart-2b226c64-e89f-4b59-87da-c27d07778ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621113595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.621113595
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2824804559
Short name T496
Test name
Test status
Simulation time 2391840507 ps
CPU time 3.06 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:47 PM PDT 24
Peak memory 217976 kb
Host smart-5e9c3ca1-d453-4363-9849-3641154c0d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824804559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2824804559
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2276824140
Short name T885
Test name
Test status
Simulation time 52146024417 ps
CPU time 13.17 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:55 PM PDT 24
Peak memory 224728 kb
Host smart-5062e363-c0d6-45f7-882e-72647207329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276824140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2276824140
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1718951450
Short name T378
Test name
Test status
Simulation time 7568144397 ps
CPU time 8.32 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 219496 kb
Host smart-24595027-b655-4332-a37d-f4d958efaf16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1718951450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1718951450
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2616628114
Short name T84
Test name
Test status
Simulation time 9800569426 ps
CPU time 44.48 seconds
Started May 09 01:10:44 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 239496 kb
Host smart-4128dc01-dbc5-4e8d-9e4a-21ed709222c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616628114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2616628114
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.291041652
Short name T566
Test name
Test status
Simulation time 76906509 ps
CPU time 0.72 seconds
Started May 09 01:10:42 PM PDT 24
Finished May 09 01:10:45 PM PDT 24
Peak memory 205544 kb
Host smart-06324c46-80c2-40f4-a091-e4e04d800a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291041652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.291041652
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.457122929
Short name T829
Test name
Test status
Simulation time 27275278162 ps
CPU time 13.47 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 216460 kb
Host smart-d0880ac3-1150-4271-9b58-66cb0cdd53de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457122929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.457122929
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.594009115
Short name T687
Test name
Test status
Simulation time 655571194 ps
CPU time 2.53 seconds
Started May 09 01:10:36 PM PDT 24
Finished May 09 01:10:40 PM PDT 24
Peak memory 216300 kb
Host smart-99e25972-f0d6-428a-b3ed-32aa0b4db914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594009115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.594009115
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3201462812
Short name T423
Test name
Test status
Simulation time 83158770 ps
CPU time 0.76 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:42 PM PDT 24
Peak memory 205852 kb
Host smart-b9cd7d83-74ff-4571-8c85-7e033d61606e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201462812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3201462812
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3808424948
Short name T518
Test name
Test status
Simulation time 8413738142 ps
CPU time 13.42 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:57 PM PDT 24
Peak memory 220260 kb
Host smart-0315a202-1652-4623-b68f-0915b0f0eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808424948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3808424948
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2163495139
Short name T347
Test name
Test status
Simulation time 30431729 ps
CPU time 0.7 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 205004 kb
Host smart-2cbea167-a997-47b9-9fed-52183a7950e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163495139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2163495139
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2062016014
Short name T594
Test name
Test status
Simulation time 3888122536 ps
CPU time 10.81 seconds
Started May 09 01:10:43 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 219000 kb
Host smart-91eea422-47ea-4feb-bfa9-e6a2a5d41f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062016014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2062016014
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1847501784
Short name T349
Test name
Test status
Simulation time 58139670 ps
CPU time 0.76 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 205776 kb
Host smart-1c0f80a1-1ea8-432c-b1ad-e94727047cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847501784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1847501784
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3056408758
Short name T366
Test name
Test status
Simulation time 9736216773 ps
CPU time 78.53 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:12:00 PM PDT 24
Peak memory 253316 kb
Host smart-1ac5d352-b2be-4193-864f-285d1afcaf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056408758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3056408758
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3952586974
Short name T78
Test name
Test status
Simulation time 152662482874 ps
CPU time 243.62 seconds
Started May 09 01:10:42 PM PDT 24
Finished May 09 01:14:48 PM PDT 24
Peak memory 249620 kb
Host smart-2632d0b3-ca5e-48fd-a194-469620191a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952586974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3952586974
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3277436614
Short name T47
Test name
Test status
Simulation time 11845730014 ps
CPU time 178.23 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:13:41 PM PDT 24
Peak memory 253020 kb
Host smart-ee436cf7-2560-4808-a81e-6f5ff1a6742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277436614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3277436614
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.223807667
Short name T581
Test name
Test status
Simulation time 481492514 ps
CPU time 6.12 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 224636 kb
Host smart-3665e6e5-9450-41ec-a678-ad521181361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223807667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.223807667
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1448053974
Short name T816
Test name
Test status
Simulation time 220578433 ps
CPU time 3.43 seconds
Started May 09 01:10:44 PM PDT 24
Finished May 09 01:10:49 PM PDT 24
Peak memory 234344 kb
Host smart-88583911-cee3-40e5-a06e-ea440c2b34ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448053974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1448053974
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1932091432
Short name T952
Test name
Test status
Simulation time 510448709 ps
CPU time 6.52 seconds
Started May 09 01:10:43 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 233048 kb
Host smart-250e37dd-ebe0-4b2b-bd10-eb7842dfa04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932091432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1932091432
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1918152974
Short name T696
Test name
Test status
Simulation time 258408273 ps
CPU time 2.81 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:43 PM PDT 24
Peak memory 218756 kb
Host smart-a1b27729-eadf-410b-a219-5c177b0df90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918152974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1918152974
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.634346087
Short name T179
Test name
Test status
Simulation time 9872165659 ps
CPU time 28.16 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:11:07 PM PDT 24
Peak memory 234792 kb
Host smart-40166c26-4161-4595-be47-1de529e4d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634346087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.634346087
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.123461032
Short name T381
Test name
Test status
Simulation time 305457228 ps
CPU time 3.39 seconds
Started May 09 01:10:42 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 220380 kb
Host smart-1d8cb72d-1576-4297-8ead-b28169ca9380
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123461032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.123461032
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2191612442
Short name T686
Test name
Test status
Simulation time 22878894 ps
CPU time 0.71 seconds
Started May 09 01:10:36 PM PDT 24
Finished May 09 01:10:38 PM PDT 24
Peak memory 205576 kb
Host smart-13a8d46f-5f32-4529-8b0c-87333b998ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191612442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2191612442
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1921936906
Short name T340
Test name
Test status
Simulation time 1468102609 ps
CPU time 6.04 seconds
Started May 09 01:10:39 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 216440 kb
Host smart-66423ecc-87a7-4b26-a576-78d988615fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921936906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1921936906
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3596876113
Short name T562
Test name
Test status
Simulation time 121798896 ps
CPU time 2.48 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:54 PM PDT 24
Peak memory 216380 kb
Host smart-d79b6820-b456-49c7-924f-66fcf24a3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596876113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3596876113
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2456286522
Short name T364
Test name
Test status
Simulation time 71267326 ps
CPU time 0.8 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:43 PM PDT 24
Peak memory 205808 kb
Host smart-75f22d13-690f-400b-af5c-12b9e75cb837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456286522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2456286522
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.895006290
Short name T716
Test name
Test status
Simulation time 139542041 ps
CPU time 2.31 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:10:43 PM PDT 24
Peak memory 212964 kb
Host smart-23689814-038a-4f14-927f-befb02b73a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895006290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.895006290
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.744485241
Short name T953
Test name
Test status
Simulation time 32343785 ps
CPU time 0.75 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:10:53 PM PDT 24
Peak memory 205020 kb
Host smart-898001ed-08dd-45ea-941e-c9509161813c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744485241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.744485241
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.4185355699
Short name T564
Test name
Test status
Simulation time 101026114 ps
CPU time 2.18 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:10:51 PM PDT 24
Peak memory 221104 kb
Host smart-4de1dc43-b243-40d6-b6ac-93c123ba2675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185355699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4185355699
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.469736729
Short name T790
Test name
Test status
Simulation time 70689131 ps
CPU time 0.75 seconds
Started May 09 01:10:42 PM PDT 24
Finished May 09 01:10:45 PM PDT 24
Peak memory 205420 kb
Host smart-8a27f2eb-991e-4b15-8b3c-6fd73e024f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469736729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.469736729
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3652536970
Short name T607
Test name
Test status
Simulation time 7208432271 ps
CPU time 90.63 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:12:24 PM PDT 24
Peak memory 249088 kb
Host smart-eff8550c-c124-4afc-a719-6a289684c509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652536970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3652536970
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3057564747
Short name T325
Test name
Test status
Simulation time 15393282937 ps
CPU time 96.73 seconds
Started May 09 01:10:53 PM PDT 24
Finished May 09 01:12:31 PM PDT 24
Peak memory 251968 kb
Host smart-dac536e6-5aec-4f88-bdfb-8500c9b6ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057564747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3057564747
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2774908569
Short name T977
Test name
Test status
Simulation time 261765429602 ps
CPU time 242.55 seconds
Started May 09 01:10:52 PM PDT 24
Finished May 09 01:14:56 PM PDT 24
Peak memory 252568 kb
Host smart-4d6de4bd-7ea7-4e79-b83e-d6d65ed6ca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774908569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2774908569
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.859612806
Short name T148
Test name
Test status
Simulation time 42892915932 ps
CPU time 53.48 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:11:42 PM PDT 24
Peak memory 240032 kb
Host smart-1f1f259a-309f-4dc3-b801-30dd3457a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859612806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.859612806
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.853765144
Short name T380
Test name
Test status
Simulation time 122756749 ps
CPU time 2.23 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:54 PM PDT 24
Peak memory 216124 kb
Host smart-7e95a349-f0f1-4d1c-b4a4-3001f72bdbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853765144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.853765144
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.926490271
Short name T797
Test name
Test status
Simulation time 203269588 ps
CPU time 2.11 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 216096 kb
Host smart-b346090c-6adc-43bb-9681-0e844a84dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926490271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.926490271
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1897073690
Short name T799
Test name
Test status
Simulation time 2235198348 ps
CPU time 3.75 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:55 PM PDT 24
Peak memory 218760 kb
Host smart-c3802d3d-4249-44e2-afb6-34828cef543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897073690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1897073690
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.850229606
Short name T511
Test name
Test status
Simulation time 12923888180 ps
CPU time 11.36 seconds
Started May 09 01:10:43 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 233288 kb
Host smart-fc06b4c7-3f48-4717-8a7a-eabfdc0a3202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850229606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.850229606
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1167059007
Short name T609
Test name
Test status
Simulation time 1047093475 ps
CPU time 12.51 seconds
Started May 09 01:10:56 PM PDT 24
Finished May 09 01:11:10 PM PDT 24
Peak memory 222260 kb
Host smart-8bb80a17-5b5d-4f92-8b1a-50644c9c018b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1167059007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1167059007
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2561269126
Short name T58
Test name
Test status
Simulation time 17484133814 ps
CPU time 151.1 seconds
Started May 09 01:10:52 PM PDT 24
Finished May 09 01:13:25 PM PDT 24
Peak memory 257516 kb
Host smart-b203c77c-84a9-4a89-aa90-fac9847c23f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561269126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2561269126
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1482629571
Short name T386
Test name
Test status
Simulation time 5059749132 ps
CPU time 28.38 seconds
Started May 09 01:10:38 PM PDT 24
Finished May 09 01:11:09 PM PDT 24
Peak memory 216476 kb
Host smart-aa93c2d9-69bc-4145-9afd-d37c15a789cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482629571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1482629571
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.303295015
Short name T383
Test name
Test status
Simulation time 714531459 ps
CPU time 4.21 seconds
Started May 09 01:10:41 PM PDT 24
Finished May 09 01:10:48 PM PDT 24
Peak memory 215936 kb
Host smart-a4206bf1-0ea5-443e-badd-f1c482427008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303295015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.303295015
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.362260021
Short name T371
Test name
Test status
Simulation time 363658469 ps
CPU time 1.52 seconds
Started May 09 01:10:40 PM PDT 24
Finished May 09 01:10:44 PM PDT 24
Peak memory 216452 kb
Host smart-4f0ce5d4-002b-44fe-84c5-7690e9f0519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362260021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.362260021
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3651447354
Short name T500
Test name
Test status
Simulation time 18608550 ps
CPU time 0.74 seconds
Started May 09 01:10:42 PM PDT 24
Finished May 09 01:10:45 PM PDT 24
Peak memory 205840 kb
Host smart-ef249e44-2f95-4bfa-a003-c8fc0b75bd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651447354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3651447354
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2376313322
Short name T981
Test name
Test status
Simulation time 5796849623 ps
CPU time 20.29 seconds
Started May 09 01:10:47 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 217888 kb
Host smart-858f4443-a176-4dc8-8e1f-f027ce6b36cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376313322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2376313322
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3640800297
Short name T896
Test name
Test status
Simulation time 47220003 ps
CPU time 0.76 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:10:59 PM PDT 24
Peak memory 204792 kb
Host smart-12a47a18-e3ec-4d3e-847a-373a392fb266
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640800297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3640800297
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3204089831
Short name T86
Test name
Test status
Simulation time 276906287 ps
CPU time 4.65 seconds
Started May 09 01:10:52 PM PDT 24
Finished May 09 01:10:58 PM PDT 24
Peak memory 219672 kb
Host smart-c253cd0f-9382-4d24-acc1-b6a907e60dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204089831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3204089831
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1175600102
Short name T463
Test name
Test status
Simulation time 51735251 ps
CPU time 0.75 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 205392 kb
Host smart-141832c9-0999-4ff3-9e3c-ab46973dffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175600102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1175600102
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.901254319
Short name T7
Test name
Test status
Simulation time 48556152048 ps
CPU time 88.52 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:12:27 PM PDT 24
Peak memory 249228 kb
Host smart-c942b7bf-787b-4193-9f9c-1590a2c2f6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901254319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.901254319
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1207186439
Short name T20
Test name
Test status
Simulation time 2455546467 ps
CPU time 51.43 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:11:44 PM PDT 24
Peak memory 249368 kb
Host smart-43de79de-8f5c-4744-bee8-efbddec2d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207186439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1207186439
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2403104141
Short name T283
Test name
Test status
Simulation time 37608534804 ps
CPU time 349.33 seconds
Started May 09 01:10:52 PM PDT 24
Finished May 09 01:16:43 PM PDT 24
Peak memory 256920 kb
Host smart-2d19b4e0-4fa5-49b2-83a5-a1111f44f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403104141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2403104141
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1876025611
Short name T211
Test name
Test status
Simulation time 61688676 ps
CPU time 2.53 seconds
Started May 09 01:10:49 PM PDT 24
Finished May 09 01:10:53 PM PDT 24
Peak memory 216712 kb
Host smart-fc309eba-fc6a-4f5c-a202-3564797db10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876025611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1876025611
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.473345431
Short name T178
Test name
Test status
Simulation time 13837325247 ps
CPU time 33.72 seconds
Started May 09 01:10:53 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 249224 kb
Host smart-027af8b4-47f6-450f-8736-f879c50575c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473345431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.473345431
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3484676835
Short name T489
Test name
Test status
Simulation time 262884735 ps
CPU time 4.42 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:56 PM PDT 24
Peak memory 225908 kb
Host smart-12fb5819-e754-42e3-b979-ccceb3826fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484676835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3484676835
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.774211830
Short name T682
Test name
Test status
Simulation time 20444178019 ps
CPU time 19.12 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 238348 kb
Host smart-1dc6149d-1128-4951-aad1-30cd74b86a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774211830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.774211830
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1992332188
Short name T12
Test name
Test status
Simulation time 19932170479 ps
CPU time 20.33 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:11:13 PM PDT 24
Peak memory 223236 kb
Host smart-f7b78c57-be93-4627-b9da-2ceab2349a4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1992332188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1992332188
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1721746684
Short name T681
Test name
Test status
Simulation time 36068656 ps
CPU time 0.97 seconds
Started May 09 01:10:52 PM PDT 24
Finished May 09 01:10:55 PM PDT 24
Peak memory 206480 kb
Host smart-96eb5145-d181-4d4e-a375-91cfb229b2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721746684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1721746684
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3532678155
Short name T403
Test name
Test status
Simulation time 6385418252 ps
CPU time 23.35 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:11:12 PM PDT 24
Peak memory 220024 kb
Host smart-8165768e-03d7-4c72-951d-299cd10ff1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532678155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3532678155
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.134563115
Short name T353
Test name
Test status
Simulation time 8231264576 ps
CPU time 25.36 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:11:15 PM PDT 24
Peak memory 216452 kb
Host smart-382e5352-a7e4-4e3a-b759-85b5c22d2f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134563115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.134563115
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2544402491
Short name T440
Test name
Test status
Simulation time 287425326 ps
CPU time 1.64 seconds
Started May 09 01:10:49 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 216412 kb
Host smart-4b7d9c3b-90f9-4dbd-a65f-bcfb7c47e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544402491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2544402491
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3415164922
Short name T691
Test name
Test status
Simulation time 393542572 ps
CPU time 0.94 seconds
Started May 09 01:10:47 PM PDT 24
Finished May 09 01:10:50 PM PDT 24
Peak memory 205736 kb
Host smart-d8c9ed52-a702-42e1-8831-c566ebf13b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415164922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3415164922
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3223302730
Short name T181
Test name
Test status
Simulation time 311084852 ps
CPU time 7.54 seconds
Started May 09 01:10:49 PM PDT 24
Finished May 09 01:10:57 PM PDT 24
Peak memory 248320 kb
Host smart-e172d362-6f59-4549-abe5-1a1b85ed7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223302730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3223302730
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1873501409
Short name T721
Test name
Test status
Simulation time 40096948 ps
CPU time 0.7 seconds
Started May 09 01:10:58 PM PDT 24
Finished May 09 01:11:00 PM PDT 24
Peak memory 204716 kb
Host smart-77a35c2a-e31e-4321-ad9d-1de1891fa838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873501409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1873501409
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.164100966
Short name T343
Test name
Test status
Simulation time 4600287848 ps
CPU time 5.4 seconds
Started May 09 01:10:52 PM PDT 24
Finished May 09 01:10:59 PM PDT 24
Peak memory 218088 kb
Host smart-e765a9bc-5602-48af-a860-305510295ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164100966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.164100966
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2209982153
Short name T426
Test name
Test status
Simulation time 56707752 ps
CPU time 0.82 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:52 PM PDT 24
Peak memory 206440 kb
Host smart-abba033e-f9fc-47b3-a680-8bf9c008181f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209982153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2209982153
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3223088044
Short name T240
Test name
Test status
Simulation time 139840126555 ps
CPU time 272.02 seconds
Started May 09 01:10:56 PM PDT 24
Finished May 09 01:15:30 PM PDT 24
Peak memory 249288 kb
Host smart-625eddf4-f812-41e0-bbe8-9f75f0b7a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223088044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3223088044
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3983681846
Short name T247
Test name
Test status
Simulation time 5793899843 ps
CPU time 31.67 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 238492 kb
Host smart-223ff522-1d94-4de3-b095-22ee69f23fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983681846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3983681846
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.4240743532
Short name T256
Test name
Test status
Simulation time 342871477662 ps
CPU time 355.71 seconds
Started May 09 01:10:55 PM PDT 24
Finished May 09 01:16:51 PM PDT 24
Peak memory 266068 kb
Host smart-fcbd0f87-bf48-48b6-9dc4-9c629e59203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240743532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.4240743532
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3013398718
Short name T311
Test name
Test status
Simulation time 1654699791 ps
CPU time 23.92 seconds
Started May 09 01:10:47 PM PDT 24
Finished May 09 01:11:13 PM PDT 24
Peak memory 238632 kb
Host smart-5ed6274a-990d-4102-8a39-73758b1086ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013398718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3013398718
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2477600995
Short name T404
Test name
Test status
Simulation time 740027021 ps
CPU time 8.49 seconds
Started May 09 01:10:48 PM PDT 24
Finished May 09 01:10:58 PM PDT 24
Peak memory 233500 kb
Host smart-063d46b6-57b0-4387-89a7-b091f2f3a42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477600995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2477600995
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2576076090
Short name T501
Test name
Test status
Simulation time 9407014359 ps
CPU time 58.54 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:11:51 PM PDT 24
Peak memory 232356 kb
Host smart-11541c42-dbcf-40f3-9779-a0e9fae34861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576076090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2576076090
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2963524098
Short name T758
Test name
Test status
Simulation time 663461035 ps
CPU time 9.97 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 229524 kb
Host smart-c118ffa0-1110-413f-ae1d-71f757b28b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963524098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2963524098
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1766512485
Short name T174
Test name
Test status
Simulation time 17636962477 ps
CPU time 17.72 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:11:09 PM PDT 24
Peak memory 234568 kb
Host smart-53034722-6276-48a1-9dde-0e7280f6bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766512485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1766512485
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1919268205
Short name T661
Test name
Test status
Simulation time 150846617 ps
CPU time 3.89 seconds
Started May 09 01:10:53 PM PDT 24
Finished May 09 01:10:58 PM PDT 24
Peak memory 220216 kb
Host smart-e842633f-9e5c-4abb-b902-e3315f08aebd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1919268205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1919268205
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3730920567
Short name T704
Test name
Test status
Simulation time 23679106955 ps
CPU time 234.22 seconds
Started May 09 01:10:55 PM PDT 24
Finished May 09 01:14:50 PM PDT 24
Peak memory 249808 kb
Host smart-4a7d3c96-5a7e-4809-a3cd-89cf40ad0d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730920567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3730920567
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3826378085
Short name T852
Test name
Test status
Simulation time 2362103757 ps
CPU time 21.55 seconds
Started May 09 01:10:49 PM PDT 24
Finished May 09 01:11:12 PM PDT 24
Peak memory 216588 kb
Host smart-b9ba4aee-cd23-4ad7-9934-416f816ccafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826378085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3826378085
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1593247967
Short name T971
Test name
Test status
Simulation time 43235779 ps
CPU time 0.69 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:10:59 PM PDT 24
Peak memory 205492 kb
Host smart-d126a9ad-94f7-4c7b-b1f5-e44a1058f903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593247967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1593247967
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2429037036
Short name T493
Test name
Test status
Simulation time 25112248 ps
CPU time 0.97 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:10:54 PM PDT 24
Peak memory 206980 kb
Host smart-bce99fab-391f-430d-bb20-cd01c24289f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429037036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2429037036
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1051517359
Short name T656
Test name
Test status
Simulation time 58974500 ps
CPU time 0.86 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:10:53 PM PDT 24
Peak memory 205828 kb
Host smart-2c8e9216-f134-4278-b057-69e3d1180fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051517359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1051517359
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3858634839
Short name T650
Test name
Test status
Simulation time 4275745828 ps
CPU time 10.82 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:11:03 PM PDT 24
Peak memory 226816 kb
Host smart-b92e0c5c-f4f4-4c8b-b600-689bac9ce70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858634839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3858634839
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.638589687
Short name T944
Test name
Test status
Simulation time 11325991 ps
CPU time 0.72 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:10:59 PM PDT 24
Peak memory 205308 kb
Host smart-2bb249d8-dfab-4b54-a3dc-ae4b696b8fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638589687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.638589687
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3909802905
Short name T672
Test name
Test status
Simulation time 1124394240 ps
CPU time 6.15 seconds
Started May 09 01:10:56 PM PDT 24
Finished May 09 01:11:04 PM PDT 24
Peak memory 237964 kb
Host smart-32ecaf91-2a49-41e2-ac46-cbdf14dcf2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909802905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3909802905
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2664999038
Short name T895
Test name
Test status
Simulation time 22366091 ps
CPU time 0.74 seconds
Started May 09 01:10:55 PM PDT 24
Finished May 09 01:10:57 PM PDT 24
Peak memory 205780 kb
Host smart-7dd50561-f923-4077-ac02-007fddcc7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664999038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2664999038
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.143985058
Short name T791
Test name
Test status
Simulation time 5877633084 ps
CPU time 62.33 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:11:53 PM PDT 24
Peak memory 249324 kb
Host smart-275f13c2-d712-4137-a789-d4e7e2c7e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143985058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.143985058
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3674321856
Short name T907
Test name
Test status
Simulation time 72459925465 ps
CPU time 146.15 seconds
Started May 09 01:10:56 PM PDT 24
Finished May 09 01:13:24 PM PDT 24
Peak memory 236592 kb
Host smart-9b8dfdc3-596c-4429-87a9-98c051b5b673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674321856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3674321856
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3688501475
Short name T285
Test name
Test status
Simulation time 283127858 ps
CPU time 5.83 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:04 PM PDT 24
Peak memory 224488 kb
Host smart-b17ffd5a-2466-41b5-a50b-ac13f4c0c607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688501475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3688501475
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1338130101
Short name T296
Test name
Test status
Simulation time 478337519 ps
CPU time 3.2 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:01 PM PDT 24
Peak memory 218436 kb
Host smart-c25ef01d-c0d6-4dce-8926-315d57b40f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338130101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1338130101
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2416495756
Short name T930
Test name
Test status
Simulation time 86326058 ps
CPU time 2.23 seconds
Started May 09 01:10:50 PM PDT 24
Finished May 09 01:10:54 PM PDT 24
Peak memory 216196 kb
Host smart-efd33ad2-0bde-4881-947b-1df21c77890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416495756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2416495756
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1956628616
Short name T931
Test name
Test status
Simulation time 2839284160 ps
CPU time 7.68 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:07 PM PDT 24
Peak memory 218916 kb
Host smart-29c91358-4225-4a54-8c1f-aa16dcd3f944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956628616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1956628616
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1990717209
Short name T104
Test name
Test status
Simulation time 506710514 ps
CPU time 2.09 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:01 PM PDT 24
Peak memory 216232 kb
Host smart-b71b5ca2-116d-4702-8838-a96150f43d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990717209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1990717209
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3537780603
Short name T339
Test name
Test status
Simulation time 1828510559 ps
CPU time 7.76 seconds
Started May 09 01:10:53 PM PDT 24
Finished May 09 01:11:02 PM PDT 24
Peak memory 222092 kb
Host smart-97deb5cc-7286-4658-9f7b-2153c2b46efe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3537780603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3537780603
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4179925815
Short name T370
Test name
Test status
Simulation time 36596222247 ps
CPU time 90.81 seconds
Started May 09 01:10:56 PM PDT 24
Finished May 09 01:12:28 PM PDT 24
Peak memory 241136 kb
Host smart-6ee2c534-10a7-42c4-9fb5-5cd83d384ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179925815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4179925815
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1991834864
Short name T547
Test name
Test status
Simulation time 2686617716 ps
CPU time 26.68 seconds
Started May 09 01:10:58 PM PDT 24
Finished May 09 01:11:26 PM PDT 24
Peak memory 216516 kb
Host smart-c694a8f3-218b-4135-b4dc-f9fd9d8574b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991834864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1991834864
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1750530145
Short name T616
Test name
Test status
Simulation time 315289762 ps
CPU time 1.95 seconds
Started May 09 01:10:51 PM PDT 24
Finished May 09 01:10:54 PM PDT 24
Peak memory 207996 kb
Host smart-d8788d57-a772-4fc2-96b4-41779528539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750530145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1750530145
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1806739593
Short name T3
Test name
Test status
Simulation time 146826137 ps
CPU time 1.53 seconds
Started May 09 01:10:58 PM PDT 24
Finished May 09 01:11:01 PM PDT 24
Peak memory 216404 kb
Host smart-7c09fde7-a7ca-45d9-b3e5-d9e0d7b8ff48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806739593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1806739593
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3166058579
Short name T345
Test name
Test status
Simulation time 89317210 ps
CPU time 0.93 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:00 PM PDT 24
Peak memory 206184 kb
Host smart-fd89ccc1-97a4-4b97-a025-784dc7273986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166058579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3166058579
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1286230187
Short name T197
Test name
Test status
Simulation time 5414462839 ps
CPU time 13.86 seconds
Started May 09 01:10:57 PM PDT 24
Finished May 09 01:11:12 PM PDT 24
Peak memory 238904 kb
Host smart-b6388cdc-69f4-433c-a7c2-fc35230f6c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286230187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1286230187
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1362906711
Short name T437
Test name
Test status
Simulation time 39226336 ps
CPU time 0.73 seconds
Started May 09 01:08:38 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 205720 kb
Host smart-c6e15eb2-afdf-49dc-b23f-3f98a457a38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362906711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
362906711
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3067332365
Short name T583
Test name
Test status
Simulation time 1089880070 ps
CPU time 12.21 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:50 PM PDT 24
Peak memory 217752 kb
Host smart-c907d5e3-bf02-44be-be04-53d2e145a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067332365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3067332365
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2025867499
Short name T14
Test name
Test status
Simulation time 61895429 ps
CPU time 0.79 seconds
Started May 09 01:08:32 PM PDT 24
Finished May 09 01:08:35 PM PDT 24
Peak memory 206428 kb
Host smart-4ca9cc87-4fb0-4075-9eb7-9d341119f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025867499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2025867499
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1526535263
Short name T905
Test name
Test status
Simulation time 41029547498 ps
CPU time 287.83 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:13:22 PM PDT 24
Peak memory 252512 kb
Host smart-8cb1515a-5c8f-474c-9268-4eb86e9d2efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526535263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1526535263
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3099058943
Short name T427
Test name
Test status
Simulation time 3256694350 ps
CPU time 30.79 seconds
Started May 09 01:08:39 PM PDT 24
Finished May 09 01:09:12 PM PDT 24
Peak memory 221880 kb
Host smart-cd459a10-e5e4-48ac-be0d-e6470f02be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099058943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3099058943
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2862285344
Short name T456
Test name
Test status
Simulation time 656484950 ps
CPU time 10.39 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:49 PM PDT 24
Peak memory 217628 kb
Host smart-34f8d75a-81ef-43a3-86dc-68cf8f08711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862285344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2862285344
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3028056285
Short name T360
Test name
Test status
Simulation time 751080985 ps
CPU time 4.44 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 224592 kb
Host smart-2c695986-5558-4079-8e3c-73e5c342a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028056285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3028056285
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3635558286
Short name T434
Test name
Test status
Simulation time 522096725 ps
CPU time 2.45 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 233764 kb
Host smart-884ac8c9-5007-4191-b99d-4e44a393e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635558286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3635558286
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4212113489
Short name T729
Test name
Test status
Simulation time 129188189 ps
CPU time 2.38 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:40 PM PDT 24
Peak memory 224536 kb
Host smart-def027a0-6d62-4a9c-8d68-ad8102f81416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212113489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4212113489
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1816072523
Short name T752
Test name
Test status
Simulation time 129154798 ps
CPU time 1.11 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 216776 kb
Host smart-39bac39d-afac-45c5-b017-aeead11fa21e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816072523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1816072523
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.125621613
Short name T70
Test name
Test status
Simulation time 164605397 ps
CPU time 3.42 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:40 PM PDT 24
Peak memory 232968 kb
Host smart-8f9793ae-d287-409b-9b2b-1c0d294f3281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125621613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
125621613
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.771509540
Short name T967
Test name
Test status
Simulation time 18318987516 ps
CPU time 13.27 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:49 PM PDT 24
Peak memory 218680 kb
Host smart-39e8cebd-e9ea-4a6e-9620-b58323f42948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771509540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.771509540
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3547818338
Short name T602
Test name
Test status
Simulation time 941538500 ps
CPU time 4.66 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:43 PM PDT 24
Peak memory 218692 kb
Host smart-e45485d2-e199-495c-a751-a6187eb92e70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3547818338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3547818338
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1294847602
Short name T68
Test name
Test status
Simulation time 145581346 ps
CPU time 1.1 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 235180 kb
Host smart-a066548a-2502-491e-b456-f6a2564a9863
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294847602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1294847602
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.757599331
Short name T168
Test name
Test status
Simulation time 105972253 ps
CPU time 0.97 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 206648 kb
Host smart-8e2e7baa-a638-442f-9518-2831f0d772b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757599331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.757599331
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2308919863
Short name T662
Test name
Test status
Simulation time 9876778147 ps
CPU time 14.8 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:08:54 PM PDT 24
Peak memory 216572 kb
Host smart-6793a8f5-4ec7-4565-9427-1e993d2eff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308919863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2308919863
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1692320276
Short name T610
Test name
Test status
Simulation time 217927985 ps
CPU time 2.35 seconds
Started May 09 01:08:32 PM PDT 24
Finished May 09 01:08:37 PM PDT 24
Peak memory 216380 kb
Host smart-3e29ca8c-15ea-4470-a933-6bb0aa9148a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692320276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1692320276
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1933391821
Short name T398
Test name
Test status
Simulation time 48625621 ps
CPU time 0.91 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 206600 kb
Host smart-ed831e7d-f3df-4e81-957f-80e2550c4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933391821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1933391821
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1038688201
Short name T735
Test name
Test status
Simulation time 261746686 ps
CPU time 1.08 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:36 PM PDT 24
Peak memory 206356 kb
Host smart-44b34a33-4d84-4807-8f65-c956418abdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038688201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1038688201
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.932083072
Short name T774
Test name
Test status
Simulation time 290436770 ps
CPU time 2.2 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 218820 kb
Host smart-9b6ebbb2-bbc2-4b7f-954c-370c64c55c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932083072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.932083072
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.65695836
Short name T9
Test name
Test status
Simulation time 47681571 ps
CPU time 0.71 seconds
Started May 09 01:11:01 PM PDT 24
Finished May 09 01:11:03 PM PDT 24
Peak memory 204748 kb
Host smart-7e10f683-6678-445f-8fdd-77c597d04d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65695836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.65695836
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.16485508
Short name T813
Test name
Test status
Simulation time 105722165 ps
CPU time 2.44 seconds
Started May 09 01:11:03 PM PDT 24
Finished May 09 01:11:06 PM PDT 24
Peak memory 233440 kb
Host smart-c63a20fe-a5ad-4c82-b067-cd83fb216008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16485508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.16485508
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.4039831181
Short name T698
Test name
Test status
Simulation time 16824621 ps
CPU time 0.77 seconds
Started May 09 01:11:00 PM PDT 24
Finished May 09 01:11:01 PM PDT 24
Peak memory 205408 kb
Host smart-9e9b139d-430f-4ba8-a718-3fa65c024cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039831181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.4039831181
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3744588098
Short name T947
Test name
Test status
Simulation time 6442644893 ps
CPU time 30.04 seconds
Started May 09 01:10:59 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 249344 kb
Host smart-7a1d7e4a-b5f2-4dfe-9e18-d8907bab65ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744588098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3744588098
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2358067737
Short name T204
Test name
Test status
Simulation time 23365266073 ps
CPU time 251.66 seconds
Started May 09 01:10:59 PM PDT 24
Finished May 09 01:15:12 PM PDT 24
Peak memory 250404 kb
Host smart-2ed32535-bf4a-4052-b816-bd00cadd09ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358067737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2358067737
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3482242692
Short name T862
Test name
Test status
Simulation time 11920212495 ps
CPU time 59.55 seconds
Started May 09 01:11:07 PM PDT 24
Finished May 09 01:12:08 PM PDT 24
Peak memory 252252 kb
Host smart-0c380878-4997-4bda-8e70-d92191881753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482242692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3482242692
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2778667435
Short name T892
Test name
Test status
Simulation time 414258091 ps
CPU time 6.7 seconds
Started May 09 01:10:59 PM PDT 24
Finished May 09 01:11:07 PM PDT 24
Peak memory 232772 kb
Host smart-b7291103-db11-43c0-a3ff-4b52e9eb9c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778667435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2778667435
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.178402242
Short name T288
Test name
Test status
Simulation time 1892212643 ps
CPU time 13.55 seconds
Started May 09 01:11:07 PM PDT 24
Finished May 09 01:11:21 PM PDT 24
Peak memory 221776 kb
Host smart-fe744c8c-3fdf-44eb-a8a3-5526820f3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178402242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.178402242
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2447280275
Short name T646
Test name
Test status
Simulation time 21046161923 ps
CPU time 78.36 seconds
Started May 09 01:11:07 PM PDT 24
Finished May 09 01:12:26 PM PDT 24
Peak memory 232148 kb
Host smart-b3cf6b1a-da7e-47c8-8f95-e1408b61b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447280275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2447280275
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.362000404
Short name T187
Test name
Test status
Simulation time 2354985674 ps
CPU time 10.89 seconds
Started May 09 01:11:03 PM PDT 24
Finished May 09 01:11:15 PM PDT 24
Peak memory 218732 kb
Host smart-61610f3c-1067-4d09-97d5-369092c59423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362000404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.362000404
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2961259566
Short name T933
Test name
Test status
Simulation time 15544851277 ps
CPU time 12.3 seconds
Started May 09 01:11:03 PM PDT 24
Finished May 09 01:11:16 PM PDT 24
Peak memory 224556 kb
Host smart-112965fa-e9d6-44dd-bead-0e555644373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961259566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2961259566
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3862950941
Short name T757
Test name
Test status
Simulation time 372504244 ps
CPU time 3.45 seconds
Started May 09 01:11:03 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 223044 kb
Host smart-6890acba-c469-4ab3-8401-90e737dd6e83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3862950941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3862950941
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3650246580
Short name T573
Test name
Test status
Simulation time 57502936 ps
CPU time 0.99 seconds
Started May 09 01:11:06 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 206568 kb
Host smart-1d646698-1a15-403b-bc34-8e991e4b38ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650246580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3650246580
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.808065527
Short name T695
Test name
Test status
Simulation time 1500134147 ps
CPU time 15.1 seconds
Started May 09 01:11:00 PM PDT 24
Finished May 09 01:11:16 PM PDT 24
Peak memory 216336 kb
Host smart-30149559-1dbc-4446-a0d6-19394bba2ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808065527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.808065527
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.903570316
Short name T805
Test name
Test status
Simulation time 69263987853 ps
CPU time 16.2 seconds
Started May 09 01:11:02 PM PDT 24
Finished May 09 01:11:19 PM PDT 24
Peak memory 216516 kb
Host smart-c1bac45a-2802-4765-9dfe-d6b4d89eca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903570316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.903570316
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3382558698
Short name T700
Test name
Test status
Simulation time 78656727 ps
CPU time 0.86 seconds
Started May 09 01:11:03 PM PDT 24
Finished May 09 01:11:05 PM PDT 24
Peak memory 206816 kb
Host smart-f19ae134-51df-4eb1-b2ee-8b483ca3edd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382558698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3382558698
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.633075576
Short name T531
Test name
Test status
Simulation time 735837487 ps
CPU time 1.05 seconds
Started May 09 01:11:01 PM PDT 24
Finished May 09 01:11:03 PM PDT 24
Peak memory 206848 kb
Host smart-10b399a1-09eb-49c9-9299-c9787c707f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633075576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.633075576
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2548761367
Short name T4
Test name
Test status
Simulation time 19281044975 ps
CPU time 16.72 seconds
Started May 09 01:10:59 PM PDT 24
Finished May 09 01:11:17 PM PDT 24
Peak memory 237152 kb
Host smart-222b9596-001b-416a-bc11-0bc9de4cd31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548761367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2548761367
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1912377957
Short name T344
Test name
Test status
Simulation time 12363856 ps
CPU time 0.71 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:12 PM PDT 24
Peak memory 205368 kb
Host smart-4ef526b5-af00-4406-8831-66eb73a91855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912377957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1912377957
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1366897643
Short name T563
Test name
Test status
Simulation time 5244118663 ps
CPU time 14.99 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 234560 kb
Host smart-df186966-67a1-4b53-9f24-8436c805d5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366897643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1366897643
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1298388667
Short name T688
Test name
Test status
Simulation time 82236061 ps
CPU time 0.78 seconds
Started May 09 01:11:06 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 206464 kb
Host smart-04d2d30d-a7be-4051-a78d-bd5674fc0c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298388667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1298388667
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1433294207
Short name T195
Test name
Test status
Simulation time 2407949941 ps
CPU time 11.27 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:24 PM PDT 24
Peak memory 224904 kb
Host smart-97b6799e-60f8-4a9a-9e05-1944ab78ff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433294207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1433294207
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2262541305
Short name T254
Test name
Test status
Simulation time 39871169002 ps
CPU time 205.6 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:14:39 PM PDT 24
Peak memory 250300 kb
Host smart-a75098a8-3f8e-4671-af59-7e9772536692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262541305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2262541305
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.440556261
Short name T855
Test name
Test status
Simulation time 7439984418 ps
CPU time 52.63 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 232872 kb
Host smart-c0553197-7a44-48e2-8979-6bca0ff42019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440556261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.440556261
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1247231917
Short name T407
Test name
Test status
Simulation time 1293708016 ps
CPU time 13.5 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 235280 kb
Host smart-69572645-389d-4112-8649-b590d18e1c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247231917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1247231917
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3769801918
Short name T574
Test name
Test status
Simulation time 619731284 ps
CPU time 15.14 seconds
Started May 09 01:11:09 PM PDT 24
Finished May 09 01:11:25 PM PDT 24
Peak memory 236124 kb
Host smart-1e12d4ff-426b-44ff-a464-939cdfd05626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769801918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3769801918
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1222151650
Short name T533
Test name
Test status
Simulation time 5997918485 ps
CPU time 9.77 seconds
Started May 09 01:11:03 PM PDT 24
Finished May 09 01:11:13 PM PDT 24
Peak memory 234348 kb
Host smart-525c0a65-297f-4374-a3a1-6b6208f966d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222151650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1222151650
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2704718328
Short name T510
Test name
Test status
Simulation time 5449434086 ps
CPU time 21.03 seconds
Started May 09 01:11:02 PM PDT 24
Finished May 09 01:11:25 PM PDT 24
Peak memory 248976 kb
Host smart-9339a3fc-218b-42be-902e-73a9c991c6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704718328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2704718328
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.145632547
Short name T540
Test name
Test status
Simulation time 1759126118 ps
CPU time 20.34 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:32 PM PDT 24
Peak memory 222424 kb
Host smart-cacd652c-f321-4013-89fa-11a65a4d92cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=145632547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.145632547
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.182871131
Short name T238
Test name
Test status
Simulation time 11485135771 ps
CPU time 169.45 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 257592 kb
Host smart-a23b7d00-e6a1-420b-a4e5-9f405499bdac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182871131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.182871131
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1479111609
Short name T527
Test name
Test status
Simulation time 17656425368 ps
CPU time 25.44 seconds
Started May 09 01:11:01 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 216528 kb
Host smart-4d784d50-5903-4a9b-95ff-bc61bc321b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479111609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1479111609
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1986727497
Short name T17
Test name
Test status
Simulation time 4461991910 ps
CPU time 7.41 seconds
Started May 09 01:11:00 PM PDT 24
Finished May 09 01:11:08 PM PDT 24
Peak memory 216528 kb
Host smart-a955ca9f-7f75-4181-ba94-54bc92361508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986727497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1986727497
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.750330126
Short name T770
Test name
Test status
Simulation time 73098810 ps
CPU time 1.4 seconds
Started May 09 01:11:07 PM PDT 24
Finished May 09 01:11:10 PM PDT 24
Peak memory 216420 kb
Host smart-697e4e02-c86c-47d1-9018-41c9cff03c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750330126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.750330126
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1439932393
Short name T743
Test name
Test status
Simulation time 135541001 ps
CPU time 1.04 seconds
Started May 09 01:11:02 PM PDT 24
Finished May 09 01:11:04 PM PDT 24
Peak memory 205840 kb
Host smart-e5f12ae0-732f-42d2-bd1f-c4f3a9a03a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439932393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1439932393
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.802038406
Short name T830
Test name
Test status
Simulation time 8672065038 ps
CPU time 29.66 seconds
Started May 09 01:11:13 PM PDT 24
Finished May 09 01:11:44 PM PDT 24
Peak memory 240020 kb
Host smart-626e59c4-86a0-4a35-9fac-e6bad0194d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802038406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.802038406
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1764123269
Short name T927
Test name
Test status
Simulation time 38836338 ps
CPU time 0.73 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:12 PM PDT 24
Peak memory 205420 kb
Host smart-34586c4e-c6f8-41c9-8831-5e7b27641faf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764123269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1764123269
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3678722905
Short name T481
Test name
Test status
Simulation time 39419047 ps
CPU time 2.2 seconds
Started May 09 01:11:13 PM PDT 24
Finished May 09 01:11:17 PM PDT 24
Peak memory 218960 kb
Host smart-312451af-1ba1-4197-9052-b470bc1970ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678722905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3678722905
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3279097174
Short name T820
Test name
Test status
Simulation time 16317855 ps
CPU time 0.8 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:14 PM PDT 24
Peak memory 205296 kb
Host smart-38231610-1cc6-4c10-a987-7b6bcf02cd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279097174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3279097174
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1366707080
Short name T278
Test name
Test status
Simulation time 7359024866 ps
CPU time 33.04 seconds
Started May 09 01:11:13 PM PDT 24
Finished May 09 01:11:47 PM PDT 24
Peak memory 249232 kb
Host smart-abf63c2a-bce3-44b9-abc1-e03150dea634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366707080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1366707080
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2878403285
Short name T191
Test name
Test status
Simulation time 38170480416 ps
CPU time 125.75 seconds
Started May 09 01:11:09 PM PDT 24
Finished May 09 01:13:16 PM PDT 24
Peak memory 254612 kb
Host smart-59302f73-2d8a-449f-897b-45b38de5ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878403285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2878403285
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3027804510
Short name T779
Test name
Test status
Simulation time 630531423 ps
CPU time 5.53 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:18 PM PDT 24
Peak memory 224580 kb
Host smart-fcc69ac7-8ddf-4bdb-85e5-ae79902c84e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027804510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3027804510
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.500336754
Short name T724
Test name
Test status
Simulation time 7137780973 ps
CPU time 15.61 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 234540 kb
Host smart-7ad36780-b429-42d6-a4c8-bd1e77094f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500336754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.500336754
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3903236986
Short name T763
Test name
Test status
Simulation time 195485932 ps
CPU time 2.55 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:16 PM PDT 24
Peak memory 218636 kb
Host smart-414b047d-c39c-4624-9d89-704faf7c6b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903236986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3903236986
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1882586077
Short name T225
Test name
Test status
Simulation time 542821765 ps
CPU time 4.57 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:15 PM PDT 24
Peak memory 233376 kb
Host smart-9aa15e42-250e-4fde-810e-6553210d5902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882586077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1882586077
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.146356201
Short name T766
Test name
Test status
Simulation time 779529878 ps
CPU time 5.8 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:18 PM PDT 24
Peak memory 233168 kb
Host smart-e83523a9-c802-4fa8-b857-eaf4b621f8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146356201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.146356201
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2472158839
Short name T874
Test name
Test status
Simulation time 1547111731 ps
CPU time 6.92 seconds
Started May 09 01:11:09 PM PDT 24
Finished May 09 01:11:18 PM PDT 24
Peak memory 219296 kb
Host smart-3315eaf8-2f5a-4f42-99dc-98fd4d8680eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2472158839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2472158839
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1925957662
Short name T229
Test name
Test status
Simulation time 8328689853 ps
CPU time 169.74 seconds
Started May 09 01:11:13 PM PDT 24
Finished May 09 01:14:04 PM PDT 24
Peak memory 272360 kb
Host smart-a8829dfe-6109-42e5-82bf-52690b54eb29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925957662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1925957662
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.567445605
Short name T720
Test name
Test status
Simulation time 3297201262 ps
CPU time 10.26 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:23 PM PDT 24
Peak memory 216812 kb
Host smart-6c171276-cf54-4c88-ad6e-7e70fe63e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567445605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.567445605
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2574541606
Short name T346
Test name
Test status
Simulation time 1043657123 ps
CPU time 2.96 seconds
Started May 09 01:11:13 PM PDT 24
Finished May 09 01:11:17 PM PDT 24
Peak memory 216384 kb
Host smart-6bdb8ce7-82ec-448a-9611-a274183860cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574541606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2574541606
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2304899637
Short name T418
Test name
Test status
Simulation time 11966533 ps
CPU time 0.68 seconds
Started May 09 01:11:13 PM PDT 24
Finished May 09 01:11:15 PM PDT 24
Peak memory 205468 kb
Host smart-9fd2edf7-c49e-4cf4-8661-a1edc65bd6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304899637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2304899637
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3420135694
Short name T832
Test name
Test status
Simulation time 73121052 ps
CPU time 0.97 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:11:14 PM PDT 24
Peak memory 206868 kb
Host smart-7d858d5c-e5a9-476a-8d7c-20740d4a45db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420135694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3420135694
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2397429505
Short name T301
Test name
Test status
Simulation time 2545094263 ps
CPU time 9.76 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:22 PM PDT 24
Peak memory 234340 kb
Host smart-e75537a5-2a85-48c7-9452-c8741803d13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397429505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2397429505
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2646120235
Short name T354
Test name
Test status
Simulation time 93209062 ps
CPU time 0.74 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 204744 kb
Host smart-f10d02b2-12be-402a-bfca-fc44b1351944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646120235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2646120235
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.398121208
Short name T586
Test name
Test status
Simulation time 3803625825 ps
CPU time 15.99 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 219768 kb
Host smart-13b66b04-e3cb-4451-b69b-011ecc2c321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398121208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.398121208
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4096576963
Short name T963
Test name
Test status
Simulation time 15872245 ps
CPU time 0.77 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:14 PM PDT 24
Peak memory 205384 kb
Host smart-4c1a4f7e-8692-4643-a23f-0c1fbc9b5cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096576963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4096576963
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.525399555
Short name T46
Test name
Test status
Simulation time 17319593403 ps
CPU time 136.77 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:13:45 PM PDT 24
Peak memory 249308 kb
Host smart-7a64e771-22bf-499f-95dd-b11ad3dd454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525399555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.525399555
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1766687736
Short name T33
Test name
Test status
Simulation time 3711261120 ps
CPU time 93.1 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:12:59 PM PDT 24
Peak memory 250128 kb
Host smart-ada1bdb9-1c40-4bfe-8d8c-eb48c3d9bdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766687736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1766687736
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.484648098
Short name T879
Test name
Test status
Simulation time 216554097 ps
CPU time 10.57 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:37 PM PDT 24
Peak memory 233820 kb
Host smart-10358f34-2f22-4f67-8a40-2ad3a85de266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484648098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.484648098
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1489237915
Short name T393
Test name
Test status
Simulation time 104398474 ps
CPU time 2.25 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:11:16 PM PDT 24
Peak memory 216188 kb
Host smart-67565952-5b3f-4f2b-9f86-43eaf3b2ee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489237915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1489237915
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2188553399
Short name T897
Test name
Test status
Simulation time 6538806993 ps
CPU time 35.88 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:11:50 PM PDT 24
Peak memory 228260 kb
Host smart-e82ac722-480c-4419-81f3-ccd09ab1441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188553399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2188553399
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2910615304
Short name T764
Test name
Test status
Simulation time 11986346030 ps
CPU time 12.77 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:11:26 PM PDT 24
Peak memory 232688 kb
Host smart-708a098d-5f1d-4354-a0bd-c6c8e514913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910615304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2910615304
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1230586647
Short name T693
Test name
Test status
Simulation time 591656485 ps
CPU time 9.19 seconds
Started May 09 01:11:12 PM PDT 24
Finished May 09 01:11:23 PM PDT 24
Peak memory 232736 kb
Host smart-7a92cf92-a319-43ea-94f5-26befafec095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230586647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1230586647
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.624969267
Short name T402
Test name
Test status
Simulation time 235556375 ps
CPU time 3.58 seconds
Started May 09 01:11:21 PM PDT 24
Finished May 09 01:11:26 PM PDT 24
Peak memory 220116 kb
Host smart-2c1774dc-6f99-41cd-86fe-c1798c8cbe11
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=624969267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.624969267
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3263370546
Short name T865
Test name
Test status
Simulation time 98419169987 ps
CPU time 460.17 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:19:08 PM PDT 24
Peak memory 258164 kb
Host smart-9803bd42-3928-49f7-a3e5-0c11b2d2759c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263370546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3263370546
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3955622075
Short name T746
Test name
Test status
Simulation time 7448114571 ps
CPU time 10.61 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:24 PM PDT 24
Peak memory 216588 kb
Host smart-72fa632a-9ce9-4210-b442-82c8f1584d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955622075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3955622075
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3001507691
Short name T678
Test name
Test status
Simulation time 823386015 ps
CPU time 5.16 seconds
Started May 09 01:11:11 PM PDT 24
Finished May 09 01:11:18 PM PDT 24
Peak memory 216448 kb
Host smart-b5706dc0-2f35-4542-a59d-2dd45d0f62ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001507691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3001507691
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.695275445
Short name T949
Test name
Test status
Simulation time 16061206 ps
CPU time 0.78 seconds
Started May 09 01:11:10 PM PDT 24
Finished May 09 01:11:13 PM PDT 24
Peak memory 205780 kb
Host smart-b95051f7-1983-4f3c-afff-d00a93d2e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695275445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.695275445
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1558963584
Short name T894
Test name
Test status
Simulation time 42764204 ps
CPU time 0.74 seconds
Started May 09 01:11:09 PM PDT 24
Finished May 09 01:11:11 PM PDT 24
Peak memory 205784 kb
Host smart-7985c71f-a01d-402b-89fb-7810dbd92643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558963584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1558963584
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.532079915
Short name T391
Test name
Test status
Simulation time 5797216557 ps
CPU time 4.25 seconds
Started May 09 01:11:21 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 233500 kb
Host smart-a77a0764-09e5-4eaa-b1e9-ed83188e1d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532079915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.532079915
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3461341668
Short name T684
Test name
Test status
Simulation time 14122865 ps
CPU time 0.76 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 204792 kb
Host smart-0781bd7c-e700-46e5-9714-0dff0d2a06b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461341668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3461341668
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3158290220
Short name T302
Test name
Test status
Simulation time 1271202346 ps
CPU time 10.08 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:36 PM PDT 24
Peak memory 221036 kb
Host smart-0106ed74-aeec-4158-a4e8-8a9534ef5a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158290220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3158290220
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.881180306
Short name T622
Test name
Test status
Simulation time 15243516 ps
CPU time 0.81 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 205468 kb
Host smart-5dfa5524-032f-499b-bb7a-f4206c758fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881180306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.881180306
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1531540580
Short name T198
Test name
Test status
Simulation time 7544229667 ps
CPU time 31.41 seconds
Started May 09 03:21:38 PM PDT 24
Finished May 09 03:22:11 PM PDT 24
Peak memory 233112 kb
Host smart-20ce826a-f11c-4f15-8b58-5ab3fadceaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531540580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1531540580
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3900809258
Short name T507
Test name
Test status
Simulation time 4910856181 ps
CPU time 66.68 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:12:34 PM PDT 24
Peak memory 239280 kb
Host smart-edbafa44-b466-49ba-b0a3-6628b2a10b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900809258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3900809258
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.468082825
Short name T237
Test name
Test status
Simulation time 25773184314 ps
CPU time 59.63 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:12:27 PM PDT 24
Peak memory 241172 kb
Host smart-be37a395-dc79-4268-b9b3-385bf8ff9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468082825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.468082825
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1389154088
Short name T88
Test name
Test status
Simulation time 7535384947 ps
CPU time 51.38 seconds
Started May 09 02:31:15 PM PDT 24
Finished May 09 02:32:13 PM PDT 24
Peak memory 249596 kb
Host smart-6d6b8349-a5ca-48dc-92db-338b21c883b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389154088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1389154088
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3180823745
Short name T207
Test name
Test status
Simulation time 221771848 ps
CPU time 5.09 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 233624 kb
Host smart-0d435eb6-aa50-45d5-8ed6-7c98907daf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180823745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3180823745
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.355769781
Short name T604
Test name
Test status
Simulation time 9298790991 ps
CPU time 31.3 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:59 PM PDT 24
Peak memory 234472 kb
Host smart-ab6629a0-05da-4614-8ad4-78467fb9f1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355769781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.355769781
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1785696510
Short name T443
Test name
Test status
Simulation time 13515540771 ps
CPU time 11.99 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 227388 kb
Host smart-98d4aa0d-82f9-4109-9721-ca96b794a62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785696510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1785696510
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2828497918
Short name T826
Test name
Test status
Simulation time 4149002888 ps
CPU time 5.07 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:34 PM PDT 24
Peak memory 217548 kb
Host smart-13810dce-f701-4069-aba2-e70e8b677fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828497918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2828497918
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2788541203
Short name T769
Test name
Test status
Simulation time 1466632990 ps
CPU time 5.83 seconds
Started May 09 02:31:37 PM PDT 24
Finished May 09 02:31:48 PM PDT 24
Peak memory 221760 kb
Host smart-4c765f6e-7210-41aa-9a22-1a725bbd48a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788541203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2788541203
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4127891782
Short name T439
Test name
Test status
Simulation time 36522115 ps
CPU time 0.97 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 206676 kb
Host smart-dec740ad-f286-45c2-80aa-52acd299afea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127891782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4127891782
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2228116795
Short name T733
Test name
Test status
Simulation time 6951046630 ps
CPU time 18.36 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:45 PM PDT 24
Peak memory 216552 kb
Host smart-fc28fa5c-ee06-44b1-b43d-61fac7312dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228116795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2228116795
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1436966579
Short name T728
Test name
Test status
Simulation time 2072562778 ps
CPU time 7.11 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:34 PM PDT 24
Peak memory 216392 kb
Host smart-c83be1de-c7bd-4c35-a49f-b299048a2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436966579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1436966579
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3986193098
Short name T626
Test name
Test status
Simulation time 135839925 ps
CPU time 0.99 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 206824 kb
Host smart-56183ce5-6fad-41c5-be6b-81da4a5e7a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986193098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3986193098
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2596789322
Short name T559
Test name
Test status
Simulation time 18063074 ps
CPU time 0.77 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 205836 kb
Host smart-5f7f1537-32af-4c5e-8731-23dbf8f78782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596789322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2596789322
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2493924728
Short name T206
Test name
Test status
Simulation time 696093464 ps
CPU time 8.25 seconds
Started May 09 01:11:22 PM PDT 24
Finished May 09 01:11:32 PM PDT 24
Peak memory 238616 kb
Host smart-f3423b58-9da6-4195-b310-514241b241f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493924728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2493924728
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2581476956
Short name T750
Test name
Test status
Simulation time 33366849 ps
CPU time 0.72 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 205696 kb
Host smart-aeda7179-4509-46f5-a21a-bac98c0fdf3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581476956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2581476956
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3922825735
Short name T625
Test name
Test status
Simulation time 3976742545 ps
CPU time 8.37 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:34 PM PDT 24
Peak memory 220208 kb
Host smart-57facf39-3613-4efa-a001-9ab6370670fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922825735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3922825735
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1189157135
Short name T942
Test name
Test status
Simulation time 22951666 ps
CPU time 0.8 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:28 PM PDT 24
Peak memory 206500 kb
Host smart-7839fcc7-31e3-4be1-aebd-c4c3c8cac158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189157135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1189157135
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3978221970
Short name T822
Test name
Test status
Simulation time 37602098 ps
CPU time 0.77 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 215532 kb
Host smart-20697f2b-b711-4483-8232-14da894b87cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978221970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3978221970
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.112932178
Short name T307
Test name
Test status
Simulation time 2342502912 ps
CPU time 13.99 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 232928 kb
Host smart-75d54773-e714-4d81-9408-072d3b595868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112932178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.112932178
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3308050657
Short name T569
Test name
Test status
Simulation time 2266121604 ps
CPU time 16.27 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:42 PM PDT 24
Peak memory 233972 kb
Host smart-2c6890c6-9131-4ace-8b00-be7235420a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308050657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3308050657
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2799400051
Short name T857
Test name
Test status
Simulation time 429841674 ps
CPU time 5.56 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:32 PM PDT 24
Peak memory 220012 kb
Host smart-eeed1a96-a48e-4416-b23d-6fce1325d4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799400051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2799400051
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.825006760
Short name T900
Test name
Test status
Simulation time 652585752 ps
CPU time 5.22 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 235756 kb
Host smart-991181de-c5e6-452b-8497-ffbd017c9e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825006760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.825006760
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1239458477
Short name T974
Test name
Test status
Simulation time 58866594614 ps
CPU time 31.35 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:11:59 PM PDT 24
Peak memory 222992 kb
Host smart-296d7b1e-7aad-4f3d-a5b2-38ca494e3b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239458477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1239458477
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3142924325
Short name T851
Test name
Test status
Simulation time 291302041 ps
CPU time 5.94 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:31 PM PDT 24
Peak memory 220572 kb
Host smart-aabef378-ce8c-46eb-b239-016c47380830
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3142924325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3142924325
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2413199596
Short name T15
Test name
Test status
Simulation time 6401856057 ps
CPU time 33.47 seconds
Started May 09 01:11:22 PM PDT 24
Finished May 09 01:11:57 PM PDT 24
Peak memory 216472 kb
Host smart-233e0350-3f37-467b-963e-aae59c6beac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413199596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2413199596
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4143245871
Short name T922
Test name
Test status
Simulation time 768750178 ps
CPU time 2.94 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 216396 kb
Host smart-8c32ad38-b89a-4ca1-95d2-c47ecfb43f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143245871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4143245871
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.664460495
Short name T911
Test name
Test status
Simulation time 307950409 ps
CPU time 2.43 seconds
Started May 09 01:11:22 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 216332 kb
Host smart-ec6db5a9-b29c-4f3b-a0d7-06ef8dd313b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664460495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.664460495
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1106707696
Short name T539
Test name
Test status
Simulation time 54387943 ps
CPU time 0.86 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 206756 kb
Host smart-04248ad7-59a3-44ff-a8c7-f37645866fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106707696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1106707696
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2319136135
Short name T792
Test name
Test status
Simulation time 4215456130 ps
CPU time 5.26 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:11:33 PM PDT 24
Peak memory 217552 kb
Host smart-ab7c9684-569c-4ddb-ac33-bf2aa7b6ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319136135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2319136135
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.390405977
Short name T342
Test name
Test status
Simulation time 42689815 ps
CPU time 0.72 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 205436 kb
Host smart-12776b09-8c53-4d5c-a44e-9de2aec14418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390405977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.390405977
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.138760863
Short name T205
Test name
Test status
Simulation time 98481692 ps
CPU time 3.6 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:39 PM PDT 24
Peak memory 218408 kb
Host smart-664052e6-76b7-4df2-b675-9fbb03851f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138760863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.138760863
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2689898138
Short name T535
Test name
Test status
Simulation time 39226008 ps
CPU time 0.8 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:30 PM PDT 24
Peak memory 206484 kb
Host smart-01989358-ff02-4846-8903-d492e7a24a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689898138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2689898138
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2702649752
Short name T515
Test name
Test status
Simulation time 2035052340 ps
CPU time 40.62 seconds
Started May 09 01:11:33 PM PDT 24
Finished May 09 01:12:15 PM PDT 24
Peak memory 252676 kb
Host smart-84a71559-0c0f-4d11-8b33-2002c4f5d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702649752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2702649752
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2428745499
Short name T34
Test name
Test status
Simulation time 14217816165 ps
CPU time 57.62 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:12:34 PM PDT 24
Peak memory 238960 kb
Host smart-a360572b-dc92-47a1-9b36-26712e46a35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428745499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2428745499
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.524161466
Short name T221
Test name
Test status
Simulation time 20237286018 ps
CPU time 146.57 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:14:03 PM PDT 24
Peak memory 249796 kb
Host smart-c4b0eab2-6b5a-4b0f-a1dd-8bb1f9e1a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524161466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.524161466
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3197000784
Short name T649
Test name
Test status
Simulation time 375797943 ps
CPU time 3.59 seconds
Started May 09 01:11:54 PM PDT 24
Finished May 09 01:11:59 PM PDT 24
Peak memory 232780 kb
Host smart-2ed74a8b-e63b-440e-bc53-2af8f25b754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197000784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3197000784
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2999897280
Short name T801
Test name
Test status
Simulation time 3390875444 ps
CPU time 9.5 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:36 PM PDT 24
Peak memory 219544 kb
Host smart-d88c57b5-ab38-4755-b91f-bff6abb66af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999897280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2999897280
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1021253667
Short name T864
Test name
Test status
Simulation time 75403316928 ps
CPU time 56.86 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:12:24 PM PDT 24
Peak memory 236108 kb
Host smart-1eac899f-d963-44d2-980c-d7b20a7c0402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021253667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1021253667
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.865918800
Short name T273
Test name
Test status
Simulation time 3515054342 ps
CPU time 7 seconds
Started May 09 01:11:25 PM PDT 24
Finished May 09 01:11:35 PM PDT 24
Peak memory 224640 kb
Host smart-49e741e6-f8bc-423e-8850-e6410b9743cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865918800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.865918800
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2634262214
Short name T939
Test name
Test status
Simulation time 34767495 ps
CPU time 2.18 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 218476 kb
Host smart-c5ebf989-8eb8-47fd-8fed-b0f1df6d6e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634262214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2634262214
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3510707200
Short name T809
Test name
Test status
Simulation time 158876919 ps
CPU time 5.14 seconds
Started May 09 01:11:33 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 222944 kb
Host smart-53e956e6-13f0-4521-a4cd-c79605b4eba5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3510707200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3510707200
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.977320014
Short name T159
Test name
Test status
Simulation time 933428506 ps
CPU time 18.31 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 232860 kb
Host smart-6c10eb9b-e3e7-4720-8719-ed8500f84531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977320014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.977320014
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3891837491
Short name T789
Test name
Test status
Simulation time 950986719 ps
CPU time 2.3 seconds
Started May 09 01:11:26 PM PDT 24
Finished May 09 01:11:31 PM PDT 24
Peak memory 216348 kb
Host smart-f9390669-0c56-447b-a068-adce5781caf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891837491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3891837491
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.829557535
Short name T585
Test name
Test status
Simulation time 16133071 ps
CPU time 0.75 seconds
Started May 09 01:11:23 PM PDT 24
Finished May 09 01:11:27 PM PDT 24
Peak memory 205564 kb
Host smart-8f61b3cc-ec8c-40bc-ae47-fff968e60af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829557535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.829557535
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3500250319
Short name T938
Test name
Test status
Simulation time 162469055 ps
CPU time 6.77 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:34 PM PDT 24
Peak memory 216336 kb
Host smart-6d2871db-b623-41c1-b40b-a6c985f31ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500250319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3500250319
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1338442268
Short name T445
Test name
Test status
Simulation time 100915318 ps
CPU time 0.88 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 206068 kb
Host smart-9df3ed6c-43fc-4641-bd62-fd76f027cb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338442268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1338442268
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2213410805
Short name T196
Test name
Test status
Simulation time 81496568 ps
CPU time 2.83 seconds
Started May 09 01:11:24 PM PDT 24
Finished May 09 01:11:29 PM PDT 24
Peak memory 233448 kb
Host smart-8db3e01d-6e12-4e7c-8f20-300563684403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213410805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2213410805
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.826363972
Short name T572
Test name
Test status
Simulation time 14348673 ps
CPU time 0.72 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:39 PM PDT 24
Peak memory 205388 kb
Host smart-d99cb70a-8f40-4287-a0f7-43e4160f112f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826363972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.826363972
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.4212536749
Short name T334
Test name
Test status
Simulation time 1982221329 ps
CPU time 11.89 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:48 PM PDT 24
Peak memory 233932 kb
Host smart-76616b84-28c9-401b-9d54-e45e9557d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212536749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4212536749
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2417296660
Short name T528
Test name
Test status
Simulation time 41940144 ps
CPU time 0.79 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 206444 kb
Host smart-e9827195-bf0f-4fbc-a3b8-3f9b92049a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417296660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2417296660
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2571224492
Short name T40
Test name
Test status
Simulation time 20403444194 ps
CPU time 149.17 seconds
Started May 09 01:11:41 PM PDT 24
Finished May 09 01:14:11 PM PDT 24
Peak memory 249320 kb
Host smart-dc41d797-2fb9-456b-8088-8884871fb716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571224492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2571224492
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1652683285
Short name T847
Test name
Test status
Simulation time 11747032754 ps
CPU time 23.81 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:12:00 PM PDT 24
Peak memory 224828 kb
Host smart-f28f6f9e-c44f-4de0-9838-243906c26fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652683285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1652683285
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1338713415
Short name T972
Test name
Test status
Simulation time 5289302791 ps
CPU time 19.51 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:58 PM PDT 24
Peak memory 237116 kb
Host smart-16079014-d8be-4356-8663-27e73143e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338713415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1338713415
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2268528992
Short name T834
Test name
Test status
Simulation time 983639472 ps
CPU time 7.9 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:45 PM PDT 24
Peak memory 233084 kb
Host smart-f36754c2-0224-46ca-a0ac-ab684da23737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268528992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2268528992
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2888849170
Short name T638
Test name
Test status
Simulation time 23163231233 ps
CPU time 45.91 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:12:21 PM PDT 24
Peak memory 218732 kb
Host smart-e08c1188-0859-466e-a0e8-f3d6fbfe1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888849170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2888849170
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.241374271
Short name T186
Test name
Test status
Simulation time 1843153312 ps
CPU time 8.07 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:44 PM PDT 24
Peak memory 216684 kb
Host smart-8784d16f-68f4-423c-8992-a08d91203b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241374271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.241374271
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1436844708
Short name T367
Test name
Test status
Simulation time 713962316 ps
CPU time 2.15 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:38 PM PDT 24
Peak memory 218812 kb
Host smart-f98836dd-cd73-4b64-aa05-b32fb9601b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436844708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1436844708
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2901467518
Short name T149
Test name
Test status
Simulation time 615868496 ps
CPU time 4.81 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:44 PM PDT 24
Peak memory 219132 kb
Host smart-409996e1-fd21-44d9-9168-9d26c30b9981
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2901467518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2901467518
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1600384854
Short name T295
Test name
Test status
Simulation time 8936444098 ps
CPU time 152.16 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:14:10 PM PDT 24
Peak memory 273600 kb
Host smart-6f08e097-a2bd-4a10-94aa-843ea448628b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600384854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1600384854
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.596960236
Short name T315
Test name
Test status
Simulation time 1169706371 ps
CPU time 18.01 seconds
Started May 09 01:11:39 PM PDT 24
Finished May 09 01:11:59 PM PDT 24
Peak memory 218108 kb
Host smart-057be0bd-18ae-42bc-9917-5dcbeaf4b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596960236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.596960236
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2024628935
Short name T451
Test name
Test status
Simulation time 1315940213 ps
CPU time 5.43 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:42 PM PDT 24
Peak memory 216372 kb
Host smart-d8d2517f-0890-4e5a-aa8d-0ccf4f048fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024628935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2024628935
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2698692803
Short name T835
Test name
Test status
Simulation time 540622738 ps
CPU time 1.42 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 216316 kb
Host smart-ca4f3315-84ad-42a7-885f-3b1653938392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698692803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2698692803
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2466890593
Short name T401
Test name
Test status
Simulation time 23784924 ps
CPU time 0.7 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 205480 kb
Host smart-b048f2b7-103c-4038-b6b7-a94b49e14c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466890593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2466890593
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1912784780
Short name T950
Test name
Test status
Simulation time 10036712891 ps
CPU time 29.83 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:12:09 PM PDT 24
Peak memory 236504 kb
Host smart-32cad7c5-ef21-4d7a-a17c-2697c25707b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912784780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1912784780
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3553315698
Short name T628
Test name
Test status
Simulation time 35308632 ps
CPU time 0.75 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:38 PM PDT 24
Peak memory 204692 kb
Host smart-8ae76495-a3bf-457c-a585-7b43269d860c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553315698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3553315698
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3601139925
Short name T673
Test name
Test status
Simulation time 7616871620 ps
CPU time 15.38 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:54 PM PDT 24
Peak memory 234312 kb
Host smart-92025aac-d38d-40d6-b678-e57151244fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601139925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3601139925
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1381750769
Short name T612
Test name
Test status
Simulation time 54099296 ps
CPU time 0.73 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 205400 kb
Host smart-3d2d00c8-45ca-441e-a14c-ac9240c1760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381750769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1381750769
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.651194458
Short name T737
Test name
Test status
Simulation time 59928130875 ps
CPU time 217.06 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:15:12 PM PDT 24
Peak memory 249272 kb
Host smart-59ab290a-df9b-48ef-b94d-1bffa3029691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651194458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.651194458
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3128305911
Short name T267
Test name
Test status
Simulation time 3766580404 ps
CPU time 83.81 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:12:59 PM PDT 24
Peak memory 249480 kb
Host smart-182d035e-cfbe-4b0a-9fb2-b566bc28f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128305911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3128305911
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1878442103
Short name T233
Test name
Test status
Simulation time 25470600180 ps
CPU time 97.42 seconds
Started May 09 01:11:41 PM PDT 24
Finished May 09 01:13:19 PM PDT 24
Peak memory 255536 kb
Host smart-f0564de7-a16a-4418-8f44-1041ccf4f458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878442103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1878442103
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3023046935
Short name T310
Test name
Test status
Simulation time 2324668159 ps
CPU time 11.94 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 232892 kb
Host smart-ac43ab21-9e1c-45d8-a2f2-d01b38bbf2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023046935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3023046935
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3512683128
Short name T551
Test name
Test status
Simulation time 188200618 ps
CPU time 2.96 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 233740 kb
Host smart-19fedb65-6559-4095-9961-ef6dc9cf59b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512683128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3512683128
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2036602272
Short name T333
Test name
Test status
Simulation time 31979889 ps
CPU time 2.46 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:39 PM PDT 24
Peak memory 221548 kb
Host smart-2f63d6a0-36ce-455a-9378-f3c6d71224e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036602272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2036602272
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.878073812
Short name T355
Test name
Test status
Simulation time 110511022 ps
CPU time 1.9 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 216140 kb
Host smart-d853a7db-6f28-46d1-afbd-5a15be87d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878073812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.878073812
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.722742420
Short name T210
Test name
Test status
Simulation time 68037723642 ps
CPU time 27.07 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:12:04 PM PDT 24
Peak memory 218668 kb
Host smart-d0819b48-d17e-4672-981d-141122bda7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722742420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.722742420
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3649849418
Short name T620
Test name
Test status
Simulation time 337700042 ps
CPU time 6.44 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 220336 kb
Host smart-54dd3e32-3ff8-4c2a-b6fb-fcd132eda622
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3649849418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3649849418
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1384141161
Short name T978
Test name
Test status
Simulation time 136749372266 ps
CPU time 271.77 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:16:09 PM PDT 24
Peak memory 264072 kb
Host smart-27e68554-28b1-4752-9586-53cdb0a6ab41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384141161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1384141161
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3745676955
Short name T935
Test name
Test status
Simulation time 4098700707 ps
CPU time 16.04 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:55 PM PDT 24
Peak memory 216616 kb
Host smart-58463fd9-a18e-4168-96bf-966dd7ccffb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745676955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3745676955
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1887243733
Short name T428
Test name
Test status
Simulation time 272193900 ps
CPU time 2.41 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:37 PM PDT 24
Peak memory 216292 kb
Host smart-8af879d4-ebb5-4c27-8dd9-38ede831bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887243733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1887243733
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2497145457
Short name T909
Test name
Test status
Simulation time 149910363 ps
CPU time 4.78 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 216500 kb
Host smart-ce2b6673-bbd4-4250-ad94-a101a33427c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497145457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2497145457
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1570729917
Short name T488
Test name
Test status
Simulation time 51524433 ps
CPU time 0.95 seconds
Started May 09 01:11:34 PM PDT 24
Finished May 09 01:11:36 PM PDT 24
Peak memory 205736 kb
Host smart-5cc27674-f9c4-4895-a88e-8ebd8dc02a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570729917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1570729917
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2682475696
Short name T190
Test name
Test status
Simulation time 1234516426 ps
CPU time 4.83 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:44 PM PDT 24
Peak memory 234312 kb
Host smart-b81ba2e7-aaf0-4575-95db-4dd2a190c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682475696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2682475696
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2141110609
Short name T973
Test name
Test status
Simulation time 20924809 ps
CPU time 0.74 seconds
Started May 09 01:11:39 PM PDT 24
Finished May 09 01:11:42 PM PDT 24
Peak memory 205636 kb
Host smart-7b9717f3-aecf-4c0a-a050-0c8229a7a3b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141110609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2141110609
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1140651154
Short name T521
Test name
Test status
Simulation time 402313263 ps
CPU time 4.01 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:43 PM PDT 24
Peak memory 233900 kb
Host smart-f2d38382-9a47-4162-9aea-da62567d195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140651154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1140651154
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3148648215
Short name T384
Test name
Test status
Simulation time 43646526 ps
CPU time 0.73 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 205760 kb
Host smart-de41257e-7e73-43c8-ab35-914bd30f2738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148648215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3148648215
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3025567983
Short name T771
Test name
Test status
Simulation time 193060910969 ps
CPU time 319.94 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:16:59 PM PDT 24
Peak memory 257508 kb
Host smart-f3b2a57e-87b8-4681-b0db-d23697544cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025567983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3025567983
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2050796885
Short name T306
Test name
Test status
Simulation time 844297969 ps
CPU time 14.84 seconds
Started May 09 01:11:41 PM PDT 24
Finished May 09 01:11:57 PM PDT 24
Peak memory 236220 kb
Host smart-297d24c4-446c-452a-882b-c91ce6deef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050796885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2050796885
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3693995973
Short name T806
Test name
Test status
Simulation time 225847994 ps
CPU time 4.35 seconds
Started May 09 01:11:40 PM PDT 24
Finished May 09 01:11:45 PM PDT 24
Peak memory 219552 kb
Host smart-7054aaad-fb23-4177-8490-e8752d6db6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693995973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3693995973
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3081649272
Short name T657
Test name
Test status
Simulation time 291023708 ps
CPU time 8.9 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:47 PM PDT 24
Peak memory 235004 kb
Host smart-c5dfa007-2500-4ad3-be65-817cc007a4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081649272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3081649272
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.753452514
Short name T756
Test name
Test status
Simulation time 2714003321 ps
CPU time 4 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:42 PM PDT 24
Peak memory 233924 kb
Host smart-45c010c5-5d1c-4a95-8241-99aa2e7c5285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753452514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.753452514
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2072826553
Short name T270
Test name
Test status
Simulation time 423030845 ps
CPU time 3.28 seconds
Started May 09 01:11:36 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 235552 kb
Host smart-7a98925e-b421-479a-89c3-33856cb1620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072826553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2072826553
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1005304316
Short name T548
Test name
Test status
Simulation time 11059327115 ps
CPU time 10.53 seconds
Started May 09 01:11:40 PM PDT 24
Finished May 09 01:11:52 PM PDT 24
Peak memory 219548 kb
Host smart-bddb7786-1010-44be-b70d-53edaf431c74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1005304316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1005304316
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1566862479
Short name T134
Test name
Test status
Simulation time 248220345 ps
CPU time 1.11 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:40 PM PDT 24
Peak memory 207028 kb
Host smart-58799eef-6f6b-4378-baf9-3109d8572132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566862479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1566862479
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.63457602
Short name T652
Test name
Test status
Simulation time 7510855436 ps
CPU time 10.3 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:50 PM PDT 24
Peak memory 216580 kb
Host smart-58bd995b-96ed-48c2-99c7-dda41c698780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63457602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.63457602
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.410918463
Short name T329
Test name
Test status
Simulation time 7336712677 ps
CPU time 6.97 seconds
Started May 09 01:11:37 PM PDT 24
Finished May 09 01:11:45 PM PDT 24
Peak memory 216496 kb
Host smart-69612012-89a4-40a2-a625-4aab631f4d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410918463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.410918463
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3271546795
Short name T858
Test name
Test status
Simulation time 35321016 ps
CPU time 1.89 seconds
Started May 09 01:11:38 PM PDT 24
Finished May 09 01:11:41 PM PDT 24
Peak memory 216404 kb
Host smart-7b6c993b-19d6-4f09-8f6a-d4a637b552bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271546795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3271546795
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1118606956
Short name T53
Test name
Test status
Simulation time 62327505 ps
CPU time 0.76 seconds
Started May 09 01:11:35 PM PDT 24
Finished May 09 01:11:37 PM PDT 24
Peak memory 205768 kb
Host smart-7d34a3f3-47bc-4bc5-906b-ab9d8621e000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118606956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1118606956
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4147180149
Short name T6
Test name
Test status
Simulation time 12238592349 ps
CPU time 36.12 seconds
Started May 09 01:11:41 PM PDT 24
Finished May 09 01:12:18 PM PDT 24
Peak memory 235860 kb
Host smart-38e33d82-b4c4-4f2c-a755-c3682d1eb3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147180149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4147180149
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1887900782
Short name T934
Test name
Test status
Simulation time 46982242 ps
CPU time 0.71 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 204760 kb
Host smart-5bdee4ce-7a20-4f62-b1f9-fda43ab999f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887900782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
887900782
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2505434263
Short name T209
Test name
Test status
Simulation time 4366272956 ps
CPU time 20.43 seconds
Started May 09 01:08:32 PM PDT 24
Finished May 09 01:08:55 PM PDT 24
Peak memory 218816 kb
Host smart-d62b7418-c282-4503-9b7d-bddb6ca41c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505434263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2505434263
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1229954645
Short name T75
Test name
Test status
Simulation time 43906555 ps
CPU time 0.73 seconds
Started May 09 01:08:32 PM PDT 24
Finished May 09 01:08:35 PM PDT 24
Peak memory 205432 kb
Host smart-a694032a-7086-48ee-94f4-ca3e5640f7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229954645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1229954645
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2272589620
Short name T220
Test name
Test status
Simulation time 11494196565 ps
CPU time 64.18 seconds
Started May 09 01:08:32 PM PDT 24
Finished May 09 01:09:39 PM PDT 24
Peak memory 249232 kb
Host smart-b302f96f-ce8b-4b4f-8b06-64c1d5eedef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272589620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2272589620
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3097025918
Short name T222
Test name
Test status
Simulation time 2862817570 ps
CPU time 37.8 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:09:18 PM PDT 24
Peak memory 233200 kb
Host smart-070f4151-17f5-4067-aba0-986aeb1a04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097025918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3097025918
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2812894346
Short name T827
Test name
Test status
Simulation time 11574811206 ps
CPU time 109.41 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:10:28 PM PDT 24
Peak memory 233396 kb
Host smart-444686b1-085b-44b3-8e3c-a83229831037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812894346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2812894346
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3536206123
Short name T762
Test name
Test status
Simulation time 310353188 ps
CPU time 4.43 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 218340 kb
Host smart-cda35284-1589-4ac8-8b68-ae0fefd003b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536206123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3536206123
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2126067243
Short name T35
Test name
Test status
Simulation time 3195000888 ps
CPU time 44.43 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:09:24 PM PDT 24
Peak memory 228488 kb
Host smart-cfd5aaf1-1988-4a4d-98bb-2cb4784fb48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126067243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2126067243
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3092559000
Short name T24
Test name
Test status
Simulation time 56896174 ps
CPU time 1.02 seconds
Started May 09 01:08:32 PM PDT 24
Finished May 09 01:08:35 PM PDT 24
Peak memory 216732 kb
Host smart-91db701e-77f5-4db3-a8b1-a44423c84d23
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092559000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3092559000
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3244428308
Short name T888
Test name
Test status
Simulation time 328442468 ps
CPU time 3.9 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:42 PM PDT 24
Peak memory 218880 kb
Host smart-dbeab602-42f9-4a19-bf82-3a9d04325eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244428308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3244428308
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1233016678
Short name T516
Test name
Test status
Simulation time 1187928566 ps
CPU time 7.44 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:43 PM PDT 24
Peak memory 234212 kb
Host smart-b64363e9-a6cf-4494-aea7-ebb143bc5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233016678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1233016678
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3405680984
Short name T449
Test name
Test status
Simulation time 198375523 ps
CPU time 4.23 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:42 PM PDT 24
Peak memory 218876 kb
Host smart-6c61c0b1-862b-46df-92c2-174a3d29ed7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3405680984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3405680984
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1404836949
Short name T425
Test name
Test status
Simulation time 410842185 ps
CPU time 6.95 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:44 PM PDT 24
Peak memory 216748 kb
Host smart-6358136b-758a-4a40-8ce0-135481337f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404836949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1404836949
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3029926879
Short name T824
Test name
Test status
Simulation time 1415034353 ps
CPU time 3.67 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:42 PM PDT 24
Peak memory 216292 kb
Host smart-5c3f71d0-4a0d-40e8-88fb-5dcdc846aafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029926879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3029926879
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3096487909
Short name T356
Test name
Test status
Simulation time 112330113 ps
CPU time 1.12 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:40 PM PDT 24
Peak memory 207336 kb
Host smart-626ca473-fcc2-4a42-902c-2758f3ac4c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096487909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3096487909
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2734724443
Short name T388
Test name
Test status
Simulation time 23379917 ps
CPU time 0.8 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 205864 kb
Host smart-104ea67d-3896-4128-8db9-efce071c2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734724443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2734724443
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1988353491
Short name T642
Test name
Test status
Simulation time 1599216407 ps
CPU time 2.87 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:38 PM PDT 24
Peak memory 234816 kb
Host smart-dcbe940d-ee36-4f8b-b507-26d22f4a9744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988353491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1988353491
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2981277063
Short name T453
Test name
Test status
Simulation time 20867080 ps
CPU time 0.72 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:39 PM PDT 24
Peak memory 205308 kb
Host smart-dcc650f4-0eab-493a-8399-a6d7a186f3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981277063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
981277063
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2088516367
Short name T804
Test name
Test status
Simulation time 542140928 ps
CPU time 8.62 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:45 PM PDT 24
Peak memory 234480 kb
Host smart-208a8d64-e7a5-487a-b19a-a4e6417e8475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088516367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2088516367
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2875242929
Short name T480
Test name
Test status
Simulation time 60264700 ps
CPU time 0.77 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:36 PM PDT 24
Peak memory 205784 kb
Host smart-3ced75e3-a013-4a19-87ac-25bf4fea3def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875242929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2875242929
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2456167084
Short name T36
Test name
Test status
Simulation time 1632985924 ps
CPU time 10.05 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 233784 kb
Host smart-50b36234-af53-4d66-844b-ee2ff0f2c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456167084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2456167084
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3248100226
Short name T22
Test name
Test status
Simulation time 37193417525 ps
CPU time 144.71 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:11:00 PM PDT 24
Peak memory 257572 kb
Host smart-056f480b-c387-43b6-ba4a-7a57e5167d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248100226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3248100226
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1459988000
Short name T890
Test name
Test status
Simulation time 8351702220 ps
CPU time 87.45 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:10:07 PM PDT 24
Peak memory 249320 kb
Host smart-8c27bc43-49eb-4d76-b8f5-9516fd82f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459988000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1459988000
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2323252515
Short name T975
Test name
Test status
Simulation time 343161562 ps
CPU time 9.77 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 237232 kb
Host smart-caad382c-8125-442f-8b9b-3069f9addf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323252515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2323252515
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4097062838
Short name T390
Test name
Test status
Simulation time 6594469695 ps
CPU time 6.59 seconds
Started May 09 01:08:38 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 217832 kb
Host smart-30464ff4-c8a0-4dc1-bc35-9e20b61ce9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097062838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4097062838
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1644188209
Short name T644
Test name
Test status
Simulation time 25334078188 ps
CPU time 69.52 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:09:46 PM PDT 24
Peak memory 230732 kb
Host smart-aa6f4cae-8c15-4b12-9686-5f9ea0cb0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644188209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1644188209
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.306646069
Short name T561
Test name
Test status
Simulation time 88819067 ps
CPU time 1.02 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:38 PM PDT 24
Peak memory 216780 kb
Host smart-b52e29bc-2625-4868-9dc2-6f6d47dbb6f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306646069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.306646069
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1037286276
Short name T819
Test name
Test status
Simulation time 193995439 ps
CPU time 3.16 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 216776 kb
Host smart-16575106-27eb-4989-9d43-6336d243db17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037286276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1037286276
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1103330354
Short name T965
Test name
Test status
Simulation time 505618098 ps
CPU time 4.27 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 235684 kb
Host smart-2e003bd7-e55b-4e57-92a4-0303819d1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103330354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1103330354
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2498061474
Short name T680
Test name
Test status
Simulation time 397712415 ps
CPU time 4.12 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 222744 kb
Host smart-b2f64495-0b90-45a8-a975-0ab626812634
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2498061474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2498061474
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3546448111
Short name T742
Test name
Test status
Simulation time 48743058816 ps
CPU time 172.12 seconds
Started May 09 01:08:39 PM PDT 24
Finished May 09 01:11:33 PM PDT 24
Peak memory 249380 kb
Host smart-6e4bda6e-3c59-45e4-8d0b-b3b748701647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546448111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3546448111
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.179917216
Short name T582
Test name
Test status
Simulation time 3177039882 ps
CPU time 14.03 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:53 PM PDT 24
Peak memory 216516 kb
Host smart-1b7dbe67-482f-4251-96c4-2835de1c6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179917216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.179917216
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2930236046
Short name T910
Test name
Test status
Simulation time 34215051 ps
CPU time 0.73 seconds
Started May 09 01:08:35 PM PDT 24
Finished May 09 01:08:38 PM PDT 24
Peak memory 205544 kb
Host smart-98c72214-1936-42ff-9c11-88209f072438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930236046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2930236046
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3783592939
Short name T508
Test name
Test status
Simulation time 84444647 ps
CPU time 1.35 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:37 PM PDT 24
Peak memory 216352 kb
Host smart-b92b4b94-83db-43d7-93d0-1cf2aaeaf148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783592939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3783592939
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.801431645
Short name T651
Test name
Test status
Simulation time 29620482 ps
CPU time 0.7 seconds
Started May 09 01:08:34 PM PDT 24
Finished May 09 01:08:37 PM PDT 24
Peak memory 205856 kb
Host smart-b76ad9b7-deb9-4bc8-88d2-350767c1313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801431645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.801431645
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.569302121
Short name T133
Test name
Test status
Simulation time 1639808774 ps
CPU time 5.56 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:08:46 PM PDT 24
Peak memory 223976 kb
Host smart-96161f0d-05ac-490c-9491-08f2531727ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569302121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.569302121
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2023466674
Short name T611
Test name
Test status
Simulation time 72857779 ps
CPU time 0.71 seconds
Started May 09 01:08:44 PM PDT 24
Finished May 09 01:08:45 PM PDT 24
Peak memory 205356 kb
Host smart-e041f959-455f-477a-868d-3a2e4c2f5cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023466674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
023466674
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3702633099
Short name T91
Test name
Test status
Simulation time 1106171862 ps
CPU time 4.29 seconds
Started May 09 01:08:39 PM PDT 24
Finished May 09 01:08:45 PM PDT 24
Peak memory 218572 kb
Host smart-e7aa5707-d1ef-483d-9d63-cf57eb4d31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702633099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3702633099
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1258418590
Short name T341
Test name
Test status
Simulation time 19748867 ps
CPU time 0.8 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:40 PM PDT 24
Peak memory 206464 kb
Host smart-9bc17c99-ab01-486b-92e9-2701224cd3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258418590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1258418590
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1894642503
Short name T243
Test name
Test status
Simulation time 14803471764 ps
CPU time 76.6 seconds
Started May 09 01:08:38 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 254424 kb
Host smart-492c01b5-12c6-47de-93a0-c00c8f67a514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894642503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1894642503
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3856638178
Short name T623
Test name
Test status
Simulation time 38006661974 ps
CPU time 83.82 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:09:58 PM PDT 24
Peak memory 253256 kb
Host smart-92fd7a00-e06d-4f93-962f-b234171cf248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856638178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3856638178
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1155410118
Short name T150
Test name
Test status
Simulation time 462356409 ps
CPU time 4.52 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:08:45 PM PDT 24
Peak memory 224564 kb
Host smart-3fbcf018-fb5a-4725-b746-87a5e3208449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155410118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1155410118
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4290969705
Short name T928
Test name
Test status
Simulation time 646933760 ps
CPU time 7.99 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 219084 kb
Host smart-4288c95b-f079-4c93-9747-a97ea32eccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290969705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4290969705
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.677047418
Short name T645
Test name
Test status
Simulation time 10501334801 ps
CPU time 52.68 seconds
Started May 09 01:08:41 PM PDT 24
Finished May 09 01:09:35 PM PDT 24
Peak memory 218676 kb
Host smart-492eb26d-a088-4e74-9fa2-a3d94f70ad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677047418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.677047418
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.698256095
Short name T430
Test name
Test status
Simulation time 26305175 ps
CPU time 1.06 seconds
Started May 09 01:08:41 PM PDT 24
Finished May 09 01:08:43 PM PDT 24
Peak memory 218020 kb
Host smart-ea80714a-71f2-41df-8d25-c05d1c203fc5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698256095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.698256095
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2693328765
Short name T421
Test name
Test status
Simulation time 2062325587 ps
CPU time 7.79 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 233600 kb
Host smart-743fc4e0-3196-4897-a40f-2f66dd55dbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693328765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2693328765
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1139439313
Short name T846
Test name
Test status
Simulation time 7786897934 ps
CPU time 14.11 seconds
Started May 09 01:08:33 PM PDT 24
Finished May 09 01:08:50 PM PDT 24
Peak memory 227840 kb
Host smart-bcd10be8-f743-4531-a370-7af85d04051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139439313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1139439313
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.346814723
Short name T970
Test name
Test status
Simulation time 1319949815 ps
CPU time 5.32 seconds
Started May 09 01:08:38 PM PDT 24
Finished May 09 01:08:46 PM PDT 24
Peak memory 218724 kb
Host smart-615f16e1-88f3-4642-b04e-ea44dc56016d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=346814723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.346814723
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.545287708
Short name T326
Test name
Test status
Simulation time 15020773800 ps
CPU time 29.07 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:09:08 PM PDT 24
Peak memory 216520 kb
Host smart-40ed33a9-cb84-4105-95d1-07dba6171edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545287708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.545287708
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.851294953
Short name T887
Test name
Test status
Simulation time 716190114 ps
CPU time 3.51 seconds
Started May 09 01:08:41 PM PDT 24
Finished May 09 01:08:46 PM PDT 24
Peak memory 216348 kb
Host smart-6de63ab2-7b89-4473-b3df-c632a27e6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851294953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.851294953
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2999224966
Short name T323
Test name
Test status
Simulation time 37591014 ps
CPU time 1.23 seconds
Started May 09 01:08:36 PM PDT 24
Finished May 09 01:08:40 PM PDT 24
Peak memory 207932 kb
Host smart-40a8f520-ca0a-4a55-8f48-55b58b5ce889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999224966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2999224966
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2360066960
Short name T917
Test name
Test status
Simulation time 101302996 ps
CPU time 0.86 seconds
Started May 09 01:08:37 PM PDT 24
Finished May 09 01:08:41 PM PDT 24
Peak memory 205908 kb
Host smart-303760d2-3d37-420e-b16c-f36fa161d5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360066960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2360066960
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2727234411
Short name T216
Test name
Test status
Simulation time 7033257678 ps
CPU time 9.16 seconds
Started May 09 01:08:41 PM PDT 24
Finished May 09 01:08:51 PM PDT 24
Peak memory 234400 kb
Host smart-068350b9-f7ac-42c5-b8b0-c07e2deffa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727234411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2727234411
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1333665518
Short name T588
Test name
Test status
Simulation time 11125943 ps
CPU time 0.74 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 205288 kb
Host smart-5735c2b4-d517-4dec-bace-3f4d01f36b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333665518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
333665518
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1062234181
Short name T705
Test name
Test status
Simulation time 480733878 ps
CPU time 2.57 seconds
Started May 09 01:08:55 PM PDT 24
Finished May 09 01:08:59 PM PDT 24
Peak memory 233980 kb
Host smart-525f6b29-6e41-44b6-b782-bc452781cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062234181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1062234181
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2422104786
Short name T731
Test name
Test status
Simulation time 71338292 ps
CPU time 0.77 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:08:52 PM PDT 24
Peak memory 206472 kb
Host smart-48f24e1c-8a92-4445-a8a8-7367fffb1e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422104786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2422104786
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3316851311
Short name T802
Test name
Test status
Simulation time 12148696331 ps
CPU time 126.65 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:11:02 PM PDT 24
Peak memory 257016 kb
Host smart-4c5e96f4-b6d8-4286-99c0-5156d022984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316851311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3316851311
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2850562327
Short name T234
Test name
Test status
Simulation time 32206259236 ps
CPU time 59.61 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:09:48 PM PDT 24
Peak memory 249428 kb
Host smart-ff77754e-2e1c-4571-8b97-24d1723d00c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850562327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2850562327
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.275794947
Short name T424
Test name
Test status
Simulation time 97931045071 ps
CPU time 38.56 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:09:28 PM PDT 24
Peak memory 219452 kb
Host smart-a1b82c99-e5d2-4b20-b316-9490b8069676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275794947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
275794947
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.757563447
Short name T901
Test name
Test status
Simulation time 52196646 ps
CPU time 2.98 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:08:53 PM PDT 24
Peak memory 232616 kb
Host smart-159b0e7c-b317-4de7-a632-50d2c63b8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757563447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.757563447
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.674482870
Short name T558
Test name
Test status
Simulation time 1887999102 ps
CPU time 6.71 seconds
Started May 09 01:08:53 PM PDT 24
Finished May 09 01:09:01 PM PDT 24
Peak memory 224576 kb
Host smart-eb34c360-b753-4bc9-9f5b-508b6ac18bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674482870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.674482870
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2907094263
Short name T276
Test name
Test status
Simulation time 26930860418 ps
CPU time 25.57 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:09:13 PM PDT 24
Peak memory 233460 kb
Host smart-87c9153d-839a-4ded-97a0-e17b5b06a8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907094263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2907094263
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.63161584
Short name T526
Test name
Test status
Simulation time 14105119 ps
CPU time 1.03 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:50 PM PDT 24
Peak memory 216796 kb
Host smart-572f004f-7f87-4f5f-be09-b1f76af274c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63161584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.63161584
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.142919304
Short name T536
Test name
Test status
Simulation time 8497107777 ps
CPU time 8.44 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:55 PM PDT 24
Peak memory 233892 kb
Host smart-bd99236b-889a-41b8-a4b0-17ddf4f93f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142919304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
142919304
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2271064877
Short name T377
Test name
Test status
Simulation time 3452507971 ps
CPU time 14.34 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:09:04 PM PDT 24
Peak memory 247168 kb
Host smart-4afc8f90-0457-4720-9b98-2673cd0f38be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271064877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2271064877
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4294628202
Short name T648
Test name
Test status
Simulation time 121772752 ps
CPU time 3.49 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:52 PM PDT 24
Peak memory 219204 kb
Host smart-07dfaf29-b4f8-46be-a415-b74484ba0fed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4294628202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4294628202
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2416255001
Short name T940
Test name
Test status
Simulation time 69129386689 ps
CPU time 72.93 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:10:02 PM PDT 24
Peak memory 236836 kb
Host smart-ba258264-4f13-44c4-aaf3-07bb8cd4a0c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416255001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2416255001
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2078111698
Short name T312
Test name
Test status
Simulation time 5778840050 ps
CPU time 24.91 seconds
Started May 09 01:08:53 PM PDT 24
Finished May 09 01:09:19 PM PDT 24
Peak memory 220372 kb
Host smart-aa72d05e-f215-491a-8cd3-4f644859eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078111698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2078111698
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2187518054
Short name T365
Test name
Test status
Simulation time 15540783 ps
CPU time 0.72 seconds
Started May 09 01:08:44 PM PDT 24
Finished May 09 01:08:46 PM PDT 24
Peak memory 205516 kb
Host smart-28aa29bb-4cc2-465c-a18d-b24e4d273c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187518054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2187518054
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3006661463
Short name T634
Test name
Test status
Simulation time 19085899 ps
CPU time 0.99 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:08:52 PM PDT 24
Peak memory 207720 kb
Host smart-44dd8b5a-6ca7-4638-8db8-edda6b539f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006661463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3006661463
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1130389255
Short name T795
Test name
Test status
Simulation time 82736930 ps
CPU time 0.79 seconds
Started May 09 01:08:44 PM PDT 24
Finished May 09 01:08:46 PM PDT 24
Peak memory 205852 kb
Host smart-6e0da61f-530d-43f6-baf9-fe05e6776cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130389255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1130389255
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3193682691
Short name T773
Test name
Test status
Simulation time 1404567734 ps
CPU time 11.38 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:58 PM PDT 24
Peak memory 249064 kb
Host smart-85726fc1-7dc9-4595-b0e5-6d6a6b948688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193682691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3193682691
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1207678602
Short name T556
Test name
Test status
Simulation time 32352782 ps
CPU time 0.73 seconds
Started May 09 01:08:50 PM PDT 24
Finished May 09 01:08:52 PM PDT 24
Peak memory 205272 kb
Host smart-c750f6a6-9743-4520-89a0-36c17d637988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207678602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
207678602
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.4086661937
Short name T412
Test name
Test status
Simulation time 1362729762 ps
CPU time 7.22 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:03 PM PDT 24
Peak memory 218548 kb
Host smart-a6406c97-d3a1-4ad9-a8d6-8049ff4f45b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086661937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.4086661937
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3714751661
Short name T579
Test name
Test status
Simulation time 27813530 ps
CPU time 0.85 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:47 PM PDT 24
Peak memory 205484 kb
Host smart-54a8a6f0-24ed-42c8-9c3a-e319865fe995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714751661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3714751661
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3021646919
Short name T184
Test name
Test status
Simulation time 72816353538 ps
CPU time 35.64 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:09:25 PM PDT 24
Peak memory 224724 kb
Host smart-1cc6be83-5e93-4cd5-9577-0a9c2d61f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021646919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3021646919
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2171539998
Short name T670
Test name
Test status
Simulation time 5625719350 ps
CPU time 35.14 seconds
Started May 09 01:08:55 PM PDT 24
Finished May 09 01:09:31 PM PDT 24
Peak memory 217628 kb
Host smart-5579eb48-8230-4e42-b4fc-09e447527d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171539998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2171539998
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.772162493
Short name T739
Test name
Test status
Simulation time 11528355522 ps
CPU time 131.33 seconds
Started May 09 01:08:49 PM PDT 24
Finished May 09 01:11:02 PM PDT 24
Peak memory 250424 kb
Host smart-90734063-2d62-4e4f-aa83-ac8b9da0253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772162493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
772162493
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2346772626
Short name T338
Test name
Test status
Simulation time 199373692 ps
CPU time 3.98 seconds
Started May 09 01:08:48 PM PDT 24
Finished May 09 01:08:54 PM PDT 24
Peak memory 224600 kb
Host smart-cf355506-fd50-4c08-a152-a4b198b1000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346772626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2346772626
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3639824548
Short name T882
Test name
Test status
Simulation time 158296244 ps
CPU time 4.14 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:53 PM PDT 24
Peak memory 234516 kb
Host smart-1bb349d6-181b-41ca-bf2c-8682707a0f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639824548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3639824548
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4144428681
Short name T291
Test name
Test status
Simulation time 5951243833 ps
CPU time 19.6 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:15 PM PDT 24
Peak memory 243708 kb
Host smart-640825ef-1f27-44f5-b4f5-3d8652f9cf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144428681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4144428681
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.948420843
Short name T26
Test name
Test status
Simulation time 90034212 ps
CPU time 1.04 seconds
Started May 09 01:08:50 PM PDT 24
Finished May 09 01:08:53 PM PDT 24
Peak memory 216660 kb
Host smart-b2ed6625-58c5-4c13-9648-ad5d1aa3e40c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948420843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.948420843
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3521575885
Short name T405
Test name
Test status
Simulation time 1865103385 ps
CPU time 7.43 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:55 PM PDT 24
Peak memory 216848 kb
Host smart-232f4a63-a6e6-4ec8-be06-8cfcf8125f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521575885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3521575885
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2929763545
Short name T828
Test name
Test status
Simulation time 2646426113 ps
CPU time 7.37 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:55 PM PDT 24
Peak memory 218668 kb
Host smart-f9100258-c787-4a0b-8744-35c1560fe941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929763545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2929763545
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2832671422
Short name T710
Test name
Test status
Simulation time 9101513788 ps
CPU time 10.46 seconds
Started May 09 01:08:54 PM PDT 24
Finished May 09 01:09:06 PM PDT 24
Peak memory 223224 kb
Host smart-91826fba-3a0b-4505-a840-e44e478303d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832671422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2832671422
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3865459615
Short name T503
Test name
Test status
Simulation time 44063283 ps
CPU time 0.95 seconds
Started May 09 01:08:53 PM PDT 24
Finished May 09 01:08:55 PM PDT 24
Peak memory 206828 kb
Host smart-8cf96425-bf68-4913-980e-6548e9a9286a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865459615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3865459615
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2544949459
Short name T964
Test name
Test status
Simulation time 593910160 ps
CPU time 6.81 seconds
Started May 09 01:08:50 PM PDT 24
Finished May 09 01:08:58 PM PDT 24
Peak memory 216360 kb
Host smart-5ff5701a-9411-4403-b3e6-59d1f9e4da5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544949459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2544949459
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.830098007
Short name T542
Test name
Test status
Simulation time 23443251626 ps
CPU time 9.89 seconds
Started May 09 01:08:45 PM PDT 24
Finished May 09 01:08:57 PM PDT 24
Peak memory 216388 kb
Host smart-78ab81fb-477b-44a4-bb50-2b09e43964a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830098007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.830098007
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3915585254
Short name T867
Test name
Test status
Simulation time 79969216 ps
CPU time 0.86 seconds
Started May 09 01:08:47 PM PDT 24
Finished May 09 01:08:50 PM PDT 24
Peak memory 206892 kb
Host smart-c4f380ac-f45a-499f-8194-5e792658360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915585254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3915585254
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.704974954
Short name T891
Test name
Test status
Simulation time 18348051 ps
CPU time 0.76 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:08:49 PM PDT 24
Peak memory 205516 kb
Host smart-9ea19f17-7d57-42ac-95b5-a8e7fc104aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704974954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.704974954
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.941417922
Short name T744
Test name
Test status
Simulation time 931166636 ps
CPU time 5.69 seconds
Started May 09 01:08:46 PM PDT 24
Finished May 09 01:08:54 PM PDT 24
Peak memory 217940 kb
Host smart-bbbafd50-4d5e-4943-8618-228f85d82ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941417922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.941417922
Directory /workspace/9.spi_device_upload/latest
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