Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3844838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4025478

1

T1

889

T2

38

T3

16209

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4537204	1			T1	4		T2	1		T3	14073
values[0x0]	1666112	1			T1	460		T2	22		T3	7991
values[0x1]	1667000	1			T1	430		T2	24		T3	7866

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2722329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5147987

1

T1

891

T2

39

T3

20474

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28774	1			T3	87		T6	5		T7	23
valid_sources[0x01]	28769	1			T3	91		T4	1		T6	1
valid_sources[0x02]	27460	1			T3	132		T4	1		T6	4
valid_sources[0x03]	33106	1			T3	122		T4	2		T6	4
valid_sources[0x04]	29437	1			T3	178		T4	2		T6	6
valid_sources[0x05]	28359	1			T3	98		T4	1		T6	5
valid_sources[0x06]	34852	1			T3	83		T6	5		T7	16
valid_sources[0x07]	29541	1			T3	154		T6	5		T7	16
valid_sources[0x08]	28158	1			T3	100		T6	3		T7	18
valid_sources[0x09]	30828	1			T3	103		T4	1		T6	3
valid_sources[0x0a]	33628	1			T3	120		T4	2		T6	5
valid_sources[0x0b]	30769	1			T3	86		T4	1		T6	1
valid_sources[0x0c]	27570	1			T2	1		T3	97		T4	1
valid_sources[0x0d]	31519	1			T3	164		T4	2		T6	1
valid_sources[0x0e]	29136	1			T3	94		T4	1		T6	2
valid_sources[0x0f]	32005	1			T3	166		T6	8		T7	12
valid_sources[0x10]	27678	1			T3	115		T6	1		T7	13
valid_sources[0x11]	28278	1			T3	107		T6	2		T7	33
valid_sources[0x12]	30262	1			T3	158		T6	1		T7	14
valid_sources[0x13]	29130	1			T3	146		T4	1		T6	4
valid_sources[0x14]	26726	1			T3	108		T4	2		T6	5
valid_sources[0x15]	29486	1			T3	138		T4	1		T6	3
valid_sources[0x16]	47744	1			T3	122		T6	3		T7	19
valid_sources[0x17]	30493	1			T3	178		T4	1		T6	3
valid_sources[0x18]	29119	1			T3	114		T4	2		T6	1
valid_sources[0x19]	36596	1			T3	122		T6	3		T7	20
valid_sources[0x1a]	30858	1			T3	117		T4	4		T6	4
valid_sources[0x1b]	31676	1			T3	126		T4	3		T6	2
valid_sources[0x1c]	28389	1			T3	132		T4	2		T6	2
valid_sources[0x1d]	30884	1			T3	111		T4	1		T6	2
valid_sources[0x1e]	28458	1			T3	149		T6	4		T7	38
valid_sources[0x1f]	29490	1			T3	106		T6	3		T7	23
valid_sources[0x20]	30620	1			T2	2		T3	126		T4	2
valid_sources[0x21]	28783	1			T3	101		T6	4		T7	15
valid_sources[0x22]	29038	1			T3	143		T6	2		T7	7
valid_sources[0x23]	47322	1			T3	77		T6	8		T7	17
valid_sources[0x24]	29340	1			T3	129		T4	1		T6	3
valid_sources[0x25]	28940	1			T3	121		T4	2		T6	4
valid_sources[0x26]	30053	1			T3	122		T4	1		T6	2
valid_sources[0x27]	29798	1			T3	140		T6	3		T7	26
valid_sources[0x28]	46118	1			T3	108		T4	2		T6	4
valid_sources[0x29]	29317	1			T3	103		T4	1		T6	1
valid_sources[0x2a]	26773	1			T3	95		T4	1		T6	2
valid_sources[0x2b]	28897	1			T3	107		T4	1		T6	2
valid_sources[0x2c]	28634	1			T3	132		T4	1		T6	1
valid_sources[0x2d]	32010	1			T3	154		T4	1		T6	2
valid_sources[0x2e]	31760	1			T3	78		T7	22		T8	3
valid_sources[0x2f]	31372	1			T3	99		T6	2		T7	8
valid_sources[0x30]	31083	1			T3	94		T6	5		T7	19
valid_sources[0x31]	42087	1			T3	125		T4	2		T6	3
valid_sources[0x32]	29639	1			T3	118		T4	1		T6	3
valid_sources[0x33]	28530	1			T3	122		T4	2		T6	2
valid_sources[0x34]	27892	1			T3	116		T4	1		T6	5
valid_sources[0x35]	29305	1			T3	101		T4	1		T6	5
valid_sources[0x36]	28233	1			T3	93		T6	2		T7	8
valid_sources[0x37]	29851	1			T3	115		T4	1		T6	2
valid_sources[0x38]	27966	1			T3	123		T6	2		T7	24
valid_sources[0x39]	28447	1			T3	107		T6	2		T7	21
valid_sources[0x3a]	28324	1			T3	158		T4	3		T6	1
valid_sources[0x3b]	30711	1			T3	125		T6	2		T7	12
valid_sources[0x3c]	30233	1			T3	147		T6	4		T7	24
valid_sources[0x3d]	30594	1			T3	87		T4	2		T6	5
valid_sources[0x3e]	31813	1			T2	1		T3	160		T4	1
valid_sources[0x3f]	30079	1			T3	93		T4	1		T6	3
valid_sources[0x40]	46119	1			T3	147		T4	2		T6	1
valid_sources[0x41]	31771	1			T3	113		T6	6		T7	25
valid_sources[0x42]	27981	1			T3	126		T6	4		T7	32
valid_sources[0x43]	28284	1			T3	150		T4	1		T6	9
valid_sources[0x44]	30849	1			T3	132		T6	7		T7	24
valid_sources[0x45]	29492	1			T3	107		T4	3		T6	4
valid_sources[0x46]	28480	1			T3	144		T4	2		T6	3
valid_sources[0x47]	31712	1			T3	107		T6	3		T7	20
valid_sources[0x48]	29234	1			T3	125		T7	20		T8	2
valid_sources[0x49]	28303	1			T3	105		T4	1		T6	2
valid_sources[0x4a]	30224	1			T3	115		T6	1		T7	16
valid_sources[0x4b]	31576	1			T3	124		T6	4		T7	24
valid_sources[0x4c]	27781	1			T3	142		T6	3		T7	20
valid_sources[0x4d]	28939	1			T2	8		T3	102		T4	1
valid_sources[0x4e]	27911	1			T3	122		T6	3		T7	13
valid_sources[0x4f]	29728	1			T3	124		T6	4		T7	21
valid_sources[0x50]	29577	1			T3	163		T4	1		T6	4
valid_sources[0x51]	30750	1			T3	72		T6	4		T7	17
valid_sources[0x52]	55404	1			T3	82		T6	3		T7	18
valid_sources[0x53]	29686	1			T3	151		T6	3		T7	18
valid_sources[0x54]	29528	1			T3	103		T6	3		T7	19
valid_sources[0x55]	31623	1			T3	118		T6	4		T7	24
valid_sources[0x56]	30982	1			T3	80		T4	1		T7	20
valid_sources[0x57]	28547	1			T2	1		T3	92		T6	4
valid_sources[0x58]	27545	1			T3	143		T4	1		T6	2
valid_sources[0x59]	30318	1			T3	112		T4	1		T6	2
valid_sources[0x5a]	32352	1			T3	70		T4	2		T6	5
valid_sources[0x5b]	36650	1			T3	141		T4	1		T6	3
valid_sources[0x5c]	27861	1			T3	124		T4	1		T6	2
valid_sources[0x5d]	28098	1			T3	115		T6	7		T7	23
valid_sources[0x5e]	28995	1			T3	109		T4	3		T6	3
valid_sources[0x5f]	28566	1			T3	98		T4	1		T6	2
valid_sources[0x60]	29383	1			T3	80		T6	1		T7	27
valid_sources[0x61]	28041	1			T3	136		T4	1		T6	2
valid_sources[0x62]	38741	1			T3	145		T6	5		T7	25
valid_sources[0x63]	27644	1			T3	96		T4	1		T6	4
valid_sources[0x64]	28907	1			T2	2		T3	100		T4	2
valid_sources[0x65]	27506	1			T3	119		T4	1		T6	3
valid_sources[0x66]	31603	1			T3	162		T6	4		T7	8
valid_sources[0x67]	28287	1			T3	145		T4	2		T6	1
valid_sources[0x68]	28639	1			T3	67		T6	4		T7	21
valid_sources[0x69]	28431	1			T3	116		T6	7		T7	11
valid_sources[0x6a]	28866	1			T3	95		T6	4		T7	17
valid_sources[0x6b]	28726	1			T3	160		T4	1		T6	5
valid_sources[0x6c]	30612	1			T2	2		T3	128		T6	3
valid_sources[0x6d]	31336	1			T3	128		T4	1		T6	2
valid_sources[0x6e]	28420	1			T3	89		T4	3		T6	2
valid_sources[0x6f]	29288	1			T3	153		T4	1		T6	2
valid_sources[0x70]	31086	1			T3	138		T4	1		T6	3
valid_sources[0x71]	29951	1			T3	128		T6	4		T7	12
valid_sources[0x72]	29700	1			T3	88		T4	2		T6	3
valid_sources[0x73]	30843	1			T3	133		T6	6		T7	16
valid_sources[0x74]	31942	1			T3	97		T4	2		T6	5
valid_sources[0x75]	32505	1			T3	110		T4	1		T6	3
valid_sources[0x76]	34317	1			T3	128		T4	2		T6	7
valid_sources[0x77]	28320	1			T3	127		T4	1		T6	2
valid_sources[0x78]	29201	1			T3	115		T4	1		T6	2
valid_sources[0x79]	27817	1			T3	128		T4	3		T6	5
valid_sources[0x7a]	30106	1			T3	92		T4	1		T6	4
valid_sources[0x7b]	30631	1			T3	102		T6	3		T7	18
valid_sources[0x7c]	30376	1			T3	130		T4	1		T7	19
valid_sources[0x7d]	30234	1			T3	115		T6	5		T7	16
valid_sources[0x7e]	31397	1			T3	124		T4	1		T6	6
valid_sources[0x7f]	31512	1			T3	133		T6	3		T7	17
valid_sources[0x80]	27508	1			T3	98		T4	1		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1046165

1

T1

2

T2

1

T3

1879

values[0x0]

all_enables

biggest_size

1501546

1

T1

459

T2

16

T3

7277

values[0x1]

all_enables

biggest_size

1477767

1

T1

428

T2

21

T3

7053