Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3863970

1

T1

5

T2

9

T3

13721

full_word

4024463

1

T1

889

T2

38

T3

16209

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7888073	1			T1	894		T2	47		T3	29930
auto[TlIntgErrCmd]	119	1			T108	8		T111	3		T112	9
auto[TlIntgErrData]	118	1			T108	12		T111	1		T112	2
auto[TlIntgErrBoth]	123	1			T108	10		T111	6		T112	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4538755

1

T1

4

T2

1

T3

14073

auto[1]

3349678

1

T1

890

T2

46

T3

15857

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3492372	1			T1	2		T3	12194		T6	1
auto[TlIntgErrNone]	partial	auto[1]	371285	1			T1	3		T2	9		T3	1527
auto[TlIntgErrNone]	full_word	auto[0]	1046217	1			T1	2		T2	1		T3	1879
auto[TlIntgErrNone]	full_word	auto[1]	2978199	1			T1	887		T2	37		T3	14330
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T108	5		T112	3		T269	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T108	2		T111	2		T112	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T108	1		T111	1		T158	2
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T112	1		T269	2		T158	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T108	9		T112	1		T269	3
auto[TlIntgErrData]	partial	auto[1]	53	1			T108	3		T111	1		T112	1
auto[TlIntgErrData]	full_word	auto[0]	9	1			T155	1		T270	1		T156	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T158	1		T272	1		T273	3
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T108	4		T111	2		T112	4
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T108	3		T111	4		T112	4
auto[TlIntgErrBoth]	full_word	auto[0]	10	1			T108	2		T112	1		T155	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T108	1		T269	1		T270	1