Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Total | Covered | Percent |
Conditions | 22 | 16 | 72.73 |
Logical | 22 | 16 | 72.73 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T6 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T6 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T6 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T6 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
17943265 |
0 |
0 |
T1 |
39891 |
27544 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
15271 |
0 |
0 |
T6 |
25461 |
19606 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
2450 |
0 |
0 |
T13 |
44896 |
980 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T23 |
0 |
9346 |
0 |
0 |
T24 |
0 |
4770 |
0 |
0 |
T38 |
0 |
79678 |
0 |
0 |
T39 |
0 |
17068 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
17943265 |
0 |
0 |
T1 |
39891 |
27544 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
15271 |
0 |
0 |
T6 |
25461 |
19606 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
36 |
0 |
0 |
T12 |
0 |
2450 |
0 |
0 |
T13 |
44896 |
980 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T23 |
0 |
9346 |
0 |
0 |
T24 |
0 |
4770 |
0 |
0 |
T38 |
0 |
79678 |
0 |
0 |
T39 |
0 |
17068 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Total | Covered | Percent |
Conditions | 22 | 18 | 81.82 |
Logical | 22 | 18 | 81.82 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T6 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T6 |
1 | 0 | 1 | Covered | T1,T3,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T6 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T6 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T6 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
18842658 |
0 |
0 |
T1 |
39891 |
29496 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
15948 |
0 |
0 |
T6 |
25461 |
20908 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T12 |
0 |
2570 |
0 |
0 |
T13 |
44896 |
1040 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T23 |
0 |
10216 |
0 |
0 |
T24 |
0 |
5120 |
0 |
0 |
T38 |
0 |
82936 |
0 |
0 |
T39 |
0 |
19332 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
18842658 |
0 |
0 |
T1 |
39891 |
29496 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
15948 |
0 |
0 |
T6 |
25461 |
20908 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
32 |
0 |
0 |
T12 |
0 |
2570 |
0 |
0 |
T13 |
44896 |
1040 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T23 |
0 |
10216 |
0 |
0 |
T24 |
0 |
5120 |
0 |
0 |
T38 |
0 |
82936 |
0 |
0 |
T39 |
0 |
19332 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 12 | 85.71 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 1 | 50.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
0 |
1 |
|
|
|
MISSING_ELSE |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T6 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T6 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T6 |
0 |
0 |
Covered |
T1,T3,T6 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
98582655 |
0 |
0 |
T1 |
39891 |
39634 |
0 |
0 |
T2 |
7706 |
0 |
0 |
0 |
T3 |
457306 |
396253 |
0 |
0 |
T6 |
25461 |
25240 |
0 |
0 |
T7 |
204112 |
0 |
0 |
0 |
T8 |
82271 |
81680 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
0 |
57902 |
0 |
0 |
T12 |
0 |
89738 |
0 |
0 |
T13 |
44896 |
44896 |
0 |
0 |
T14 |
0 |
43904 |
0 |
0 |
T15 |
0 |
6310 |
0 |
0 |
T16 |
0 |
30184 |
0 |
0 |
T17 |
68770 |
0 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Total | Covered | Percent |
Conditions | 22 | 17 | 77.27 |
Logical | 22 | 17 | 77.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T7,T17 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T7 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T7,T17 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T7 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T7,T17 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T7,T17 |
1 | 0 | 1 | Covered | T3,T7,T17 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T7,T17 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T7,T17 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T7,T17 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T7,T17 |
1 | 0 | Covered | T3,T7,T17 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T17 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T17 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
6105016 |
0 |
0 |
T3 |
457306 |
20093 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
33229 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T14 |
44736 |
0 |
0 |
0 |
T17 |
68770 |
29620 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T29 |
0 |
3953 |
0 |
0 |
T30 |
0 |
5373 |
0 |
0 |
T31 |
0 |
603 |
0 |
0 |
T32 |
0 |
60591 |
0 |
0 |
T35 |
0 |
26527 |
0 |
0 |
T47 |
0 |
14805 |
0 |
0 |
T49 |
0 |
48229 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
29119923 |
0 |
0 |
T2 |
7706 |
7392 |
0 |
0 |
T3 |
457306 |
55896 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
200528 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
88520 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T17 |
68770 |
65824 |
0 |
0 |
T20 |
106610 |
102176 |
0 |
0 |
T22 |
0 |
60776 |
0 |
0 |
T29 |
0 |
14632 |
0 |
0 |
T30 |
0 |
24400 |
0 |
0 |
T31 |
0 |
1656 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
29119923 |
0 |
0 |
T2 |
7706 |
7392 |
0 |
0 |
T3 |
457306 |
55896 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
200528 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
88520 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T17 |
68770 |
65824 |
0 |
0 |
T20 |
106610 |
102176 |
0 |
0 |
T22 |
0 |
60776 |
0 |
0 |
T29 |
0 |
14632 |
0 |
0 |
T30 |
0 |
24400 |
0 |
0 |
T31 |
0 |
1656 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
29119923 |
0 |
0 |
T2 |
7706 |
7392 |
0 |
0 |
T3 |
457306 |
55896 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
200528 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
88520 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T17 |
68770 |
65824 |
0 |
0 |
T20 |
106610 |
102176 |
0 |
0 |
T22 |
0 |
60776 |
0 |
0 |
T29 |
0 |
14632 |
0 |
0 |
T30 |
0 |
24400 |
0 |
0 |
T31 |
0 |
1656 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
6105016 |
0 |
0 |
T3 |
457306 |
20093 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
33229 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T14 |
44736 |
0 |
0 |
0 |
T17 |
68770 |
29620 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T29 |
0 |
3953 |
0 |
0 |
T30 |
0 |
5373 |
0 |
0 |
T31 |
0 |
603 |
0 |
0 |
T32 |
0 |
60591 |
0 |
0 |
T35 |
0 |
26527 |
0 |
0 |
T47 |
0 |
14805 |
0 |
0 |
T49 |
0 |
48229 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 9 | 56.25 |
Logical | 16 | 9 | 56.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T2,T3,T7 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T3,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T7,T17 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T7 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T7,T17 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T7,T17 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T7,T17 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T7,T17 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T2,T3,T7 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T7,T17 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
196317 |
0 |
0 |
T3 |
457306 |
639 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
1072 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T14 |
44736 |
0 |
0 |
0 |
T17 |
68770 |
957 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T29 |
0 |
125 |
0 |
0 |
T30 |
0 |
173 |
0 |
0 |
T31 |
0 |
19 |
0 |
0 |
T32 |
0 |
1953 |
0 |
0 |
T35 |
0 |
852 |
0 |
0 |
T47 |
0 |
475 |
0 |
0 |
T49 |
0 |
1552 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
29119923 |
0 |
0 |
T2 |
7706 |
7392 |
0 |
0 |
T3 |
457306 |
55896 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
200528 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
88520 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T17 |
68770 |
65824 |
0 |
0 |
T20 |
106610 |
102176 |
0 |
0 |
T22 |
0 |
60776 |
0 |
0 |
T29 |
0 |
14632 |
0 |
0 |
T30 |
0 |
24400 |
0 |
0 |
T31 |
0 |
1656 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
29119923 |
0 |
0 |
T2 |
7706 |
7392 |
0 |
0 |
T3 |
457306 |
55896 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
200528 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
88520 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T17 |
68770 |
65824 |
0 |
0 |
T20 |
106610 |
102176 |
0 |
0 |
T22 |
0 |
60776 |
0 |
0 |
T29 |
0 |
14632 |
0 |
0 |
T30 |
0 |
24400 |
0 |
0 |
T31 |
0 |
1656 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
29119923 |
0 |
0 |
T2 |
7706 |
7392 |
0 |
0 |
T3 |
457306 |
55896 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
200528 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
88520 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T17 |
68770 |
65824 |
0 |
0 |
T20 |
106610 |
102176 |
0 |
0 |
T22 |
0 |
60776 |
0 |
0 |
T29 |
0 |
14632 |
0 |
0 |
T30 |
0 |
24400 |
0 |
0 |
T31 |
0 |
1656 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
128991517 |
196317 |
0 |
0 |
T3 |
457306 |
639 |
0 |
0 |
T6 |
25461 |
0 |
0 |
0 |
T7 |
204112 |
1072 |
0 |
0 |
T8 |
82271 |
0 |
0 |
0 |
T10 |
92266 |
0 |
0 |
0 |
T11 |
58291 |
0 |
0 |
0 |
T13 |
44896 |
0 |
0 |
0 |
T14 |
44736 |
0 |
0 |
0 |
T17 |
68770 |
957 |
0 |
0 |
T20 |
106610 |
0 |
0 |
0 |
T29 |
0 |
125 |
0 |
0 |
T30 |
0 |
173 |
0 |
0 |
T31 |
0 |
19 |
0 |
0 |
T32 |
0 |
1953 |
0 |
0 |
T35 |
0 |
852 |
0 |
0 |
T47 |
0 |
475 |
0 |
0 |
T49 |
0 |
1552 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T4 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T4 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T3,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T4 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
2633154 |
0 |
0 |
T1 |
281162 |
832 |
0 |
0 |
T2 |
11981 |
0 |
0 |
0 |
T3 |
139763 |
8320 |
0 |
0 |
T4 |
3407 |
443 |
0 |
0 |
T5 |
948 |
0 |
0 |
0 |
T6 |
15883 |
832 |
0 |
0 |
T7 |
121950 |
0 |
0 |
0 |
T8 |
26656 |
832 |
0 |
0 |
T9 |
1606 |
100 |
0 |
0 |
T10 |
222579 |
0 |
0 |
0 |
T11 |
0 |
832 |
0 |
0 |
T13 |
0 |
832 |
0 |
0 |
T14 |
0 |
832 |
0 |
0 |
T28 |
0 |
100 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
2633154 |
0 |
0 |
T1 |
281162 |
832 |
0 |
0 |
T2 |
11981 |
0 |
0 |
0 |
T3 |
139763 |
8320 |
0 |
0 |
T4 |
3407 |
443 |
0 |
0 |
T5 |
948 |
0 |
0 |
0 |
T6 |
15883 |
832 |
0 |
0 |
T7 |
121950 |
0 |
0 |
0 |
T8 |
26656 |
832 |
0 |
0 |
T9 |
1606 |
100 |
0 |
0 |
T10 |
222579 |
0 |
0 |
0 |
T11 |
0 |
832 |
0 |
0 |
T13 |
0 |
832 |
0 |
0 |
T14 |
0 |
832 |
0 |
0 |
T28 |
0 |
100 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 12 | 80.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 13 | 86.67 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 8 | 33.33 |
Logical | 24 | 8 | 33.33 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
6 |
66.67 |
TERNARY |
130 |
2 |
1 |
50.00 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T4,T17 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T7 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T7 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T7 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T7 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
378539 |
0 |
0 |
T3 |
139763 |
765 |
0 |
0 |
T4 |
3407 |
483 |
0 |
0 |
T5 |
948 |
0 |
0 |
0 |
T6 |
15883 |
0 |
0 |
0 |
T7 |
121950 |
601 |
0 |
0 |
T8 |
26656 |
0 |
0 |
0 |
T9 |
1606 |
100 |
0 |
0 |
T10 |
222579 |
0 |
0 |
0 |
T13 |
228469 |
0 |
0 |
0 |
T17 |
558862 |
2362 |
0 |
0 |
T24 |
0 |
10 |
0 |
0 |
T28 |
0 |
100 |
0 |
0 |
T29 |
0 |
289 |
0 |
0 |
T30 |
0 |
109 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
429645282 |
0 |
0 |
T1 |
281162 |
281101 |
0 |
0 |
T2 |
11981 |
11890 |
0 |
0 |
T3 |
139763 |
139754 |
0 |
0 |
T4 |
3407 |
3309 |
0 |
0 |
T5 |
948 |
866 |
0 |
0 |
T6 |
15883 |
15829 |
0 |
0 |
T7 |
121950 |
121876 |
0 |
0 |
T8 |
26656 |
26561 |
0 |
0 |
T9 |
1606 |
1521 |
0 |
0 |
T10 |
222579 |
222512 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
429730063 |
378539 |
0 |
0 |
T3 |
139763 |
765 |
0 |
0 |
T4 |
3407 |
483 |
0 |
0 |
T5 |
948 |
0 |
0 |
0 |
T6 |
15883 |
0 |
0 |
0 |
T7 |
121950 |
601 |
0 |
0 |
T8 |
26656 |
0 |
0 |
0 |
T9 |
1606 |
100 |
0 |
0 |
T10 |
222579 |
0 |
0 |
0 |
T13 |
228469 |
0 |
0 |
0 |
T17 |
558862 |
2362 |
0 |
0 |
T24 |
0 |
10 |
0 |
0 |
T28 |
0 |
100 |
0 |
0 |
T29 |
0 |
289 |
0 |
0 |
T30 |
0 |
109 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |