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Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.18 100.00 72.73 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.63 95.00 76.19 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.77 98.25 100.00 100.00 90.62 100.00 u_readsram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 100.00 81.82 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.62 100.00 90.48 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.77 98.25 100.00 100.00 90.62 100.00 u_readsram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.10 85.71 31.25 71.43 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.07 84.62 36.11 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 100.00 33.33 u_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 56.48 84.00 40.00 45.45


Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 77.27 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 95.00 78.57 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.66 99.29 91.20 91.67 96.13 100.00 u_spi_tpm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.06 100.00 56.25 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 100.00 75.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 100.00 83.33 u_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91


Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.33 95.00 75.00 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.01 94.37 60.00 73.08 84.62 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.67 80.00 31.25 71.43 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.32 82.50 47.22 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.01 94.37 60.00 73.08 84.62 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45


Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.67 86.67 33.33 66.67 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.36 85.00 45.45 55.00 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.01 94.37 60.00 73.08 84.62 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45


Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.33 95.00 75.00 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
87.66 94.37 71.67 84.62 100.00 u_tlul2sram_ingress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Go back
Module Instances:
tb.dut.u_readcmd.u_readsram.u_sram_fifo
tb.dut.u_readcmd.u_readsram.u_fifo
tb.dut.u_upload.u_arbiter.u_req_fifo
tb.dut.u_spi_tpm.u_sram_fifo
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
tb.dut.u_tlul2sram_egress.u_reqfifo
tb.dut.u_tlul2sram_egress.u_sramreqfifo
tb.dut.u_tlul2sram_egress.u_rspfifo
tb.dut.u_tlul2sram_ingress.u_reqfifo
Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
TotalCoveredPercent
Conditions221672.73
Logical221672.73
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T3,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T6
10Not Covered
11CoveredT1,T3,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T3,T6
101Not Covered
110Not Covered
111CoveredT1,T3,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T6
110Not Covered
111CoveredT1,T3,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T3,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 130 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T6
0 0 Covered T1,T3,T6


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 128991517 17943265 0 0
DepthKnown_A 128991517 98582655 0 0
RvalidKnown_A 128991517 98582655 0 0
WreadyKnown_A 128991517 98582655 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 128991517 17943265 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 17943265 0 0
T1 39891 27544 0 0
T2 7706 0 0 0
T3 457306 15271 0 0
T6 25461 19606 0 0
T7 204112 0 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 0 36 0 0
T12 0 2450 0 0
T13 44896 980 0 0
T17 68770 0 0 0
T20 106610 0 0 0
T23 0 9346 0 0
T24 0 4770 0 0
T38 0 79678 0 0
T39 0 17068 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 17943265 0 0
T1 39891 27544 0 0
T2 7706 0 0 0
T3 457306 15271 0 0
T6 25461 19606 0 0
T7 204112 0 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 0 36 0 0
T12 0 2450 0 0
T13 44896 980 0 0
T17 68770 0 0 0
T20 106610 0 0 0
T23 0 9346 0 0
T24 0 4770 0 0
T38 0 79678 0 0
T39 0 17068 0 0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
TotalCoveredPercent
Conditions221881.82
Logical221881.82
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T3,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T6
10Not Covered
11CoveredT1,T3,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T3,T6
101CoveredT1,T3,T6
110Not Covered
111CoveredT1,T3,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T6
110Not Covered
111CoveredT1,T3,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T2,T3
11CoveredT1,T3,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T3,T6
10CoveredT1,T3,T6
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 130 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T6
0 0 Covered T1,T3,T6


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 128991517 18842658 0 0
DepthKnown_A 128991517 98582655 0 0
RvalidKnown_A 128991517 98582655 0 0
WreadyKnown_A 128991517 98582655 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 128991517 18842658 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 18842658 0 0
T1 39891 29496 0 0
T2 7706 0 0 0
T3 457306 15948 0 0
T6 25461 20908 0 0
T7 204112 0 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 0 32 0 0
T12 0 2570 0 0
T13 44896 1040 0 0
T17 68770 0 0 0
T20 106610 0 0 0
T23 0 10216 0 0
T24 0 5120 0 0
T38 0 82936 0 0
T39 0 19332 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 18842658 0 0
T1 39891 29496 0 0
T2 7706 0 0 0
T3 457306 15948 0 0
T6 25461 20908 0 0
T7 204112 0 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 0 32 0 0
T12 0 2570 0 0
T13 44896 1040 0 0
T17 68770 0 0 0
T20 106610 0 0 0
T23 0 10216 0 0
T24 0 5120 0 0
T38 0 82936 0 0
T39 0 19332 0 0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL141285.71
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS1232150.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 0 1
MISSING_ELSE
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T6
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T3,T6
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T6
0 0 Covered T1,T3,T6


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 128991517 0 0 0
DepthKnown_A 128991517 98582655 0 0
RvalidKnown_A 128991517 98582655 0 0
WreadyKnown_A 128991517 98582655 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 128991517 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 98582655 0 0
T1 39891 39634 0 0
T2 7706 0 0 0
T3 457306 396253 0 0
T6 25461 25240 0 0
T7 204112 0 0 0
T8 82271 81680 0 0
T10 92266 0 0 0
T11 0 57902 0 0
T12 0 89738 0 0
T13 44896 44896 0 0
T14 0 43904 0 0
T15 0 6310 0 0
T16 0 30184 0 0
T17 68770 0 0 0
T20 106610 0 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 0 0 0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
TotalCoveredPercent
Conditions221777.27
Logical221777.27
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T7,T17
10CoveredT1,T2,T3
11CoveredT2,T3,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11CoveredT3,T7,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101Not Covered
110Not Covered
111CoveredT3,T7,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT3,T7,T17
101CoveredT3,T7,T17
110Not Covered
111CoveredT3,T7,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T7,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT3,T7,T17
10CoveredT3,T7,T17
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 130 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T3,T7,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T7
0 0 Covered T2,T3,T7


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T7,T17
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 128991517 6105016 0 0
DepthKnown_A 128991517 29119923 0 0
RvalidKnown_A 128991517 29119923 0 0
WreadyKnown_A 128991517 29119923 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 128991517 6105016 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 6105016 0 0
T3 457306 20093 0 0
T6 25461 0 0 0
T7 204112 33229 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T14 44736 0 0 0
T17 68770 29620 0 0
T20 106610 0 0 0
T29 0 3953 0 0
T30 0 5373 0 0
T31 0 603 0 0
T32 0 60591 0 0
T35 0 26527 0 0
T47 0 14805 0 0
T49 0 48229 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 29119923 0 0
T2 7706 7392 0 0
T3 457306 55896 0 0
T6 25461 0 0 0
T7 204112 200528 0 0
T8 82271 0 0 0
T10 92266 88520 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T17 68770 65824 0 0
T20 106610 102176 0 0
T22 0 60776 0 0
T29 0 14632 0 0
T30 0 24400 0 0
T31 0 1656 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 29119923 0 0
T2 7706 7392 0 0
T3 457306 55896 0 0
T6 25461 0 0 0
T7 204112 200528 0 0
T8 82271 0 0 0
T10 92266 88520 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T17 68770 65824 0 0
T20 106610 102176 0 0
T22 0 60776 0 0
T29 0 14632 0 0
T30 0 24400 0 0
T31 0 1656 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 29119923 0 0
T2 7706 7392 0 0
T3 457306 55896 0 0
T6 25461 0 0 0
T7 204112 200528 0 0
T8 82271 0 0 0
T10 92266 88520 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T17 68770 65824 0 0
T20 106610 102176 0 0
T22 0 60776 0 0
T29 0 14632 0 0
T30 0 24400 0 0
T31 0 1656 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 6105016 0 0
T3 457306 20093 0 0
T6 25461 0 0 0
T7 204112 33229 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T14 44736 0 0 0
T17 68770 29620 0 0
T20 106610 0 0 0
T29 0 3953 0 0
T30 0 5373 0 0
T31 0 603 0 0
T32 0 60591 0 0
T35 0 26527 0 0
T47 0 14805 0 0
T49 0 48229 0 0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
TotalCoveredPercent
Conditions16956.25
Logical16956.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T7
10Not Covered
11CoveredT3,T7,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101Not Covered
110Not Covered
111CoveredT3,T7,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT3,T7,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T7,T17
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T7,T17


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T7
0 0 Covered T2,T3,T7


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T7,T17
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 128991517 196317 0 0
DepthKnown_A 128991517 29119923 0 0
RvalidKnown_A 128991517 29119923 0 0
WreadyKnown_A 128991517 29119923 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 128991517 196317 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 196317 0 0
T3 457306 639 0 0
T6 25461 0 0 0
T7 204112 1072 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T14 44736 0 0 0
T17 68770 957 0 0
T20 106610 0 0 0
T29 0 125 0 0
T30 0 173 0 0
T31 0 19 0 0
T32 0 1953 0 0
T35 0 852 0 0
T47 0 475 0 0
T49 0 1552 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 29119923 0 0
T2 7706 7392 0 0
T3 457306 55896 0 0
T6 25461 0 0 0
T7 204112 200528 0 0
T8 82271 0 0 0
T10 92266 88520 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T17 68770 65824 0 0
T20 106610 102176 0 0
T22 0 60776 0 0
T29 0 14632 0 0
T30 0 24400 0 0
T31 0 1656 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 29119923 0 0
T2 7706 7392 0 0
T3 457306 55896 0 0
T6 25461 0 0 0
T7 204112 200528 0 0
T8 82271 0 0 0
T10 92266 88520 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T17 68770 65824 0 0
T20 106610 102176 0 0
T22 0 60776 0 0
T29 0 14632 0 0
T30 0 24400 0 0
T31 0 1656 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 29119923 0 0
T2 7706 7392 0 0
T3 457306 55896 0 0
T6 25461 0 0 0
T7 204112 200528 0 0
T8 82271 0 0 0
T10 92266 88520 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T17 68770 65824 0 0
T20 106610 102176 0 0
T22 0 60776 0 0
T29 0 14632 0 0
T30 0 24400 0 0
T31 0 1656 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 128991517 196317 0 0
T3 457306 639 0 0
T6 25461 0 0 0
T7 204112 1072 0 0
T8 82271 0 0 0
T10 92266 0 0 0
T11 58291 0 0 0
T13 44896 0 0 0
T14 44736 0 0 0
T17 68770 957 0 0
T20 106610 0 0 0
T29 0 125 0 0
T30 0 173 0 0
T31 0 19 0 0
T32 0 1953 0 0
T35 0 852 0 0
T47 0 475 0 0
T49 0 1552 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T4
110Not Covered
111CoveredT1,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429730063 2633154 0 0
DepthKnown_A 429730063 429645282 0 0
RvalidKnown_A 429730063 429645282 0 0
WreadyKnown_A 429730063 429645282 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429730063 2633154 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 2633154 0 0
T1 281162 832 0 0
T2 11981 0 0 0
T3 139763 8320 0 0
T4 3407 443 0 0
T5 948 0 0 0
T6 15883 832 0 0
T7 121950 0 0 0
T8 26656 832 0 0
T9 1606 100 0 0
T10 222579 0 0 0
T11 0 832 0 0
T13 0 832 0 0
T14 0 832 0 0
T28 0 100 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 2633154 0 0
T1 281162 832 0 0
T2 11981 0 0 0
T3 139763 8320 0 0
T4 3407 443 0 0
T5 948 0 0 0
T6 15883 832 0 0
T7 121950 0 0 0
T8 26656 832 0 0
T9 1606 100 0 0
T10 222579 0 0 0
T11 0 832 0 0
T13 0 832 0 0
T14 0 832 0 0
T28 0 100 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL151280.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429730063 0 0 0
DepthKnown_A 429730063 429645282 0 0
RvalidKnown_A 429730063 429645282 0 0
WreadyKnown_A 429730063 429645282 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429730063 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
Line No.TotalCoveredPercent
TOTAL151386.67
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
TotalCoveredPercent
Conditions24833.33
Logical24833.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 6 66.67
TERNARY 130 2 1 50.00
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 111 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429730063 0 0 0
DepthKnown_A 429730063 429645282 0 0
RvalidKnown_A 429730063 429645282 0 0
WreadyKnown_A 429730063 429645282 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429730063 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 0 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T4,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T4,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T4,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T4,T17
110Not Covered
111CoveredT3,T4,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T7


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T7
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 429730063 378539 0 0
DepthKnown_A 429730063 429645282 0 0
RvalidKnown_A 429730063 429645282 0 0
WreadyKnown_A 429730063 429645282 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 429730063 378539 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 378539 0 0
T3 139763 765 0 0
T4 3407 483 0 0
T5 948 0 0 0
T6 15883 0 0 0
T7 121950 601 0 0
T8 26656 0 0 0
T9 1606 100 0 0
T10 222579 0 0 0
T13 228469 0 0 0
T17 558862 2362 0 0
T24 0 10 0 0
T28 0 100 0 0
T29 0 289 0 0
T30 0 109 0 0
T31 0 8 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 429645282 0 0
T1 281162 281101 0 0
T2 11981 11890 0 0
T3 139763 139754 0 0
T4 3407 3309 0 0
T5 948 866 0 0
T6 15883 15829 0 0
T7 121950 121876 0 0
T8 26656 26561 0 0
T9 1606 1521 0 0
T10 222579 222512 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 429730063 378539 0 0
T3 139763 765 0 0
T4 3407 483 0 0
T5 948 0 0 0
T6 15883 0 0 0
T7 121950 601 0 0
T8 26656 0 0 0
T9 1606 100 0 0
T10 222579 0 0 0
T13 228469 0 0 0
T17 558862 2362 0 0
T24 0 10 0 0
T28 0 100 0 0
T29 0 289 0 0
T30 0 109 0 0
T31 0 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%