Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	432025235	6508640	0	0
DepthKnown_A	432025235	431898216	0	0
RvalidKnown_A	432025235	431898216	0	0
WreadyKnown_A	432025235	431898216	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	6508640	0	0
T1	281162	62	0	0
T2	11981	47	0	0
T3	139763	20980	0	0
T4	3407	1	0	0
T5	948	10	0	0
T6	15883	50	0	0
T7	121950	4471	0	0
T8	26656	62	0	0
T9	1606	1	0	0
T10	222579	772	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	431898216	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	431898216	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	431898216	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	432025235	13179112	0	0
DepthKnown_A	432025235	431898216	0	0
RvalidKnown_A	432025235	431898216	0	0
WreadyKnown_A	432025235	431898216	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	13179112	0	0
T1	281162	102	0	0
T2	11981	47	0	0
T3	139763	20845	0	0
T4	3407	1	0	0
T5	948	10	0	0
T6	15883	50	0	0
T7	121950	4405	0	0
T8	26656	62	0	0
T9	1606	1	0	0
T10	222579	3270	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	431898216	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	431898216	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432025235	431898216	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0