Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T17
1	0	Covered	T3,T7,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Unreachable
1	1	Covered	T3,T7,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T24,T32

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T24,T32
1	0	Covered	T3,T24,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T3,T24,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	687713097	557347860	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	687713097	3106622	0	0
GntImpliesValid_A	687713097	3106622	0	0
GrantKnown_A	687713097	557347860	0	0
IdxKnown_A	687713097	557347860	0	0
IndexIsCorrect_A	687713097	3106622	0	0
LockArbDecision_A	687713097	0	0	0
NoReadyValidNoGrant_A	687713097	0	0	0
ReadyAndValidImplyGrant_A	687713097	3106622	0	0
ReqAndReadyImplyGrant_A	687713097	3106622	0	0
ReqImpliesValid_A	687713097	3106622	0	0
ReqStaysHighUntilGranted0_M	687713097	0	0	0
RoundRobin_A	687713097	6	0	926
ValidKnown_A	687713097	557347860	0	0
gen_data_port_assertion.DataFlow_A	687713097	3106622	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	557347860	0	0
T1	321053	320735	0	0
T2	27393	19282	0	0
T3	1054375	591903	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	66805	41069	0	0
T7	530174	322404	0	0
T8	191198	108241	0	0
T9	1606	1521	0	0
T10	407111	311032	0	0
T11	58291	57902	0	0
T13	89792	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	137540	65824	0	0
T20	213220	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	557347860	0	0
T1	321053	320735	0	0
T2	27393	19282	0	0
T3	1054375	591903	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	66805	41069	0	0
T7	530174	322404	0	0
T8	191198	108241	0	0
T9	1606	1521	0	0
T10	407111	311032	0	0
T11	58291	57902	0	0
T13	89792	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	137540	65824	0	0
T20	213220	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	557347860	0	0
T1	321053	320735	0	0
T2	27393	19282	0	0
T3	1054375	591903	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	66805	41069	0	0
T7	530174	322404	0	0
T8	191198	108241	0	0
T9	1606	1521	0	0
T10	407111	311032	0	0
T11	58291	57902	0	0
T13	89792	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	137540	65824	0	0
T20	213220	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	6	0	926
T25	0	1	0	0
T45	995294	1	0	1
T46	282986	0	0	1
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	561881	0	0	1
T66	555903	0	0	1
T67	3837	0	0	1
T68	593392	0	0	1
T69	4538	0	0	1
T70	493239	0	0	1
T71	192859	0	0	1
T72	1435	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	557347860	0	0
T1	321053	320735	0	0
T2	27393	19282	0	0
T3	1054375	591903	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	66805	41069	0	0
T7	530174	322404	0	0
T8	191198	108241	0	0
T9	1606	1521	0	0
T10	407111	311032	0	0
T11	58291	57902	0	0
T13	89792	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	137540	65824	0	0
T20	213220	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687713097	3106622	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	1054375	16914	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	66805	832	0	0
T7	530174	5146	0	0
T8	191198	832	0	0
T9	1606	200	0	0
T10	407111	0	0	0
T11	116582	0	0	0
T13	89792	832	0	0
T14	89472	0	0	0
T17	137540	4796	0	0
T20	213220	0	0	0
T24	0	12	0	0
T28	0	200	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6963	0	0
T35	0	5471	0	0
T47	0	2208	0	0
T49	0	4691	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T17
1	0	Covered	T3,T7,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Unreachable
1	1	Covered	T3,T7,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T7,T17
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128991517	29119923	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	128991517	658210	0	0
GntImpliesValid_A	128991517	658210	0	0
GrantKnown_A	128991517	29119923	0	0
IdxKnown_A	128991517	29119923	0	0
IndexIsCorrect_A	128991517	658210	0	0
LockArbDecision_A	128991517	0	0	0
NoReadyValidNoGrant_A	128991517	0	0	0
ReadyAndValidImplyGrant_A	128991517	658210	0	0
ReqAndReadyImplyGrant_A	128991517	658210	0	0
ReqImpliesValid_A	128991517	658210	0	0
ReqStaysHighUntilGranted0_M	128991517	0	0	0
RoundRobin_A	128991517	0	0	0
ValidKnown_A	128991517	29119923	0	0
gen_data_port_assertion.DataFlow_A	128991517	658210	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	29119923	0	0
T2	7706	7392	0	0
T3	457306	55896	0	0
T6	25461	0	0	0
T7	204112	200528	0	0
T8	82271	0	0	0
T10	92266	88520	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T17	68770	65824	0	0
T20	106610	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	29119923	0	0
T2	7706	7392	0	0
T3	457306	55896	0	0
T6	25461	0	0	0
T7	204112	200528	0	0
T8	82271	0	0	0
T10	92266	88520	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T17	68770	65824	0	0
T20	106610	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	29119923	0	0
T2	7706	7392	0	0
T3	457306	55896	0	0
T6	25461	0	0	0
T7	204112	200528	0	0
T8	82271	0	0	0
T10	92266	88520	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T17	68770	65824	0	0
T20	106610	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	29119923	0	0
T2	7706	7392	0	0
T3	457306	55896	0	0
T6	25461	0	0	0
T7	204112	200528	0	0
T8	82271	0	0	0
T10	92266	88520	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T17	68770	65824	0	0
T20	106610	102176	0	0
T22	0	60776	0	0
T29	0	14632	0	0
T30	0	24400	0	0
T31	0	1656	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	658210	0	0
T3	457306	2320	0	0
T6	25461	0	0	0
T7	204112	3473	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	3267	0	0
T20	106610	0	0	0
T29	0	393	0	0
T30	0	611	0	0
T31	0	51	0	0
T32	0	6704	0	0
T35	0	2607	0	0
T47	0	1191	0	0
T49	0	4691	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T24,T32

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T24,T32
1	0	Covered	T3,T24,T32

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Unreachable
1	1	Covered	T3,T24,T32

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T24,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T24,T32
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T24,T32
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T24,T32
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128991517	98582655	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	128991517	501445	0	0
GntImpliesValid_A	128991517	501445	0	0
GrantKnown_A	128991517	98582655	0	0
IdxKnown_A	128991517	98582655	0	0
IndexIsCorrect_A	128991517	501445	0	0
LockArbDecision_A	128991517	0	0	0
NoReadyValidNoGrant_A	128991517	0	0	0
ReadyAndValidImplyGrant_A	128991517	501445	0	0
ReqAndReadyImplyGrant_A	128991517	501445	0	0
ReqImpliesValid_A	128991517	501445	0	0
ReqStaysHighUntilGranted0_M	128991517	0	0	0
RoundRobin_A	128991517	0	0	0
ValidKnown_A	128991517	98582655	0	0
gen_data_port_assertion.DataFlow_A	128991517	501445	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	98582655	0	0
T1	39891	39634	0	0
T2	7706	0	0	0
T3	457306	396253	0	0
T6	25461	25240	0	0
T7	204112	0	0	0
T8	82271	81680	0	0
T10	92266	0	0	0
T11	0	57902	0	0
T12	0	89738	0	0
T13	44896	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	68770	0	0	0
T20	106610	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	98582655	0	0
T1	39891	39634	0	0
T2	7706	0	0	0
T3	457306	396253	0	0
T6	25461	25240	0	0
T7	204112	0	0	0
T8	82271	81680	0	0
T10	92266	0	0	0
T11	0	57902	0	0
T12	0	89738	0	0
T13	44896	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	68770	0	0	0
T20	106610	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	98582655	0	0
T1	39891	39634	0	0
T2	7706	0	0	0
T3	457306	396253	0	0
T6	25461	25240	0	0
T7	204112	0	0	0
T8	82271	81680	0	0
T10	92266	0	0	0
T11	0	57902	0	0
T12	0	89738	0	0
T13	44896	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	68770	0	0	0
T20	106610	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	98582655	0	0
T1	39891	39634	0	0
T2	7706	0	0	0
T3	457306	396253	0	0
T6	25461	25240	0	0
T7	204112	0	0	0
T8	82271	81680	0	0
T10	92266	0	0	0
T11	0	57902	0	0
T12	0	89738	0	0
T13	44896	44896	0	0
T14	0	43904	0	0
T15	0	6310	0	0
T16	0	30184	0	0
T17	68770	0	0	0
T20	106610	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128991517	501445	0	0
T3	457306	4838	0	0
T6	25461	0	0	0
T7	204112	0	0	0
T8	82271	0	0	0
T10	92266	0	0	0
T11	58291	0	0	0
T13	44896	0	0	0
T14	44736	0	0	0
T17	68770	0	0	0
T20	106610	0	0	0
T24	0	12	0	0
T32	0	259	0	0
T35	0	2864	0	0
T37	0	134	0	0
T47	0	1017	0	0
T50	0	6432	0	0
T59	0	774	0	0
T60	0	1457	0	0
T73	0	7	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	429730063	429645282	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	429730063	1946967	0	0
GntImpliesValid_A	429730063	1946967	0	0
GrantKnown_A	429730063	429645282	0	0
IdxKnown_A	429730063	429645282	0	0
IndexIsCorrect_A	429730063	1946967	0	0
LockArbDecision_A	429730063	0	0	0
NoReadyValidNoGrant_A	429730063	0	0	0
ReadyAndValidImplyGrant_A	429730063	1946967	0	0
ReqAndReadyImplyGrant_A	429730063	1946967	0	0
ReqImpliesValid_A	429730063	1946967	0	0
ReqStaysHighUntilGranted0_M	429730063	0	0	0
RoundRobin_A	429730063	6	0	926
ValidKnown_A	429730063	429645282	0	0
gen_data_port_assertion.DataFlow_A	429730063	1946967	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	429645282	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	429645282	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	429645282	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	6	0	926
T25	0	1	0	0
T45	995294	1	0	1
T46	282986	0	0	1
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	561881	0	0	1
T66	555903	0	0	1
T67	3837	0	0	1
T68	593392	0	0	1
T69	4538	0	0	1
T70	493239	0	0	1
T71	192859	0	0	1
T72	1435	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	429645282	0	0
T1	281162	281101	0	0
T2	11981	11890	0	0
T3	139763	139754	0	0
T4	3407	3309	0	0
T5	948	866	0	0
T6	15883	15829	0	0
T7	121950	121876	0	0
T8	26656	26561	0	0
T9	1606	1521	0	0
T10	222579	222512	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429730063	1946967	0	0
T1	281162	832	0	0
T2	11981	0	0	0
T3	139763	9756	0	0
T4	3407	200	0	0
T5	948	0	0	0
T6	15883	832	0	0
T7	121950	1673	0	0
T8	26656	832	0	0
T9	1606	200	0	0
T10	222579	0	0	0
T13	0	832	0	0
T17	0	1529	0	0
T28	0	200	0	0