Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.95 98.35 94.20 98.61 89.36 97.14 95.81 98.17


Total test records in report: 1101
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T1016 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3091620386 May 12 12:45:43 PM PDT 24 May 12 12:45:46 PM PDT 24 66697708 ps
T1017 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.255695216 May 12 12:46:20 PM PDT 24 May 12 12:46:21 PM PDT 24 52607533 ps
T1018 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.783422512 May 12 12:46:22 PM PDT 24 May 12 12:46:23 PM PDT 24 35650714 ps
T1019 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.259619078 May 12 12:46:02 PM PDT 24 May 12 12:46:06 PM PDT 24 84288320 ps
T1020 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1657522373 May 12 12:45:55 PM PDT 24 May 12 12:46:00 PM PDT 24 99558117 ps
T130 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1394913873 May 12 12:45:58 PM PDT 24 May 12 12:46:01 PM PDT 24 120140096 ps
T1021 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2921658142 May 12 12:45:58 PM PDT 24 May 12 12:46:00 PM PDT 24 18417878 ps
T121 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1564372610 May 12 12:45:58 PM PDT 24 May 12 12:46:08 PM PDT 24 170181079 ps
T1022 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.912998172 May 12 12:46:06 PM PDT 24 May 12 12:46:07 PM PDT 24 16686046 ps
T1023 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2815238178 May 12 12:46:04 PM PDT 24 May 12 12:46:24 PM PDT 24 593122717 ps
T1024 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1508487102 May 12 12:45:58 PM PDT 24 May 12 12:46:01 PM PDT 24 308687617 ps
T1025 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1204561735 May 12 12:45:44 PM PDT 24 May 12 12:45:48 PM PDT 24 12402872 ps
T94 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.270132832 May 12 12:45:42 PM PDT 24 May 12 12:45:45 PM PDT 24 260620255 ps
T160 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3880398600 May 12 12:45:44 PM PDT 24 May 12 12:45:55 PM PDT 24 713188680 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3075407250 May 12 12:46:00 PM PDT 24 May 12 12:46:04 PM PDT 24 162876754 ps
T131 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.199218641 May 12 12:45:44 PM PDT 24 May 12 12:45:48 PM PDT 24 24414250 ps
T1026 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3973005179 May 12 12:45:56 PM PDT 24 May 12 12:45:58 PM PDT 24 13960449 ps
T1027 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2621863966 May 12 12:46:33 PM PDT 24 May 12 12:46:35 PM PDT 24 25279215 ps
T1028 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.770581706 May 12 12:46:15 PM PDT 24 May 12 12:46:16 PM PDT 24 42659776 ps
T1029 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1683521153 May 12 12:45:38 PM PDT 24 May 12 12:45:39 PM PDT 24 12941205 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3935039019 May 12 12:45:54 PM PDT 24 May 12 12:45:58 PM PDT 24 167803477 ps
T1031 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3785834457 May 12 12:45:44 PM PDT 24 May 12 12:45:49 PM PDT 24 392399888 ps
T1032 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1563790316 May 12 12:46:27 PM PDT 24 May 12 12:46:29 PM PDT 24 44928983 ps
T1033 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1741714513 May 12 12:46:12 PM PDT 24 May 12 12:46:15 PM PDT 24 126592560 ps
T1034 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4105422278 May 12 12:46:09 PM PDT 24 May 12 12:46:12 PM PDT 24 537749088 ps
T1035 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3841009129 May 12 12:45:54 PM PDT 24 May 12 12:45:58 PM PDT 24 231560748 ps
T1036 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1250481133 May 12 12:45:41 PM PDT 24 May 12 12:45:47 PM PDT 24 163596568 ps
T1037 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1194488951 May 12 12:45:57 PM PDT 24 May 12 12:46:03 PM PDT 24 297108977 ps
T1038 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2173265117 May 12 12:46:06 PM PDT 24 May 12 12:46:07 PM PDT 24 70065472 ps
T1039 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1852699552 May 12 12:45:40 PM PDT 24 May 12 12:45:44 PM PDT 24 272934966 ps
T1040 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3740536138 May 12 12:45:52 PM PDT 24 May 12 12:45:58 PM PDT 24 152191990 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.967397755 May 12 12:45:44 PM PDT 24 May 12 12:45:50 PM PDT 24 249164180 ps
T132 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3583045562 May 12 12:45:40 PM PDT 24 May 12 12:45:43 PM PDT 24 85003260 ps
T1042 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2407271703 May 12 12:45:46 PM PDT 24 May 12 12:45:51 PM PDT 24 126052588 ps
T1043 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4211967685 May 12 12:45:56 PM PDT 24 May 12 12:45:58 PM PDT 24 74067231 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.69475125 May 12 12:45:52 PM PDT 24 May 12 12:46:03 PM PDT 24 76298291 ps
T1045 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4251113228 May 12 12:45:44 PM PDT 24 May 12 12:45:47 PM PDT 24 11933797 ps
T1046 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2761818399 May 12 12:45:47 PM PDT 24 May 12 12:45:50 PM PDT 24 55310932 ps
T133 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2222079442 May 12 12:46:04 PM PDT 24 May 12 12:46:07 PM PDT 24 39913473 ps
T1047 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2101188112 May 12 12:45:41 PM PDT 24 May 12 12:45:44 PM PDT 24 31872185 ps
T134 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1519846445 May 12 12:45:57 PM PDT 24 May 12 12:46:20 PM PDT 24 366718283 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2539834259 May 12 12:46:07 PM PDT 24 May 12 12:46:08 PM PDT 24 199717208 ps
T1049 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2114994976 May 12 12:45:51 PM PDT 24 May 12 12:45:54 PM PDT 24 38424088 ps
T135 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1390217640 May 12 12:46:01 PM PDT 24 May 12 12:46:24 PM PDT 24 1309115096 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.6133440 May 12 12:46:00 PM PDT 24 May 12 12:46:03 PM PDT 24 194074269 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4070498716 May 12 12:45:50 PM PDT 24 May 12 12:45:55 PM PDT 24 128208379 ps
T1052 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3875914241 May 12 12:46:09 PM PDT 24 May 12 12:46:13 PM PDT 24 55437487 ps
T95 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.154200119 May 12 12:45:42 PM PDT 24 May 12 12:45:46 PM PDT 24 34427318 ps
T1053 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3313828116 May 12 12:45:54 PM PDT 24 May 12 12:46:34 PM PDT 24 10792334949 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2337705798 May 12 12:45:56 PM PDT 24 May 12 12:46:03 PM PDT 24 53214810 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.306539619 May 12 12:46:13 PM PDT 24 May 12 12:46:17 PM PDT 24 222181626 ps
T136 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1030527113 May 12 12:45:59 PM PDT 24 May 12 12:46:26 PM PDT 24 7213712106 ps
T1056 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2828172380 May 12 12:46:23 PM PDT 24 May 12 12:46:30 PM PDT 24 362402325 ps
T272 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2379995524 May 12 12:45:52 PM PDT 24 May 12 12:46:04 PM PDT 24 194496637 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1559304727 May 12 12:46:24 PM PDT 24 May 12 12:46:29 PM PDT 24 639900922 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3673000192 May 12 12:45:48 PM PDT 24 May 12 12:45:51 PM PDT 24 12942908 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.717560790 May 12 12:45:58 PM PDT 24 May 12 12:46:03 PM PDT 24 185448400 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3969119797 May 12 12:45:45 PM PDT 24 May 12 12:45:49 PM PDT 24 12971963 ps
T96 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2175825939 May 12 12:45:39 PM PDT 24 May 12 12:45:41 PM PDT 24 23043650 ps
T1061 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2132182838 May 12 12:45:44 PM PDT 24 May 12 12:45:50 PM PDT 24 191996727 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1363635789 May 12 12:46:04 PM PDT 24 May 12 12:46:09 PM PDT 24 68588999 ps
T1063 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.524045023 May 12 12:45:55 PM PDT 24 May 12 12:45:59 PM PDT 24 102323770 ps
T1064 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3562704996 May 12 12:46:11 PM PDT 24 May 12 12:46:12 PM PDT 24 20437919 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1627481952 May 12 12:46:00 PM PDT 24 May 12 12:46:08 PM PDT 24 92422744 ps
T1066 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1998676456 May 12 12:45:56 PM PDT 24 May 12 12:46:05 PM PDT 24 1094424699 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3280717808 May 12 12:46:01 PM PDT 24 May 12 12:46:15 PM PDT 24 200175593 ps
T1068 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1174776471 May 12 12:46:13 PM PDT 24 May 12 12:46:15 PM PDT 24 133673978 ps
T1069 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3571944828 May 12 12:45:49 PM PDT 24 May 12 12:45:51 PM PDT 24 29716450 ps
T1070 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4057703074 May 12 12:46:08 PM PDT 24 May 12 12:46:11 PM PDT 24 57386711 ps
T1071 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2594363214 May 12 12:45:56 PM PDT 24 May 12 12:45:58 PM PDT 24 52140400 ps
T1072 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2955170994 May 12 12:45:44 PM PDT 24 May 12 12:45:50 PM PDT 24 655466585 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.502494442 May 12 12:45:43 PM PDT 24 May 12 12:45:46 PM PDT 24 13914454 ps
T1074 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.939570449 May 12 12:45:37 PM PDT 24 May 12 12:45:39 PM PDT 24 15252206 ps
T1075 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.595244614 May 12 12:45:50 PM PDT 24 May 12 12:45:54 PM PDT 24 109023211 ps
T1076 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1567096196 May 12 12:45:41 PM PDT 24 May 12 12:45:45 PM PDT 24 215793420 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3887989234 May 12 12:45:57 PM PDT 24 May 12 12:46:00 PM PDT 24 64813581 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.469098810 May 12 12:46:07 PM PDT 24 May 12 12:46:12 PM PDT 24 217437522 ps
T1079 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2261236891 May 12 12:45:39 PM PDT 24 May 12 12:45:42 PM PDT 24 113971463 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2079469404 May 12 12:45:41 PM PDT 24 May 12 12:45:44 PM PDT 24 117905734 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3285925204 May 12 12:45:50 PM PDT 24 May 12 12:46:04 PM PDT 24 202145872 ps
T1082 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3068984274 May 12 12:45:51 PM PDT 24 May 12 12:45:54 PM PDT 24 27373203 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2786409739 May 12 12:45:38 PM PDT 24 May 12 12:45:41 PM PDT 24 117425714 ps
T1084 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.973555834 May 12 12:45:51 PM PDT 24 May 12 12:45:54 PM PDT 24 207786741 ps
T1085 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2462466016 May 12 12:45:49 PM PDT 24 May 12 12:45:52 PM PDT 24 81781107 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.687073776 May 12 12:45:41 PM PDT 24 May 12 12:45:44 PM PDT 24 144592141 ps
T1087 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1638744382 May 12 12:45:40 PM PDT 24 May 12 12:45:45 PM PDT 24 144243061 ps
T1088 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2485039160 May 12 12:45:56 PM PDT 24 May 12 12:45:58 PM PDT 24 20786420 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1963883538 May 12 12:46:03 PM PDT 24 May 12 12:46:05 PM PDT 24 23991963 ps
T1090 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3392543495 May 12 12:45:48 PM PDT 24 May 12 12:45:52 PM PDT 24 294844315 ps
T273 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1983950795 May 12 12:46:27 PM PDT 24 May 12 12:46:46 PM PDT 24 285726557 ps
T1091 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3039174990 May 12 12:45:43 PM PDT 24 May 12 12:45:47 PM PDT 24 37337408 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3565338415 May 12 12:45:40 PM PDT 24 May 12 12:45:49 PM PDT 24 1511935934 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3728072811 May 12 12:45:41 PM PDT 24 May 12 12:45:51 PM PDT 24 359408773 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2780184993 May 12 12:45:43 PM PDT 24 May 12 12:46:00 PM PDT 24 614844486 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3194732089 May 12 12:45:47 PM PDT 24 May 12 12:45:51 PM PDT 24 29005441 ps
T1096 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1815189819 May 12 12:45:42 PM PDT 24 May 12 12:45:44 PM PDT 24 23722967 ps
T1097 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1059320050 May 12 12:46:04 PM PDT 24 May 12 12:46:08 PM PDT 24 551298533 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2009226635 May 12 12:45:53 PM PDT 24 May 12 12:46:01 PM PDT 24 290257995 ps
T1099 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2121717145 May 12 12:45:47 PM PDT 24 May 12 12:45:52 PM PDT 24 275170044 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2083922667 May 12 12:45:42 PM PDT 24 May 12 12:45:47 PM PDT 24 52032558 ps
T1101 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.560076551 May 12 12:45:44 PM PDT 24 May 12 12:45:55 PM PDT 24 342727473 ps

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.580902251
Short name T3
Test name
Test status
Simulation time 58235239042 ps
CPU time 159.53 seconds
Started May 12 12:52:41 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 257372 kb
Host smart-7f717439-496e-4b36-8fb4-ecadd04a557f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580902251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.580902251
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2702043237
Short name T33
Test name
Test status
Simulation time 18198659825 ps
CPU time 216.12 seconds
Started May 12 12:53:30 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 256444 kb
Host smart-2ea09726-d224-4d7e-80ae-811a6a7afeb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702043237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2702043237
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_upload.1840534970
Short name T12
Test name
Test status
Simulation time 1014048571 ps
CPU time 9.23 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 240804 kb
Host smart-51e4341c-a7d8-438a-8646-6a53a3e97114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840534970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1840534970
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3055675427
Short name T34
Test name
Test status
Simulation time 37379565285 ps
CPU time 428.65 seconds
Started May 12 12:54:13 PM PDT 24
Finished May 12 01:01:23 PM PDT 24
Peak memory 265356 kb
Host smart-63a74985-115f-41bb-8534-581e49de7eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055675427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3055675427
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.646955377
Short name T124
Test name
Test status
Simulation time 415202641 ps
CPU time 2.94 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:16 PM PDT 24
Peak memory 218028 kb
Host smart-cabd7b11-2731-435a-8c95-7b650f9fee13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646955377 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.646955377
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3669883970
Short name T32
Test name
Test status
Simulation time 3123635147 ps
CPU time 49.33 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:51:54 PM PDT 24
Peak memory 237340 kb
Host smart-fa93ade7-3697-4c95-9a27-af52091fa773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669883970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3669883970
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.518656640
Short name T79
Test name
Test status
Simulation time 56929568 ps
CPU time 0.79 seconds
Started May 12 12:50:49 PM PDT 24
Finished May 12 12:50:51 PM PDT 24
Peak memory 216032 kb
Host smart-049f016a-0c66-4f2b-8ac5-46c53e2c268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518656640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.518656640
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1299871611
Short name T170
Test name
Test status
Simulation time 11089279382 ps
CPU time 128.3 seconds
Started May 12 12:54:24 PM PDT 24
Finished May 12 12:56:33 PM PDT 24
Peak memory 257452 kb
Host smart-7466af30-4e1e-4c3d-861c-53bf70fea083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299871611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1299871611
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1857814106
Short name T193
Test name
Test status
Simulation time 122315704753 ps
CPU time 541.29 seconds
Started May 12 12:52:31 PM PDT 24
Finished May 12 01:01:33 PM PDT 24
Peak memory 267136 kb
Host smart-0d5d2d1c-7ca7-4b24-981d-776f1af0bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857814106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1857814106
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3049599071
Short name T45
Test name
Test status
Simulation time 121376210818 ps
CPU time 788.87 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 01:06:51 PM PDT 24
Peak memory 266864 kb
Host smart-8d88f254-9171-4ef6-81cf-1c56b475fc6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049599071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3049599071
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4063882835
Short name T80
Test name
Test status
Simulation time 87093525 ps
CPU time 1.06 seconds
Started May 12 12:51:05 PM PDT 24
Finished May 12 12:51:07 PM PDT 24
Peak memory 235092 kb
Host smart-f6467986-4a62-4ab0-9163-db09c8849dae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063882835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4063882835
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3221703876
Short name T35
Test name
Test status
Simulation time 16696553877 ps
CPU time 129.32 seconds
Started May 12 12:53:26 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 265924 kb
Host smart-b60aea5d-f2a4-4127-aa9a-9762bde201a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221703876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3221703876
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2051188038
Short name T184
Test name
Test status
Simulation time 231897107392 ps
CPU time 469.76 seconds
Started May 12 12:53:07 PM PDT 24
Finished May 12 01:00:58 PM PDT 24
Peak memory 262304 kb
Host smart-33f3fd2f-7594-4036-a7db-e2e2f1ef12f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051188038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2051188038
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.772815276
Short name T57
Test name
Test status
Simulation time 49838599389 ps
CPU time 48.06 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 240984 kb
Host smart-4c82f61d-c3bf-4b92-aee7-83a45ddbd27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772815276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.772815276
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4022118117
Short name T182
Test name
Test status
Simulation time 200432087736 ps
CPU time 462.72 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 01:01:31 PM PDT 24
Peak memory 263292 kb
Host smart-0abc5883-a8e2-496f-8948-8b31fc3f9770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022118117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4022118117
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2673083267
Short name T158
Test name
Test status
Simulation time 12431780843 ps
CPU time 14.15 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 216864 kb
Host smart-932dfdfc-1667-483f-a84b-0c4028d71816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673083267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2673083267
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.635892430
Short name T139
Test name
Test status
Simulation time 25111562708 ps
CPU time 147.83 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 257464 kb
Host smart-e5cd0ca7-f6ac-4da1-a3bb-6895a7a78e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635892430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.635892430
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1226417040
Short name T119
Test name
Test status
Simulation time 275218029 ps
CPU time 5.05 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:18 PM PDT 24
Peak memory 215736 kb
Host smart-a61de0c8-f88f-4a81-90e4-28867ffbe26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226417040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
226417040
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.270132832
Short name T94
Test name
Test status
Simulation time 260620255 ps
CPU time 1.2 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:45 PM PDT 24
Peak memory 207396 kb
Host smart-047ddbd1-db7f-41a9-917f-6e12e69bd9be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270132832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.270132832
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2715611728
Short name T227
Test name
Test status
Simulation time 12954379091 ps
CPU time 204.56 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:57:06 PM PDT 24
Peak memory 256340 kb
Host smart-41c74d86-cfd6-43b2-8813-cbb810051432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715611728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2715611728
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3072957556
Short name T44
Test name
Test status
Simulation time 54045474240 ps
CPU time 274.54 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:58:31 PM PDT 24
Peak memory 257476 kb
Host smart-8b4a3429-5609-4fa1-bb57-ddb161f7694b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072957556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3072957556
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2638552304
Short name T4
Test name
Test status
Simulation time 35146557 ps
CPU time 1.07 seconds
Started May 12 12:51:46 PM PDT 24
Finished May 12 12:51:47 PM PDT 24
Peak memory 216940 kb
Host smart-69c71a7b-cc84-431d-8dd7-4aca4d5c1a66
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638552304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2638552304
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3378075350
Short name T238
Test name
Test status
Simulation time 110603706931 ps
CPU time 719.6 seconds
Started May 12 12:51:29 PM PDT 24
Finished May 12 01:03:30 PM PDT 24
Peak memory 273540 kb
Host smart-ae4c86d0-a69f-4b35-83dd-9a8f5d4f27bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378075350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3378075350
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1243638762
Short name T166
Test name
Test status
Simulation time 154980053093 ps
CPU time 236.24 seconds
Started May 12 12:52:17 PM PDT 24
Finished May 12 12:56:14 PM PDT 24
Peak memory 255008 kb
Host smart-074c8b47-7f32-4093-8acf-8d423690422e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243638762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1243638762
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.913652848
Short name T26
Test name
Test status
Simulation time 301885885262 ps
CPU time 728.58 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 01:06:13 PM PDT 24
Peak memory 273936 kb
Host smart-ccca679d-ca4a-4f4e-a396-db4e9d920841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913652848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.913652848
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2390577352
Short name T232
Test name
Test status
Simulation time 118587280866 ps
CPU time 262.79 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:56:23 PM PDT 24
Peak memory 254648 kb
Host smart-64e9a002-846e-432c-b844-3ed702090e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390577352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2390577352
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3620427507
Short name T243
Test name
Test status
Simulation time 54536337263 ps
CPU time 518.75 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 01:02:27 PM PDT 24
Peak memory 249340 kb
Host smart-eb93276c-7e9b-43ee-abbb-eff2ec20ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620427507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3620427507
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2294396797
Short name T257
Test name
Test status
Simulation time 18708449608 ps
CPU time 112.58 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:55:37 PM PDT 24
Peak memory 252548 kb
Host smart-dc349301-794c-42ea-a495-f7a7bc4411f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294396797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2294396797
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2629710527
Short name T180
Test name
Test status
Simulation time 259668561362 ps
CPU time 466.18 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 01:01:57 PM PDT 24
Peak memory 250312 kb
Host smart-a6c9f183-623f-4e76-91a3-7f93071f97f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629710527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2629710527
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2370602196
Short name T5
Test name
Test status
Simulation time 19366345 ps
CPU time 0.72 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:13 PM PDT 24
Peak memory 204620 kb
Host smart-40aac24e-1aaa-4de9-9f5f-6eac1ac52299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370602196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
370602196
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3845681010
Short name T99
Test name
Test status
Simulation time 9464220696 ps
CPU time 38.75 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 251372 kb
Host smart-6012ee61-abba-4330-8e4d-e855370478f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845681010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3845681010
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4018518519
Short name T250
Test name
Test status
Simulation time 6277432518 ps
CPU time 117.87 seconds
Started May 12 12:53:35 PM PDT 24
Finished May 12 12:55:33 PM PDT 24
Peak memory 269140 kb
Host smart-03bf8411-f951-4c01-bf87-596541253bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018518519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4018518519
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2049726263
Short name T198
Test name
Test status
Simulation time 33270872283 ps
CPU time 102.44 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 241352 kb
Host smart-4460bc55-c09f-4763-add1-4637644b3cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049726263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2049726263
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2571004439
Short name T92
Test name
Test status
Simulation time 19963833765 ps
CPU time 152.71 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 250728 kb
Host smart-ffcff4e3-99f4-4741-8b3a-486b1cc42739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571004439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2571004439
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.508481811
Short name T248
Test name
Test status
Simulation time 20526923258 ps
CPU time 219.8 seconds
Started May 12 12:54:01 PM PDT 24
Finished May 12 12:57:42 PM PDT 24
Peak memory 254092 kb
Host smart-5a94b8a2-2b65-446a-bdc1-95f6b2824ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508481811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.508481811
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1564372610
Short name T121
Test name
Test status
Simulation time 170181079 ps
CPU time 4.34 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 215776 kb
Host smart-85a93b71-6d0e-468b-9b37-69b6247524c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564372610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1564372610
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.688389552
Short name T270
Test name
Test status
Simulation time 2274990853 ps
CPU time 14.8 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:46:42 PM PDT 24
Peak memory 216144 kb
Host smart-51e352b6-ae51-4a2f-85b6-10c9e7773e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688389552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.688389552
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2276515154
Short name T188
Test name
Test status
Simulation time 45982065784 ps
CPU time 208.14 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:57:20 PM PDT 24
Peak memory 240884 kb
Host smart-96821402-33de-468c-85cb-e985aab00beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276515154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2276515154
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2174087658
Short name T20
Test name
Test status
Simulation time 1578065194 ps
CPU time 9.39 seconds
Started May 12 12:51:05 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 216240 kb
Host smart-a2c26bd5-34a8-413b-b27c-0ec347bde704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174087658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2174087658
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3005621979
Short name T151
Test name
Test status
Simulation time 226613676 ps
CPU time 9.58 seconds
Started May 12 12:52:00 PM PDT 24
Finished May 12 12:52:10 PM PDT 24
Peak memory 240820 kb
Host smart-d5acdbd3-5cff-4a97-aa98-9fdbf3618bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005621979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3005621979
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1500451748
Short name T221
Test name
Test status
Simulation time 13174578744 ps
CPU time 78.55 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:53:29 PM PDT 24
Peak memory 250672 kb
Host smart-dfbef58b-1646-45ff-9c74-4e499a9a19cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500451748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1500451748
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3041702171
Short name T369
Test name
Test status
Simulation time 271128621 ps
CPU time 4.93 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:51:10 PM PDT 24
Peak memory 233996 kb
Host smart-9036dbd6-d224-41e0-a4bb-2eb4c8f062f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041702171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3041702171
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3012399835
Short name T241
Test name
Test status
Simulation time 1033093673 ps
CPU time 5.45 seconds
Started May 12 12:51:03 PM PDT 24
Finished May 12 12:51:09 PM PDT 24
Peak memory 234764 kb
Host smart-92f77c41-f4d7-48a8-8ea7-466c7b7abd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012399835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3012399835
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2095931658
Short name T152
Test name
Test status
Simulation time 10571402766 ps
CPU time 30.86 seconds
Started May 12 12:51:06 PM PDT 24
Finished May 12 12:51:38 PM PDT 24
Peak memory 236716 kb
Host smart-74c76420-949e-47d7-9ddd-b6f0cc2c762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095931658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2095931658
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2745952475
Short name T63
Test name
Test status
Simulation time 515363898723 ps
CPU time 445.94 seconds
Started May 12 12:51:54 PM PDT 24
Finished May 12 12:59:21 PM PDT 24
Peak memory 270472 kb
Host smart-3098cd45-427b-413b-bbc3-b56efb685447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745952475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2745952475
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3674518477
Short name T252
Test name
Test status
Simulation time 1281168925 ps
CPU time 5.5 seconds
Started May 12 12:52:00 PM PDT 24
Finished May 12 12:52:06 PM PDT 24
Peak memory 224148 kb
Host smart-512184e5-c3a3-4e92-a7f9-d96d091d1470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674518477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3674518477
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1679403621
Short name T310
Test name
Test status
Simulation time 1762928735 ps
CPU time 14.02 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 232736 kb
Host smart-db84f784-95c5-410c-bebe-254c8ed2bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679403621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1679403621
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3434650876
Short name T240
Test name
Test status
Simulation time 101248337906 ps
CPU time 200.03 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:54:25 PM PDT 24
Peak memory 253080 kb
Host smart-f48f9e2f-f137-496d-a340-60881bef68e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434650876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3434650876
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2831962326
Short name T266
Test name
Test status
Simulation time 466786355051 ps
CPU time 450.79 seconds
Started May 12 12:52:53 PM PDT 24
Finished May 12 01:00:25 PM PDT 24
Peak memory 265676 kb
Host smart-f04167b0-5093-49ad-90cc-7d0c98354ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831962326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2831962326
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.65678917
Short name T251
Test name
Test status
Simulation time 2752266322 ps
CPU time 19.97 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:54:10 PM PDT 24
Peak memory 233892 kb
Host smart-42544e8a-20b2-45b5-9059-34326bd84a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65678917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.65678917
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.445412177
Short name T8
Test name
Test status
Simulation time 533152753 ps
CPU time 4.93 seconds
Started May 12 12:50:54 PM PDT 24
Finished May 12 12:51:00 PM PDT 24
Peak memory 233444 kb
Host smart-4ff51e02-c72d-4428-8201-4e5dccfc7efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445412177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.445412177
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3893838745
Short name T107
Test name
Test status
Simulation time 266196479 ps
CPU time 3.69 seconds
Started May 12 12:46:17 PM PDT 24
Finished May 12 12:46:26 PM PDT 24
Peak memory 215704 kb
Host smart-eef8ce5a-6467-46f5-97db-7c189119860b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893838745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3893838745
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2780184993
Short name T1094
Test name
Test status
Simulation time 614844486 ps
CPU time 15.28 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 207460 kb
Host smart-70f7a8de-79a1-4a22-bb4d-35987265e14a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780184993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2780184993
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3977820515
Short name T977
Test name
Test status
Simulation time 7256589060 ps
CPU time 36.69 seconds
Started May 12 12:45:39 PM PDT 24
Finished May 12 12:46:16 PM PDT 24
Peak memory 207504 kb
Host smart-a260b904-663c-4d95-b9fa-b0d0d9cf8855
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977820515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3977820515
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4070498716
Short name T1051
Test name
Test status
Simulation time 128208379 ps
CPU time 3.61 seconds
Started May 12 12:45:50 PM PDT 24
Finished May 12 12:45:55 PM PDT 24
Peak memory 218440 kb
Host smart-6fb2eab7-14fe-44e1-8a26-1204ac9dc6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070498716 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4070498716
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2222079442
Short name T133
Test name
Test status
Simulation time 39913473 ps
CPU time 2.33 seconds
Started May 12 12:46:04 PM PDT 24
Finished May 12 12:46:07 PM PDT 24
Peak memory 215692 kb
Host smart-15fb7d3e-3cf4-47c6-879f-d981bfe29668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222079442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
222079442
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2621863966
Short name T1027
Test name
Test status
Simulation time 25279215 ps
CPU time 0.71 seconds
Started May 12 12:46:33 PM PDT 24
Finished May 12 12:46:35 PM PDT 24
Peak memory 204172 kb
Host smart-3fd97fc4-a1d6-492e-873a-d9e171734eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621863966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
621863966
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2337705798
Short name T1054
Test name
Test status
Simulation time 53214810 ps
CPU time 1.97 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 215728 kb
Host smart-07cbe5fd-b131-445a-b71f-4831e89d948f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337705798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2337705798
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2436780125
Short name T985
Test name
Test status
Simulation time 11382833 ps
CPU time 0.66 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:41 PM PDT 24
Peak memory 203816 kb
Host smart-ce5d7d2f-755c-4932-b875-0b4e0fab7db9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436780125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2436780125
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2786409739
Short name T1083
Test name
Test status
Simulation time 117425714 ps
CPU time 2.65 seconds
Started May 12 12:45:38 PM PDT 24
Finished May 12 12:45:41 PM PDT 24
Peak memory 215916 kb
Host smart-80fe5e1a-596e-4199-b52b-0f5a904e2eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786409739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2786409739
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.482870956
Short name T110
Test name
Test status
Simulation time 472621792 ps
CPU time 3.07 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:52 PM PDT 24
Peak memory 215692 kb
Host smart-1476e7f7-8b0c-4630-9659-6453f8c9ef73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482870956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.482870956
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.154825199
Short name T108
Test name
Test status
Simulation time 289845923 ps
CPU time 18.3 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 216088 kb
Host smart-a587dfc2-b22a-43c1-977c-c3ffbabf492b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154825199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.154825199
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3565338415
Short name T1092
Test name
Test status
Simulation time 1511935934 ps
CPU time 7.62 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 215648 kb
Host smart-52294515-f05e-46a0-bd0e-9714c8b86906
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565338415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3565338415
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3591753465
Short name T991
Test name
Test status
Simulation time 361866818 ps
CPU time 11.43 seconds
Started May 12 12:45:50 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 207488 kb
Host smart-39d57168-0619-4d77-ae65-05b4d633dca4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591753465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3591753465
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2175825939
Short name T96
Test name
Test status
Simulation time 23043650 ps
CPU time 1.37 seconds
Started May 12 12:45:39 PM PDT 24
Finished May 12 12:45:41 PM PDT 24
Peak memory 216688 kb
Host smart-163c7762-1891-4114-83aa-ac8ce0432f4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175825939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2175825939
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3075407250
Short name T161
Test name
Test status
Simulation time 162876754 ps
CPU time 3.73 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:04 PM PDT 24
Peak memory 217048 kb
Host smart-96c3f920-6ea6-4eee-9149-ac9cf785657e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075407250 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3075407250
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3194732089
Short name T1095
Test name
Test status
Simulation time 29005441 ps
CPU time 1.69 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 207576 kb
Host smart-99e7728f-8380-4922-aea7-0b5cb62fae4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194732089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
194732089
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.255695216
Short name T1017
Test name
Test status
Simulation time 52607533 ps
CPU time 0.77 seconds
Started May 12 12:46:20 PM PDT 24
Finished May 12 12:46:21 PM PDT 24
Peak memory 204140 kb
Host smart-0de83a74-1f88-4413-827b-bb8f2f61caa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255695216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.255695216
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2079469404
Short name T1080
Test name
Test status
Simulation time 117905734 ps
CPU time 1.2 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 215644 kb
Host smart-4972f1f7-e896-459c-b166-a76932dd951f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079469404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2079469404
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3571944828
Short name T1069
Test name
Test status
Simulation time 29716450 ps
CPU time 0.67 seconds
Started May 12 12:45:49 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 203828 kb
Host smart-4fa9949f-03c7-4a86-8303-6580d93082c7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571944828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3571944828
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3935039019
Short name T1030
Test name
Test status
Simulation time 167803477 ps
CPU time 2.74 seconds
Started May 12 12:45:54 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 215680 kb
Host smart-fad546cb-3ca8-447f-a4ff-984cf210f206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935039019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3935039019
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3208951503
Short name T113
Test name
Test status
Simulation time 414345496 ps
CPU time 2.59 seconds
Started May 12 12:45:49 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 215948 kb
Host smart-b18e3af5-aaaf-4c48-af0e-1edd54f2552b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208951503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
208951503
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2379995524
Short name T272
Test name
Test status
Simulation time 194496637 ps
CPU time 11.28 seconds
Started May 12 12:45:52 PM PDT 24
Finished May 12 12:46:04 PM PDT 24
Peak memory 222888 kb
Host smart-b65f743b-3ea8-4139-a2d9-728268c022c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379995524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2379995524
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.6133440
Short name T1050
Test name
Test status
Simulation time 194074269 ps
CPU time 1.94 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 216484 kb
Host smart-480806c5-5b5c-4453-b8a5-bbf71826142a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6133440 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.6133440
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3785834457
Short name T1031
Test name
Test status
Simulation time 392399888 ps
CPU time 2.49 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 207448 kb
Host smart-f51b18c4-379f-44bc-931c-7c20513d1434
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785834457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3785834457
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4206558871
Short name T982
Test name
Test status
Simulation time 27838854 ps
CPU time 0.71 seconds
Started May 12 12:46:10 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 204132 kb
Host smart-8869995c-4273-45b8-87e6-83063a3fbea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206558871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4206558871
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2988969645
Short name T988
Test name
Test status
Simulation time 701126502 ps
CPU time 4.06 seconds
Started May 12 12:46:18 PM PDT 24
Finished May 12 12:46:22 PM PDT 24
Peak memory 215652 kb
Host smart-c77fb9ac-299a-4949-8327-fc67129fb9d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988969645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2988969645
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3052049952
Short name T122
Test name
Test status
Simulation time 188103378 ps
CPU time 4.59 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 215836 kb
Host smart-8411ecb0-6f7a-4904-b040-488207709e54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052049952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3052049952
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.925288779
Short name T999
Test name
Test status
Simulation time 411280158 ps
CPU time 12.47 seconds
Started May 12 12:45:53 PM PDT 24
Finished May 12 12:46:06 PM PDT 24
Peak memory 215760 kb
Host smart-23a622c1-663f-451a-ab86-9a43e1438268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925288779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.925288779
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1174776471
Short name T1068
Test name
Test status
Simulation time 133673978 ps
CPU time 1.63 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:46:15 PM PDT 24
Peak memory 215680 kb
Host smart-f776631b-6da5-4ea6-a898-0ec138ffde6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174776471 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1174776471
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3392543495
Short name T1090
Test name
Test status
Simulation time 294844315 ps
CPU time 1.92 seconds
Started May 12 12:45:48 PM PDT 24
Finished May 12 12:45:52 PM PDT 24
Peak memory 207476 kb
Host smart-5630e673-43fa-4dd0-a28d-66eec7156b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392543495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3392543495
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1963883538
Short name T1089
Test name
Test status
Simulation time 23991963 ps
CPU time 0.74 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 12:46:05 PM PDT 24
Peak memory 203876 kb
Host smart-2ff3b4d7-f074-4c33-8762-ca358d64b0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963883538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1963883538
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1194488951
Short name T1037
Test name
Test status
Simulation time 297108977 ps
CPU time 3.75 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 215708 kb
Host smart-89cdf43c-ddd9-4785-997b-e4c540bf28c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194488951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1194488951
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4057703074
Short name T1070
Test name
Test status
Simulation time 57386711 ps
CPU time 2.28 seconds
Started May 12 12:46:08 PM PDT 24
Finished May 12 12:46:11 PM PDT 24
Peak memory 215776 kb
Host smart-571ab80c-5e09-48cd-9099-deba4fd8ecfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057703074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4057703074
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3280717808
Short name T1067
Test name
Test status
Simulation time 200175593 ps
CPU time 12.72 seconds
Started May 12 12:46:01 PM PDT 24
Finished May 12 12:46:15 PM PDT 24
Peak memory 215808 kb
Host smart-f54b8e06-9dd5-49b1-8af2-f58c1cc4db66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280717808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3280717808
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.469098810
Short name T1078
Test name
Test status
Simulation time 217437522 ps
CPU time 3.86 seconds
Started May 12 12:46:07 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 217936 kb
Host smart-ed64028c-566d-467a-af18-8cb338ea3b5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469098810 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.469098810
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1825093447
Short name T127
Test name
Test status
Simulation time 109232071 ps
CPU time 2.6 seconds
Started May 12 12:45:53 PM PDT 24
Finished May 12 12:45:56 PM PDT 24
Peak memory 215668 kb
Host smart-e40c25bf-cf15-494f-8f6d-19777d522746
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825093447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1825093447
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2492200155
Short name T976
Test name
Test status
Simulation time 168739048 ps
CPU time 0.67 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:45:53 PM PDT 24
Peak memory 203748 kb
Host smart-edf6f425-b7e3-492a-8f2d-af45b80f44db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492200155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2492200155
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1363635789
Short name T1062
Test name
Test status
Simulation time 68588999 ps
CPU time 3.97 seconds
Started May 12 12:46:04 PM PDT 24
Finished May 12 12:46:09 PM PDT 24
Peak memory 215640 kb
Host smart-394dd101-a450-4673-b019-a323e5376480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363635789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1363635789
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3361099360
Short name T106
Test name
Test status
Simulation time 94207811 ps
CPU time 1.62 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:46:14 PM PDT 24
Peak memory 215692 kb
Host smart-5d84c841-ac6a-4dc1-b368-9546081fe78b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361099360 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3361099360
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2462466016
Short name T1085
Test name
Test status
Simulation time 81781107 ps
CPU time 1.36 seconds
Started May 12 12:45:49 PM PDT 24
Finished May 12 12:45:52 PM PDT 24
Peak memory 215640 kb
Host smart-56ec6b10-aa7f-4c9f-bba6-d1ce0d382238
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462466016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2462466016
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3475896872
Short name T1014
Test name
Test status
Simulation time 30989227 ps
CPU time 0.7 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:48 PM PDT 24
Peak memory 203592 kb
Host smart-26cf858c-f606-4e92-bb07-0a4754e1cea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475896872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3475896872
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3740536138
Short name T1040
Test name
Test status
Simulation time 152191990 ps
CPU time 4.04 seconds
Started May 12 12:45:52 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 215672 kb
Host smart-756a04c7-3c92-4d0f-9249-08e28451007c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740536138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3740536138
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3841009129
Short name T1035
Test name
Test status
Simulation time 231560748 ps
CPU time 3 seconds
Started May 12 12:45:54 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 215692 kb
Host smart-c0f15bd5-f3b3-480a-9cba-0db24e9fc8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841009129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3841009129
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.454152160
Short name T156
Test name
Test status
Simulation time 1784536806 ps
CPU time 14.11 seconds
Started May 12 12:45:46 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 215560 kb
Host smart-c7730417-8f6e-4d69-abe0-7a14e6125fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454152160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.454152160
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4181885946
Short name T157
Test name
Test status
Simulation time 452135411 ps
CPU time 2.65 seconds
Started May 12 12:45:50 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 217976 kb
Host smart-874231ef-a3e6-4035-a5a5-e4ef55d6afad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181885946 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4181885946
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1394913873
Short name T130
Test name
Test status
Simulation time 120140096 ps
CPU time 2.11 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 215676 kb
Host smart-c337c0ae-0d53-42d3-b0bb-c7cfd3eb6308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394913873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1394913873
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1783488248
Short name T998
Test name
Test status
Simulation time 10700655 ps
CPU time 0.7 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:45:59 PM PDT 24
Peak memory 204128 kb
Host smart-d628815b-6cd1-4e7c-9162-a68e17be1c1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783488248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1783488248
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1741714513
Short name T1033
Test name
Test status
Simulation time 126592560 ps
CPU time 1.73 seconds
Started May 12 12:46:12 PM PDT 24
Finished May 12 12:46:15 PM PDT 24
Peak memory 215764 kb
Host smart-3e838eb7-b363-4603-934f-813740e17bf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741714513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1741714513
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2307001147
Short name T118
Test name
Test status
Simulation time 149341788 ps
CPU time 2.18 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 216720 kb
Host smart-43b78ea0-f93a-4a6e-b184-1f0740bba79e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307001147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2307001147
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3285925204
Short name T1081
Test name
Test status
Simulation time 202145872 ps
CPU time 12.57 seconds
Started May 12 12:45:50 PM PDT 24
Finished May 12 12:46:04 PM PDT 24
Peak memory 215592 kb
Host smart-71cc2f39-116e-421f-9e05-289145b0781f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285925204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3285925204
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.259619078
Short name T1019
Test name
Test status
Simulation time 84288320 ps
CPU time 2.51 seconds
Started May 12 12:46:02 PM PDT 24
Finished May 12 12:46:06 PM PDT 24
Peak memory 216704 kb
Host smart-a7ea3f18-d962-4fbd-9f2f-45c195770fcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259619078 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.259619078
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.524045023
Short name T1063
Test name
Test status
Simulation time 102323770 ps
CPU time 2.72 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:59 PM PDT 24
Peak memory 207368 kb
Host smart-23c13f5f-4698-4a43-8d32-ae04835b2945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524045023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.524045023
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2024412085
Short name T1003
Test name
Test status
Simulation time 32809683 ps
CPU time 0.82 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:46:17 PM PDT 24
Peak memory 203724 kb
Host smart-418ce2af-8239-4147-bc21-db5d7df54cb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024412085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2024412085
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3875914241
Short name T1052
Test name
Test status
Simulation time 55437487 ps
CPU time 3.75 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:46:13 PM PDT 24
Peak memory 215616 kb
Host smart-0b007cbc-1910-4faa-8197-ff8cff529b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875914241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3875914241
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3465968717
Short name T116
Test name
Test status
Simulation time 164402919 ps
CPU time 2.28 seconds
Started May 12 12:46:05 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 215744 kb
Host smart-b0c265ae-8c0a-49c7-9628-c2b33af1809c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465968717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3465968717
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.560076551
Short name T1101
Test name
Test status
Simulation time 342727473 ps
CPU time 7.79 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:55 PM PDT 24
Peak memory 216008 kb
Host smart-adba63c4-e236-4f0b-a769-2441c700641b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560076551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.560076551
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4105422278
Short name T1034
Test name
Test status
Simulation time 537749088 ps
CPU time 2.6 seconds
Started May 12 12:46:09 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 217300 kb
Host smart-e51456e9-efa4-4ed0-b5aa-127d763ced23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105422278 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4105422278
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4211967685
Short name T1043
Test name
Test status
Simulation time 74067231 ps
CPU time 1.47 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 207448 kb
Host smart-d281d0dc-dc2d-4943-b6de-ef204dab66e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211967685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4211967685
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2214305351
Short name T1000
Test name
Test status
Simulation time 36687923 ps
CPU time 0.74 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:45:53 PM PDT 24
Peak memory 204040 kb
Host smart-f7d0c4f2-2acf-4e31-9af4-821de252cd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214305351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2214305351
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2955170994
Short name T1072
Test name
Test status
Simulation time 655466585 ps
CPU time 3.78 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 215700 kb
Host smart-51dc277f-0a02-4215-9009-3c50ddf75c1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955170994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2955170994
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3960697133
Short name T120
Test name
Test status
Simulation time 182290919 ps
CPU time 4.47 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:04 PM PDT 24
Peak memory 215704 kb
Host smart-62156726-50cc-4112-91dc-76d1fe46d400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960697133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3960697133
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2815238178
Short name T1023
Test name
Test status
Simulation time 593122717 ps
CPU time 18.56 seconds
Started May 12 12:46:04 PM PDT 24
Finished May 12 12:46:24 PM PDT 24
Peak memory 223764 kb
Host smart-b471412f-4979-41bd-a3a0-6fb7163afa4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815238178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2815238178
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1644909248
Short name T996
Test name
Test status
Simulation time 23885482 ps
CPU time 1.49 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 215708 kb
Host smart-e3e088c7-df18-4089-820d-3cfebdd39185
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644909248 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1644909248
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3068984274
Short name T1082
Test name
Test status
Simulation time 27373203 ps
CPU time 1.67 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 215628 kb
Host smart-0cd884c6-6577-482c-ae0f-f2822b6f1777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068984274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3068984274
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4251113228
Short name T1045
Test name
Test status
Simulation time 11933797 ps
CPU time 0.74 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:47 PM PDT 24
Peak memory 204060 kb
Host smart-2719c35c-e911-4949-be01-320b9a384841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251113228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4251113228
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.379187383
Short name T993
Test name
Test status
Simulation time 53928756 ps
CPU time 1.69 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 215644 kb
Host smart-4d878a24-0f9e-4ee7-a052-006cb514da5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379187383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.379187383
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2632903236
Short name T1002
Test name
Test status
Simulation time 34213537 ps
CPU time 1.9 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 216472 kb
Host smart-8c7369eb-ee4d-47a6-ab13-12528d94864e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632903236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2632903236
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3728072811
Short name T1093
Test name
Test status
Simulation time 359408773 ps
CPU time 7.76 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 215976 kb
Host smart-f37290f9-e2d7-4333-967f-6c6bfabb7f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728072811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3728072811
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.973555834
Short name T1084
Test name
Test status
Simulation time 207786741 ps
CPU time 1.79 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 215584 kb
Host smart-f0a5a708-5d74-4d04-878f-293c7be7148a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973555834 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.973555834
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3887989234
Short name T1077
Test name
Test status
Simulation time 64813581 ps
CPU time 1.24 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 207448 kb
Host smart-4186a006-b597-42a7-afaa-0efba1674a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887989234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3887989234
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2539834259
Short name T1048
Test name
Test status
Simulation time 199717208 ps
CPU time 0.73 seconds
Started May 12 12:46:07 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 203780 kb
Host smart-e28df860-10e3-4dd8-a21f-ce6d9b039feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539834259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2539834259
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1339577589
Short name T147
Test name
Test status
Simulation time 78453458 ps
CPU time 1.67 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:57 PM PDT 24
Peak memory 207444 kb
Host smart-77e8216f-e4cf-4a2c-a7cc-ac4d95ecd9d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339577589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1339577589
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1983950795
Short name T273
Test name
Test status
Simulation time 285726557 ps
CPU time 18.07 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:46:46 PM PDT 24
Peak memory 215528 kb
Host smart-588f7372-a5bc-4f79-98f3-b5e3fae97784
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983950795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1983950795
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.306539619
Short name T1055
Test name
Test status
Simulation time 222181626 ps
CPU time 2.81 seconds
Started May 12 12:46:13 PM PDT 24
Finished May 12 12:46:17 PM PDT 24
Peak memory 217192 kb
Host smart-e4b34402-30c7-484a-9e5d-4a8354782a20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306539619 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.306539619
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3954411153
Short name T128
Test name
Test status
Simulation time 74347610 ps
CPU time 1.95 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 215256 kb
Host smart-ba0b96f9-2ac7-4453-ab33-9505cb3044be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954411153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3954411153
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1204561735
Short name T1025
Test name
Test status
Simulation time 12402872 ps
CPU time 0.77 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:48 PM PDT 24
Peak memory 203628 kb
Host smart-13ad003b-ec91-4b31-82d8-0c3c06ce99df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204561735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1204561735
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1250481133
Short name T1036
Test name
Test status
Simulation time 163596568 ps
CPU time 4.08 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:47 PM PDT 24
Peak memory 215576 kb
Host smart-e9c2a2b9-775d-46d7-a6eb-202e1d4ebe55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250481133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1250481133
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1785338250
Short name T123
Test name
Test status
Simulation time 461193094 ps
CPU time 3.36 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 216480 kb
Host smart-2aa1a010-98cc-44fa-b8fc-fd2fa22e56ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785338250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1785338250
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1008497694
Short name T112
Test name
Test status
Simulation time 2064515861 ps
CPU time 12.07 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 12:46:17 PM PDT 24
Peak memory 216372 kb
Host smart-ddb2214e-9780-44b1-aa17-e437f566f17a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008497694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1008497694
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3874626587
Short name T125
Test name
Test status
Simulation time 2757425498 ps
CPU time 15.9 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 215584 kb
Host smart-875dd8aa-311d-499f-a4ed-edac8244f484
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874626587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3874626587
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1030527113
Short name T136
Test name
Test status
Simulation time 7213712106 ps
CPU time 25.83 seconds
Started May 12 12:45:59 PM PDT 24
Finished May 12 12:46:26 PM PDT 24
Peak memory 207668 kb
Host smart-58687e05-3973-4c06-a6ca-db16a815d5e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030527113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1030527113
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.154200119
Short name T95
Test name
Test status
Simulation time 34427318 ps
CPU time 1.17 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:46 PM PDT 24
Peak memory 207424 kb
Host smart-c2ad8c45-d0a8-4d51-9b51-dfd20dadbd80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154200119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.154200119
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.366218046
Short name T109
Test name
Test status
Simulation time 44263264 ps
CPU time 2.85 seconds
Started May 12 12:45:38 PM PDT 24
Finished May 12 12:45:42 PM PDT 24
Peak memory 217392 kb
Host smart-cb9982ce-31f3-48e3-8b4b-9a628fe8b6b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366218046 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.366218046
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3933743759
Short name T1015
Test name
Test status
Simulation time 99116968 ps
CPU time 1.26 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 207592 kb
Host smart-2d7d56cd-49ea-46f6-ac3f-bf354fa9b9cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933743759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
933743759
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2921658142
Short name T1021
Test name
Test status
Simulation time 18417878 ps
CPU time 0.73 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 203792 kb
Host smart-e0160234-fa0d-43a0-8c1f-0ab82a27661f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921658142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
921658142
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.199218641
Short name T131
Test name
Test status
Simulation time 24414250 ps
CPU time 1.66 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:48 PM PDT 24
Peak memory 215612 kb
Host smart-c03fd051-f3fc-4e75-a637-d16e788d777f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199218641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.199218641
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3296999745
Short name T1001
Test name
Test status
Simulation time 26901913 ps
CPU time 0.65 seconds
Started May 12 12:45:39 PM PDT 24
Finished May 12 12:45:41 PM PDT 24
Peak memory 203780 kb
Host smart-046f2494-ca63-40c6-8a52-e3feabcd040b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296999745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3296999745
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1559304727
Short name T1057
Test name
Test status
Simulation time 639900922 ps
CPU time 4.19 seconds
Started May 12 12:46:24 PM PDT 24
Finished May 12 12:46:29 PM PDT 24
Peak memory 215576 kb
Host smart-31866390-c79c-4e83-9d40-7db9259a46af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559304727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1559304727
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1162844053
Short name T117
Test name
Test status
Simulation time 1360434681 ps
CPU time 2.93 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 218324 kb
Host smart-2c5f9e85-384a-4400-9f8a-b1c7aa01d010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162844053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
162844053
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.24057730
Short name T271
Test name
Test status
Simulation time 294098132 ps
CPU time 7.63 seconds
Started May 12 12:46:05 PM PDT 24
Finished May 12 12:46:13 PM PDT 24
Peak memory 215696 kb
Host smart-c47db20e-3707-4ea3-80aa-88c2a00b180a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_t
l_intg_err.24057730
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3562704996
Short name T1064
Test name
Test status
Simulation time 20437919 ps
CPU time 0.7 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 203728 kb
Host smart-bf1f0c5a-70fa-4060-8aac-db5a607d1ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562704996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3562704996
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2380571562
Short name T1011
Test name
Test status
Simulation time 26509382 ps
CPU time 0.72 seconds
Started May 12 12:46:08 PM PDT 24
Finished May 12 12:46:09 PM PDT 24
Peak memory 203844 kb
Host smart-53f5e4a7-302e-4603-af96-831d1e6d7ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380571562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2380571562
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1815189819
Short name T1096
Test name
Test status
Simulation time 23722967 ps
CPU time 0.69 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 203824 kb
Host smart-f8791843-8b36-4237-8f72-ffa1bd3184bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815189819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1815189819
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1700374710
Short name T989
Test name
Test status
Simulation time 37179613 ps
CPU time 0.68 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 204036 kb
Host smart-83240875-11bb-4303-be47-973dbcde94fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700374710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1700374710
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2485039160
Short name T1088
Test name
Test status
Simulation time 20786420 ps
CPU time 0.69 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 203728 kb
Host smart-1f390aab-b522-4f4f-b415-c90ae88998c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485039160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2485039160
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.18062079
Short name T978
Test name
Test status
Simulation time 18707277 ps
CPU time 0.68 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:46:15 PM PDT 24
Peak memory 204104 kb
Host smart-aca89b8b-29c3-4231-943e-2c8d99bea9a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.18062079
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2114994976
Short name T1049
Test name
Test status
Simulation time 38424088 ps
CPU time 0.7 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 204052 kb
Host smart-dfc27da0-9391-4b1b-a42b-59320e14daa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114994976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2114994976
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3298682451
Short name T975
Test name
Test status
Simulation time 25029123 ps
CPU time 0.69 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 203908 kb
Host smart-dee6ce1f-f34d-49a6-96d3-cd8e54521f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298682451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3298682451
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2101188112
Short name T1047
Test name
Test status
Simulation time 31872185 ps
CPU time 0.66 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 204036 kb
Host smart-a07fba09-8264-4737-a023-c8fd2c729f3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101188112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2101188112
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1441782057
Short name T1010
Test name
Test status
Simulation time 12967010 ps
CPU time 0.69 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:42 PM PDT 24
Peak memory 203704 kb
Host smart-9b09f9fd-74ce-464c-b320-d7cc97c6f084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441782057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1441782057
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.313076902
Short name T126
Test name
Test status
Simulation time 541924139 ps
CPU time 20.45 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 215728 kb
Host smart-fcadab55-76da-439f-b5e7-deaf2d7bb0e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313076902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.313076902
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3313828116
Short name T1053
Test name
Test status
Simulation time 10792334949 ps
CPU time 38.55 seconds
Started May 12 12:45:54 PM PDT 24
Finished May 12 12:46:34 PM PDT 24
Peak memory 215616 kb
Host smart-abec5b8e-3026-4049-9919-53a5eb64e4d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313828116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3313828116
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2642181460
Short name T93
Test name
Test status
Simulation time 17066636 ps
CPU time 0.94 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 207200 kb
Host smart-854ba7a2-06ee-43ab-83a3-a3f5f62da058
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642181460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2642181460
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1517283057
Short name T159
Test name
Test status
Simulation time 121158485 ps
CPU time 2.81 seconds
Started May 12 12:45:52 PM PDT 24
Finished May 12 12:45:57 PM PDT 24
Peak memory 216940 kb
Host smart-33a03c75-c7dd-4640-88d5-223c7de4b2cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517283057 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1517283057
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3583045562
Short name T132
Test name
Test status
Simulation time 85003260 ps
CPU time 1.32 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:43 PM PDT 24
Peak memory 215940 kb
Host smart-b0ac4280-0367-45c7-95af-e75cf2a7b43f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583045562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
583045562
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3073455661
Short name T1012
Test name
Test status
Simulation time 28787188 ps
CPU time 0.68 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:45:56 PM PDT 24
Peak memory 203696 kb
Host smart-7d5312f3-3592-4422-b239-f9dae2597cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073455661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
073455661
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2083922667
Short name T1100
Test name
Test status
Simulation time 52032558 ps
CPU time 1.73 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:47 PM PDT 24
Peak memory 215548 kb
Host smart-0e698981-adfc-4b2b-a0d1-331a4f491769
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083922667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2083922667
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2060955827
Short name T983
Test name
Test status
Simulation time 14739265 ps
CPU time 0.65 seconds
Started May 12 12:45:51 PM PDT 24
Finished May 12 12:45:53 PM PDT 24
Peak memory 204044 kb
Host smart-78dadd27-5288-4b63-805e-c1d1cb714152
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060955827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2060955827
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2009226635
Short name T1098
Test name
Test status
Simulation time 290257995 ps
CPU time 1.8 seconds
Started May 12 12:45:53 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 215492 kb
Host smart-0d450413-5cc2-46de-a21d-d577b1b66b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009226635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2009226635
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.967397755
Short name T1041
Test name
Test status
Simulation time 249164180 ps
CPU time 2.79 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 215716 kb
Host smart-f3cc33ea-a5a1-495b-9fcb-8949eb9d79ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967397755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.967397755
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3400166405
Short name T269
Test name
Test status
Simulation time 203168527 ps
CPU time 12.53 seconds
Started May 12 12:45:46 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 215668 kb
Host smart-824caa6c-44e6-4abf-b1bb-47bf5dad9f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400166405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3400166405
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3189481629
Short name T994
Test name
Test status
Simulation time 13965391 ps
CPU time 0.74 seconds
Started May 12 12:46:11 PM PDT 24
Finished May 12 12:46:12 PM PDT 24
Peak memory 203700 kb
Host smart-9bf47058-6c30-4ef0-9e82-5c9d3fe730e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189481629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3189481629
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3164283994
Short name T980
Test name
Test status
Simulation time 43917613 ps
CPU time 0.7 seconds
Started May 12 12:46:06 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 204136 kb
Host smart-5818f752-258a-4a6e-9c83-fdebbc5c0376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164283994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3164283994
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3135995245
Short name T981
Test name
Test status
Simulation time 13778996 ps
CPU time 0.68 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 203720 kb
Host smart-375d7aa5-2be1-41b3-a4c7-d4011edf7250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135995245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3135995245
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4280712465
Short name T995
Test name
Test status
Simulation time 19559911 ps
CPU time 0.75 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 203820 kb
Host smart-97b81e48-7963-43a5-a119-40ff13fc73d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280712465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4280712465
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.94885950
Short name T987
Test name
Test status
Simulation time 14164131 ps
CPU time 0.71 seconds
Started May 12 12:46:07 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 203920 kb
Host smart-fdde383f-4c6c-4d28-a02f-32f1c904f89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94885950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.94885950
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1683521153
Short name T1029
Test name
Test status
Simulation time 12941205 ps
CPU time 0.68 seconds
Started May 12 12:45:38 PM PDT 24
Finished May 12 12:45:39 PM PDT 24
Peak memory 203760 kb
Host smart-09a908ed-8ac7-4f9b-9dc6-ed76d5405ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683521153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1683521153
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2782609618
Short name T1013
Test name
Test status
Simulation time 44086067 ps
CPU time 0.73 seconds
Started May 12 12:46:28 PM PDT 24
Finished May 12 12:46:29 PM PDT 24
Peak memory 204152 kb
Host smart-a86e8f73-154c-4040-8268-c012065fba35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782609618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2782609618
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.912998172
Short name T1022
Test name
Test status
Simulation time 16686046 ps
CPU time 0.73 seconds
Started May 12 12:46:06 PM PDT 24
Finished May 12 12:46:07 PM PDT 24
Peak memory 203788 kb
Host smart-9cf62ca0-27b5-4cc8-8ddf-e9425f9ae71f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912998172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.912998172
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.967940697
Short name T1009
Test name
Test status
Simulation time 46293977 ps
CPU time 0.75 seconds
Started May 12 12:46:14 PM PDT 24
Finished May 12 12:46:15 PM PDT 24
Peak memory 203852 kb
Host smart-387546f0-04b7-4aaa-94eb-b07ca076e8c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967940697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.967940697
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.783422512
Short name T1018
Test name
Test status
Simulation time 35650714 ps
CPU time 0.73 seconds
Started May 12 12:46:22 PM PDT 24
Finished May 12 12:46:23 PM PDT 24
Peak memory 203820 kb
Host smart-50cdc5b8-4849-4fdc-b5bf-be78bd0d68fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783422512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.783422512
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1390217640
Short name T135
Test name
Test status
Simulation time 1309115096 ps
CPU time 21.92 seconds
Started May 12 12:46:01 PM PDT 24
Finished May 12 12:46:24 PM PDT 24
Peak memory 215688 kb
Host smart-24c932a6-af18-4376-8319-ce5718ab7c1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390217640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1390217640
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1519846445
Short name T134
Test name
Test status
Simulation time 366718283 ps
CPU time 21.55 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:46:20 PM PDT 24
Peak memory 207376 kb
Host smart-f50c9157-1c04-4ec1-9607-5f4c13e95a9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519846445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1519846445
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2594363214
Short name T1071
Test name
Test status
Simulation time 52140400 ps
CPU time 0.96 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 207124 kb
Host smart-206b8a3a-d1d5-4698-bb68-45f063e1f532
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594363214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2594363214
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2760944265
Short name T1006
Test name
Test status
Simulation time 149851818 ps
CPU time 2.45 seconds
Started May 12 12:45:52 PM PDT 24
Finished May 12 12:45:56 PM PDT 24
Peak memory 216712 kb
Host smart-918c14f4-2af4-4fcd-b2ea-d40e7b0cd8c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760944265 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2760944265
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3680964408
Short name T1005
Test name
Test status
Simulation time 22904548 ps
CPU time 1.41 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:46 PM PDT 24
Peak memory 207328 kb
Host smart-f36b31f4-5835-48d7-a30f-6a3d4f985ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680964408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
680964408
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.69475125
Short name T1044
Test name
Test status
Simulation time 76298291 ps
CPU time 0.69 seconds
Started May 12 12:45:52 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 204176 kb
Host smart-e122389b-5a9d-47b4-9136-2b8450eb38f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69475125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.69475125
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1627481952
Short name T1065
Test name
Test status
Simulation time 92422744 ps
CPU time 1.87 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 215684 kb
Host smart-8c8c118f-a5da-457b-b33f-7445f4642cec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627481952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1627481952
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3673000192
Short name T1058
Test name
Test status
Simulation time 12942908 ps
CPU time 0.64 seconds
Started May 12 12:45:48 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 203624 kb
Host smart-a9547f3b-bb5e-46d6-9947-9a71b456ebf7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673000192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3673000192
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3040888535
Short name T146
Test name
Test status
Simulation time 248307906 ps
CPU time 3.77 seconds
Started May 12 12:45:49 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 215672 kb
Host smart-c52e78c5-0fb7-4d60-9f0f-077b3f21c205
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040888535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3040888535
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.687073776
Short name T1086
Test name
Test status
Simulation time 144592141 ps
CPU time 1.8 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 215632 kb
Host smart-fb623f93-5ca4-4453-ac1a-18c8376d84a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687073776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.687073776
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2138220547
Short name T1007
Test name
Test status
Simulation time 30682407 ps
CPU time 0.69 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:46:29 PM PDT 24
Peak memory 203676 kb
Host smart-adac137a-4568-410d-9826-29c3ba658774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138220547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2138220547
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3934895838
Short name T997
Test name
Test status
Simulation time 62581552 ps
CPU time 0.72 seconds
Started May 12 12:46:06 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 204064 kb
Host smart-e96f869d-bcb9-4520-b136-9b2d3b188d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934895838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3934895838
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3973005179
Short name T1026
Test name
Test status
Simulation time 13960449 ps
CPU time 0.71 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:45:58 PM PDT 24
Peak memory 203748 kb
Host smart-7d2d7849-1126-462e-a249-649c30349393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973005179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3973005179
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4033728993
Short name T986
Test name
Test status
Simulation time 51206629 ps
CPU time 0.68 seconds
Started May 12 12:46:21 PM PDT 24
Finished May 12 12:46:22 PM PDT 24
Peak memory 203868 kb
Host smart-54db5261-fd61-4fc1-b3d1-12534d245273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033728993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4033728993
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.939570449
Short name T1074
Test name
Test status
Simulation time 15252206 ps
CPU time 0.76 seconds
Started May 12 12:45:37 PM PDT 24
Finished May 12 12:45:39 PM PDT 24
Peak memory 203872 kb
Host smart-3fe19ea9-771b-412b-870d-44645202cdfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939570449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.939570449
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.770581706
Short name T1028
Test name
Test status
Simulation time 42659776 ps
CPU time 0.67 seconds
Started May 12 12:46:15 PM PDT 24
Finished May 12 12:46:16 PM PDT 24
Peak memory 204104 kb
Host smart-66d85bd0-7854-4427-941e-74f31599f219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770581706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.770581706
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2433805266
Short name T979
Test name
Test status
Simulation time 16137408 ps
CPU time 0.73 seconds
Started May 12 12:45:57 PM PDT 24
Finished May 12 12:45:59 PM PDT 24
Peak memory 204124 kb
Host smart-0d7cb698-2ffb-4edf-b381-24ae5817ec72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433805266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2433805266
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2761818399
Short name T1046
Test name
Test status
Simulation time 55310932 ps
CPU time 0.72 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 203860 kb
Host smart-77e48f50-7d38-4945-a0da-6bb41e10e5b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761818399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2761818399
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1315247548
Short name T990
Test name
Test status
Simulation time 18219389 ps
CPU time 0.73 seconds
Started May 12 12:45:42 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 203784 kb
Host smart-837bbfd9-14cb-4513-807f-061496b77620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315247548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1315247548
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1297036512
Short name T1008
Test name
Test status
Simulation time 50392893 ps
CPU time 0.79 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:45:46 PM PDT 24
Peak memory 203772 kb
Host smart-2039c90d-a2c7-405a-8f1b-b3238d28330d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297036512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1297036512
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1852699552
Short name T1039
Test name
Test status
Simulation time 272934966 ps
CPU time 2.69 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 217292 kb
Host smart-892c0141-4ae3-4d65-b1ed-9eb9057022d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852699552 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1852699552
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3039174990
Short name T1091
Test name
Test status
Simulation time 37337408 ps
CPU time 1.17 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:45:47 PM PDT 24
Peak memory 207224 kb
Host smart-19ba2858-0b19-44ea-9386-5eaed74c5860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039174990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
039174990
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1563790316
Short name T1032
Test name
Test status
Simulation time 44928983 ps
CPU time 0.69 seconds
Started May 12 12:46:27 PM PDT 24
Finished May 12 12:46:29 PM PDT 24
Peak memory 203676 kb
Host smart-961dc37b-d8ad-4691-9e54-55a007403604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563790316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
563790316
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.717560790
Short name T1059
Test name
Test status
Simulation time 185448400 ps
CPU time 3.99 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:03 PM PDT 24
Peak memory 215504 kb
Host smart-62e57710-19b2-4ad9-be6a-7611327de28d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717560790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.717560790
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2828172380
Short name T1056
Test name
Test status
Simulation time 362402325 ps
CPU time 6.62 seconds
Started May 12 12:46:23 PM PDT 24
Finished May 12 12:46:30 PM PDT 24
Peak memory 215900 kb
Host smart-f4e28228-1b44-4697-b8ab-1a84a432ff6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828172380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2828172380
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1494617559
Short name T129
Test name
Test status
Simulation time 545092117 ps
CPU time 1.88 seconds
Started May 12 12:45:54 PM PDT 24
Finished May 12 12:45:57 PM PDT 24
Peak memory 215708 kb
Host smart-302cdfad-0326-4478-a929-8c1b174aed88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494617559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
494617559
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3969119797
Short name T1060
Test name
Test status
Simulation time 12971963 ps
CPU time 0.67 seconds
Started May 12 12:45:45 PM PDT 24
Finished May 12 12:45:49 PM PDT 24
Peak memory 203728 kb
Host smart-69d60c6e-8c75-4f51-bec8-256e0ba42666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969119797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
969119797
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.595244614
Short name T1075
Test name
Test status
Simulation time 109023211 ps
CPU time 2.79 seconds
Started May 12 12:45:50 PM PDT 24
Finished May 12 12:45:54 PM PDT 24
Peak memory 215432 kb
Host smart-f97d1db4-9aab-4e3d-9789-d47f26c8788f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595244614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.595244614
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2261236891
Short name T1079
Test name
Test status
Simulation time 113971463 ps
CPU time 2.84 seconds
Started May 12 12:45:39 PM PDT 24
Finished May 12 12:45:42 PM PDT 24
Peak memory 215772 kb
Host smart-f99f9a14-ee67-446d-b7c6-de16b32249eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261236891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
261236891
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2722317899
Short name T111
Test name
Test status
Simulation time 1135039215 ps
CPU time 7.9 seconds
Started May 12 12:45:46 PM PDT 24
Finished May 12 12:45:56 PM PDT 24
Peak memory 215632 kb
Host smart-7aa3827f-0de6-4522-a513-c577f1311b52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722317899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2722317899
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1508487102
Short name T1024
Test name
Test status
Simulation time 308687617 ps
CPU time 1.54 seconds
Started May 12 12:45:58 PM PDT 24
Finished May 12 12:46:01 PM PDT 24
Peak memory 215612 kb
Host smart-c04cf19a-0646-4ff1-a3d8-a846c9842f84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508487102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1508487102
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3091620386
Short name T1016
Test name
Test status
Simulation time 66697708 ps
CPU time 1.27 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:45:46 PM PDT 24
Peak memory 207416 kb
Host smart-26add644-1dd7-42da-aea4-6448a92fe8b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091620386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
091620386
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2173265117
Short name T1038
Test name
Test status
Simulation time 70065472 ps
CPU time 0.76 seconds
Started May 12 12:46:06 PM PDT 24
Finished May 12 12:46:07 PM PDT 24
Peak memory 204088 kb
Host smart-67688144-a080-4876-a885-e5973faec8ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173265117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
173265117
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2132182838
Short name T1061
Test name
Test status
Simulation time 191996727 ps
CPU time 3.93 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 215700 kb
Host smart-ee33cc36-8e23-46be-b5ea-657506e2b951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132182838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2132182838
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1657522373
Short name T1020
Test name
Test status
Simulation time 99558117 ps
CPU time 3.71 seconds
Started May 12 12:45:55 PM PDT 24
Finished May 12 12:46:00 PM PDT 24
Peak memory 215664 kb
Host smart-4b0806de-1f8f-41fe-8bb8-e9ec7b9f1bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657522373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
657522373
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.917150406
Short name T155
Test name
Test status
Simulation time 682503475 ps
CPU time 15.75 seconds
Started May 12 12:46:00 PM PDT 24
Finished May 12 12:46:17 PM PDT 24
Peak memory 215800 kb
Host smart-55071392-8de7-44f8-b9cb-1d28630223ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917150406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.917150406
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1638744382
Short name T1087
Test name
Test status
Simulation time 144243061 ps
CPU time 3.45 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:45 PM PDT 24
Peak memory 218108 kb
Host smart-f1c0976b-2f54-4af1-89ad-41553652ded3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638744382 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1638744382
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1071293668
Short name T162
Test name
Test status
Simulation time 52120551 ps
CPU time 1.41 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:45:47 PM PDT 24
Peak memory 207408 kb
Host smart-4c696cb3-1ad1-4b29-a292-614165f56a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071293668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
071293668
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.502494442
Short name T1073
Test name
Test status
Simulation time 13914454 ps
CPU time 0.71 seconds
Started May 12 12:45:43 PM PDT 24
Finished May 12 12:45:46 PM PDT 24
Peak memory 204116 kb
Host smart-f9cef380-7a5c-4508-a520-230f8a412d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502494442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.502494442
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1462922749
Short name T1004
Test name
Test status
Simulation time 160432629 ps
CPU time 3.87 seconds
Started May 12 12:46:03 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 215528 kb
Host smart-329cdcd8-915c-43e2-a0f8-abf4c1dc651c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462922749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1462922749
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2121717145
Short name T1099
Test name
Test status
Simulation time 275170044 ps
CPU time 1.91 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:52 PM PDT 24
Peak memory 215772 kb
Host smart-7592d9d4-f4b9-4e31-a4b0-8da6418c7a44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121717145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
121717145
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3880398600
Short name T160
Test name
Test status
Simulation time 713188680 ps
CPU time 8.05 seconds
Started May 12 12:45:44 PM PDT 24
Finished May 12 12:45:55 PM PDT 24
Peak memory 216192 kb
Host smart-4373f69f-6f76-44ca-b7bf-3016ad305792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880398600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3880398600
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.937628563
Short name T984
Test name
Test status
Simulation time 516262123 ps
CPU time 2.52 seconds
Started May 12 12:45:40 PM PDT 24
Finished May 12 12:45:44 PM PDT 24
Peak memory 216544 kb
Host smart-421b7e72-fad9-4654-9e30-1edbc1b1472e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937628563 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.937628563
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1567096196
Short name T1076
Test name
Test status
Simulation time 215793420 ps
CPU time 1.83 seconds
Started May 12 12:45:41 PM PDT 24
Finished May 12 12:45:45 PM PDT 24
Peak memory 207224 kb
Host smart-42ff43e4-b324-4731-ae74-8dbdf269d2d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567096196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
567096196
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3967888287
Short name T992
Test name
Test status
Simulation time 53273681 ps
CPU time 0.69 seconds
Started May 12 12:45:47 PM PDT 24
Finished May 12 12:45:50 PM PDT 24
Peak memory 203948 kb
Host smart-3ae4153b-dcfc-4a73-9b4c-75abea872186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967888287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
967888287
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1059320050
Short name T1097
Test name
Test status
Simulation time 551298533 ps
CPU time 2.82 seconds
Started May 12 12:46:04 PM PDT 24
Finished May 12 12:46:08 PM PDT 24
Peak memory 215632 kb
Host smart-fd5d6d4b-95d8-4c90-80c6-5745f12a6a48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059320050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1059320050
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2407271703
Short name T1042
Test name
Test status
Simulation time 126052588 ps
CPU time 2.18 seconds
Started May 12 12:45:46 PM PDT 24
Finished May 12 12:45:51 PM PDT 24
Peak memory 215712 kb
Host smart-4484040f-ba31-49b0-99e9-528e3bdf6c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407271703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
407271703
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1998676456
Short name T1066
Test name
Test status
Simulation time 1094424699 ps
CPU time 7.41 seconds
Started May 12 12:45:56 PM PDT 24
Finished May 12 12:46:05 PM PDT 24
Peak memory 215944 kb
Host smart-dc38c0a1-eeb7-4a2d-a8be-4f64d17a07a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998676456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1998676456
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3056162173
Short name T689
Test name
Test status
Simulation time 23494746 ps
CPU time 0.73 seconds
Started May 12 12:51:03 PM PDT 24
Finished May 12 12:51:04 PM PDT 24
Peak memory 205620 kb
Host smart-ddc31f8f-59a3-42b0-884e-81252b94a64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056162173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
056162173
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.58754414
Short name T620
Test name
Test status
Simulation time 321195957 ps
CPU time 2.18 seconds
Started May 12 12:51:02 PM PDT 24
Finished May 12 12:51:05 PM PDT 24
Peak memory 218452 kb
Host smart-89dc02f5-4567-427b-8133-3bcc7a21f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58754414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.58754414
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1779543167
Short name T738
Test name
Test status
Simulation time 15201512 ps
CPU time 0.83 seconds
Started May 12 12:50:49 PM PDT 24
Finished May 12 12:50:51 PM PDT 24
Peak memory 206340 kb
Host smart-fcad43cc-ed97-4a76-b197-726996b30068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779543167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1779543167
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2308202337
Short name T769
Test name
Test status
Simulation time 116082532996 ps
CPU time 88.53 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:52:34 PM PDT 24
Peak memory 238452 kb
Host smart-89834f22-6da1-4a3a-a292-fcd421f61cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308202337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2308202337
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4048878492
Short name T514
Test name
Test status
Simulation time 9666103005 ps
CPU time 44.24 seconds
Started May 12 12:50:59 PM PDT 24
Finished May 12 12:51:44 PM PDT 24
Peak memory 241568 kb
Host smart-d462d87c-d39a-40df-a82b-d8b5bb0dc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048878492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4048878492
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2480004095
Short name T481
Test name
Test status
Simulation time 28549020669 ps
CPU time 84.35 seconds
Started May 12 12:50:54 PM PDT 24
Finished May 12 12:52:19 PM PDT 24
Peak memory 241164 kb
Host smart-aa23a2f1-9d23-482a-8c3c-15f26c586a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480004095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2480004095
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1284761256
Short name T893
Test name
Test status
Simulation time 82558018 ps
CPU time 3 seconds
Started May 12 12:50:48 PM PDT 24
Finished May 12 12:50:52 PM PDT 24
Peak memory 224372 kb
Host smart-2f2fea1a-2444-4382-ac95-479733b3a909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284761256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1284761256
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2854654457
Short name T787
Test name
Test status
Simulation time 31999508 ps
CPU time 2.24 seconds
Started May 12 12:50:49 PM PDT 24
Finished May 12 12:50:52 PM PDT 24
Peak memory 221524 kb
Host smart-30f24f83-ebf5-4e54-b902-a650f1a96dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854654457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2854654457
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3475437137
Short name T507
Test name
Test status
Simulation time 28920188150 ps
CPU time 34.07 seconds
Started May 12 12:50:49 PM PDT 24
Finished May 12 12:51:24 PM PDT 24
Peak memory 233852 kb
Host smart-125f4c6a-4b34-4224-a7fc-b6a13e926617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475437137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3475437137
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3962842679
Short name T390
Test name
Test status
Simulation time 37728830 ps
CPU time 1.12 seconds
Started May 12 12:50:44 PM PDT 24
Finished May 12 12:50:46 PM PDT 24
Peak memory 216744 kb
Host smart-b358a9f3-3fe3-40ed-b951-2a82c3abf0d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962842679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3962842679
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1796820957
Short name T358
Test name
Test status
Simulation time 3590383805 ps
CPU time 4.71 seconds
Started May 12 12:50:54 PM PDT 24
Finished May 12 12:51:00 PM PDT 24
Peak memory 222456 kb
Host smart-406456f7-35cb-4933-b1cd-affa144c7139
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1796820957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1796820957
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2263242768
Short name T785
Test name
Test status
Simulation time 39974047558 ps
CPU time 349.8 seconds
Started May 12 12:50:49 PM PDT 24
Finished May 12 12:56:40 PM PDT 24
Peak memory 250464 kb
Host smart-80a09ced-ddeb-4c19-85a6-0802b9704868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263242768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2263242768
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2029313714
Short name T852
Test name
Test status
Simulation time 11623298 ps
CPU time 0.76 seconds
Started May 12 12:50:49 PM PDT 24
Finished May 12 12:50:50 PM PDT 24
Peak memory 205484 kb
Host smart-1646fb71-399c-43f3-8ea0-c8a44bc1a628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029313714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2029313714
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.939799103
Short name T672
Test name
Test status
Simulation time 5024489558 ps
CPU time 14.96 seconds
Started May 12 12:50:50 PM PDT 24
Finished May 12 12:51:06 PM PDT 24
Peak memory 216400 kb
Host smart-3f78fdc6-d6b2-42b4-8f63-75319b01f9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939799103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.939799103
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4126064852
Short name T51
Test name
Test status
Simulation time 118534841 ps
CPU time 1.48 seconds
Started May 12 12:50:59 PM PDT 24
Finished May 12 12:51:01 PM PDT 24
Peak memory 216368 kb
Host smart-4f289942-5b06-44be-8753-2ad268434e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126064852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4126064852
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1403988479
Short name T426
Test name
Test status
Simulation time 43501121 ps
CPU time 0.72 seconds
Started May 12 12:50:55 PM PDT 24
Finished May 12 12:50:57 PM PDT 24
Peak memory 205700 kb
Host smart-c931c34b-a4b0-4f89-bc04-d035034ee735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403988479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1403988479
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3162561835
Short name T504
Test name
Test status
Simulation time 3976909677 ps
CPU time 9.06 seconds
Started May 12 12:51:09 PM PDT 24
Finished May 12 12:51:19 PM PDT 24
Peak memory 224076 kb
Host smart-6a226c7a-aaeb-4d9c-9cf1-e32ad0133e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162561835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3162561835
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.954957033
Short name T908
Test name
Test status
Simulation time 36052573 ps
CPU time 2.5 seconds
Started May 12 12:50:52 PM PDT 24
Finished May 12 12:50:56 PM PDT 24
Peak memory 234372 kb
Host smart-2f9a4563-9b61-419c-8afc-7caacf88b5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954957033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.954957033
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4209286432
Short name T962
Test name
Test status
Simulation time 56121733 ps
CPU time 0.84 seconds
Started May 12 12:51:01 PM PDT 24
Finished May 12 12:51:02 PM PDT 24
Peak memory 206412 kb
Host smart-a0516db1-db8b-4e91-888e-8e405e8a2060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209286432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4209286432
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3689844277
Short name T462
Test name
Test status
Simulation time 10039580445 ps
CPU time 45.21 seconds
Started May 12 12:51:14 PM PDT 24
Finished May 12 12:52:01 PM PDT 24
Peak memory 249152 kb
Host smart-bbcf88e1-053d-488b-89b7-dbc02eae6709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689844277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3689844277
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2322535207
Short name T143
Test name
Test status
Simulation time 45664333850 ps
CPU time 206.2 seconds
Started May 12 12:50:53 PM PDT 24
Finished May 12 12:54:20 PM PDT 24
Peak memory 271992 kb
Host smart-f52d4bbb-e364-4856-b537-c57330388a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322535207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2322535207
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2338254415
Short name T141
Test name
Test status
Simulation time 65368913547 ps
CPU time 267.63 seconds
Started May 12 12:50:58 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 257488 kb
Host smart-5bbeaa36-c223-4e01-a375-a1c53076b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338254415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2338254415
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.712478760
Short name T384
Test name
Test status
Simulation time 112042736 ps
CPU time 3.4 seconds
Started May 12 12:51:07 PM PDT 24
Finished May 12 12:51:11 PM PDT 24
Peak memory 233040 kb
Host smart-9da18a9e-eea3-407a-b310-ba7032afca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712478760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.712478760
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2772432205
Short name T297
Test name
Test status
Simulation time 975220197 ps
CPU time 5.99 seconds
Started May 12 12:50:51 PM PDT 24
Finished May 12 12:50:57 PM PDT 24
Peak memory 237464 kb
Host smart-03604ecf-a641-4419-a564-9b67dccf48f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772432205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2772432205
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4247451625
Short name T838
Test name
Test status
Simulation time 263611186 ps
CPU time 1.04 seconds
Started May 12 12:51:08 PM PDT 24
Finished May 12 12:51:09 PM PDT 24
Peak memory 217976 kb
Host smart-88006040-d245-49ea-b583-0fad5b0cc439
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247451625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4247451625
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3418432011
Short name T42
Test name
Test status
Simulation time 1920885160 ps
CPU time 6.74 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:19 PM PDT 24
Peak memory 218720 kb
Host smart-3df0e81b-ef4b-4e67-a66f-2f2e5758ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418432011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3418432011
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2827284600
Short name T870
Test name
Test status
Simulation time 30705096921 ps
CPU time 21.49 seconds
Started May 12 12:50:59 PM PDT 24
Finished May 12 12:51:22 PM PDT 24
Peak memory 233664 kb
Host smart-3e7fdb3b-2309-4f57-bdbc-d2cf86d00b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827284600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2827284600
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1170470614
Short name T578
Test name
Test status
Simulation time 180890030 ps
CPU time 3.93 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:51:08 PM PDT 24
Peak memory 219260 kb
Host smart-04f3307e-ac14-40cd-993e-6dedb07ece74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1170470614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1170470614
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.187052481
Short name T82
Test name
Test status
Simulation time 37210607 ps
CPU time 1.02 seconds
Started May 12 12:51:01 PM PDT 24
Finished May 12 12:51:03 PM PDT 24
Peak memory 234948 kb
Host smart-db9f5d57-79b4-4cb3-8fc9-c432f778347a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187052481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.187052481
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2544628313
Short name T632
Test name
Test status
Simulation time 194305310045 ps
CPU time 133.02 seconds
Started May 12 12:50:52 PM PDT 24
Finished May 12 12:53:06 PM PDT 24
Peak memory 252624 kb
Host smart-28570539-4aa4-4802-adda-faa89a3474a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544628313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2544628313
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3166381727
Short name T381
Test name
Test status
Simulation time 30131917379 ps
CPU time 32.13 seconds
Started May 12 12:50:51 PM PDT 24
Finished May 12 12:51:24 PM PDT 24
Peak memory 216512 kb
Host smart-b59e070c-6826-43fa-8120-738e3ec5858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166381727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3166381727
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.583692126
Short name T736
Test name
Test status
Simulation time 179948362 ps
CPU time 1.75 seconds
Started May 12 12:50:57 PM PDT 24
Finished May 12 12:51:00 PM PDT 24
Peak memory 216272 kb
Host smart-99e5ccbf-87c5-4f3d-a519-604bdd625487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583692126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.583692126
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3950261831
Short name T886
Test name
Test status
Simulation time 14185524 ps
CPU time 0.75 seconds
Started May 12 12:51:02 PM PDT 24
Finished May 12 12:51:03 PM PDT 24
Peak memory 205368 kb
Host smart-6e7eedb0-addd-400c-9821-d8e5c788a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950261831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3950261831
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.260818846
Short name T290
Test name
Test status
Simulation time 692664507 ps
CPU time 5.72 seconds
Started May 12 12:51:01 PM PDT 24
Finished May 12 12:51:07 PM PDT 24
Peak memory 233892 kb
Host smart-817b03c0-4a43-444a-ac9d-fbabc7ad7871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260818846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.260818846
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.607257484
Short name T550
Test name
Test status
Simulation time 19887657 ps
CPU time 0.74 seconds
Started May 12 12:51:58 PM PDT 24
Finished May 12 12:51:59 PM PDT 24
Peak memory 205260 kb
Host smart-bba0d409-cb5b-4227-b48d-c4b2e1dbc5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607257484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.607257484
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1762215270
Short name T67
Test name
Test status
Simulation time 40403197 ps
CPU time 2.5 seconds
Started May 12 12:52:01 PM PDT 24
Finished May 12 12:52:04 PM PDT 24
Peak memory 233904 kb
Host smart-cd0f2da5-31ce-438c-8b4b-995d35e553a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762215270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1762215270
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.556559299
Short name T794
Test name
Test status
Simulation time 62462082 ps
CPU time 0.78 seconds
Started May 12 12:51:45 PM PDT 24
Finished May 12 12:51:46 PM PDT 24
Peak memory 206676 kb
Host smart-1f5bf442-e3f3-409d-9bf9-60e6cc692126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556559299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.556559299
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1720087209
Short name T396
Test name
Test status
Simulation time 754279506 ps
CPU time 5.58 seconds
Started May 12 12:51:47 PM PDT 24
Finished May 12 12:51:54 PM PDT 24
Peak memory 224444 kb
Host smart-9e1f783c-6962-476e-8967-13f96dbff053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720087209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1720087209
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3167250734
Short name T90
Test name
Test status
Simulation time 14329494121 ps
CPU time 130.2 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 257860 kb
Host smart-c318959b-bbd4-4400-aab6-e58ef2914757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167250734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3167250734
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2115013344
Short name T47
Test name
Test status
Simulation time 2204720690 ps
CPU time 49.87 seconds
Started May 12 12:51:52 PM PDT 24
Finished May 12 12:52:43 PM PDT 24
Peak memory 249372 kb
Host smart-0662547b-b1e4-4924-9f77-ef9ff4043c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115013344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2115013344
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3965961207
Short name T346
Test name
Test status
Simulation time 2419071455 ps
CPU time 12.94 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 235920 kb
Host smart-d3f2c026-514f-4b3a-88b2-c40bffa07e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965961207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3965961207
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1791951081
Short name T948
Test name
Test status
Simulation time 696516425 ps
CPU time 8.58 seconds
Started May 12 12:51:46 PM PDT 24
Finished May 12 12:51:55 PM PDT 24
Peak memory 224480 kb
Host smart-ec2d517a-691d-477d-a955-5da7ee75c59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791951081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1791951081
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.457054587
Short name T276
Test name
Test status
Simulation time 12214799932 ps
CPU time 55.74 seconds
Started May 12 12:51:52 PM PDT 24
Finished May 12 12:52:49 PM PDT 24
Peak memory 244704 kb
Host smart-aca36ffd-342a-4192-9098-5a5e55a37340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457054587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.457054587
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1957149413
Short name T338
Test name
Test status
Simulation time 76587578 ps
CPU time 2.27 seconds
Started May 12 12:51:49 PM PDT 24
Finished May 12 12:51:52 PM PDT 24
Peak memory 221044 kb
Host smart-d6326559-e739-4488-a898-51d67a8ca240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957149413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1957149413
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2178355217
Short name T177
Test name
Test status
Simulation time 5039074755 ps
CPU time 3.82 seconds
Started May 12 12:51:49 PM PDT 24
Finished May 12 12:51:54 PM PDT 24
Peak memory 234332 kb
Host smart-fcab3eeb-1055-4acb-8c0f-e977d7ed3a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178355217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2178355217
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2640540827
Short name T897
Test name
Test status
Simulation time 2824196876 ps
CPU time 6.7 seconds
Started May 12 12:51:45 PM PDT 24
Finished May 12 12:51:52 PM PDT 24
Peak memory 221812 kb
Host smart-14720587-9402-4462-9112-d4c51be56169
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2640540827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2640540827
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2561689185
Short name T167
Test name
Test status
Simulation time 62214785 ps
CPU time 1.1 seconds
Started May 12 12:51:52 PM PDT 24
Finished May 12 12:51:54 PM PDT 24
Peak memory 206756 kb
Host smart-cf6b4ac3-98c8-40b1-a443-3126705d5b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561689185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2561689185
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3332186018
Short name T606
Test name
Test status
Simulation time 588582764 ps
CPU time 8.92 seconds
Started May 12 12:51:45 PM PDT 24
Finished May 12 12:51:55 PM PDT 24
Peak memory 216256 kb
Host smart-184dbea8-0ecf-4c46-afe3-f15f161aa486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332186018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3332186018
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1340490412
Short name T521
Test name
Test status
Simulation time 2738720352 ps
CPU time 8.8 seconds
Started May 12 12:51:41 PM PDT 24
Finished May 12 12:51:50 PM PDT 24
Peak memory 216352 kb
Host smart-7308014a-1fb2-49b6-9a94-7c2f44c2de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340490412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1340490412
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3134121435
Short name T470
Test name
Test status
Simulation time 139146190 ps
CPU time 2.34 seconds
Started May 12 12:51:45 PM PDT 24
Finished May 12 12:51:48 PM PDT 24
Peak memory 216224 kb
Host smart-a9d9ff61-702b-45bb-9058-ca3702a7024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134121435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3134121435
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.442690865
Short name T879
Test name
Test status
Simulation time 95120321 ps
CPU time 0.74 seconds
Started May 12 12:51:47 PM PDT 24
Finished May 12 12:51:48 PM PDT 24
Peak memory 205744 kb
Host smart-7927ec1d-924d-4973-89fb-190c5672d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442690865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.442690865
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3235777593
Short name T13
Test name
Test status
Simulation time 2331313396 ps
CPU time 9.3 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:52:08 PM PDT 24
Peak memory 233484 kb
Host smart-e2eda600-25de-45d5-8844-5a01e141ddee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235777593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3235777593
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4256581134
Short name T728
Test name
Test status
Simulation time 50752573 ps
CPU time 0.75 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:51:57 PM PDT 24
Peak memory 205248 kb
Host smart-48c4f9fe-097b-4da3-b63f-78f22ef43b57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256581134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4256581134
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1000051846
Short name T671
Test name
Test status
Simulation time 2700286471 ps
CPU time 21.44 seconds
Started May 12 12:51:50 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 219580 kb
Host smart-97421f54-2f5e-4ed3-99f4-18c5bab17217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000051846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1000051846
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3903291897
Short name T491
Test name
Test status
Simulation time 70959812 ps
CPU time 0.78 seconds
Started May 12 12:52:00 PM PDT 24
Finished May 12 12:52:01 PM PDT 24
Peak memory 205672 kb
Host smart-46f6ce8b-380c-4903-adde-3e96133e6f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903291897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3903291897
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3897363386
Short name T850
Test name
Test status
Simulation time 4175313300 ps
CPU time 36.26 seconds
Started May 12 12:51:54 PM PDT 24
Finished May 12 12:52:32 PM PDT 24
Peak memory 249148 kb
Host smart-c35d4186-e1c7-4df4-b8d8-d06a171d89de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897363386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3897363386
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3854422674
Short name T226
Test name
Test status
Simulation time 258412787838 ps
CPU time 448.81 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:59:27 PM PDT 24
Peak memory 255804 kb
Host smart-57e3cdc0-fea4-4b6b-91d1-fa20f550c9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854422674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3854422674
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.464549751
Short name T208
Test name
Test status
Simulation time 63398746551 ps
CPU time 544.74 seconds
Started May 12 12:51:49 PM PDT 24
Finished May 12 01:00:54 PM PDT 24
Peak memory 265652 kb
Host smart-caf88347-fa8c-4f57-b511-09b650e18feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464549751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.464549751
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1812400011
Short name T793
Test name
Test status
Simulation time 125160035 ps
CPU time 4.2 seconds
Started May 12 12:52:07 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 224424 kb
Host smart-c71536fb-2e92-4d55-9601-d233d4f335cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812400011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1812400011
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1822847485
Short name T709
Test name
Test status
Simulation time 68258973 ps
CPU time 3.56 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:52:02 PM PDT 24
Peak memory 233648 kb
Host smart-cd33de72-c3cf-4668-97c1-4ae44157b78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822847485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1822847485
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2966717577
Short name T655
Test name
Test status
Simulation time 757641147 ps
CPU time 11.74 seconds
Started May 12 12:51:54 PM PDT 24
Finished May 12 12:52:07 PM PDT 24
Peak memory 246716 kb
Host smart-d1e834f7-36ae-4589-82b7-78ded8415249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966717577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2966717577
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3923971264
Short name T339
Test name
Test status
Simulation time 43629132 ps
CPU time 1.01 seconds
Started May 12 12:51:51 PM PDT 24
Finished May 12 12:51:53 PM PDT 24
Peak memory 217980 kb
Host smart-8bb96dde-ba54-4245-82a5-4806a6b90c47
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923971264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3923971264
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1945411912
Short name T916
Test name
Test status
Simulation time 1113631987 ps
CPU time 9.53 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:52:10 PM PDT 24
Peak memory 229292 kb
Host smart-9d104f58-fe8d-4af7-a890-cf09a72bedcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945411912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1945411912
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3222343750
Short name T716
Test name
Test status
Simulation time 5245305435 ps
CPU time 10.94 seconds
Started May 12 12:51:56 PM PDT 24
Finished May 12 12:52:08 PM PDT 24
Peak memory 218808 kb
Host smart-eedaf10a-c1c8-46f4-a0c6-bbbf3a59e7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222343750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3222343750
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2553007585
Short name T762
Test name
Test status
Simulation time 367705536 ps
CPU time 3.96 seconds
Started May 12 12:51:54 PM PDT 24
Finished May 12 12:51:58 PM PDT 24
Peak memory 222976 kb
Host smart-1b5779f2-125e-4dd3-9a04-8d8f9f5ee38e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2553007585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2553007585
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1574163394
Short name T49
Test name
Test status
Simulation time 30092185465 ps
CPU time 39.06 seconds
Started May 12 12:51:56 PM PDT 24
Finished May 12 12:52:36 PM PDT 24
Peak memory 216536 kb
Host smart-5d0b8a2a-7033-4d8f-8c7e-3d04d455c865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574163394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1574163394
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3573655421
Short name T442
Test name
Test status
Simulation time 11187490196 ps
CPU time 18.43 seconds
Started May 12 12:51:48 PM PDT 24
Finished May 12 12:52:07 PM PDT 24
Peak memory 216520 kb
Host smart-b9f3d0eb-74b3-40b3-bbf3-9fa74dd71fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573655421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3573655421
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3088204744
Short name T675
Test name
Test status
Simulation time 303546331 ps
CPU time 1.4 seconds
Started May 12 12:51:58 PM PDT 24
Finished May 12 12:52:01 PM PDT 24
Peak memory 208036 kb
Host smart-7eabffad-61a7-417a-baba-f465c08fc6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088204744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3088204744
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1474690245
Short name T647
Test name
Test status
Simulation time 58372978 ps
CPU time 0.92 seconds
Started May 12 12:51:47 PM PDT 24
Finished May 12 12:51:49 PM PDT 24
Peak memory 205792 kb
Host smart-7edbc7b7-6373-40d8-bfed-ff5f5515dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474690245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1474690245
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4165917991
Short name T621
Test name
Test status
Simulation time 1202484226 ps
CPU time 8.63 seconds
Started May 12 12:51:50 PM PDT 24
Finished May 12 12:51:59 PM PDT 24
Peak memory 218688 kb
Host smart-b94ffbb7-0b26-4ba3-9b15-cc23dccd928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165917991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4165917991
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1919908796
Short name T532
Test name
Test status
Simulation time 18754970 ps
CPU time 0.72 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 204696 kb
Host smart-2d9a61fe-6cd6-48d3-ac97-7c906c7e976e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919908796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1919908796
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.328486453
Short name T880
Test name
Test status
Simulation time 115339947 ps
CPU time 2.05 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:52:00 PM PDT 24
Peak memory 216168 kb
Host smart-4a67e46f-d5c7-41f3-8bb5-3b75a14183f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328486453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.328486453
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3731239785
Short name T562
Test name
Test status
Simulation time 18324223 ps
CPU time 0.83 seconds
Started May 12 12:51:47 PM PDT 24
Finished May 12 12:51:49 PM PDT 24
Peak memory 205308 kb
Host smart-da94f773-6c30-4866-966f-84a46919419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731239785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3731239785
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3971687478
Short name T473
Test name
Test status
Simulation time 180384831119 ps
CPU time 305.94 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 257400 kb
Host smart-109ed4ab-d8f4-428c-a6dc-76f6f1ff67e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971687478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3971687478
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.879979758
Short name T520
Test name
Test status
Simulation time 56200545727 ps
CPU time 156.8 seconds
Started May 12 12:51:54 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 254184 kb
Host smart-ee038172-9603-4335-b341-40b126f7350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879979758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.879979758
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_intercept.336061114
Short name T430
Test name
Test status
Simulation time 968726879 ps
CPU time 9.93 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:19 PM PDT 24
Peak memory 219552 kb
Host smart-609b7bec-e943-4ac6-8591-5507b444bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336061114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.336061114
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.450992603
Short name T756
Test name
Test status
Simulation time 2927056640 ps
CPU time 25.57 seconds
Started May 12 12:51:53 PM PDT 24
Finished May 12 12:52:19 PM PDT 24
Peak memory 249168 kb
Host smart-3072525a-c8f4-49bd-89b9-88ed451105c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450992603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.450992603
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2367826305
Short name T694
Test name
Test status
Simulation time 26225749 ps
CPU time 1.14 seconds
Started May 12 12:52:05 PM PDT 24
Finished May 12 12:52:07 PM PDT 24
Peak memory 216748 kb
Host smart-ec6bdaee-90b0-40f2-9a26-044a4c92448d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367826305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2367826305
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.82775023
Short name T890
Test name
Test status
Simulation time 112538762361 ps
CPU time 31.57 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:43 PM PDT 24
Peak memory 244904 kb
Host smart-8b265ee3-67d1-40e4-a0f1-12bf975dac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82775023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.82775023
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3620114538
Short name T544
Test name
Test status
Simulation time 655573060 ps
CPU time 3.87 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:16 PM PDT 24
Peak memory 222180 kb
Host smart-d3641f0e-71d7-492f-b684-127f4059a41b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620114538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3620114538
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4209500934
Short name T98
Test name
Test status
Simulation time 4100690615 ps
CPU time 88.18 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:53:28 PM PDT 24
Peak memory 249288 kb
Host smart-5c82242c-ce9f-4483-bfbb-96a7a8c9c095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209500934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4209500934
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2569382354
Short name T414
Test name
Test status
Simulation time 16238434 ps
CPU time 0.74 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:10 PM PDT 24
Peak memory 205504 kb
Host smart-f5526039-7fda-4166-8fdf-cea4645c6965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569382354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2569382354
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3438053833
Short name T747
Test name
Test status
Simulation time 1442939653 ps
CPU time 4.86 seconds
Started May 12 12:52:03 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 216392 kb
Host smart-a5c58657-3cc9-4938-b8ec-3857841e4bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438053833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3438053833
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3933302771
Short name T965
Test name
Test status
Simulation time 303800471 ps
CPU time 1.26 seconds
Started May 12 12:52:04 PM PDT 24
Finished May 12 12:52:06 PM PDT 24
Peak memory 207948 kb
Host smart-630a9a5c-6ace-4010-b0d7-0fd066145a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933302771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3933302771
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3330747442
Short name T714
Test name
Test status
Simulation time 84062668 ps
CPU time 0.83 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:12 PM PDT 24
Peak memory 205772 kb
Host smart-08f1d606-092f-46e4-a4b9-34f08bcb4086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330747442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3330747442
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.71458429
Short name T23
Test name
Test status
Simulation time 575490770 ps
CPU time 6.95 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:19 PM PDT 24
Peak memory 224424 kb
Host smart-5adf232f-edcf-4a43-8bcc-12378ab604ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71458429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.71458429
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2303955731
Short name T915
Test name
Test status
Simulation time 45246171 ps
CPU time 0.71 seconds
Started May 12 12:51:54 PM PDT 24
Finished May 12 12:51:56 PM PDT 24
Peak memory 205268 kb
Host smart-255c17de-38b6-4a7e-8fae-77875fc8f927
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303955731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2303955731
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1179680498
Short name T506
Test name
Test status
Simulation time 1838026785 ps
CPU time 12.13 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:21 PM PDT 24
Peak memory 234684 kb
Host smart-88017a53-5d29-412b-a441-d2cd78cd2d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179680498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1179680498
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2370519302
Short name T899
Test name
Test status
Simulation time 56012140 ps
CPU time 0.73 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:51:59 PM PDT 24
Peak memory 206676 kb
Host smart-8ad9895c-8152-43f2-b8f3-a2e7c7bbdeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370519302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2370519302
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2158906213
Short name T282
Test name
Test status
Simulation time 11459836267 ps
CPU time 80.31 seconds
Started May 12 12:52:02 PM PDT 24
Finished May 12 12:53:23 PM PDT 24
Peak memory 249568 kb
Host smart-0392badf-2672-4ac4-9280-df0738af34e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158906213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2158906213
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3690097109
Short name T775
Test name
Test status
Simulation time 6778455865 ps
CPU time 62.52 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:53:01 PM PDT 24
Peak memory 251624 kb
Host smart-f13f2e4a-e075-442f-ac6a-591ce489caba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690097109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3690097109
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.320213358
Short name T935
Test name
Test status
Simulation time 7737214142 ps
CPU time 81.38 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:53:30 PM PDT 24
Peak memory 271320 kb
Host smart-5f3da7de-d8ab-4ff4-8518-af419fee7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320213358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.320213358
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3346451055
Short name T512
Test name
Test status
Simulation time 1609259690 ps
CPU time 4.8 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:14 PM PDT 24
Peak memory 218412 kb
Host smart-1e038349-3d05-470d-b072-9bc0ced383f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346451055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3346451055
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1894015648
Short name T878
Test name
Test status
Simulation time 592261318 ps
CPU time 3 seconds
Started May 12 12:52:01 PM PDT 24
Finished May 12 12:52:04 PM PDT 24
Peak memory 235472 kb
Host smart-f1de7550-49d9-4e48-a51f-0ca190d31983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894015648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1894015648
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3740628114
Short name T566
Test name
Test status
Simulation time 56889358 ps
CPU time 1.11 seconds
Started May 12 12:51:56 PM PDT 24
Finished May 12 12:51:59 PM PDT 24
Peak memory 216652 kb
Host smart-0d1d1116-0345-4828-861c-9b86df2b63c6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740628114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3740628114
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.897611856
Short name T216
Test name
Test status
Simulation time 942787474 ps
CPU time 4.64 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:52:05 PM PDT 24
Peak memory 233640 kb
Host smart-178ed416-28c9-4084-8b4c-163a146b7024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897611856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.897611856
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3698687005
Short name T505
Test name
Test status
Simulation time 56885670149 ps
CPU time 27.1 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:52:24 PM PDT 24
Peak memory 219840 kb
Host smart-c8460413-d41c-4716-b52d-c48035330cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698687005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3698687005
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2224014219
Short name T154
Test name
Test status
Simulation time 3932125452 ps
CPU time 7.67 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:52:04 PM PDT 24
Peak memory 220820 kb
Host smart-fc762bf6-a8a8-4770-8e12-4f435959256a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2224014219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2224014219
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2025633417
Short name T761
Test name
Test status
Simulation time 4324851893 ps
CPU time 28.8 seconds
Started May 12 12:51:58 PM PDT 24
Finished May 12 12:52:27 PM PDT 24
Peak memory 249236 kb
Host smart-c17bf69d-7550-49df-9b7f-5b87521383c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025633417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2025633417
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4100058273
Short name T665
Test name
Test status
Simulation time 5393781277 ps
CPU time 34.14 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:52:34 PM PDT 24
Peak memory 216424 kb
Host smart-6557e1fc-c551-4011-9d45-684d75aa466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100058273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4100058273
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3283662939
Short name T858
Test name
Test status
Simulation time 3960876189 ps
CPU time 11.3 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 216464 kb
Host smart-9c5b06d1-53d0-4ea3-a46b-de68d5272380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283662939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3283662939
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2815017882
Short name T612
Test name
Test status
Simulation time 23954860 ps
CPU time 0.89 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:10 PM PDT 24
Peak memory 206420 kb
Host smart-273d7efb-7a99-4397-83cc-09b0fc51e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815017882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2815017882
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2953968839
Short name T766
Test name
Test status
Simulation time 67224781 ps
CPU time 0.87 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:14 PM PDT 24
Peak memory 205700 kb
Host smart-e4b94b29-dbb0-4355-96e8-17c3f6d8ba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953968839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2953968839
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2428455463
Short name T279
Test name
Test status
Simulation time 920539454 ps
CPU time 7.45 seconds
Started May 12 12:52:09 PM PDT 24
Finished May 12 12:52:18 PM PDT 24
Peak memory 221356 kb
Host smart-427d8f46-d9cb-418c-9680-cdfb1b18448d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428455463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2428455463
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.395750802
Short name T776
Test name
Test status
Simulation time 16338570 ps
CPU time 0.72 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:12 PM PDT 24
Peak memory 205900 kb
Host smart-3fbe998a-6edb-479c-801f-cb813d6b45d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395750802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.395750802
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1752632565
Short name T377
Test name
Test status
Simulation time 692388758 ps
CPU time 2.74 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:10 PM PDT 24
Peak memory 218484 kb
Host smart-6dec5311-291b-4d81-b4d9-5e2217df3bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752632565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1752632565
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.663713289
Short name T670
Test name
Test status
Simulation time 18575396 ps
CPU time 0.81 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:51:57 PM PDT 24
Peak memory 206388 kb
Host smart-83d64c66-4006-4f01-802c-5b035ee1ccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663713289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.663713289
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.625084622
Short name T892
Test name
Test status
Simulation time 18247165735 ps
CPU time 127.91 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:54:20 PM PDT 24
Peak memory 236696 kb
Host smart-2e13ce75-2da1-4ba6-9f9a-3bab0b64bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625084622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.625084622
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1477271010
Short name T440
Test name
Test status
Simulation time 4443496225 ps
CPU time 37.97 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:50 PM PDT 24
Peak memory 239020 kb
Host smart-4f1a9fd3-73e8-4d21-b133-89f19cc4fbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477271010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1477271010
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3186094917
Short name T27
Test name
Test status
Simulation time 112246666172 ps
CPU time 226.96 seconds
Started May 12 12:52:00 PM PDT 24
Finished May 12 12:55:48 PM PDT 24
Peak memory 248904 kb
Host smart-9df80e24-0704-4124-80ae-845b45501c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186094917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3186094917
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.615759643
Short name T690
Test name
Test status
Simulation time 5525825122 ps
CPU time 6.6 seconds
Started May 12 12:52:04 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 241000 kb
Host smart-1775fcb9-974c-4334-a255-b5668aa1eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615759643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.615759643
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.891842992
Short name T698
Test name
Test status
Simulation time 194795531 ps
CPU time 5.3 seconds
Started May 12 12:51:56 PM PDT 24
Finished May 12 12:52:02 PM PDT 24
Peak memory 233660 kb
Host smart-9173ba80-6131-4703-a0b0-7ad94b677fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891842992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.891842992
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3657520318
Short name T928
Test name
Test status
Simulation time 12306632955 ps
CPU time 51.29 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:52:48 PM PDT 24
Peak memory 233492 kb
Host smart-56cf877c-6c52-477c-ab5f-10ec3b54a95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657520318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3657520318
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1750852574
Short name T410
Test name
Test status
Simulation time 16698174 ps
CPU time 1.1 seconds
Started May 12 12:51:58 PM PDT 24
Finished May 12 12:52:00 PM PDT 24
Peak memory 216676 kb
Host smart-2374aee2-ad5f-4549-a89a-472603d3d0d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750852574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1750852574
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2339400340
Short name T268
Test name
Test status
Simulation time 31697740900 ps
CPU time 28.12 seconds
Started May 12 12:51:56 PM PDT 24
Finished May 12 12:52:25 PM PDT 24
Peak memory 220400 kb
Host smart-f29d79d1-3e5b-48cb-a519-1539c94a5da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339400340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2339400340
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1057446030
Short name T594
Test name
Test status
Simulation time 891765574 ps
CPU time 2.79 seconds
Started May 12 12:52:05 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 233592 kb
Host smart-6b6cb98c-bfa4-4bab-bb11-ece68864b0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057446030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1057446030
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2316323483
Short name T844
Test name
Test status
Simulation time 1773923297 ps
CPU time 5.52 seconds
Started May 12 12:52:09 PM PDT 24
Finished May 12 12:52:17 PM PDT 24
Peak memory 222096 kb
Host smart-86090f9a-cf3d-4d21-a0ad-534963f20546
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2316323483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2316323483
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.208384054
Short name T18
Test name
Test status
Simulation time 158666653 ps
CPU time 1.18 seconds
Started May 12 12:52:02 PM PDT 24
Finished May 12 12:52:04 PM PDT 24
Peak memory 207136 kb
Host smart-07abf420-cff2-4eb8-b1c5-57084a32eb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208384054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.208384054
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1693620483
Short name T519
Test name
Test status
Simulation time 2236387352 ps
CPU time 32.56 seconds
Started May 12 12:52:03 PM PDT 24
Finished May 12 12:52:36 PM PDT 24
Peak memory 216724 kb
Host smart-4f13969e-150b-449f-b53d-bd1602aa84d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693620483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1693620483
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.49082295
Short name T927
Test name
Test status
Simulation time 24733584 ps
CPU time 0.75 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:51:57 PM PDT 24
Peak memory 205452 kb
Host smart-4d987afc-b3c7-45ec-9807-44a14d1cc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49082295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.49082295
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1717838173
Short name T904
Test name
Test status
Simulation time 17607712 ps
CPU time 0.78 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:08 PM PDT 24
Peak memory 205680 kb
Host smart-6fe5ffe6-234e-4b3c-9457-d41325f6715e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717838173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1717838173
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1560148528
Short name T691
Test name
Test status
Simulation time 32022512 ps
CPU time 0.86 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:12 PM PDT 24
Peak memory 205788 kb
Host smart-32c2ada2-971c-41d3-bbf1-ad3202650145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560148528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1560148528
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3524039764
Short name T902
Test name
Test status
Simulation time 18887928665 ps
CPU time 11.93 seconds
Started May 12 12:51:58 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 230592 kb
Host smart-d89499d7-e808-4bd3-a935-2c81e3b11eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524039764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3524039764
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.375351299
Short name T76
Test name
Test status
Simulation time 110279534 ps
CPU time 0.71 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:52:14 PM PDT 24
Peak memory 205200 kb
Host smart-5ed72595-5ee6-4782-986f-d038dcd7f051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375351299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.375351299
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.26291709
Short name T363
Test name
Test status
Simulation time 225294476 ps
CPU time 3.79 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 233228 kb
Host smart-ab1e2f00-47eb-4ca6-9846-edb0cfa31b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26291709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.26291709
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3669185341
Short name T845
Test name
Test status
Simulation time 58382333 ps
CPU time 0.8 seconds
Started May 12 12:51:57 PM PDT 24
Finished May 12 12:51:59 PM PDT 24
Peak memory 206656 kb
Host smart-be46d0cc-f5f1-484a-a3f2-709270185b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669185341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3669185341
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.13096307
Short name T508
Test name
Test status
Simulation time 4446335173 ps
CPU time 75.67 seconds
Started May 12 12:52:05 PM PDT 24
Finished May 12 12:53:21 PM PDT 24
Peak memory 249320 kb
Host smart-0272040a-f5c0-43d1-be02-d7417c17f75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13096307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.13096307
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4118058642
Short name T25
Test name
Test status
Simulation time 53619068388 ps
CPU time 215.49 seconds
Started May 12 12:52:07 PM PDT 24
Finished May 12 12:55:44 PM PDT 24
Peak memory 257552 kb
Host smart-0c435578-a4ad-4823-b6fa-7f101e1acead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118058642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4118058642
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2505782586
Short name T710
Test name
Test status
Simulation time 47587101 ps
CPU time 2.59 seconds
Started May 12 12:52:21 PM PDT 24
Finished May 12 12:52:24 PM PDT 24
Peak memory 224464 kb
Host smart-2db83bdb-3a98-4b67-8bcc-a6654bed60ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505782586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2505782586
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.932323352
Short name T853
Test name
Test status
Simulation time 148227776 ps
CPU time 4.69 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:12 PM PDT 24
Peak memory 233748 kb
Host smart-8ef2271e-412f-4607-864b-3b9b99d64d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932323352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.932323352
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2476650902
Short name T382
Test name
Test status
Simulation time 8330044560 ps
CPU time 20.57 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:28 PM PDT 24
Peak memory 232732 kb
Host smart-fd699e6e-7dfa-458b-af4e-d2761be1ce5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476650902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2476650902
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1418101623
Short name T28
Test name
Test status
Simulation time 37928951 ps
CPU time 1.03 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:52:15 PM PDT 24
Peak memory 216664 kb
Host smart-9842fda0-439e-4093-a94c-79369e9c24ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418101623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1418101623
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4050403828
Short name T898
Test name
Test status
Simulation time 43668827817 ps
CPU time 24.16 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:32 PM PDT 24
Peak memory 222628 kb
Host smart-9d5c8aa7-ba5c-43f1-a408-600df430229d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050403828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4050403828
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1498797754
Short name T15
Test name
Test status
Simulation time 83815638 ps
CPU time 2.73 seconds
Started May 12 12:52:02 PM PDT 24
Finished May 12 12:52:06 PM PDT 24
Peak memory 233520 kb
Host smart-fa761e5e-a680-4641-a479-cc3355843866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498797754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1498797754
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1714789917
Short name T651
Test name
Test status
Simulation time 254863270 ps
CPU time 4.86 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 222420 kb
Host smart-2693542c-02e7-45d3-83c0-7b9cf9474059
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1714789917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1714789917
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3413446398
Short name T169
Test name
Test status
Simulation time 36910659673 ps
CPU time 221.03 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:55:54 PM PDT 24
Peak memory 255576 kb
Host smart-d297148d-4e41-4ca6-81c2-fbb3ca32a2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413446398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3413446398
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.698669194
Short name T318
Test name
Test status
Simulation time 4186086590 ps
CPU time 6.46 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 216468 kb
Host smart-432d829c-6025-4f24-b0a8-a1ee573bf34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698669194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.698669194
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.740270394
Short name T609
Test name
Test status
Simulation time 874778141 ps
CPU time 4.28 seconds
Started May 12 12:51:55 PM PDT 24
Finished May 12 12:52:00 PM PDT 24
Peak memory 216324 kb
Host smart-36aafb10-19e1-4fa3-b65b-2be0851dcc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740270394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.740270394
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.191400637
Short name T524
Test name
Test status
Simulation time 105938998 ps
CPU time 2.09 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:52:01 PM PDT 24
Peak memory 216352 kb
Host smart-d827cbd7-dbfc-49bc-8abb-70d9667b550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191400637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.191400637
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1590453138
Short name T650
Test name
Test status
Simulation time 23016904 ps
CPU time 0.75 seconds
Started May 12 12:52:09 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 205752 kb
Host smart-d9bd2f8a-d1a7-4634-ab2a-eb6190ae18e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590453138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1590453138
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.317720975
Short name T482
Test name
Test status
Simulation time 1959841892 ps
CPU time 9.28 seconds
Started May 12 12:52:01 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 236892 kb
Host smart-c3088596-b27b-4644-a39a-0c4997c2d09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317720975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.317720975
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1951057099
Short name T464
Test name
Test status
Simulation time 16491115 ps
CPU time 0.74 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 205400 kb
Host smart-4b8c7d7c-be0e-4a83-856e-f6239765fa91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951057099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1951057099
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1459875692
Short name T14
Test name
Test status
Simulation time 3325985243 ps
CPU time 35.44 seconds
Started May 12 12:52:13 PM PDT 24
Finished May 12 12:52:49 PM PDT 24
Peak memory 220628 kb
Host smart-c41e1027-ccb4-4469-891d-63593d0a8d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459875692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1459875692
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1459861083
Short name T350
Test name
Test status
Simulation time 97298372 ps
CPU time 0.83 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:11 PM PDT 24
Peak memory 206696 kb
Host smart-e0e88d44-c1dd-4da7-bc89-1a5aae53bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459861083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1459861083
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.996421734
Short name T917
Test name
Test status
Simulation time 5404907367 ps
CPU time 73.91 seconds
Started May 12 12:52:13 PM PDT 24
Finished May 12 12:53:28 PM PDT 24
Peak memory 255228 kb
Host smart-e82f68dd-1f86-4220-a5ef-99d62a4e71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996421734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.996421734
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1999676995
Short name T874
Test name
Test status
Simulation time 11042663077 ps
CPU time 21.01 seconds
Started May 12 12:52:05 PM PDT 24
Finished May 12 12:52:26 PM PDT 24
Peak memory 217404 kb
Host smart-b597bec4-70d9-4945-b66e-d4180be305da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999676995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1999676995
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1827288010
Short name T145
Test name
Test status
Simulation time 32296098176 ps
CPU time 318.94 seconds
Started May 12 12:52:13 PM PDT 24
Finished May 12 12:57:33 PM PDT 24
Peak memory 250756 kb
Host smart-bb6c2e1b-c2d8-4ab3-8a46-5d2e5b693c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827288010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1827288010
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.919603384
Short name T600
Test name
Test status
Simulation time 177604975 ps
CPU time 3.7 seconds
Started May 12 12:52:09 PM PDT 24
Finished May 12 12:52:15 PM PDT 24
Peak memory 224416 kb
Host smart-0a6d0373-49bf-4730-a6fd-9b9afb732ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919603384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.919603384
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.297708745
Short name T114
Test name
Test status
Simulation time 78118620 ps
CPU time 2.04 seconds
Started May 12 12:52:04 PM PDT 24
Finished May 12 12:52:07 PM PDT 24
Peak memory 216032 kb
Host smart-b72947f8-34a4-44af-a587-8af962cb4051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297708745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.297708745
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2977138355
Short name T862
Test name
Test status
Simulation time 20946245107 ps
CPU time 36.42 seconds
Started May 12 12:52:05 PM PDT 24
Finished May 12 12:52:42 PM PDT 24
Peak memory 218976 kb
Host smart-c2cb075e-2040-4044-94cf-0ae4f0ad6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977138355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2977138355
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3267067536
Short name T86
Test name
Test status
Simulation time 29329337 ps
CPU time 1.08 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 216640 kb
Host smart-4081d6b8-5b43-4224-90e6-33ff83150237
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267067536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3267067536
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1197194174
Short name T740
Test name
Test status
Simulation time 187548732 ps
CPU time 3.06 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:16 PM PDT 24
Peak memory 233032 kb
Host smart-73fd02b5-223f-4288-b601-319eca0c318b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197194174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1197194174
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3184395270
Short name T952
Test name
Test status
Simulation time 24344062558 ps
CPU time 18.05 seconds
Started May 12 12:52:06 PM PDT 24
Finished May 12 12:52:25 PM PDT 24
Peak memory 238164 kb
Host smart-32c0c52a-6c22-43bc-abc8-3f358435d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184395270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3184395270
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2053694354
Short name T702
Test name
Test status
Simulation time 1196495703 ps
CPU time 8.44 seconds
Started May 12 12:52:09 PM PDT 24
Finished May 12 12:52:19 PM PDT 24
Peak memory 222560 kb
Host smart-0d3101f4-3f96-4d30-bd73-bc24b6faa736
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2053694354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2053694354
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.886152055
Short name T531
Test name
Test status
Simulation time 994645772 ps
CPU time 4.14 seconds
Started May 12 12:52:04 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 216356 kb
Host smart-56d8814a-380c-4dd1-84e6-a5061865cf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886152055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.886152055
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4111398376
Short name T10
Test name
Test status
Simulation time 2248285518 ps
CPU time 9.88 seconds
Started May 12 12:52:09 PM PDT 24
Finished May 12 12:52:21 PM PDT 24
Peak memory 216384 kb
Host smart-c82e561b-6d1b-410a-a09e-d522f6d91119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111398376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4111398376
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2336443435
Short name T88
Test name
Test status
Simulation time 44451422 ps
CPU time 0.85 seconds
Started May 12 12:52:07 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 206588 kb
Host smart-131a2ad3-3983-4cf0-a1d7-305e1310ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336443435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2336443435
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.608388631
Short name T479
Test name
Test status
Simulation time 48777522 ps
CPU time 0.8 seconds
Started May 12 12:52:08 PM PDT 24
Finished May 12 12:52:10 PM PDT 24
Peak memory 205864 kb
Host smart-0f65f817-b193-4561-922a-e25ad8797a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608388631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.608388631
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2275499097
Short name T212
Test name
Test status
Simulation time 1247478996 ps
CPU time 5.64 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:17 PM PDT 24
Peak memory 233676 kb
Host smart-6846d645-ec98-40ae-ab49-1ba26230750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275499097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2275499097
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3429286775
Short name T75
Test name
Test status
Simulation time 43993703 ps
CPU time 0.69 seconds
Started May 12 12:52:27 PM PDT 24
Finished May 12 12:52:28 PM PDT 24
Peak memory 205704 kb
Host smart-367b7433-a984-43bb-83ab-c5c047845372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429286775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3429286775
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1329333132
Short name T385
Test name
Test status
Simulation time 3394337185 ps
CPU time 7.62 seconds
Started May 12 12:52:22 PM PDT 24
Finished May 12 12:52:30 PM PDT 24
Peak memory 218904 kb
Host smart-d83a3768-4a19-4074-8596-8de5698fc648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329333132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1329333132
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.464962900
Short name T364
Test name
Test status
Simulation time 58467486 ps
CPU time 0.73 seconds
Started May 12 12:52:10 PM PDT 24
Finished May 12 12:52:13 PM PDT 24
Peak memory 206364 kb
Host smart-78bea39c-2a0a-405d-ba2a-7036ec9a2255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464962900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.464962900
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.35681750
Short name T967
Test name
Test status
Simulation time 35920390120 ps
CPU time 111.97 seconds
Started May 12 12:52:17 PM PDT 24
Finished May 12 12:54:10 PM PDT 24
Peak memory 252468 kb
Host smart-8ef759d3-e6ce-4048-99f7-e0ca5aac0236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35681750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.35681750
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2026667573
Short name T196
Test name
Test status
Simulation time 127408699079 ps
CPU time 218.39 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:55:52 PM PDT 24
Peak memory 249272 kb
Host smart-26e16bd4-72a8-4c0a-b8cb-e6eea242d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026667573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2026667573
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1823056657
Short name T41
Test name
Test status
Simulation time 26142105540 ps
CPU time 139.03 seconds
Started May 12 12:52:14 PM PDT 24
Finished May 12 12:54:34 PM PDT 24
Peak memory 270772 kb
Host smart-26937321-1d97-4b45-9ec3-87eec9e6a658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823056657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1823056657
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2518186234
Short name T309
Test name
Test status
Simulation time 7237537017 ps
CPU time 21.06 seconds
Started May 12 12:52:41 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 224604 kb
Host smart-00273eb8-0176-4e40-9ad4-79e0b6f9df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518186234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2518186234
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3034542472
Short name T530
Test name
Test status
Simulation time 76279744 ps
CPU time 2.97 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:16 PM PDT 24
Peak memory 234732 kb
Host smart-f9ac446e-8265-45e8-aca3-9158ff70d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034542472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3034542472
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1535658632
Short name T724
Test name
Test status
Simulation time 577533226 ps
CPU time 8.69 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:21 PM PDT 24
Peak memory 236260 kb
Host smart-6cb8cbdf-fa09-4ec1-b435-e2e983e0b867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535658632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1535658632
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3231386396
Short name T549
Test name
Test status
Simulation time 16201301 ps
CPU time 1.08 seconds
Started May 12 12:52:07 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 216628 kb
Host smart-1822a181-a5b8-457a-a8cd-f60ee594324a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231386396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3231386396
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3213671847
Short name T768
Test name
Test status
Simulation time 473854053 ps
CPU time 3.35 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:52:17 PM PDT 24
Peak memory 218624 kb
Host smart-ad69cab6-8446-492a-b922-971b4b63ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213671847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3213671847
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2592587526
Short name T178
Test name
Test status
Simulation time 338960065 ps
CPU time 2.27 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:52:16 PM PDT 24
Peak memory 218800 kb
Host smart-b604ec5d-6a9a-4bde-9993-b8ae390183e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592587526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2592587526
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.211508045
Short name T354
Test name
Test status
Simulation time 5334909427 ps
CPU time 11.78 seconds
Started May 12 12:52:11 PM PDT 24
Finished May 12 12:52:24 PM PDT 24
Peak memory 223256 kb
Host smart-3bad491a-c34f-4e6e-adfc-dedcf6424b76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=211508045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.211508045
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.193675240
Short name T355
Test name
Test status
Simulation time 67954089 ps
CPU time 0.87 seconds
Started May 12 12:52:24 PM PDT 24
Finished May 12 12:52:26 PM PDT 24
Peak memory 206716 kb
Host smart-681f46ef-d75b-4332-8bce-198ecbc1148a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193675240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.193675240
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2517694648
Short name T490
Test name
Test status
Simulation time 1717195725 ps
CPU time 23.31 seconds
Started May 12 12:52:14 PM PDT 24
Finished May 12 12:52:38 PM PDT 24
Peak memory 219084 kb
Host smart-45243255-5ee8-464e-99a0-b3634147c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517694648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2517694648
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1517819362
Short name T865
Test name
Test status
Simulation time 2776974730 ps
CPU time 8.63 seconds
Started May 12 12:52:13 PM PDT 24
Finished May 12 12:52:23 PM PDT 24
Peak memory 216372 kb
Host smart-83ee522b-af84-4ec9-b06c-793c9960bfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517819362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1517819362
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1450587153
Short name T564
Test name
Test status
Simulation time 24324244 ps
CPU time 0.92 seconds
Started May 12 12:52:14 PM PDT 24
Finished May 12 12:52:16 PM PDT 24
Peak memory 207068 kb
Host smart-ade7f350-c9b8-4e65-a692-898daa8c4d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450587153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1450587153
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2969678190
Short name T855
Test name
Test status
Simulation time 42240079 ps
CPU time 0.81 seconds
Started May 12 12:52:12 PM PDT 24
Finished May 12 12:52:14 PM PDT 24
Peak memory 205608 kb
Host smart-ef5837c7-0e42-4f7e-88aa-d27680a39074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969678190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2969678190
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2944349653
Short name T526
Test name
Test status
Simulation time 9206141963 ps
CPU time 9.87 seconds
Started May 12 12:52:15 PM PDT 24
Finished May 12 12:52:25 PM PDT 24
Peak memory 217396 kb
Host smart-eeba36b4-2093-493f-b78e-da985d3b5030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944349653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2944349653
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1744966231
Short name T726
Test name
Test status
Simulation time 21097577 ps
CPU time 0.71 seconds
Started May 12 12:52:30 PM PDT 24
Finished May 12 12:52:32 PM PDT 24
Peak memory 205584 kb
Host smart-58ec7d95-add9-40b3-a9c0-e0e763649173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744966231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1744966231
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2384873043
Short name T973
Test name
Test status
Simulation time 286940494 ps
CPU time 5.84 seconds
Started May 12 12:52:19 PM PDT 24
Finished May 12 12:52:26 PM PDT 24
Peak memory 233692 kb
Host smart-fc341f2b-e137-4651-a8b0-7ac5d8e79de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384873043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2384873043
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2759407102
Short name T89
Test name
Test status
Simulation time 66418475 ps
CPU time 0.8 seconds
Started May 12 12:52:15 PM PDT 24
Finished May 12 12:52:17 PM PDT 24
Peak memory 206340 kb
Host smart-581fe20d-01e6-4d40-b782-96c400d263df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759407102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2759407102
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2898916568
Short name T229
Test name
Test status
Simulation time 31299390889 ps
CPU time 97.2 seconds
Started May 12 12:52:28 PM PDT 24
Finished May 12 12:54:11 PM PDT 24
Peak memory 265168 kb
Host smart-c39c9fcd-1ae0-45e0-bb3a-3422d2318cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898916568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2898916568
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1565094061
Short name T258
Test name
Test status
Simulation time 178883630270 ps
CPU time 258.55 seconds
Started May 12 12:52:30 PM PDT 24
Finished May 12 12:56:49 PM PDT 24
Peak memory 250508 kb
Host smart-02d134c2-2d93-45d1-bb7f-81418c79c244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565094061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1565094061
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3734978975
Short name T58
Test name
Test status
Simulation time 389213801 ps
CPU time 3.35 seconds
Started May 12 12:52:25 PM PDT 24
Finished May 12 12:52:29 PM PDT 24
Peak memory 228832 kb
Host smart-5b6f10f2-c739-41f1-9ed6-9b7761aa47d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734978975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3734978975
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4263487257
Short name T206
Test name
Test status
Simulation time 1087271364 ps
CPU time 11.2 seconds
Started May 12 12:52:33 PM PDT 24
Finished May 12 12:52:45 PM PDT 24
Peak memory 233560 kb
Host smart-bb296084-5475-4ec5-a19f-a7bf2c85eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263487257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4263487257
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1777540588
Short name T331
Test name
Test status
Simulation time 274933696 ps
CPU time 2.19 seconds
Started May 12 12:52:41 PM PDT 24
Finished May 12 12:52:44 PM PDT 24
Peak memory 216320 kb
Host smart-a2e26991-9808-4f58-9e55-b6ab3db27024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777540588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1777540588
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2722707845
Short name T857
Test name
Test status
Simulation time 25619462 ps
CPU time 1.07 seconds
Started May 12 12:52:31 PM PDT 24
Finished May 12 12:52:32 PM PDT 24
Peak memory 216680 kb
Host smart-a25f3029-b8dd-4ca3-acf4-c39128662776
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722707845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2722707845
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3142635556
Short name T264
Test name
Test status
Simulation time 3700990233 ps
CPU time 14.61 seconds
Started May 12 12:52:23 PM PDT 24
Finished May 12 12:52:38 PM PDT 24
Peak memory 232208 kb
Host smart-98082e9b-a4a2-40a9-a5d2-84544d6e042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142635556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3142635556
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1194478127
Short name T496
Test name
Test status
Simulation time 83078280 ps
CPU time 2.56 seconds
Started May 12 12:52:26 PM PDT 24
Finished May 12 12:52:29 PM PDT 24
Peak memory 232532 kb
Host smart-b27abf03-2675-4626-89e4-cabfa344e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194478127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1194478127
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3429001209
Short name T970
Test name
Test status
Simulation time 467199697 ps
CPU time 3.88 seconds
Started May 12 12:52:30 PM PDT 24
Finished May 12 12:52:39 PM PDT 24
Peak memory 220228 kb
Host smart-abc1c987-43f8-41ff-8c5a-b95094c2eaf9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429001209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3429001209
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1750602868
Short name T582
Test name
Test status
Simulation time 26862165562 ps
CPU time 27.34 seconds
Started May 12 12:52:28 PM PDT 24
Finished May 12 12:52:56 PM PDT 24
Peak memory 217512 kb
Host smart-4ec0aff7-e8fa-4454-9afb-9e6bf3c6f316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750602868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1750602868
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1039409994
Short name T465
Test name
Test status
Simulation time 35730362458 ps
CPU time 16.84 seconds
Started May 12 12:52:23 PM PDT 24
Finished May 12 12:52:40 PM PDT 24
Peak memory 216480 kb
Host smart-908e02af-22f1-4103-96fb-87aff6b3ed63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039409994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1039409994
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2064487903
Short name T2
Test name
Test status
Simulation time 123535515 ps
CPU time 1.35 seconds
Started May 12 12:52:16 PM PDT 24
Finished May 12 12:52:18 PM PDT 24
Peak memory 207676 kb
Host smart-3f7181e9-8e61-403d-b286-5b296a6e7c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064487903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2064487903
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1658994594
Short name T316
Test name
Test status
Simulation time 125830723 ps
CPU time 1.31 seconds
Started May 12 12:52:35 PM PDT 24
Finished May 12 12:52:37 PM PDT 24
Peak memory 216388 kb
Host smart-f1aed788-3336-4216-89c4-7a5de73803e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658994594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1658994594
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.252637124
Short name T759
Test name
Test status
Simulation time 186192897 ps
CPU time 0.83 seconds
Started May 12 12:52:24 PM PDT 24
Finished May 12 12:52:26 PM PDT 24
Peak memory 205756 kb
Host smart-36ba8a2e-c001-434a-b2fa-ec9ef5d3cd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252637124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.252637124
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3495246257
Short name T171
Test name
Test status
Simulation time 15626082400 ps
CPU time 8.03 seconds
Started May 12 12:52:30 PM PDT 24
Finished May 12 12:52:38 PM PDT 24
Peak memory 218788 kb
Host smart-025fd3df-b9d8-43bd-84f3-465f49a90e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495246257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3495246257
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4070129505
Short name T325
Test name
Test status
Simulation time 35282718 ps
CPU time 0.71 seconds
Started May 12 12:52:49 PM PDT 24
Finished May 12 12:52:50 PM PDT 24
Peak memory 204684 kb
Host smart-c40fe926-708f-4a27-9453-7b2fa2e0bd00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070129505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4070129505
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1900602834
Short name T480
Test name
Test status
Simulation time 2020022192 ps
CPU time 10.48 seconds
Started May 12 12:52:32 PM PDT 24
Finished May 12 12:52:43 PM PDT 24
Peak memory 219172 kb
Host smart-c948bf4c-08e3-45c2-9dd2-1a592824decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900602834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1900602834
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.156035698
Short name T699
Test name
Test status
Simulation time 13870274 ps
CPU time 0.74 seconds
Started May 12 12:52:24 PM PDT 24
Finished May 12 12:52:25 PM PDT 24
Peak memory 205420 kb
Host smart-8f700214-ed52-4e6f-b2c6-dae568aa09e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156035698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.156035698
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3569292048
Short name T235
Test name
Test status
Simulation time 329242703226 ps
CPU time 187.15 seconds
Started May 12 12:52:39 PM PDT 24
Finished May 12 12:55:47 PM PDT 24
Peak memory 252712 kb
Host smart-e1fe0168-e7d2-4451-859f-e15410db85b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569292048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3569292048
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3977281189
Short name T413
Test name
Test status
Simulation time 27164477802 ps
CPU time 57.83 seconds
Started May 12 12:52:34 PM PDT 24
Finished May 12 12:53:32 PM PDT 24
Peak memory 241084 kb
Host smart-b02a3234-485e-490f-8c99-e7cb743c5f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977281189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3977281189
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2203263875
Short name T499
Test name
Test status
Simulation time 128393167 ps
CPU time 2.83 seconds
Started May 12 12:52:42 PM PDT 24
Finished May 12 12:52:46 PM PDT 24
Peak memory 232580 kb
Host smart-e9998bf7-325c-4fcf-880b-f68386262dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203263875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2203263875
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3447036168
Short name T871
Test name
Test status
Simulation time 3378998294 ps
CPU time 24.51 seconds
Started May 12 12:52:38 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 219908 kb
Host smart-ddbbae1d-c958-4abe-8ab1-cb6eb5515b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447036168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3447036168
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2627088816
Short name T298
Test name
Test status
Simulation time 6819170909 ps
CPU time 35.12 seconds
Started May 12 12:52:39 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 238776 kb
Host smart-e20f7a7a-1d89-4b03-a3f9-1beb573e0733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627088816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2627088816
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.718423323
Short name T392
Test name
Test status
Simulation time 53497621 ps
CPU time 1.03 seconds
Started May 12 12:52:22 PM PDT 24
Finished May 12 12:52:23 PM PDT 24
Peak memory 216668 kb
Host smart-47f1a70e-3d11-4c85-8684-f0b0147a1e0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718423323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.718423323
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2305659263
Short name T260
Test name
Test status
Simulation time 9770876933 ps
CPU time 16.88 seconds
Started May 12 12:52:32 PM PDT 24
Finished May 12 12:52:50 PM PDT 24
Peak memory 227608 kb
Host smart-2cfef521-69fb-448c-8a8b-f612dec97319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305659263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2305659263
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.377520765
Short name T942
Test name
Test status
Simulation time 447999944 ps
CPU time 6.54 seconds
Started May 12 12:52:37 PM PDT 24
Finished May 12 12:52:43 PM PDT 24
Peak memory 218764 kb
Host smart-a86f7506-6ae5-464f-a8f4-d5348951b18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377520765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.377520765
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3017998611
Short name T652
Test name
Test status
Simulation time 1138488115 ps
CPU time 11.42 seconds
Started May 12 12:52:42 PM PDT 24
Finished May 12 12:52:54 PM PDT 24
Peak memory 222148 kb
Host smart-2b9d1df0-46f7-428f-ac2c-c644098f6636
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3017998611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3017998611
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1148025525
Short name T461
Test name
Test status
Simulation time 40507550 ps
CPU time 1.05 seconds
Started May 12 12:52:42 PM PDT 24
Finished May 12 12:52:44 PM PDT 24
Peak memory 206680 kb
Host smart-9c3a2890-76c9-4657-89ee-79c61708635c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148025525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1148025525
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2344847829
Short name T571
Test name
Test status
Simulation time 6590114497 ps
CPU time 39.01 seconds
Started May 12 12:52:35 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 216748 kb
Host smart-de68e1ee-98cc-4a52-b601-d50884953ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344847829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2344847829
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1489851978
Short name T326
Test name
Test status
Simulation time 655827839 ps
CPU time 3.99 seconds
Started May 12 12:52:28 PM PDT 24
Finished May 12 12:52:33 PM PDT 24
Peak memory 216160 kb
Host smart-2bc360b8-6a54-47a5-a432-c57400146d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489851978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1489851978
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3597669453
Short name T947
Test name
Test status
Simulation time 245203087 ps
CPU time 2.52 seconds
Started May 12 12:52:33 PM PDT 24
Finished May 12 12:52:36 PM PDT 24
Peak memory 216440 kb
Host smart-77325317-4fd7-40b7-b06e-15650b693435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597669453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3597669453
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3738578954
Short name T420
Test name
Test status
Simulation time 153090724 ps
CPU time 0.82 seconds
Started May 12 12:52:29 PM PDT 24
Finished May 12 12:52:30 PM PDT 24
Peak memory 205804 kb
Host smart-19a379b5-07f2-459e-a76f-c0cbb9323283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738578954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3738578954
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2414231117
Short name T39
Test name
Test status
Simulation time 1279806982 ps
CPU time 11.27 seconds
Started May 12 12:52:32 PM PDT 24
Finished May 12 12:52:44 PM PDT 24
Peak memory 234512 kb
Host smart-42b5e9ab-a55a-4452-b772-694ada44928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414231117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2414231117
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3494795035
Short name T328
Test name
Test status
Simulation time 12229884 ps
CPU time 0.76 seconds
Started May 12 12:51:06 PM PDT 24
Finished May 12 12:51:08 PM PDT 24
Peak memory 205248 kb
Host smart-78aa25ba-c8a8-4a2f-9ed8-842e68260d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494795035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
494795035
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4291287227
Short name T201
Test name
Test status
Simulation time 98692006 ps
CPU time 2.66 seconds
Started May 12 12:50:57 PM PDT 24
Finished May 12 12:51:01 PM PDT 24
Peak memory 234652 kb
Host smart-9b61a50e-f429-486e-81d9-324d960e4eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291287227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4291287227
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2006844343
Short name T729
Test name
Test status
Simulation time 18736929 ps
CPU time 0.84 seconds
Started May 12 12:50:53 PM PDT 24
Finished May 12 12:50:55 PM PDT 24
Peak memory 206580 kb
Host smart-b17996d9-45e6-4f4f-9130-5b1fd5e8a465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006844343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2006844343
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.596190444
Short name T228
Test name
Test status
Simulation time 7293515315 ps
CPU time 102.66 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:52:48 PM PDT 24
Peak memory 256440 kb
Host smart-817e37a7-d8f2-4b1a-b6d5-a15e5e5cc745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596190444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.596190444
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3963058395
Short name T828
Test name
Test status
Simulation time 61200978541 ps
CPU time 120.34 seconds
Started May 12 12:51:14 PM PDT 24
Finished May 12 12:53:16 PM PDT 24
Peak memory 240860 kb
Host smart-3f6b770c-ee10-4170-82a9-44b5657ff28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963058395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3963058395
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.626258117
Short name T308
Test name
Test status
Simulation time 3588422323 ps
CPU time 17.47 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:30 PM PDT 24
Peak memory 249264 kb
Host smart-1afd7a27-d49b-4420-a0a4-6c74798a5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626258117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.626258117
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3160095816
Short name T362
Test name
Test status
Simulation time 3382696727 ps
CPU time 8.43 seconds
Started May 12 12:51:02 PM PDT 24
Finished May 12 12:51:11 PM PDT 24
Peak memory 233556 kb
Host smart-a1c2d531-045e-4108-80fa-0e1875a384c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160095816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3160095816
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2924091380
Short name T554
Test name
Test status
Simulation time 451755825 ps
CPU time 2.66 seconds
Started May 12 12:50:57 PM PDT 24
Finished May 12 12:51:01 PM PDT 24
Peak memory 218780 kb
Host smart-6ef7c647-d381-4140-96a5-6085dbe2eacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924091380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2924091380
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2485956292
Short name T9
Test name
Test status
Simulation time 16094362 ps
CPU time 1.02 seconds
Started May 12 12:51:00 PM PDT 24
Finished May 12 12:51:02 PM PDT 24
Peak memory 216628 kb
Host smart-1c162d97-ab54-48b7-a015-3dce20f17c3f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485956292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2485956292
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.533910685
Short name T912
Test name
Test status
Simulation time 25938820726 ps
CPU time 21.61 seconds
Started May 12 12:50:57 PM PDT 24
Finished May 12 12:51:20 PM PDT 24
Peak memory 241056 kb
Host smart-c7fdc374-e6dc-4648-823e-46894f783f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533910685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
533910685
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.809618853
Short name T292
Test name
Test status
Simulation time 444663040 ps
CPU time 2.79 seconds
Started May 12 12:51:12 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 234848 kb
Host smart-31f08efb-8fb8-4702-9777-f77304c3b53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809618853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.809618853
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1414567223
Short name T553
Test name
Test status
Simulation time 1198477393 ps
CPU time 3.57 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:51:09 PM PDT 24
Peak memory 219988 kb
Host smart-77dba92b-e5cb-448a-96c9-9c16b4b85e68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1414567223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1414567223
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.561846034
Short name T81
Test name
Test status
Simulation time 66556460 ps
CPU time 1.04 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:13 PM PDT 24
Peak memory 234920 kb
Host smart-62e63d75-15a7-4913-b913-49c9b97c9f7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561846034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.561846034
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4017530196
Short name T434
Test name
Test status
Simulation time 32887694 ps
CPU time 0.71 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:14 PM PDT 24
Peak memory 205476 kb
Host smart-73199534-f4e0-4c8c-a0db-b8999b9811a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017530196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4017530196
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2784102278
Short name T697
Test name
Test status
Simulation time 1123586792 ps
CPU time 3.23 seconds
Started May 12 12:51:15 PM PDT 24
Finished May 12 12:51:20 PM PDT 24
Peak memory 216204 kb
Host smart-bcde74d6-7414-4719-84d0-46b5ad63c20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784102278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2784102278
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.953082744
Short name T31
Test name
Test status
Simulation time 18850989 ps
CPU time 0.92 seconds
Started May 12 12:51:05 PM PDT 24
Finished May 12 12:51:07 PM PDT 24
Peak memory 206956 kb
Host smart-1ce78b68-0b61-43ef-ba1f-44cf16a72f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953082744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.953082744
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4235470257
Short name T920
Test name
Test status
Simulation time 91598221 ps
CPU time 0.85 seconds
Started May 12 12:51:10 PM PDT 24
Finished May 12 12:51:11 PM PDT 24
Peak memory 205744 kb
Host smart-5878cde1-61a2-4559-ad2a-6223c92e6036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235470257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4235470257
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1157610222
Short name T841
Test name
Test status
Simulation time 398965319 ps
CPU time 3.6 seconds
Started May 12 12:51:10 PM PDT 24
Finished May 12 12:51:15 PM PDT 24
Peak memory 232728 kb
Host smart-424f8b9d-3e74-4635-8a0e-916f536844af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157610222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1157610222
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1890722612
Short name T863
Test name
Test status
Simulation time 12148304 ps
CPU time 0.72 seconds
Started May 12 12:52:39 PM PDT 24
Finished May 12 12:52:40 PM PDT 24
Peak memory 204628 kb
Host smart-f1f1dd89-1360-49a7-863e-30a8b2f246bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890722612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1890722612
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2665140464
Short name T896
Test name
Test status
Simulation time 1527530805 ps
CPU time 2.23 seconds
Started May 12 12:52:42 PM PDT 24
Finished May 12 12:52:45 PM PDT 24
Peak memory 218548 kb
Host smart-45d1960f-fe9d-4773-8c90-14cffb189323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665140464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2665140464
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.402653758
Short name T542
Test name
Test status
Simulation time 38867552 ps
CPU time 0.86 seconds
Started May 12 12:52:36 PM PDT 24
Finished May 12 12:52:37 PM PDT 24
Peak memory 206704 kb
Host smart-4aed7dd5-0ae3-4c0e-9ffb-f6d00334fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402653758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.402653758
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3131148622
Short name T236
Test name
Test status
Simulation time 53481619054 ps
CPU time 390.13 seconds
Started May 12 12:52:42 PM PDT 24
Finished May 12 12:59:13 PM PDT 24
Peak memory 257312 kb
Host smart-151cc7ce-8a8b-4061-b5dd-61921c40a6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131148622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3131148622
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.303440247
Short name T376
Test name
Test status
Simulation time 10606973440 ps
CPU time 73.72 seconds
Started May 12 12:52:44 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 255452 kb
Host smart-f6ee24ef-32c1-4e18-92c5-1db617b262f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303440247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.303440247
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1137628841
Short name T635
Test name
Test status
Simulation time 15561569969 ps
CPU time 126.48 seconds
Started May 12 12:52:48 PM PDT 24
Finished May 12 12:54:56 PM PDT 24
Peak memory 241092 kb
Host smart-f418fa8d-1606-4910-8ef0-861518f1305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137628841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1137628841
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2053243882
Short name T349
Test name
Test status
Simulation time 31504051400 ps
CPU time 23.61 seconds
Started May 12 12:52:46 PM PDT 24
Finished May 12 12:53:10 PM PDT 24
Peak memory 232860 kb
Host smart-10dc7b3b-2777-42de-a214-52b341fcffe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053243882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2053243882
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3201700281
Short name T219
Test name
Test status
Simulation time 127094790 ps
CPU time 3.22 seconds
Started May 12 12:52:45 PM PDT 24
Finished May 12 12:52:49 PM PDT 24
Peak memory 233160 kb
Host smart-0d3c3aa1-8578-4205-b45c-2ed3b40765ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201700281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3201700281
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2122703466
Short name T616
Test name
Test status
Simulation time 2312344274 ps
CPU time 13.49 seconds
Started May 12 12:52:41 PM PDT 24
Finished May 12 12:52:56 PM PDT 24
Peak memory 229740 kb
Host smart-7e8532c8-0029-4a59-99fc-dcb28cc9123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122703466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2122703466
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2238747298
Short name T352
Test name
Test status
Simulation time 72193638 ps
CPU time 2.14 seconds
Started May 12 12:52:41 PM PDT 24
Finished May 12 12:52:44 PM PDT 24
Peak memory 216104 kb
Host smart-0b1a3411-b9c9-493b-8296-4ed400678369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238747298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2238747298
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.514283526
Short name T763
Test name
Test status
Simulation time 10634518023 ps
CPU time 26.38 seconds
Started May 12 12:52:48 PM PDT 24
Finished May 12 12:53:16 PM PDT 24
Peak memory 233616 kb
Host smart-1ee2b248-fa57-4632-bdc3-83e22c4693ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514283526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.514283526
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2834733775
Short name T873
Test name
Test status
Simulation time 1594883262 ps
CPU time 4.08 seconds
Started May 12 12:52:48 PM PDT 24
Finished May 12 12:52:52 PM PDT 24
Peak memory 222744 kb
Host smart-713b5322-8699-4345-ace1-2cacc09fcef9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2834733775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2834733775
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1337528893
Short name T604
Test name
Test status
Simulation time 3985042950 ps
CPU time 5.18 seconds
Started May 12 12:52:33 PM PDT 24
Finished May 12 12:52:39 PM PDT 24
Peak memory 216588 kb
Host smart-ff064dab-7d7c-48d8-9221-70e1817b090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337528893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1337528893
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4064625239
Short name T22
Test name
Test status
Simulation time 1075742741 ps
CPU time 6.38 seconds
Started May 12 12:52:35 PM PDT 24
Finished May 12 12:52:42 PM PDT 24
Peak memory 216488 kb
Host smart-21cbe036-e802-42b0-bf35-447d7d28ddca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064625239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4064625239
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1232263469
Short name T402
Test name
Test status
Simulation time 109126881 ps
CPU time 2.08 seconds
Started May 12 12:52:34 PM PDT 24
Finished May 12 12:52:36 PM PDT 24
Peak memory 216296 kb
Host smart-1313d34c-ea0a-46d6-8282-d28e89b6d682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232263469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1232263469
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.971734631
Short name T487
Test name
Test status
Simulation time 27091959 ps
CPU time 0.74 seconds
Started May 12 12:52:45 PM PDT 24
Finished May 12 12:52:47 PM PDT 24
Peak memory 205432 kb
Host smart-9082b6f9-9189-4948-bd41-af6a306edbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971734631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.971734631
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.417822108
Short name T287
Test name
Test status
Simulation time 3512409629 ps
CPU time 7.53 seconds
Started May 12 12:52:45 PM PDT 24
Finished May 12 12:52:53 PM PDT 24
Peak memory 233792 kb
Host smart-fc8e6197-f3fa-4c34-95ed-853687482f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417822108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.417822108
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3247312545
Short name T795
Test name
Test status
Simulation time 47716354 ps
CPU time 0.75 seconds
Started May 12 12:52:58 PM PDT 24
Finished May 12 12:53:00 PM PDT 24
Peak memory 205276 kb
Host smart-6cd09b6f-43c4-491d-b7dc-ca9a87ccb9a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247312545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3247312545
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.448727489
Short name T799
Test name
Test status
Simulation time 1782519563 ps
CPU time 7.13 seconds
Started May 12 12:52:51 PM PDT 24
Finished May 12 12:52:59 PM PDT 24
Peak memory 233580 kb
Host smart-b7e76df3-b65d-4dfe-9eaf-75f5cea458d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448727489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.448727489
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2169982841
Short name T327
Test name
Test status
Simulation time 32075257 ps
CPU time 0.78 seconds
Started May 12 12:52:51 PM PDT 24
Finished May 12 12:52:53 PM PDT 24
Peak memory 205300 kb
Host smart-24b5a81d-2c0d-4354-b911-393b740feaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169982841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2169982841
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2555691044
Short name T639
Test name
Test status
Simulation time 140419715226 ps
CPU time 102.57 seconds
Started May 12 12:52:46 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 235816 kb
Host smart-416da9f4-fb83-41c8-9f72-91d0ef46efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555691044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2555691044
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1974786933
Short name T224
Test name
Test status
Simulation time 19813993466 ps
CPU time 185.2 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:56:02 PM PDT 24
Peak memory 256144 kb
Host smart-ceb913c5-dce7-4bb1-b78d-29cf8c09ae0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974786933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1974786933
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3330020867
Short name T854
Test name
Test status
Simulation time 141664433896 ps
CPU time 362.58 seconds
Started May 12 12:52:46 PM PDT 24
Finished May 12 12:58:49 PM PDT 24
Peak memory 252804 kb
Host smart-3a90d6d8-9925-41cd-8f09-0ff5af6a62cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330020867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3330020867
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3198735197
Short name T972
Test name
Test status
Simulation time 95550736 ps
CPU time 4.15 seconds
Started May 12 12:52:45 PM PDT 24
Finished May 12 12:52:50 PM PDT 24
Peak memory 232652 kb
Host smart-d39dcb10-5a61-46ce-bb31-b8a8e0bf324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198735197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3198735197
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.836081781
Short name T945
Test name
Test status
Simulation time 461637775 ps
CPU time 3.36 seconds
Started May 12 12:52:44 PM PDT 24
Finished May 12 12:52:48 PM PDT 24
Peak memory 219456 kb
Host smart-0eacabc5-cf62-4fc0-beac-00c818846e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836081781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.836081781
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3212077155
Short name T529
Test name
Test status
Simulation time 2641148617 ps
CPU time 29.84 seconds
Started May 12 12:52:49 PM PDT 24
Finished May 12 12:53:20 PM PDT 24
Peak memory 240976 kb
Host smart-c497b513-35e5-482d-b586-5cfe31c75f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212077155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3212077155
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2475384407
Short name T839
Test name
Test status
Simulation time 2312197216 ps
CPU time 6.31 seconds
Started May 12 12:52:51 PM PDT 24
Finished May 12 12:52:59 PM PDT 24
Peak memory 237892 kb
Host smart-f5f598f5-5111-4b31-968b-f78495828fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475384407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2475384407
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4035907184
Short name T552
Test name
Test status
Simulation time 29338067 ps
CPU time 1.98 seconds
Started May 12 12:52:49 PM PDT 24
Finished May 12 12:52:53 PM PDT 24
Peak memory 216072 kb
Host smart-29f803e6-70ee-403c-aabf-da9420c95cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035907184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4035907184
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1643413155
Short name T930
Test name
Test status
Simulation time 143920922 ps
CPU time 4.02 seconds
Started May 12 12:52:46 PM PDT 24
Finished May 12 12:52:51 PM PDT 24
Peak memory 220444 kb
Host smart-195442bf-3e46-4428-8eb9-aaa8282a3105
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1643413155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1643413155
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2609830790
Short name T800
Test name
Test status
Simulation time 2120199648 ps
CPU time 43.26 seconds
Started May 12 12:53:00 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 238220 kb
Host smart-fe45a172-a1d2-469a-8014-2343cf1c10e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609830790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2609830790
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3714612505
Short name T849
Test name
Test status
Simulation time 9330871491 ps
CPU time 15.21 seconds
Started May 12 12:52:54 PM PDT 24
Finished May 12 12:53:11 PM PDT 24
Peak memory 216436 kb
Host smart-7f5470a3-1e18-44e9-b449-b0a790a0c9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714612505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3714612505
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3003574264
Short name T407
Test name
Test status
Simulation time 14346557 ps
CPU time 0.72 seconds
Started May 12 12:52:49 PM PDT 24
Finished May 12 12:52:51 PM PDT 24
Peak memory 205476 kb
Host smart-8adc453b-bc29-4bcc-a717-67f0d57b5e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003574264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3003574264
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4072817966
Short name T602
Test name
Test status
Simulation time 828516600 ps
CPU time 6.69 seconds
Started May 12 12:52:50 PM PDT 24
Finished May 12 12:52:57 PM PDT 24
Peak memory 216460 kb
Host smart-f83c06c4-3e65-4370-93ed-488e770b3b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072817966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4072817966
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2485078495
Short name T883
Test name
Test status
Simulation time 25365076 ps
CPU time 0.7 seconds
Started May 12 12:52:49 PM PDT 24
Finished May 12 12:52:51 PM PDT 24
Peak memory 205364 kb
Host smart-5f70c8b1-2f4e-4439-8457-7629e20850c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485078495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2485078495
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.427237526
Short name T365
Test name
Test status
Simulation time 77631894365 ps
CPU time 59.22 seconds
Started May 12 12:52:52 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 249096 kb
Host smart-a0e8e5d5-1fcb-42d9-8b04-6e200d642f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427237526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.427237526
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.532821238
Short name T630
Test name
Test status
Simulation time 66090619 ps
CPU time 0.71 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:52:57 PM PDT 24
Peak memory 204688 kb
Host smart-0bcc2c08-60a7-406a-a831-663925ee988c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532821238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.532821238
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2258439704
Short name T425
Test name
Test status
Simulation time 1200074515 ps
CPU time 4.87 seconds
Started May 12 12:52:53 PM PDT 24
Finished May 12 12:52:59 PM PDT 24
Peak memory 234180 kb
Host smart-098293d0-0b86-49e5-a33d-0352bca3598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258439704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2258439704
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.945078908
Short name T523
Test name
Test status
Simulation time 18187317 ps
CPU time 0.81 seconds
Started May 12 12:53:01 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 206380 kb
Host smart-01ae7caa-8dcc-4233-843c-c84475c40cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945078908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.945078908
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2175041348
Short name T469
Test name
Test status
Simulation time 38255826630 ps
CPU time 52.67 seconds
Started May 12 12:52:50 PM PDT 24
Finished May 12 12:53:44 PM PDT 24
Peak memory 253504 kb
Host smart-abd1054a-2496-492c-92b8-8bb0e5e8e4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175041348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2175041348
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.507188579
Short name T751
Test name
Test status
Simulation time 6528639866 ps
CPU time 29.32 seconds
Started May 12 12:52:53 PM PDT 24
Finished May 12 12:53:23 PM PDT 24
Peak memory 232900 kb
Host smart-beb46161-f802-4a1f-bd25-7a2fe14e0ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507188579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.507188579
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.668136756
Short name T176
Test name
Test status
Simulation time 35602232884 ps
CPU time 61.23 seconds
Started May 12 12:52:52 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 252460 kb
Host smart-93709af0-b149-4050-8aa8-63811c376527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668136756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.668136756
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1955951762
Short name T654
Test name
Test status
Simulation time 167945159 ps
CPU time 3.18 seconds
Started May 12 12:52:50 PM PDT 24
Finished May 12 12:52:54 PM PDT 24
Peak memory 224652 kb
Host smart-8380d121-20b4-4531-8ea7-07891f4f1b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955951762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1955951762
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1266281590
Short name T611
Test name
Test status
Simulation time 400854083 ps
CPU time 5.43 seconds
Started May 12 12:52:50 PM PDT 24
Finished May 12 12:52:57 PM PDT 24
Peak memory 235160 kb
Host smart-0ef7400b-ff7f-4730-b73f-6ea87e66c0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266281590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1266281590
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2033073862
Short name T115
Test name
Test status
Simulation time 2673725405 ps
CPU time 33.57 seconds
Started May 12 12:52:58 PM PDT 24
Finished May 12 12:53:33 PM PDT 24
Peak memory 248828 kb
Host smart-d8411f8f-a57e-4ec8-8f34-e07bf62c0811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033073862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2033073862
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.322991488
Short name T223
Test name
Test status
Simulation time 58742990387 ps
CPU time 38.59 seconds
Started May 12 12:52:54 PM PDT 24
Finished May 12 12:53:33 PM PDT 24
Peak memory 248868 kb
Host smart-d134b994-f8c4-45ef-9544-f4a819cdc375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322991488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.322991488
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2635961625
Short name T527
Test name
Test status
Simulation time 573749924 ps
CPU time 3.64 seconds
Started May 12 12:52:53 PM PDT 24
Finished May 12 12:52:58 PM PDT 24
Peak memory 232748 kb
Host smart-d43707aa-8e7e-4437-81a7-2057a0687ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635961625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2635961625
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1132457098
Short name T439
Test name
Test status
Simulation time 1170941403 ps
CPU time 11.05 seconds
Started May 12 12:53:01 PM PDT 24
Finished May 12 12:53:13 PM PDT 24
Peak memory 220032 kb
Host smart-a5c8b3d3-b0e6-4d7b-aa6b-18ecf5ecb486
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132457098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1132457098
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.159816761
Short name T189
Test name
Test status
Simulation time 1611169397 ps
CPU time 19.84 seconds
Started May 12 12:52:54 PM PDT 24
Finished May 12 12:53:15 PM PDT 24
Peak memory 224616 kb
Host smart-5bf403c8-7931-4b7f-8859-21c0bbb5855b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159816761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.159816761
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1547741816
Short name T321
Test name
Test status
Simulation time 670512160 ps
CPU time 3.47 seconds
Started May 12 12:52:56 PM PDT 24
Finished May 12 12:53:01 PM PDT 24
Peak memory 216316 kb
Host smart-a8724a6f-f100-42c8-a953-7df9ee9c18ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547741816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1547741816
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2776304340
Short name T367
Test name
Test status
Simulation time 1919659763 ps
CPU time 4.59 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:53:01 PM PDT 24
Peak memory 216324 kb
Host smart-3a915095-3793-403f-abdf-ec5318ad0eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776304340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2776304340
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2308566899
Short name T551
Test name
Test status
Simulation time 782353764 ps
CPU time 3.71 seconds
Started May 12 12:52:58 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 216448 kb
Host smart-c5464abe-3d35-4892-9dcb-98e4d7fe437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308566899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2308566899
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4045229001
Short name T951
Test name
Test status
Simulation time 158042887 ps
CPU time 0.85 seconds
Started May 12 12:52:52 PM PDT 24
Finished May 12 12:52:54 PM PDT 24
Peak memory 205836 kb
Host smart-95db4df4-bc9d-4ed0-85dd-09b21ea60598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045229001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4045229001
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2026158845
Short name T637
Test name
Test status
Simulation time 1827947622 ps
CPU time 6.75 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 229560 kb
Host smart-08a42125-3cc4-4c44-8adf-5188f5de4bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026158845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2026158845
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2211314484
Short name T528
Test name
Test status
Simulation time 32893396 ps
CPU time 0.76 seconds
Started May 12 12:53:02 PM PDT 24
Finished May 12 12:53:04 PM PDT 24
Peak memory 205364 kb
Host smart-22d86255-0bbe-4418-b7bf-4ad029c55e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211314484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2211314484
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2270429106
Short name T222
Test name
Test status
Simulation time 486049778 ps
CPU time 3.4 seconds
Started May 12 12:52:57 PM PDT 24
Finished May 12 12:53:02 PM PDT 24
Peak memory 219492 kb
Host smart-0a5eff61-3874-4f5a-b971-fea4b5ed8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270429106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2270429106
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.907102444
Short name T918
Test name
Test status
Simulation time 22849541 ps
CPU time 0.75 seconds
Started May 12 12:52:56 PM PDT 24
Finished May 12 12:52:58 PM PDT 24
Peak memory 206404 kb
Host smart-ce083116-2d77-4fc2-b91e-033768e5c922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907102444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.907102444
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1721917186
Short name T563
Test name
Test status
Simulation time 5045511316 ps
CPU time 33.7 seconds
Started May 12 12:52:50 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 224624 kb
Host smart-4a70a1e3-b18a-409e-9346-600d4e818e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721917186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1721917186
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3046730097
Short name T819
Test name
Test status
Simulation time 5918082260 ps
CPU time 21.01 seconds
Started May 12 12:53:00 PM PDT 24
Finished May 12 12:53:23 PM PDT 24
Peak memory 241108 kb
Host smart-b517a4fc-3c59-47a9-863d-2ed4fbcd59b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046730097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3046730097
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2737318253
Short name T239
Test name
Test status
Simulation time 14779844556 ps
CPU time 153.27 seconds
Started May 12 12:52:51 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 250288 kb
Host smart-b6922196-2ed4-49b0-ba59-a89941e94e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737318253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2737318253
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2884282071
Short name T313
Test name
Test status
Simulation time 1674690087 ps
CPU time 23.44 seconds
Started May 12 12:52:56 PM PDT 24
Finished May 12 12:53:21 PM PDT 24
Peak memory 224320 kb
Host smart-83ee9267-73cf-47af-b944-0c3bc566083e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884282071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2884282071
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3964112410
Short name T617
Test name
Test status
Simulation time 15545990085 ps
CPU time 15.15 seconds
Started May 12 12:52:48 PM PDT 24
Finished May 12 12:53:04 PM PDT 24
Peak memory 233848 kb
Host smart-9e311f69-042b-4149-8155-150862ca7717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964112410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3964112410
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.450723026
Short name T957
Test name
Test status
Simulation time 538338905 ps
CPU time 9.73 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:53:10 PM PDT 24
Peak memory 219172 kb
Host smart-116c37e8-82c3-4f8e-ab95-58e039519fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450723026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.450723026
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3672689209
Short name T194
Test name
Test status
Simulation time 1644055350 ps
CPU time 7.4 seconds
Started May 12 12:52:54 PM PDT 24
Finished May 12 12:53:02 PM PDT 24
Peak memory 237336 kb
Host smart-33c7812f-fbd2-42f7-bc2e-bd41108e54a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672689209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3672689209
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4227152894
Short name T663
Test name
Test status
Simulation time 903175065 ps
CPU time 4.25 seconds
Started May 12 12:52:49 PM PDT 24
Finished May 12 12:52:54 PM PDT 24
Peak memory 218532 kb
Host smart-12a91899-f4bf-41b5-8bac-f3282bf3683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227152894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4227152894
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2531153191
Short name T445
Test name
Test status
Simulation time 968108599 ps
CPU time 10.79 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:53:11 PM PDT 24
Peak memory 219984 kb
Host smart-ad316c98-2ec9-4064-a930-6d01e8a77e53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2531153191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2531153191
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1927075705
Short name T165
Test name
Test status
Simulation time 4324196997 ps
CPU time 27.83 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:53:28 PM PDT 24
Peak memory 239468 kb
Host smart-01180160-e8f0-47f5-8cd5-2b2a6bd1e446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927075705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1927075705
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1927317158
Short name T822
Test name
Test status
Simulation time 1657269863 ps
CPU time 16.48 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:53:12 PM PDT 24
Peak memory 216284 kb
Host smart-0737c7b8-f3f2-4b11-a642-a9217e3ef467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927317158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1927317158
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.716422258
Short name T753
Test name
Test status
Simulation time 782662378 ps
CPU time 2.57 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:52:59 PM PDT 24
Peak memory 216124 kb
Host smart-97a916b0-5561-488c-b057-660677aea3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716422258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.716422258
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3403177259
Short name T814
Test name
Test status
Simulation time 278871297 ps
CPU time 1.52 seconds
Started May 12 12:52:54 PM PDT 24
Finished May 12 12:52:56 PM PDT 24
Peak memory 216340 kb
Host smart-9c795f2f-10e4-48eb-86ef-db1ba5b9f59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403177259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3403177259
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3589200303
Short name T869
Test name
Test status
Simulation time 42535961 ps
CPU time 0.77 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:53:01 PM PDT 24
Peak memory 205764 kb
Host smart-839ffc06-cddf-4c0b-9654-c1c7c928404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589200303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3589200303
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.709621965
Short name T746
Test name
Test status
Simulation time 2549915780 ps
CPU time 9.98 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:53:10 PM PDT 24
Peak memory 235532 kb
Host smart-92c15b36-1812-4eda-89dd-eda63c084ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709621965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.709621965
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1473856197
Short name T418
Test name
Test status
Simulation time 31444217 ps
CPU time 0.76 seconds
Started May 12 12:53:08 PM PDT 24
Finished May 12 12:53:09 PM PDT 24
Peak memory 205232 kb
Host smart-6b2f58af-08ec-4d35-b872-ebc95a5021d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473856197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1473856197
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2594412722
Short name T330
Test name
Test status
Simulation time 1710780199 ps
CPU time 15.85 seconds
Started May 12 12:53:03 PM PDT 24
Finished May 12 12:53:20 PM PDT 24
Peak memory 235208 kb
Host smart-66b37e1c-f39b-4074-8d8b-ddf80eba5536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594412722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2594412722
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4108171936
Short name T477
Test name
Test status
Simulation time 36585221 ps
CPU time 0.81 seconds
Started May 12 12:52:52 PM PDT 24
Finished May 12 12:52:54 PM PDT 24
Peak memory 206276 kb
Host smart-3ca1efb3-edc0-44db-ae02-3b2e1c6203aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108171936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4108171936
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2838810246
Short name T225
Test name
Test status
Simulation time 103409287284 ps
CPU time 201.23 seconds
Started May 12 12:52:57 PM PDT 24
Finished May 12 12:56:19 PM PDT 24
Peak memory 249324 kb
Host smart-a39867db-adcf-47b7-9e3e-6e7b0b04692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838810246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2838810246
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1607585068
Short name T259
Test name
Test status
Simulation time 25614247758 ps
CPU time 104.69 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 250332 kb
Host smart-3a14076b-c916-43f8-b174-a3f501b8849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607585068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1607585068
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.916413186
Short name T556
Test name
Test status
Simulation time 413449438661 ps
CPU time 270.97 seconds
Started May 12 12:52:59 PM PDT 24
Finished May 12 12:57:32 PM PDT 24
Peak memory 249264 kb
Host smart-ac92723a-ba27-4c65-a386-6b329b82eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916413186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.916413186
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.52815434
Short name T395
Test name
Test status
Simulation time 1287044726 ps
CPU time 14.63 seconds
Started May 12 12:52:54 PM PDT 24
Finished May 12 12:53:10 PM PDT 24
Peak memory 232728 kb
Host smart-7346ea8a-14fa-4f1e-b69b-6b58d9a1c4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52815434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.52815434
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.108442627
Short name T503
Test name
Test status
Simulation time 1090390438 ps
CPU time 11.66 seconds
Started May 12 12:53:01 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 219520 kb
Host smart-44bebe7e-d224-458c-801f-53178430fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108442627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.108442627
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2561018515
Short name T296
Test name
Test status
Simulation time 10193286999 ps
CPU time 82.42 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:54:19 PM PDT 24
Peak memory 233556 kb
Host smart-257429ca-ed4d-4fe3-b7ec-f7af21a8bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561018515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2561018515
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1187564105
Short name T36
Test name
Test status
Simulation time 1277589516 ps
CPU time 7 seconds
Started May 12 12:53:04 PM PDT 24
Finished May 12 12:53:12 PM PDT 24
Peak memory 234708 kb
Host smart-bdd0d9f3-77da-49df-8c57-91aa0b2cc5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187564105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1187564105
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.729924487
Short name T894
Test name
Test status
Simulation time 2186757681 ps
CPU time 8.66 seconds
Started May 12 12:53:03 PM PDT 24
Finished May 12 12:53:13 PM PDT 24
Peak memory 229816 kb
Host smart-6af0bd21-12f5-4eda-aaec-45c66f25393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729924487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.729924487
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.642129905
Short name T366
Test name
Test status
Simulation time 800676473 ps
CPU time 5.57 seconds
Started May 12 12:53:04 PM PDT 24
Finished May 12 12:53:11 PM PDT 24
Peak memory 222452 kb
Host smart-f16cca71-266d-4796-b36e-ce145d47292d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=642129905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.642129905
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.337172136
Short name T163
Test name
Test status
Simulation time 75663569 ps
CPU time 0.97 seconds
Started May 12 12:53:10 PM PDT 24
Finished May 12 12:53:12 PM PDT 24
Peak memory 206416 kb
Host smart-a3ca2bdb-4098-41c7-a6c2-2279222b6fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337172136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.337172136
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3745863358
Short name T317
Test name
Test status
Simulation time 35512298115 ps
CPU time 49.04 seconds
Started May 12 12:53:00 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 216412 kb
Host smart-46290040-8542-43df-bb53-110e8ae1440b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745863358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3745863358
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2027023965
Short name T815
Test name
Test status
Simulation time 258643017 ps
CPU time 2.96 seconds
Started May 12 12:53:00 PM PDT 24
Finished May 12 12:53:04 PM PDT 24
Peak memory 216280 kb
Host smart-79918362-83d9-404f-a3fa-c718f7682b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027023965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2027023965
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1866974310
Short name T778
Test name
Test status
Simulation time 418599382 ps
CPU time 5.21 seconds
Started May 12 12:52:57 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 216288 kb
Host smart-3b7a936d-d857-47a2-ac95-2a69ee1b9fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866974310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1866974310
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2229805556
Short name T575
Test name
Test status
Simulation time 64335248 ps
CPU time 0.7 seconds
Started May 12 12:52:55 PM PDT 24
Finished May 12 12:52:57 PM PDT 24
Peak memory 205720 kb
Host smart-d32739ed-a683-4757-88b2-6f53f7b9da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229805556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2229805556
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.163685796
Short name T207
Test name
Test status
Simulation time 48383540719 ps
CPU time 27.27 seconds
Started May 12 12:52:57 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 217568 kb
Host smart-b9af0267-c75b-49db-9567-5e25aa37031c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163685796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.163685796
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.675099547
Short name T357
Test name
Test status
Simulation time 39348107 ps
CPU time 0.72 seconds
Started May 12 12:53:08 PM PDT 24
Finished May 12 12:53:09 PM PDT 24
Peak memory 204752 kb
Host smart-7441a4d7-6aeb-42b1-b639-594142aafeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675099547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.675099547
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2183431512
Short name T511
Test name
Test status
Simulation time 417138217 ps
CPU time 3.47 seconds
Started May 12 12:53:12 PM PDT 24
Finished May 12 12:53:16 PM PDT 24
Peak memory 218732 kb
Host smart-5896e507-d4bb-4012-8b5e-b66bf95b3082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183431512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2183431512
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3485063467
Short name T324
Test name
Test status
Simulation time 20899837 ps
CPU time 0.8 seconds
Started May 12 12:53:03 PM PDT 24
Finished May 12 12:53:05 PM PDT 24
Peak memory 206664 kb
Host smart-c16aefc7-08d9-4936-b1e5-fad8edb68255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485063467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3485063467
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3230295967
Short name T267
Test name
Test status
Simulation time 2939443325 ps
CPU time 36 seconds
Started May 12 12:53:05 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 252848 kb
Host smart-c6a8f6e3-d70b-4b70-9feb-4b303a945387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230295967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3230295967
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1640984399
Short name T966
Test name
Test status
Simulation time 32219219260 ps
CPU time 291.46 seconds
Started May 12 12:53:11 PM PDT 24
Finished May 12 12:58:04 PM PDT 24
Peak memory 253756 kb
Host smart-076f50c7-483b-415e-bbff-ed78d603fb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640984399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1640984399
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3864764921
Short name T783
Test name
Test status
Simulation time 255606850 ps
CPU time 4.04 seconds
Started May 12 12:53:12 PM PDT 24
Finished May 12 12:53:17 PM PDT 24
Peak memory 224456 kb
Host smart-d0901344-1628-441c-a81e-1e4c5592cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864764921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3864764921
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1864476119
Short name T640
Test name
Test status
Simulation time 5693107073 ps
CPU time 26.98 seconds
Started May 12 12:53:04 PM PDT 24
Finished May 12 12:53:32 PM PDT 24
Peak memory 218936 kb
Host smart-0915262b-1647-471b-8a38-dcd92f275672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864476119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1864476119
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3388429334
Short name T286
Test name
Test status
Simulation time 5227385524 ps
CPU time 36.15 seconds
Started May 12 12:53:02 PM PDT 24
Finished May 12 12:53:39 PM PDT 24
Peak memory 237240 kb
Host smart-845bab5b-24a6-47eb-a202-2fc05748abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388429334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3388429334
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.284587500
Short name T964
Test name
Test status
Simulation time 16556787438 ps
CPU time 30.77 seconds
Started May 12 12:53:08 PM PDT 24
Finished May 12 12:53:40 PM PDT 24
Peak memory 236252 kb
Host smart-c8553783-c5f2-4b54-9e05-abaed3004003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284587500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.284587500
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3961635380
Short name T944
Test name
Test status
Simulation time 551799881 ps
CPU time 4.22 seconds
Started May 12 12:53:02 PM PDT 24
Finished May 12 12:53:07 PM PDT 24
Peak memory 233640 kb
Host smart-aaa20e30-8599-47c5-a405-9d437f390ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961635380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3961635380
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.582525011
Short name T971
Test name
Test status
Simulation time 1806995306 ps
CPU time 7.45 seconds
Started May 12 12:53:09 PM PDT 24
Finished May 12 12:53:17 PM PDT 24
Peak memory 222316 kb
Host smart-ebbbfd28-9852-44d2-9f4d-c0afa9106d8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=582525011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.582525011
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1165830153
Short name T974
Test name
Test status
Simulation time 20242979048 ps
CPU time 152.2 seconds
Started May 12 12:53:05 PM PDT 24
Finished May 12 12:55:38 PM PDT 24
Peak memory 250328 kb
Host smart-5eae2e72-6a55-4461-9db0-00084251addc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165830153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1165830153
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.671009207
Short name T688
Test name
Test status
Simulation time 5208524669 ps
CPU time 26.12 seconds
Started May 12 12:53:09 PM PDT 24
Finished May 12 12:53:37 PM PDT 24
Peak memory 216428 kb
Host smart-e8e35715-046d-4529-8b4f-0099ac4e6d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671009207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.671009207
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3647439077
Short name T543
Test name
Test status
Simulation time 1633244498 ps
CPU time 7.62 seconds
Started May 12 12:53:10 PM PDT 24
Finished May 12 12:53:18 PM PDT 24
Peak memory 216288 kb
Host smart-080b87e1-02ef-43f2-94a9-5ae049a8d457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647439077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3647439077
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1127168884
Short name T733
Test name
Test status
Simulation time 55165852 ps
CPU time 2.29 seconds
Started May 12 12:53:03 PM PDT 24
Finished May 12 12:53:06 PM PDT 24
Peak memory 216660 kb
Host smart-2b43075e-e121-4034-8b71-be37cd7b13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127168884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1127168884
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3699060930
Short name T895
Test name
Test status
Simulation time 63330744 ps
CPU time 0.74 seconds
Started May 12 12:53:01 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 205704 kb
Host smart-cb6c89c6-b1ee-44f0-bf84-bae4bbd1bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699060930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3699060930
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3245282946
Short name T954
Test name
Test status
Simulation time 14098962304 ps
CPU time 10.98 seconds
Started May 12 12:53:02 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 232428 kb
Host smart-e6989262-b7c4-43f8-982a-565608ad2d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245282946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3245282946
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.397568971
Short name T836
Test name
Test status
Simulation time 12830564 ps
CPU time 0.71 seconds
Started May 12 12:53:12 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 205692 kb
Host smart-4ab9f4cb-e22e-4ada-b3ef-4b2bb53a5b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397568971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.397568971
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1688508499
Short name T537
Test name
Test status
Simulation time 1061812803 ps
CPU time 2.93 seconds
Started May 12 12:53:11 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 219576 kb
Host smart-45a79eb9-231e-4f23-a8f5-a1d277286ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688508499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1688508499
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3059652118
Short name T780
Test name
Test status
Simulation time 23491060 ps
CPU time 0.77 seconds
Started May 12 12:53:11 PM PDT 24
Finished May 12 12:53:13 PM PDT 24
Peak memory 206356 kb
Host smart-b163f36b-e0d7-4a54-8936-38978d3d08d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059652118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3059652118
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.29127258
Short name T46
Test name
Test status
Simulation time 353733457310 ps
CPU time 215.75 seconds
Started May 12 12:53:13 PM PDT 24
Finished May 12 12:56:50 PM PDT 24
Peak memory 238212 kb
Host smart-7160045b-3540-4250-9135-24c15076bb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29127258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.29127258
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1383490124
Short name T696
Test name
Test status
Simulation time 824265892 ps
CPU time 17.92 seconds
Started May 12 12:53:23 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 221616 kb
Host smart-7d16eb77-946b-4d53-b2eb-06db71e51afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383490124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1383490124
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3440565029
Short name T64
Test name
Test status
Simulation time 14181077467 ps
CPU time 83.72 seconds
Started May 12 12:53:11 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 257468 kb
Host smart-27d2db56-d859-42d1-bae2-64a5ab0d7b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440565029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3440565029
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2708125234
Short name T605
Test name
Test status
Simulation time 2456190358 ps
CPU time 11.4 seconds
Started May 12 12:53:16 PM PDT 24
Finished May 12 12:53:28 PM PDT 24
Peak memory 241052 kb
Host smart-1fead82f-39cf-46d8-9493-177c2cef4755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708125234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2708125234
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2916809795
Short name T472
Test name
Test status
Simulation time 1103025581 ps
CPU time 10.55 seconds
Started May 12 12:53:13 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 224384 kb
Host smart-0d287068-2e3d-4e81-8fb0-3c2eac68e67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916809795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2916809795
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1008885501
Short name T656
Test name
Test status
Simulation time 14600155082 ps
CPU time 135.93 seconds
Started May 12 12:53:11 PM PDT 24
Finished May 12 12:55:28 PM PDT 24
Peak memory 238212 kb
Host smart-1a5027cc-7bc2-4f29-aa27-0576dde2cc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008885501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1008885501
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2027812445
Short name T695
Test name
Test status
Simulation time 1492287717 ps
CPU time 6.82 seconds
Started May 12 12:53:09 PM PDT 24
Finished May 12 12:53:17 PM PDT 24
Peak memory 218836 kb
Host smart-db994490-eed8-4992-82e4-ec8b3b68df50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027812445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2027812445
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2244776522
Short name T441
Test name
Test status
Simulation time 16900638142 ps
CPU time 10.75 seconds
Started May 12 12:53:15 PM PDT 24
Finished May 12 12:53:27 PM PDT 24
Peak memory 216900 kb
Host smart-b26694a5-4499-4c48-a5ba-347e3439de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244776522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2244776522
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1672779850
Short name T823
Test name
Test status
Simulation time 82573780 ps
CPU time 3.76 seconds
Started May 12 12:53:18 PM PDT 24
Finished May 12 12:53:22 PM PDT 24
Peak memory 222900 kb
Host smart-76bff88a-6ddb-4510-9cf3-c6d20027a46f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1672779850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1672779850
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3428806831
Short name T474
Test name
Test status
Simulation time 42868354 ps
CPU time 1.08 seconds
Started May 12 12:53:11 PM PDT 24
Finished May 12 12:53:13 PM PDT 24
Peak memory 207012 kb
Host smart-826810fe-ba83-411f-a8bc-1ec1e178972c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428806831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3428806831
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2581250992
Short name T433
Test name
Test status
Simulation time 15688982080 ps
CPU time 15.62 seconds
Started May 12 12:53:14 PM PDT 24
Finished May 12 12:53:30 PM PDT 24
Peak memory 216400 kb
Host smart-421e5653-b984-4786-b206-01eb0c59ebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581250992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2581250992
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2366919062
Short name T598
Test name
Test status
Simulation time 7255431128 ps
CPU time 7.74 seconds
Started May 12 12:53:09 PM PDT 24
Finished May 12 12:53:18 PM PDT 24
Peak memory 216528 kb
Host smart-b7bd191e-a354-4b9e-80d6-4364249449d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366919062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2366919062
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1214019028
Short name T449
Test name
Test status
Simulation time 365038505 ps
CPU time 1.63 seconds
Started May 12 12:53:13 PM PDT 24
Finished May 12 12:53:16 PM PDT 24
Peak memory 216304 kb
Host smart-0bc139c7-2d13-4988-abda-df7272cdc560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214019028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1214019028
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2100523587
Short name T958
Test name
Test status
Simulation time 31897334 ps
CPU time 0.77 seconds
Started May 12 12:53:09 PM PDT 24
Finished May 12 12:53:10 PM PDT 24
Peak memory 205716 kb
Host smart-a06292a2-83df-478e-9647-02b16363e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100523587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2100523587
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2043247861
Short name T837
Test name
Test status
Simulation time 10234652042 ps
CPU time 11.17 seconds
Started May 12 12:53:13 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 228928 kb
Host smart-de2429d8-7fd5-4d9d-9160-ab60cfdf79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043247861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2043247861
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.102173797
Short name T340
Test name
Test status
Simulation time 17170193 ps
CPU time 0.73 seconds
Started May 12 12:53:17 PM PDT 24
Finished May 12 12:53:19 PM PDT 24
Peak memory 204620 kb
Host smart-e4fd3105-f2a1-4845-a20e-67a4731d4723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102173797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.102173797
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2835731265
Short name T885
Test name
Test status
Simulation time 731697596 ps
CPU time 9.46 seconds
Started May 12 12:53:22 PM PDT 24
Finished May 12 12:53:32 PM PDT 24
Peak memory 219872 kb
Host smart-0431b600-6f6d-4251-8039-cbdb9bd80247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835731265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2835731265
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2581894814
Short name T333
Test name
Test status
Simulation time 17283482 ps
CPU time 0.78 seconds
Started May 12 12:53:12 PM PDT 24
Finished May 12 12:53:14 PM PDT 24
Peak memory 205400 kb
Host smart-83eb8537-4b60-41c5-9068-071ff28c75ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581894814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2581894814
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.592493975
Short name T181
Test name
Test status
Simulation time 528325135523 ps
CPU time 557.28 seconds
Started May 12 12:53:27 PM PDT 24
Finished May 12 01:02:45 PM PDT 24
Peak memory 252068 kb
Host smart-d7ea23fd-fb2d-44ad-b68b-4b8ecd475b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592493975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.592493975
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.698120398
Short name T234
Test name
Test status
Simulation time 303730030270 ps
CPU time 435.72 seconds
Started May 12 12:53:35 PM PDT 24
Finished May 12 01:00:51 PM PDT 24
Peak memory 249624 kb
Host smart-896d44f2-0a59-4de2-adfc-a4e3618304cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698120398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.698120398
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2799206574
Short name T277
Test name
Test status
Simulation time 29565259028 ps
CPU time 277.34 seconds
Started May 12 12:53:17 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 265732 kb
Host smart-cb2bb4d7-0b0f-43bd-9fd8-622611f0d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799206574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2799206574
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1520863976
Short name T307
Test name
Test status
Simulation time 293653954 ps
CPU time 9.6 seconds
Started May 12 12:53:23 PM PDT 24
Finished May 12 12:53:34 PM PDT 24
Peak memory 240896 kb
Host smart-55379c1d-f374-4db2-8fe3-d63b723869f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520863976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1520863976
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3787555069
Short name T493
Test name
Test status
Simulation time 4698748952 ps
CPU time 17.15 seconds
Started May 12 12:53:13 PM PDT 24
Finished May 12 12:53:31 PM PDT 24
Peak memory 224516 kb
Host smart-32617592-43c7-4185-9bf2-9d20b615e305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787555069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3787555069
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2740820362
Short name T545
Test name
Test status
Simulation time 1302776407 ps
CPU time 6.31 seconds
Started May 12 12:53:23 PM PDT 24
Finished May 12 12:53:30 PM PDT 24
Peak memory 234596 kb
Host smart-41646dc0-4d01-4530-934e-69a33e4120d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740820362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2740820362
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4215282599
Short name T625
Test name
Test status
Simulation time 115508440 ps
CPU time 3 seconds
Started May 12 12:53:37 PM PDT 24
Finished May 12 12:53:41 PM PDT 24
Peak memory 218876 kb
Host smart-e941dccd-56b9-4efd-9b4e-d8e0356066bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215282599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4215282599
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2360601563
Short name T842
Test name
Test status
Simulation time 1638049475 ps
CPU time 5.03 seconds
Started May 12 12:53:16 PM PDT 24
Finished May 12 12:53:22 PM PDT 24
Peak memory 233604 kb
Host smart-0cc2770a-de9e-4c01-bc56-caf76aaae7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360601563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2360601563
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1473360384
Short name T846
Test name
Test status
Simulation time 352827029 ps
CPU time 5.41 seconds
Started May 12 12:53:18 PM PDT 24
Finished May 12 12:53:23 PM PDT 24
Peak memory 218744 kb
Host smart-23e0ec09-634b-4a98-b7bd-29c076d20d58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1473360384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1473360384
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3846577851
Short name T443
Test name
Test status
Simulation time 4411826426 ps
CPU time 29.68 seconds
Started May 12 12:53:13 PM PDT 24
Finished May 12 12:53:44 PM PDT 24
Peak memory 216424 kb
Host smart-a472b823-b1b9-41e6-984d-eaa9948acbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846577851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3846577851
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1681188615
Short name T457
Test name
Test status
Simulation time 8829084142 ps
CPU time 7.51 seconds
Started May 12 12:53:10 PM PDT 24
Finished May 12 12:53:23 PM PDT 24
Peak memory 216480 kb
Host smart-45f8ed88-a433-4f1f-9cb5-898f89f70b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681188615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1681188615
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3952124003
Short name T812
Test name
Test status
Simulation time 333837285 ps
CPU time 2.48 seconds
Started May 12 12:53:27 PM PDT 24
Finished May 12 12:53:31 PM PDT 24
Peak memory 216284 kb
Host smart-b750cd98-daed-4562-9af8-c708d5cdb74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952124003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3952124003
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1295203119
Short name T891
Test name
Test status
Simulation time 158610335 ps
CPU time 0.87 seconds
Started May 12 12:53:20 PM PDT 24
Finished May 12 12:53:21 PM PDT 24
Peak memory 206748 kb
Host smart-ce5fb35d-c29c-4b93-a23f-177c1498949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295203119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1295203119
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2313486140
Short name T138
Test name
Test status
Simulation time 3523729955 ps
CPU time 5.03 seconds
Started May 12 12:53:15 PM PDT 24
Finished May 12 12:53:21 PM PDT 24
Peak memory 216512 kb
Host smart-66690bf6-1c33-4e2f-99b4-b149303a6dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313486140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2313486140
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3239754143
Short name T833
Test name
Test status
Simulation time 60843129 ps
CPU time 0.73 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 204596 kb
Host smart-ac38ed98-f988-4590-b55b-372cd7960560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239754143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3239754143
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3555295686
Short name T830
Test name
Test status
Simulation time 828043728 ps
CPU time 7.22 seconds
Started May 12 12:53:28 PM PDT 24
Finished May 12 12:53:36 PM PDT 24
Peak memory 233716 kb
Host smart-35d04367-5a04-462a-a25e-458892a6aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555295686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3555295686
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.664705896
Short name T466
Test name
Test status
Simulation time 22423334 ps
CPU time 0.81 seconds
Started May 12 12:53:24 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 206716 kb
Host smart-189f437b-470a-450a-8c63-970cb1417f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664705896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.664705896
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1352702337
Short name T249
Test name
Test status
Simulation time 242584023887 ps
CPU time 155.61 seconds
Started May 12 12:53:29 PM PDT 24
Finished May 12 12:56:10 PM PDT 24
Peak memory 240976 kb
Host smart-07b44292-0d67-4e3b-bd31-fa3794a40fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352702337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1352702337
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1082932992
Short name T568
Test name
Test status
Simulation time 1740894609 ps
CPU time 36.92 seconds
Started May 12 12:53:35 PM PDT 24
Finished May 12 12:54:13 PM PDT 24
Peak memory 256368 kb
Host smart-be7ff65a-d5b1-4f48-9d4e-42658a446015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082932992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1082932992
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1991923650
Short name T311
Test name
Test status
Simulation time 618993398 ps
CPU time 4.24 seconds
Started May 12 12:53:36 PM PDT 24
Finished May 12 12:53:41 PM PDT 24
Peak memory 224392 kb
Host smart-fdbbc02e-ab6a-4679-a6e8-820d543f594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991923650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1991923650
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.50831408
Short name T829
Test name
Test status
Simulation time 2678634850 ps
CPU time 5.11 seconds
Started May 12 12:53:23 PM PDT 24
Finished May 12 12:53:29 PM PDT 24
Peak memory 218700 kb
Host smart-aec7462e-c21d-4013-9154-a2f967176c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50831408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.50831408
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3994977540
Short name T661
Test name
Test status
Simulation time 234623217972 ps
CPU time 115.81 seconds
Started May 12 12:53:24 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 219548 kb
Host smart-47c5a719-f2d0-4717-8278-953560f0d1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994977540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3994977540
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4028028995
Short name T666
Test name
Test status
Simulation time 1441712059 ps
CPU time 6.68 seconds
Started May 12 12:53:37 PM PDT 24
Finished May 12 12:53:44 PM PDT 24
Peak memory 233572 kb
Host smart-933a1374-cdd5-4655-962f-2e94be93fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028028995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4028028995
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4124836121
Short name T618
Test name
Test status
Simulation time 1871639003 ps
CPU time 8.56 seconds
Started May 12 12:53:31 PM PDT 24
Finished May 12 12:53:40 PM PDT 24
Peak memory 239220 kb
Host smart-d2df3736-05be-496d-9899-567998982e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124836121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4124836121
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3485192802
Short name T54
Test name
Test status
Simulation time 1141201382 ps
CPU time 7.56 seconds
Started May 12 12:53:26 PM PDT 24
Finished May 12 12:53:34 PM PDT 24
Peak memory 222044 kb
Host smart-bbf177a9-49bc-460a-93fb-10a06a9b5afa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3485192802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3485192802
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1447549687
Short name T185
Test name
Test status
Simulation time 255099032634 ps
CPU time 557.91 seconds
Started May 12 12:53:25 PM PDT 24
Finished May 12 01:02:43 PM PDT 24
Peak memory 250796 kb
Host smart-7b3aea42-625b-4105-a24a-e79f1ad5536c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447549687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1447549687
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1355056211
Short name T791
Test name
Test status
Simulation time 12890911315 ps
CPU time 31.5 seconds
Started May 12 12:53:22 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 216416 kb
Host smart-24cdb4fe-579e-4e17-992a-ea7e69e8e35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355056211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1355056211
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1201885113
Short name T65
Test name
Test status
Simulation time 5853145642 ps
CPU time 17.73 seconds
Started May 12 12:53:25 PM PDT 24
Finished May 12 12:53:43 PM PDT 24
Peak memory 216620 kb
Host smart-878b5125-56fc-4cd8-a398-18ce8f5b051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201885113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1201885113
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.105226119
Short name T719
Test name
Test status
Simulation time 90901774 ps
CPU time 4.89 seconds
Started May 12 12:53:27 PM PDT 24
Finished May 12 12:53:33 PM PDT 24
Peak memory 216296 kb
Host smart-d08fa039-39bf-4d52-91a5-d7aecb24da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105226119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.105226119
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1275204903
Short name T679
Test name
Test status
Simulation time 100814295 ps
CPU time 0.76 seconds
Started May 12 12:53:23 PM PDT 24
Finished May 12 12:53:24 PM PDT 24
Peak memory 205816 kb
Host smart-9627f7f7-a140-40c7-848b-1c8f0997acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275204903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1275204903
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3571362745
Short name T807
Test name
Test status
Simulation time 169250506 ps
CPU time 3.38 seconds
Started May 12 12:53:21 PM PDT 24
Finished May 12 12:53:25 PM PDT 24
Peak memory 233876 kb
Host smart-2939cad5-c450-4959-86d9-41750a11b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571362745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3571362745
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3483657655
Short name T712
Test name
Test status
Simulation time 12304840 ps
CPU time 0.68 seconds
Started May 12 12:53:30 PM PDT 24
Finished May 12 12:53:32 PM PDT 24
Peak memory 205268 kb
Host smart-300ce16d-af00-4f45-8b8b-84fe374a5f3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483657655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3483657655
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.372836315
Short name T900
Test name
Test status
Simulation time 415042768 ps
CPU time 5.89 seconds
Started May 12 12:53:37 PM PDT 24
Finished May 12 12:53:43 PM PDT 24
Peak memory 233684 kb
Host smart-681968bd-c8f4-4341-a348-a64a1dfa36cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372836315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.372836315
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2685407816
Short name T877
Test name
Test status
Simulation time 71063180 ps
CPU time 0.82 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:53:46 PM PDT 24
Peak memory 206380 kb
Host smart-a55a782d-7e05-48cb-88b5-bf899fafde1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685407816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2685407816
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1470202422
Short name T933
Test name
Test status
Simulation time 23428588272 ps
CPU time 204.43 seconds
Started May 12 12:53:32 PM PDT 24
Finished May 12 12:56:57 PM PDT 24
Peak memory 250204 kb
Host smart-c67a8583-b4e4-41b4-8ed5-b5918eaa2bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470202422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1470202422
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1190385911
Short name T233
Test name
Test status
Simulation time 23953970599 ps
CPU time 301.64 seconds
Started May 12 12:53:30 PM PDT 24
Finished May 12 12:58:33 PM PDT 24
Peak memory 263752 kb
Host smart-73b9a942-cd5f-4a6f-b580-3749c7235d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190385911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1190385911
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3311169778
Short name T941
Test name
Test status
Simulation time 33877833 ps
CPU time 2.17 seconds
Started May 12 12:53:34 PM PDT 24
Finished May 12 12:53:37 PM PDT 24
Peak memory 223900 kb
Host smart-a07642db-429f-457b-947f-5e0e27713697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311169778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3311169778
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.180156378
Short name T591
Test name
Test status
Simulation time 888000942 ps
CPU time 4.15 seconds
Started May 12 12:53:32 PM PDT 24
Finished May 12 12:53:37 PM PDT 24
Peak memory 234280 kb
Host smart-f1872d8e-24a8-4295-bfac-249efeaf1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180156378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.180156378
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3888077647
Short name T454
Test name
Test status
Simulation time 4255767177 ps
CPU time 29.98 seconds
Started May 12 12:53:27 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 224652 kb
Host smart-9914862c-68d7-4c87-b670-4d109cb9d2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888077647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3888077647
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3204840266
Short name T856
Test name
Test status
Simulation time 1577581833 ps
CPU time 6.39 seconds
Started May 12 12:53:33 PM PDT 24
Finished May 12 12:53:40 PM PDT 24
Peak memory 224428 kb
Host smart-ea622c32-ad27-4364-8d8f-5b75a34d7e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204840266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3204840266
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2647667161
Short name T209
Test name
Test status
Simulation time 905697540 ps
CPU time 4.38 seconds
Started May 12 12:53:27 PM PDT 24
Finished May 12 12:53:33 PM PDT 24
Peak memory 218820 kb
Host smart-513557ad-5577-4f7c-b0fb-b9f0d85ccdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647667161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2647667161
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1080406601
Short name T648
Test name
Test status
Simulation time 662422499 ps
CPU time 4.74 seconds
Started May 12 12:53:34 PM PDT 24
Finished May 12 12:53:39 PM PDT 24
Peak memory 222788 kb
Host smart-e146691e-af52-4ba5-9b17-c3dfe86a44d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1080406601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1080406601
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1803468173
Short name T557
Test name
Test status
Simulation time 12605979951 ps
CPU time 141.04 seconds
Started May 12 12:53:32 PM PDT 24
Finished May 12 12:55:53 PM PDT 24
Peak memory 257448 kb
Host smart-8113fa0e-db1e-4ee1-aa9c-f410d4496dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803468173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1803468173
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2579007488
Short name T963
Test name
Test status
Simulation time 17767285493 ps
CPU time 12.8 seconds
Started May 12 12:53:28 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 216424 kb
Host smart-d77f994e-3d08-48d5-9549-eda5b93e6806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579007488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2579007488
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.777534805
Short name T913
Test name
Test status
Simulation time 3018776216 ps
CPU time 8.56 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 216508 kb
Host smart-4fe343a7-de3c-4f47-ab38-6758aef9142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777534805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.777534805
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1378954351
Short name T725
Test name
Test status
Simulation time 54359658 ps
CPU time 1.38 seconds
Started May 12 12:53:37 PM PDT 24
Finished May 12 12:53:39 PM PDT 24
Peak memory 208152 kb
Host smart-8e25b005-7ebd-47d7-b59e-a5d17a721211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378954351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1378954351
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.682020995
Short name T561
Test name
Test status
Simulation time 158236503 ps
CPU time 0.89 seconds
Started May 12 12:53:39 PM PDT 24
Finished May 12 12:53:40 PM PDT 24
Peak memory 206768 kb
Host smart-b6aa802d-9140-4967-99be-cde1d57ee2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682020995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.682020995
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.734078513
Short name T204
Test name
Test status
Simulation time 868956619 ps
CPU time 7.35 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:53 PM PDT 24
Peak memory 234012 kb
Host smart-6d73ca8e-fadd-4edd-9720-9608fad91b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734078513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.734078513
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3362676346
Short name T581
Test name
Test status
Simulation time 13616692 ps
CPU time 0.74 seconds
Started May 12 12:51:09 PM PDT 24
Finished May 12 12:51:11 PM PDT 24
Peak memory 204672 kb
Host smart-781482dd-d0c3-4be5-9c16-665c3ce6b10b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362676346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
362676346
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3275622109
Short name T835
Test name
Test status
Simulation time 122844536 ps
CPU time 3.17 seconds
Started May 12 12:51:09 PM PDT 24
Finished May 12 12:51:13 PM PDT 24
Peak memory 233604 kb
Host smart-bd24d91a-0f03-4b95-b4b4-664809e7cb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275622109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3275622109
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1857196681
Short name T397
Test name
Test status
Simulation time 17990689 ps
CPU time 0.78 seconds
Started May 12 12:51:04 PM PDT 24
Finished May 12 12:51:05 PM PDT 24
Peak memory 205688 kb
Host smart-4cadd9de-a7aa-4f98-8a46-b406b619e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857196681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1857196681
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.707663361
Short name T790
Test name
Test status
Simulation time 2455498105 ps
CPU time 27.51 seconds
Started May 12 12:51:10 PM PDT 24
Finished May 12 12:51:38 PM PDT 24
Peak memory 256280 kb
Host smart-c34fd813-d434-47b6-be7f-713fa88f6380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707663361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.707663361
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1549742019
Short name T534
Test name
Test status
Simulation time 24830093859 ps
CPU time 64.29 seconds
Started May 12 12:51:02 PM PDT 24
Finished May 12 12:52:07 PM PDT 24
Peak memory 240448 kb
Host smart-13a5bfc5-7c2b-4f6f-b5e1-7141d803d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549742019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1549742019
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1074601341
Short name T256
Test name
Test status
Simulation time 577233940307 ps
CPU time 285.04 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:56:02 PM PDT 24
Peak memory 254448 kb
Host smart-4c05be4b-73fe-4e2a-bb47-d13a44ac544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074601341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1074601341
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1270224623
Short name T498
Test name
Test status
Simulation time 2154533458 ps
CPU time 9.81 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:24 PM PDT 24
Peak memory 240328 kb
Host smart-5069c95e-5e8e-4038-9056-8f22b478970a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270224623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1270224623
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2923429467
Short name T302
Test name
Test status
Simulation time 564691775 ps
CPU time 3.75 seconds
Started May 12 12:51:31 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 233584 kb
Host smart-facd3653-220b-4967-8d73-aa35e3bc98d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923429467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2923429467
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2975226923
Short name T633
Test name
Test status
Simulation time 44065235 ps
CPU time 1.01 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:15 PM PDT 24
Peak memory 218160 kb
Host smart-cfb54264-4dd5-40cc-86f1-c503be07ce70
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975226923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2975226923
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2507638629
Short name T303
Test name
Test status
Simulation time 1194159135 ps
CPU time 3.5 seconds
Started May 12 12:51:09 PM PDT 24
Finished May 12 12:51:14 PM PDT 24
Peak memory 217012 kb
Host smart-4ef00960-9dea-465a-bebb-517b686c6e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507638629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2507638629
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2671659139
Short name T590
Test name
Test status
Simulation time 421612575 ps
CPU time 3.31 seconds
Started May 12 12:51:07 PM PDT 24
Finished May 12 12:51:11 PM PDT 24
Peak memory 233588 kb
Host smart-250c17ef-c38e-4666-8255-475eb7b28761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671659139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2671659139
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.83062385
Short name T643
Test name
Test status
Simulation time 204642752 ps
CPU time 3.88 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:21 PM PDT 24
Peak memory 222504 kb
Host smart-1335fa60-74c0-482b-8265-b96bdd9a9400
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=83062385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct
.83062385
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.776136218
Short name T84
Test name
Test status
Simulation time 89868786 ps
CPU time 1.18 seconds
Started May 12 12:51:03 PM PDT 24
Finished May 12 12:51:05 PM PDT 24
Peak memory 236740 kb
Host smart-855fb5fb-b3fe-4e0e-826e-336de9ecec67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776136218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.776136218
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1758413065
Short name T263
Test name
Test status
Simulation time 40087615072 ps
CPU time 366.99 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:57:24 PM PDT 24
Peak memory 263712 kb
Host smart-8845ffa3-13a5-432d-bf42-c0cb39d8b278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758413065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1758413065
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1322425518
Short name T314
Test name
Test status
Simulation time 2325621613 ps
CPU time 12.26 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:25 PM PDT 24
Peak memory 216744 kb
Host smart-342b6ea5-c85e-4b15-8f6d-91cb5da03d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322425518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1322425518
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2355010190
Short name T378
Test name
Test status
Simulation time 8325556876 ps
CPU time 21.32 seconds
Started May 12 12:51:18 PM PDT 24
Finished May 12 12:51:40 PM PDT 24
Peak memory 218352 kb
Host smart-9d2fe94e-682c-4011-8cfc-ac3189003ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355010190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2355010190
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3671411191
Short name T541
Test name
Test status
Simulation time 434676735 ps
CPU time 1.4 seconds
Started May 12 12:51:18 PM PDT 24
Finished May 12 12:51:20 PM PDT 24
Peak memory 216368 kb
Host smart-c354cfcc-f56b-4b3c-861d-ff34fa4c0e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671411191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3671411191
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1458455448
Short name T811
Test name
Test status
Simulation time 71816758 ps
CPU time 0.88 seconds
Started May 12 12:51:17 PM PDT 24
Finished May 12 12:51:19 PM PDT 24
Peak memory 205764 kb
Host smart-bd01aaf1-d52c-41bb-9fb3-53f8b469789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458455448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1458455448
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.285223659
Short name T444
Test name
Test status
Simulation time 1159645200 ps
CPU time 10.04 seconds
Started May 12 12:51:17 PM PDT 24
Finished May 12 12:51:28 PM PDT 24
Peak memory 242712 kb
Host smart-57a5d19a-fc5c-49dd-8bb8-ad9c6043ebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285223659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.285223659
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1858664400
Short name T453
Test name
Test status
Simulation time 45291846 ps
CPU time 0.78 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 205160 kb
Host smart-a8d45f06-3dc4-4f2d-88e0-dd87f9a1352c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858664400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1858664400
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4218617739
Short name T103
Test name
Test status
Simulation time 1207769802 ps
CPU time 10.02 seconds
Started May 12 12:53:32 PM PDT 24
Finished May 12 12:53:43 PM PDT 24
Peak memory 236864 kb
Host smart-dc1e4737-7ee7-4163-a1a2-a3a97ca7087e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218617739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4218617739
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1962257031
Short name T644
Test name
Test status
Simulation time 36521272 ps
CPU time 0.77 seconds
Started May 12 12:53:37 PM PDT 24
Finished May 12 12:53:38 PM PDT 24
Peak memory 205336 kb
Host smart-233f4de3-595e-4d40-9f75-a90a6e896a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962257031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1962257031
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1825626780
Short name T55
Test name
Test status
Simulation time 126203403924 ps
CPU time 221.99 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:57:28 PM PDT 24
Peak memory 249192 kb
Host smart-a98c369c-cd7f-4886-bbc2-9006e1d09d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825626780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1825626780
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.980062822
Short name T175
Test name
Test status
Simulation time 104667347228 ps
CPU time 212.73 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:57:19 PM PDT 24
Peak memory 249372 kb
Host smart-0787efe2-22d1-407f-9b60-1bef1b1ce216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980062822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.980062822
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1527084735
Short name T739
Test name
Test status
Simulation time 469680335 ps
CPU time 5.2 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:53:47 PM PDT 24
Peak memory 240800 kb
Host smart-bad5efc7-a4d4-4667-a295-3db4ae4ee549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527084735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1527084735
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1647209507
Short name T179
Test name
Test status
Simulation time 1715268673 ps
CPU time 20.54 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:54:03 PM PDT 24
Peak memory 224680 kb
Host smart-23cab403-9ac5-48b7-88c8-ceea1db6138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647209507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1647209507
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2726407876
Short name T817
Test name
Test status
Simulation time 8942264343 ps
CPU time 14.55 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 232752 kb
Host smart-bb582d30-40a5-4270-8de9-5b8ed7d828d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726407876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2726407876
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3634163195
Short name T220
Test name
Test status
Simulation time 2675331144 ps
CPU time 11.21 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 228312 kb
Host smart-16aed5e0-b69f-4626-a1af-08159c60f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634163195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3634163195
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3860231393
Short name T645
Test name
Test status
Simulation time 4286867535 ps
CPU time 8.02 seconds
Started May 12 12:53:30 PM PDT 24
Finished May 12 12:53:39 PM PDT 24
Peak memory 227084 kb
Host smart-b6cc514c-b388-4e6e-bdf5-f50028f4e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860231393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3860231393
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1777547131
Short name T820
Test name
Test status
Simulation time 327060760 ps
CPU time 3.93 seconds
Started May 12 12:53:32 PM PDT 24
Finished May 12 12:53:36 PM PDT 24
Peak memory 219908 kb
Host smart-e5f81b3f-35dc-429c-92cc-e83968475826
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777547131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1777547131
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2563077212
Short name T371
Test name
Test status
Simulation time 171164640 ps
CPU time 1.03 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:46 PM PDT 24
Peak memory 206772 kb
Host smart-98159713-1181-40e9-84e2-e5e7cde04c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563077212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2563077212
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3787942741
Short name T921
Test name
Test status
Simulation time 2553340048 ps
CPU time 19.04 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 216480 kb
Host smart-c018877b-9cb1-408f-9c81-2feafe09d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787942741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3787942741
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1177016918
Short name T359
Test name
Test status
Simulation time 3011904793 ps
CPU time 6.87 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 216428 kb
Host smart-78de83ef-cf63-4b90-afd8-61e7e167779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177016918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1177016918
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1299094687
Short name T937
Test name
Test status
Simulation time 71555866 ps
CPU time 0.99 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 207828 kb
Host smart-cada87ec-3ff8-4872-b0a0-d3ef07010533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299094687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1299094687
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2390745470
Short name T638
Test name
Test status
Simulation time 55124278 ps
CPU time 0.78 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:46 PM PDT 24
Peak memory 205832 kb
Host smart-f0a344e2-bdea-4474-a612-1809590ae405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390745470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2390745470
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3632671592
Short name T717
Test name
Test status
Simulation time 1082381609 ps
CPU time 2.91 seconds
Started May 12 12:53:30 PM PDT 24
Finished May 12 12:53:33 PM PDT 24
Peak memory 218936 kb
Host smart-4c189683-34cf-4983-a7cc-a290df178a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632671592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3632671592
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3630611832
Short name T415
Test name
Test status
Simulation time 14644351 ps
CPU time 0.7 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:53:51 PM PDT 24
Peak memory 205560 kb
Host smart-c3ad9057-2eca-4ab7-a33c-a86029a9697a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630611832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3630611832
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2208827521
Short name T102
Test name
Test status
Simulation time 212207280 ps
CPU time 3.41 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 234428 kb
Host smart-473f79f5-5853-42c3-8e96-8be0134aa9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208827521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2208827521
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1318893616
Short name T438
Test name
Test status
Simulation time 53257921 ps
CPU time 0.77 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:53:43 PM PDT 24
Peak memory 206384 kb
Host smart-b3b755ff-d48c-41a2-aa71-7365fbd99d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318893616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1318893616
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3041767385
Short name T312
Test name
Test status
Simulation time 803009546 ps
CPU time 7.44 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 232956 kb
Host smart-fda81103-b5d7-44ee-b724-520a2c39385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041767385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3041767385
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.454543021
Short name T398
Test name
Test status
Simulation time 4043099720 ps
CPU time 17.44 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:54:12 PM PDT 24
Peak memory 234812 kb
Host smart-c1cfc2d2-99f0-4da1-901e-60640b7982cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454543021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.454543021
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2614213612
Short name T940
Test name
Test status
Simulation time 304546905 ps
CPU time 3.26 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:44 PM PDT 24
Peak memory 233632 kb
Host smart-62dceeae-4991-4921-a264-68dcfb16577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614213612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2614213612
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1197520240
Short name T1
Test name
Test status
Simulation time 11246582321 ps
CPU time 11.62 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:06 PM PDT 24
Peak memory 233388 kb
Host smart-becac0bc-b07b-49cd-828c-465e484a60f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197520240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1197520240
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3944713221
Short name T754
Test name
Test status
Simulation time 22489821056 ps
CPU time 11.18 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:53:53 PM PDT 24
Peak memory 236904 kb
Host smart-cd957fad-5305-4d03-9048-79e55c0c1826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944713221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3944713221
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1048018741
Short name T796
Test name
Test status
Simulation time 3166064265 ps
CPU time 5.86 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 220472 kb
Host smart-07952388-4036-49b9-a54d-9f497f9abbf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1048018741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1048018741
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2273732562
Short name T61
Test name
Test status
Simulation time 193030896357 ps
CPU time 411.42 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 01:00:32 PM PDT 24
Peak memory 273844 kb
Host smart-2e0a49d2-ded1-4779-8ff3-f65560495082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273732562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2273732562
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3489466726
Short name T429
Test name
Test status
Simulation time 11035305494 ps
CPU time 26.96 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:54:13 PM PDT 24
Peak memory 220032 kb
Host smart-65d59f57-7a25-4b0f-a470-2984a8fbd166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489466726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3489466726
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1374257796
Short name T864
Test name
Test status
Simulation time 9204933038 ps
CPU time 19.82 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 216400 kb
Host smart-d04b09bf-a601-409c-b887-9184c48acffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374257796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1374257796
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2021084900
Short name T755
Test name
Test status
Simulation time 36449297 ps
CPU time 1.25 seconds
Started May 12 12:53:35 PM PDT 24
Finished May 12 12:53:36 PM PDT 24
Peak memory 208232 kb
Host smart-b5dd396b-4a7e-480b-97de-98cb063d41e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021084900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2021084900
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2945143798
Short name T910
Test name
Test status
Simulation time 97184552 ps
CPU time 1 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 206076 kb
Host smart-497a7690-901b-4fcb-b98c-064b70d8c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945143798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2945143798
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.219342485
Short name T658
Test name
Test status
Simulation time 222830239 ps
CPU time 2.89 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:51 PM PDT 24
Peak memory 216304 kb
Host smart-7a0ad797-bb59-4db2-882b-70b89e382bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219342485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.219342485
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1012740927
Short name T901
Test name
Test status
Simulation time 14440858 ps
CPU time 0.7 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:53:48 PM PDT 24
Peak memory 205616 kb
Host smart-fad73627-35c3-4405-878f-ea30e87fcbed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012740927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1012740927
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2643095932
Short name T525
Test name
Test status
Simulation time 145204599 ps
CPU time 2.16 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:43 PM PDT 24
Peak memory 216056 kb
Host smart-19914721-e28a-4352-8be0-dd594d0b63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643095932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2643095932
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2750602847
Short name T72
Test name
Test status
Simulation time 28172219 ps
CPU time 0.75 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 205280 kb
Host smart-952d1404-2507-4a47-ad3d-f89a5cd321f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750602847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2750602847
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3801286121
Short name T195
Test name
Test status
Simulation time 112434904143 ps
CPU time 151.42 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:56:15 PM PDT 24
Peak memory 241000 kb
Host smart-6bf75a8c-fcf3-40ea-a75b-ee28c0ef01e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801286121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3801286121
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1533464970
Short name T587
Test name
Test status
Simulation time 3411965546 ps
CPU time 10.1 seconds
Started May 12 12:53:52 PM PDT 24
Finished May 12 12:54:03 PM PDT 24
Peak memory 217808 kb
Host smart-c21df0fe-9961-4d43-a9e6-2dd8087edf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533464970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1533464970
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1560447192
Short name T538
Test name
Test status
Simulation time 80132697713 ps
CPU time 169.84 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:56:32 PM PDT 24
Peak memory 257444 kb
Host smart-dfadbb6f-1de8-446f-9b26-4cca32e4e9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560447192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1560447192
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.546813591
Short name T803
Test name
Test status
Simulation time 4099478281 ps
CPU time 57.53 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 249176 kb
Host smart-9d2ed28e-4f21-4496-9a93-266fc833f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546813591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.546813591
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2131413368
Short name T205
Test name
Test status
Simulation time 447806243 ps
CPU time 7.41 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 234004 kb
Host smart-b8afab41-0560-4226-8665-52cfa74cb2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131413368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2131413368
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4079779673
Short name T731
Test name
Test status
Simulation time 75752571 ps
CPU time 2.25 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 216280 kb
Host smart-c018aada-bc4a-4246-aa48-3a44e15afcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079779673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4079779673
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1919452400
Short name T43
Test name
Test status
Simulation time 785170909 ps
CPU time 5.66 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 233416 kb
Host smart-e644a720-d2d9-42fa-b212-612e394f03f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919452400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1919452400
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1502492925
Short name T291
Test name
Test status
Simulation time 68666644 ps
CPU time 2.9 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:49 PM PDT 24
Peak memory 233952 kb
Host smart-c3d805af-fda2-47b6-af52-d2f9c62bb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502492925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1502492925
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.104333740
Short name T884
Test name
Test status
Simulation time 1078067816 ps
CPU time 13.12 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 222884 kb
Host smart-d8d38866-f371-43f9-9938-a2745cfcd1c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104333740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.104333740
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.175733418
Short name T447
Test name
Test status
Simulation time 8044084952 ps
CPU time 19.11 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:54:03 PM PDT 24
Peak memory 217648 kb
Host smart-f7f800eb-df6e-4633-81cd-717e090a3d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175733418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.175733418
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3985876704
Short name T734
Test name
Test status
Simulation time 333559312 ps
CPU time 5.29 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:51 PM PDT 24
Peak memory 216436 kb
Host smart-fce2590a-69a9-4cd7-a7ec-5f44becdfbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985876704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3985876704
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2142477929
Short name T614
Test name
Test status
Simulation time 16485212559 ps
CPU time 10.99 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 216364 kb
Host smart-63df2e9b-9f9d-4b43-a65e-4bbeb501612d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142477929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2142477929
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3233461953
Short name T478
Test name
Test status
Simulation time 90942868 ps
CPU time 3.9 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 216372 kb
Host smart-5bd7af8f-c153-4ec8-acb0-603c30edf157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233461953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3233461953
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3434605674
Short name T500
Test name
Test status
Simulation time 76649667 ps
CPU time 0.93 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:42 PM PDT 24
Peak memory 205972 kb
Host smart-d7949948-9405-4178-b4ae-d46347575ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434605674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3434605674
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3537391913
Short name T497
Test name
Test status
Simulation time 82576973 ps
CPU time 2.2 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:53:51 PM PDT 24
Peak memory 216076 kb
Host smart-348fa5e0-efea-48b6-98da-b004604055db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537391913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3537391913
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2289686383
Short name T401
Test name
Test status
Simulation time 19175952 ps
CPU time 0.74 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:53:53 PM PDT 24
Peak memory 205332 kb
Host smart-9b20d238-1f39-49d4-a1cd-4edb963534a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289686383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2289686383
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2929140530
Short name T484
Test name
Test status
Simulation time 379551697 ps
CPU time 3.03 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 218476 kb
Host smart-b42622d7-b62b-4d56-9a85-12f69701b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929140530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2929140530
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2277967209
Short name T685
Test name
Test status
Simulation time 14463243 ps
CPU time 0.85 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:47 PM PDT 24
Peak memory 206688 kb
Host smart-c7bb21f7-b84a-439d-890a-924f1d5e2cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277967209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2277967209
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3272566751
Short name T244
Test name
Test status
Simulation time 18567792356 ps
CPU time 99.61 seconds
Started May 12 12:53:52 PM PDT 24
Finished May 12 12:55:32 PM PDT 24
Peak memory 254344 kb
Host smart-3fca93e4-0dad-4e1f-a320-d6494e8b364e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272566751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3272566751
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1303539002
Short name T144
Test name
Test status
Simulation time 5025721625 ps
CPU time 79.51 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:55:08 PM PDT 24
Peak memory 249900 kb
Host smart-601b3788-56fd-4a75-998c-3d5cfb3cedf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303539002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1303539002
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2746895576
Short name T589
Test name
Test status
Simulation time 2677383349 ps
CPU time 30.05 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:54:24 PM PDT 24
Peak memory 224700 kb
Host smart-4ce4fd97-1578-4222-915d-149ecae28eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746895576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2746895576
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2048170475
Short name T150
Test name
Test status
Simulation time 8985145142 ps
CPU time 21.14 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:54:02 PM PDT 24
Peak memory 239248 kb
Host smart-cef8b98e-91a3-4e0a-9d0c-d4cc99833273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048170475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2048170475
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1204910870
Short name T693
Test name
Test status
Simulation time 286238733 ps
CPU time 3.48 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 232656 kb
Host smart-d4daf86e-01dd-428e-83e4-ef53c28bbd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204910870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1204910870
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.154179679
Short name T522
Test name
Test status
Simulation time 4025844466 ps
CPU time 42.46 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 234560 kb
Host smart-651ec1a6-0a90-48c4-8044-878c37825b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154179679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.154179679
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3647284989
Short name T218
Test name
Test status
Simulation time 6662782877 ps
CPU time 15.26 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 228132 kb
Host smart-e512ad6d-d991-48e2-8102-02da25fe742c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647284989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3647284989
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.894071318
Short name T336
Test name
Test status
Simulation time 48706044 ps
CPU time 2.09 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:46 PM PDT 24
Peak memory 218904 kb
Host smart-4ceefe9c-6df9-4092-a901-c6b0e1a3e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894071318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.894071318
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4289310046
Short name T393
Test name
Test status
Simulation time 1019875458 ps
CPU time 5.05 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 223036 kb
Host smart-0df68950-12b9-47b9-9802-a8a070ebc7a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289310046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4289310046
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.311288612
Short name T592
Test name
Test status
Simulation time 2208759726 ps
CPU time 18.36 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 216488 kb
Host smart-9da9e9e4-181b-4347-b075-0efe7c4a20e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311288612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.311288612
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2089096564
Short name T573
Test name
Test status
Simulation time 3021205225 ps
CPU time 4.81 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 216436 kb
Host smart-22c98dd7-e8fa-481f-a584-fc805806eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089096564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2089096564
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2660609379
Short name T678
Test name
Test status
Simulation time 65307657 ps
CPU time 1.11 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 207828 kb
Host smart-fd63dc28-c9f2-46e4-a567-030d9d998473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660609379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2660609379
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1537818910
Short name T760
Test name
Test status
Simulation time 11435179 ps
CPU time 0.68 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:48 PM PDT 24
Peak memory 205472 kb
Host smart-0bd0bf56-a9d5-4fee-ac12-8a409a7a5d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537818910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1537818910
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1713112055
Short name T380
Test name
Test status
Simulation time 87184731 ps
CPU time 2.2 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 216048 kb
Host smart-900d2546-ed3b-4698-9af1-edde702d1c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713112055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1713112055
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3773496107
Short name T471
Test name
Test status
Simulation time 51563271 ps
CPU time 0.69 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 205276 kb
Host smart-f0f2ee94-188c-45ea-b0cb-72854ab5d10a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773496107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3773496107
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.320828459
Short name T300
Test name
Test status
Simulation time 59766905 ps
CPU time 2.11 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:53:51 PM PDT 24
Peak memory 218620 kb
Host smart-094941aa-3cb9-45ac-9cdb-a7a381b75505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320828459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.320828459
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1659926471
Short name T21
Test name
Test status
Simulation time 40397855 ps
CPU time 0.78 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:47 PM PDT 24
Peak memory 206708 kb
Host smart-eaf844d2-776b-438b-b5b3-60ccacaa8dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659926471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1659926471
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.4278780603
Short name T706
Test name
Test status
Simulation time 4029720426 ps
CPU time 63.73 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:54:56 PM PDT 24
Peak memory 251404 kb
Host smart-1663cd19-b674-4b87-b538-aa9c961864d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278780603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.4278780603
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.702127293
Short name T925
Test name
Test status
Simulation time 2135195641 ps
CPU time 24.54 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 240872 kb
Host smart-42eee99a-6826-4975-8735-3014136cf9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702127293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.702127293
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1345007286
Short name T806
Test name
Test status
Simulation time 1202462169 ps
CPU time 4.55 seconds
Started May 12 12:53:47 PM PDT 24
Finished May 12 12:53:53 PM PDT 24
Peak memory 224412 kb
Host smart-e7e25ee4-75fa-4143-8016-a2e733ab2ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345007286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1345007286
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1361384395
Short name T374
Test name
Test status
Simulation time 28829046 ps
CPU time 2.33 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 220924 kb
Host smart-4663a406-4d7f-4643-832d-d1808e95781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361384395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1361384395
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1233178902
Short name T40
Test name
Test status
Simulation time 5351430119 ps
CPU time 21.63 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 232580 kb
Host smart-c1dbe895-cfb1-41b2-a9bc-cc80fa4b6620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233178902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1233178902
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3102369114
Short name T692
Test name
Test status
Simulation time 199854518 ps
CPU time 2.79 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:49 PM PDT 24
Peak memory 233576 kb
Host smart-3f678baf-3f0f-446f-863c-0fa4f0be2c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102369114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3102369114
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.171066741
Short name T467
Test name
Test status
Simulation time 1237481117 ps
CPU time 4.36 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:48 PM PDT 24
Peak memory 222800 kb
Host smart-01fa8fb0-fa86-4c88-8861-502c2a4edf2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=171066741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.171066741
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.873963699
Short name T348
Test name
Test status
Simulation time 2707659141 ps
CPU time 8.3 seconds
Started May 12 12:53:55 PM PDT 24
Finished May 12 12:54:04 PM PDT 24
Peak memory 216412 kb
Host smart-d41d3a99-05c8-4c9f-b36a-e7fe6b9fe90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873963699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.873963699
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3453062323
Short name T677
Test name
Test status
Simulation time 1109511886 ps
CPU time 5.5 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:49 PM PDT 24
Peak memory 216400 kb
Host smart-a647d08b-1650-4641-9663-dce341a7a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453062323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3453062323
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1458013293
Short name T329
Test name
Test status
Simulation time 235764926 ps
CPU time 1.29 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:47 PM PDT 24
Peak memory 208040 kb
Host smart-619cd867-0b04-478e-b8dc-bfd7dd4c0421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458013293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1458013293
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2817801064
Short name T721
Test name
Test status
Simulation time 106498222 ps
CPU time 0.82 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:41 PM PDT 24
Peak memory 205712 kb
Host smart-887dd91f-5b1a-4adc-9774-e4263364c3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817801064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2817801064
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1047790730
Short name T720
Test name
Test status
Simulation time 800592566 ps
CPU time 5.14 seconds
Started May 12 12:53:40 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 236948 kb
Host smart-ffaa8a5e-004f-4148-8d82-cd2564a751f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047790730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1047790730
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.865079947
Short name T344
Test name
Test status
Simulation time 20061873 ps
CPU time 0.66 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:48 PM PDT 24
Peak memory 205740 kb
Host smart-15a1dfec-6133-46d3-b491-0176c9c3d85c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865079947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.865079947
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2736640337
Short name T758
Test name
Test status
Simulation time 898216778 ps
CPU time 5.07 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:49 PM PDT 24
Peak memory 237880 kb
Host smart-c803310e-6a77-49b9-b4f0-3cf8007fd548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736640337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2736640337
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1713301294
Short name T427
Test name
Test status
Simulation time 194777698 ps
CPU time 0.73 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 205600 kb
Host smart-0bd7deca-5892-4dbb-867c-accbd1cc5e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713301294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1713301294
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4018119727
Short name T60
Test name
Test status
Simulation time 19598573770 ps
CPU time 92.86 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:55:24 PM PDT 24
Peak memory 238404 kb
Host smart-f4c611b7-b871-44f4-8bcc-f9be91aff79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018119727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4018119727
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2164538718
Short name T213
Test name
Test status
Simulation time 29500303625 ps
CPU time 248.16 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:58:00 PM PDT 24
Peak memory 256168 kb
Host smart-229563d5-e432-4d90-9823-c2b8fc8d739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164538718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2164538718
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1368656531
Short name T153
Test name
Test status
Simulation time 9226020034 ps
CPU time 37.59 seconds
Started May 12 12:53:41 PM PDT 24
Finished May 12 12:54:20 PM PDT 24
Peak memory 232896 kb
Host smart-f1d24339-7d9a-442a-b8cf-3e0cc6049ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368656531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1368656531
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.716796682
Short name T642
Test name
Test status
Simulation time 288685346 ps
CPU time 4.91 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 218552 kb
Host smart-4f024c51-565a-4342-b077-5384479210bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716796682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.716796682
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1494599113
Short name T924
Test name
Test status
Simulation time 2315761538 ps
CPU time 29.21 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:54:14 PM PDT 24
Peak memory 234288 kb
Host smart-63c2381f-187d-43f0-937b-329282a411cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494599113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1494599113
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3208722468
Short name T936
Test name
Test status
Simulation time 5102215363 ps
CPU time 15.91 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:54:04 PM PDT 24
Peak memory 233324 kb
Host smart-ad8b325c-bdf8-47fb-a7bb-b8a363086914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208722468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3208722468
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2776719027
Short name T801
Test name
Test status
Simulation time 379999150 ps
CPU time 2.85 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 233192 kb
Host smart-0d00b303-4d3a-450d-aa23-7170795a4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776719027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2776719027
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3112795108
Short name T535
Test name
Test status
Simulation time 823268643 ps
CPU time 5.04 seconds
Started May 12 12:53:52 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 222444 kb
Host smart-357a7656-da07-42d2-8c0f-f7518f9fba6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3112795108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3112795108
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1453193653
Short name T168
Test name
Test status
Simulation time 18237773775 ps
CPU time 170.18 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:56:54 PM PDT 24
Peak memory 241332 kb
Host smart-b64b3e6d-77fe-4da1-a270-95a7bb760600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453193653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1453193653
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3177680727
Short name T30
Test name
Test status
Simulation time 901966568 ps
CPU time 4.01 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:49 PM PDT 24
Peak memory 216364 kb
Host smart-39347c9a-962b-45ba-b1be-ee31bb38509e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177680727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3177680727
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2283254535
Short name T646
Test name
Test status
Simulation time 10750837605 ps
CPU time 15.34 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:54:09 PM PDT 24
Peak memory 216432 kb
Host smart-a148069e-a92a-4054-b15e-42597bc2b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283254535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2283254535
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1075857283
Short name T649
Test name
Test status
Simulation time 89071820 ps
CPU time 1.27 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 216284 kb
Host smart-709c2225-5805-4d84-8e84-6a9cf4c33690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075857283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1075857283
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2916534954
Short name T770
Test name
Test status
Simulation time 93863511 ps
CPU time 0.81 seconds
Started May 12 12:53:43 PM PDT 24
Finished May 12 12:53:44 PM PDT 24
Peak memory 205836 kb
Host smart-b8462ee6-7a9b-4c27-a841-eaed3cc43562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916534954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2916534954
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2755139363
Short name T203
Test name
Test status
Simulation time 1622338661 ps
CPU time 7.08 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:53 PM PDT 24
Peak memory 233448 kb
Host smart-b623fb0a-8ba4-44bf-a47a-8b99f0610250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755139363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2755139363
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2595643199
Short name T827
Test name
Test status
Simulation time 13360807 ps
CPU time 0.69 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 205284 kb
Host smart-9960af36-a490-4e83-beaa-298f945c5c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595643199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2595643199
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1568568389
Short name T211
Test name
Test status
Simulation time 240616766 ps
CPU time 4.01 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:01 PM PDT 24
Peak memory 233668 kb
Host smart-38c95a88-a625-44b9-ab63-bb2ec82f1645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568568389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1568568389
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.4074651945
Short name T419
Test name
Test status
Simulation time 19702910 ps
CPU time 0.83 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:53:50 PM PDT 24
Peak memory 206684 kb
Host smart-871acb71-b0e8-4772-adc5-6c71e7cf6c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074651945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4074651945
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2012069738
Short name T253
Test name
Test status
Simulation time 4624036895 ps
CPU time 57.26 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:54:48 PM PDT 24
Peak memory 253304 kb
Host smart-23d66324-60ec-4186-b70f-2679b2d595aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012069738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2012069738
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.292844207
Short name T231
Test name
Test status
Simulation time 3302973009 ps
CPU time 67.52 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:55:07 PM PDT 24
Peak memory 253132 kb
Host smart-25646358-c752-43c3-8813-4907ce7dd936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292844207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.292844207
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1279106269
Short name T488
Test name
Test status
Simulation time 39096891976 ps
CPU time 123.49 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:55:57 PM PDT 24
Peak memory 251236 kb
Host smart-a81dfe51-2ff0-485f-bd8d-6733f4b83cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279106269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1279106269
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2804295070
Short name T718
Test name
Test status
Simulation time 982943850 ps
CPU time 9.87 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 224424 kb
Host smart-487fc586-b64d-4d56-b67e-e2138a7b3567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804295070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2804295070
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3606587852
Short name T515
Test name
Test status
Simulation time 4269358140 ps
CPU time 10.09 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 234248 kb
Host smart-d9cfe57e-95c2-4b48-acdb-426e3dabbc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606587852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3606587852
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.242126141
Short name T299
Test name
Test status
Simulation time 15485886682 ps
CPU time 57.23 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:54:49 PM PDT 24
Peak memory 236628 kb
Host smart-b18be78a-de63-4600-9d69-765bcfefe689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242126141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.242126141
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1380169452
Short name T237
Test name
Test status
Simulation time 560978050 ps
CPU time 3.68 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:47 PM PDT 24
Peak memory 224384 kb
Host smart-8672446d-ece1-4b99-9475-67c8bcf09fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380169452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1380169452
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3395510584
Short name T580
Test name
Test status
Simulation time 90859354 ps
CPU time 2.31 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 218880 kb
Host smart-398c8897-6c5c-40b8-b9f8-b5430dd20bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395510584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3395510584
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1074568654
Short name T399
Test name
Test status
Simulation time 451710478 ps
CPU time 7.25 seconds
Started May 12 12:53:57 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 222268 kb
Host smart-37df3710-c6b7-47a9-93f2-56e6a318ce71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074568654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1074568654
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1704156501
Short name T70
Test name
Test status
Simulation time 197296039155 ps
CPU time 492.79 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 01:02:05 PM PDT 24
Peak memory 272632 kb
Host smart-a5905d09-00b2-4bdd-98a1-7b7c99826a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704156501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1704156501
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1896933189
Short name T315
Test name
Test status
Simulation time 8719078665 ps
CPU time 23.83 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 216828 kb
Host smart-20556116-41b6-47d8-b503-68603f3040b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896933189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1896933189
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3696651432
Short name T938
Test name
Test status
Simulation time 482226330 ps
CPU time 3.54 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:53:53 PM PDT 24
Peak memory 216276 kb
Host smart-151f4079-14d0-476b-85ec-9f0baaa757d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696651432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3696651432
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3419799627
Short name T772
Test name
Test status
Simulation time 108996880 ps
CPU time 1.08 seconds
Started May 12 12:53:42 PM PDT 24
Finished May 12 12:53:45 PM PDT 24
Peak memory 207852 kb
Host smart-ede57b99-214a-40c6-96dd-d8eb4cc715bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419799627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3419799627
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3414450066
Short name T53
Test name
Test status
Simulation time 36005694 ps
CPU time 0.75 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:48 PM PDT 24
Peak memory 205848 kb
Host smart-e350fb7f-5f9d-4f28-b416-e4b9625f3ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414450066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3414450066
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2821200446
Short name T909
Test name
Test status
Simulation time 3266784395 ps
CPU time 13.82 seconds
Started May 12 12:53:55 PM PDT 24
Finished May 12 12:54:09 PM PDT 24
Peak memory 229608 kb
Host smart-7e67bc79-60bc-444a-9df5-60082192f18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821200446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2821200446
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1845802246
Short name T459
Test name
Test status
Simulation time 63152426 ps
CPU time 0.71 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 205380 kb
Host smart-d65c5c5a-22a8-4403-b489-e19eba327b97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845802246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1845802246
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.662179953
Short name T808
Test name
Test status
Simulation time 66138935 ps
CPU time 3.21 seconds
Started May 12 12:53:46 PM PDT 24
Finished May 12 12:53:51 PM PDT 24
Peak memory 233792 kb
Host smart-1905805f-fd32-40c4-ac06-446f9fda2df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662179953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.662179953
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1383669134
Short name T19
Test name
Test status
Simulation time 20069633 ps
CPU time 0.81 seconds
Started May 12 12:53:49 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 206668 kb
Host smart-85561724-67d0-4ef7-984d-9c2f2f22ddf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383669134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1383669134
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1215183130
Short name T405
Test name
Test status
Simulation time 97382463027 ps
CPU time 195.04 seconds
Started May 12 12:53:55 PM PDT 24
Finished May 12 12:57:10 PM PDT 24
Peak memory 255224 kb
Host smart-a26fadb4-1384-4d37-9a34-8545e69aa9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215183130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1215183130
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3512018556
Short name T37
Test name
Test status
Simulation time 15429402475 ps
CPU time 77.87 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:55:10 PM PDT 24
Peak memory 251316 kb
Host smart-c31a7b4a-d3f4-465b-8b74-9a8e51848a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512018556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3512018556
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1144005032
Short name T197
Test name
Test status
Simulation time 13211734137 ps
CPU time 97.74 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:55:29 PM PDT 24
Peak memory 250956 kb
Host smart-762b000d-0289-4d23-8aa2-5e8c8549636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144005032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1144005032
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3667988038
Short name T680
Test name
Test status
Simulation time 7496673350 ps
CPU time 31.82 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 232908 kb
Host smart-ca8af34a-8122-4563-b027-06f172296902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667988038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3667988038
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2733584033
Short name T200
Test name
Test status
Simulation time 124427158 ps
CPU time 2.95 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 233792 kb
Host smart-bee6b705-0508-43c9-9ce5-6a39e30797d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733584033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2733584033
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.41273729
Short name T548
Test name
Test status
Simulation time 14360393544 ps
CPU time 16.66 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 240860 kb
Host smart-3cd53960-711a-455d-b1bf-bf7084cb7d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41273729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.41273729
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.736805347
Short name T246
Test name
Test status
Simulation time 466119641 ps
CPU time 2.37 seconds
Started May 12 12:53:45 PM PDT 24
Finished May 12 12:53:49 PM PDT 24
Peak memory 218724 kb
Host smart-eaca229c-4241-48e0-9df4-e7a7bb58ebf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736805347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.736805347
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3149648751
Short name T343
Test name
Test status
Simulation time 325571256 ps
CPU time 2.83 seconds
Started May 12 12:53:44 PM PDT 24
Finished May 12 12:53:48 PM PDT 24
Peak memory 216704 kb
Host smart-1c4bc89b-2162-4f12-ba82-acbbb0bbe222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149648751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3149648751
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.450673700
Short name T687
Test name
Test status
Simulation time 803449576 ps
CPU time 13.19 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:54:04 PM PDT 24
Peak memory 218660 kb
Host smart-2eaf575f-d18c-4100-ac47-3b25ad0ebdaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=450673700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.450673700
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1027234232
Short name T843
Test name
Test status
Simulation time 3565160208 ps
CPU time 35.57 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:30 PM PDT 24
Peak memory 250452 kb
Host smart-1b07777a-be8b-4859-82c6-69e93a7cc467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027234232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1027234232
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.824056127
Short name T403
Test name
Test status
Simulation time 831211716 ps
CPU time 1.81 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 216264 kb
Host smart-820209e5-5ebb-498f-9294-7aa1befd12d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824056127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.824056127
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3768916159
Short name T569
Test name
Test status
Simulation time 18434000668 ps
CPU time 27 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 216464 kb
Host smart-3a03745a-ab86-4b43-9967-4f8c3f094e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768916159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3768916159
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4170129538
Short name T889
Test name
Test status
Simulation time 153781645 ps
CPU time 1.19 seconds
Started May 12 12:54:01 PM PDT 24
Finished May 12 12:54:02 PM PDT 24
Peak memory 207876 kb
Host smart-492bd48c-49d3-44c0-841d-f750f1188f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170129538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4170129538
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3263511128
Short name T137
Test name
Test status
Simulation time 83632240 ps
CPU time 0.89 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 205936 kb
Host smart-3d46a84c-c2be-49a7-b2cb-eaabdcb15926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263511128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3263511128
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.144610508
Short name T510
Test name
Test status
Simulation time 75954363101 ps
CPU time 14.75 seconds
Started May 12 12:53:51 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 234452 kb
Host smart-eb2478c4-b750-4725-8c1e-994b27d0b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144610508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.144610508
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2559860227
Short name T565
Test name
Test status
Simulation time 31770875 ps
CPU time 0.72 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:53:52 PM PDT 24
Peak memory 204640 kb
Host smart-17ff966a-9013-448e-8202-3e3ec4035760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559860227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2559860227
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3109634867
Short name T104
Test name
Test status
Simulation time 211499477 ps
CPU time 3.83 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 219872 kb
Host smart-62ef1791-4a2e-4582-8a2e-9344131dde6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109634867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3109634867
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3202726335
Short name T351
Test name
Test status
Simulation time 17139061 ps
CPU time 0.75 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:54:04 PM PDT 24
Peak memory 205344 kb
Host smart-139d1d77-07df-4e0b-b02c-0a28e8b486d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202726335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3202726335
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1782553281
Short name T786
Test name
Test status
Simulation time 25006809356 ps
CPU time 233.97 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:57:47 PM PDT 24
Peak memory 249292 kb
Host smart-6c61c848-deb5-4de5-9b47-d815a3dfb315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782553281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1782553281
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1852912498
Short name T824
Test name
Test status
Simulation time 278230908 ps
CPU time 3.51 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 224480 kb
Host smart-c4315ae9-45c6-4e7a-80ca-90bdebdfd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852912498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1852912498
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2348598184
Short name T435
Test name
Test status
Simulation time 1864551025 ps
CPU time 19.56 seconds
Started May 12 12:54:00 PM PDT 24
Finished May 12 12:54:20 PM PDT 24
Peak memory 234168 kb
Host smart-bf83a402-77b8-4970-8782-40bb99120b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348598184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2348598184
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.781020662
Short name T653
Test name
Test status
Simulation time 6948119049 ps
CPU time 34.72 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:54:26 PM PDT 24
Peak memory 216824 kb
Host smart-9d7b008a-58e9-4398-aaac-a8d99e6df3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781020662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.781020662
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.534001330
Short name T601
Test name
Test status
Simulation time 676816858 ps
CPU time 10.51 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 227576 kb
Host smart-3eb22550-aed2-4c0c-b8c1-2659d7d5ab9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534001330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.534001330
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4106646442
Short name T217
Test name
Test status
Simulation time 2114477563 ps
CPU time 4.86 seconds
Started May 12 12:53:52 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 217724 kb
Host smart-8fabbc8b-09dc-45b0-b245-b1a9ca28345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106646442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4106646442
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3654388219
Short name T674
Test name
Test status
Simulation time 197132593 ps
CPU time 5.22 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:15 PM PDT 24
Peak memory 222864 kb
Host smart-459d8d58-a3ce-41cb-a452-7e958ab365c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654388219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3654388219
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3047403595
Short name T78
Test name
Test status
Simulation time 54664620 ps
CPU time 1.22 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 206960 kb
Host smart-083c7ece-0494-4828-bb8a-ccc29dc4d7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047403595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3047403595
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2774816596
Short name T7
Test name
Test status
Simulation time 2710001860 ps
CPU time 16.47 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:54:28 PM PDT 24
Peak memory 216564 kb
Host smart-60464112-a664-4e3f-bd5a-a71e20f03592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774816596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2774816596
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3547450491
Short name T483
Test name
Test status
Simulation time 569747000 ps
CPU time 2.59 seconds
Started May 12 12:53:55 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 216204 kb
Host smart-63d71556-f0c6-44e3-89a7-cb2fd04b409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547450491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3547450491
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2913459112
Short name T969
Test name
Test status
Simulation time 723973304 ps
CPU time 2.55 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 216108 kb
Host smart-a4c8eaed-2273-4238-a8b8-65e9dbd8c5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913459112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2913459112
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2306954509
Short name T821
Test name
Test status
Simulation time 188092376 ps
CPU time 0.72 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 205724 kb
Host smart-ab4970af-367c-428a-a40d-cc173b22d3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306954509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2306954509
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3526786061
Short name T172
Test name
Test status
Simulation time 153592304608 ps
CPU time 42.51 seconds
Started May 12 12:53:57 PM PDT 24
Finished May 12 12:54:41 PM PDT 24
Peak memory 240844 kb
Host smart-71da0b1f-a3be-4ba3-a4c5-93f556a9cdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526786061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3526786061
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3293490120
Short name T423
Test name
Test status
Simulation time 13780932 ps
CPU time 0.74 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 205644 kb
Host smart-9b72bda2-c289-4590-bc0b-6aee42875d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293490120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3293490120
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1920888763
Short name T715
Test name
Test status
Simulation time 259400771 ps
CPU time 5.08 seconds
Started May 12 12:53:53 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 233908 kb
Host smart-93db9bac-5b41-4423-ac85-a79fc49a822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920888763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1920888763
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.552246798
Short name T322
Test name
Test status
Simulation time 52140895 ps
CPU time 0.75 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 205340 kb
Host smart-7277852a-4e94-49e5-982a-9597d84918e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552246798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.552246798
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1213541021
Short name T713
Test name
Test status
Simulation time 15922329921 ps
CPU time 9.44 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 234268 kb
Host smart-15ed2400-04bf-4b8f-935b-ffa77634eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213541021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1213541021
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3680637628
Short name T261
Test name
Test status
Simulation time 28867986445 ps
CPU time 311.45 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:59:11 PM PDT 24
Peak memory 265768 kb
Host smart-eee62a45-9889-48fd-914a-020aec78cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680637628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3680637628
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3750242510
Short name T627
Test name
Test status
Simulation time 6595842258 ps
CPU time 101.3 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:55:41 PM PDT 24
Peak memory 249360 kb
Host smart-5191b0f0-350e-48d2-95f8-6bb3c6d1f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750242510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3750242510
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3528176841
Short name T848
Test name
Test status
Simulation time 3991284479 ps
CPU time 4.69 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 218856 kb
Host smart-09bf560c-71be-44c6-9927-0c95cdbd44e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528176841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3528176841
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.322511392
Short name T750
Test name
Test status
Simulation time 1046568105 ps
CPU time 14.49 seconds
Started May 12 12:53:48 PM PDT 24
Finished May 12 12:54:04 PM PDT 24
Peak memory 238860 kb
Host smart-ccb611ae-bbc2-46a0-9074-f379d5d7ede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322511392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.322511392
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.310601092
Short name T610
Test name
Test status
Simulation time 279554911 ps
CPU time 3.81 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 224400 kb
Host smart-ce7061f5-4763-4174-8bb9-4c5ef16fb3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310601092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.310601092
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2391593837
Short name T448
Test name
Test status
Simulation time 2981711732 ps
CPU time 5.85 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:02 PM PDT 24
Peak memory 218548 kb
Host smart-ff1277bf-9b50-4155-8b7a-4eb3c09f0176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391593837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2391593837
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.187832577
Short name T148
Test name
Test status
Simulation time 4785282982 ps
CPU time 13.93 seconds
Started May 12 12:54:13 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 222924 kb
Host smart-ae9ccd6d-c734-4fb4-8cc6-ca39a804431e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=187832577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.187832577
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.573835160
Short name T437
Test name
Test status
Simulation time 38709211 ps
CPU time 0.68 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:53:55 PM PDT 24
Peak memory 205572 kb
Host smart-1acf9d17-867b-4c09-8996-72ddfd7e6d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573835160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.573835160
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.547866457
Short name T946
Test name
Test status
Simulation time 756785788 ps
CPU time 4.58 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 216268 kb
Host smart-39107b73-d91f-4ad0-9ce8-031097a084fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547866457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.547866457
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1066615595
Short name T667
Test name
Test status
Simulation time 48858082 ps
CPU time 0.97 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:57 PM PDT 24
Peak memory 207912 kb
Host smart-330f852a-c9f1-40c1-bbbb-a6629157f476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066615595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1066615595
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.360120400
Short name T394
Test name
Test status
Simulation time 13776231 ps
CPU time 0.68 seconds
Started May 12 12:54:01 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 205724 kb
Host smart-55b87244-88d3-4223-8558-ea33753bb083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360120400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.360120400
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1144392066
Short name T861
Test name
Test status
Simulation time 1056012605 ps
CPU time 9.87 seconds
Started May 12 12:53:50 PM PDT 24
Finished May 12 12:54:01 PM PDT 24
Peak memory 240568 kb
Host smart-6f9e5679-aec5-48aa-b3c2-e1b8394192c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144392066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1144392066
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3700542019
Short name T334
Test name
Test status
Simulation time 95710717 ps
CPU time 0.73 seconds
Started May 12 12:51:15 PM PDT 24
Finished May 12 12:51:17 PM PDT 24
Peak memory 205264 kb
Host smart-f981dd79-923c-4fdf-8f82-3869b02d9b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700542019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
700542019
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3976208999
Short name T372
Test name
Test status
Simulation time 136918858 ps
CPU time 2.35 seconds
Started May 12 12:51:17 PM PDT 24
Finished May 12 12:51:20 PM PDT 24
Peak memory 220960 kb
Host smart-4b177380-6582-4d7d-8339-c148c2dea0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976208999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3976208999
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3225310361
Short name T583
Test name
Test status
Simulation time 60918239 ps
CPU time 0.76 seconds
Started May 12 12:51:03 PM PDT 24
Finished May 12 12:51:04 PM PDT 24
Peak memory 206400 kb
Host smart-947c5da0-0a6f-45a7-a4a3-2dfb44e18e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225310361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3225310361
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1582515770
Short name T926
Test name
Test status
Simulation time 2144968917 ps
CPU time 38.77 seconds
Started May 12 12:51:06 PM PDT 24
Finished May 12 12:51:45 PM PDT 24
Peak memory 249252 kb
Host smart-07b65850-cfeb-43ca-8cd7-25159b4bf387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582515770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1582515770
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3893465812
Short name T87
Test name
Test status
Simulation time 6784418417 ps
CPU time 31.52 seconds
Started May 12 12:51:10 PM PDT 24
Finished May 12 12:51:43 PM PDT 24
Peak memory 249864 kb
Host smart-aa6e2228-6199-42d5-a3a1-d7b295077045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893465812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3893465812
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1493537218
Short name T810
Test name
Test status
Simulation time 2099769461 ps
CPU time 21.18 seconds
Started May 12 12:51:06 PM PDT 24
Finished May 12 12:51:29 PM PDT 24
Peak memory 217376 kb
Host smart-eb5e014b-3aae-4f64-ad5e-bd541e6b8de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493537218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1493537218
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4288338199
Short name T48
Test name
Test status
Simulation time 553788144 ps
CPU time 3.43 seconds
Started May 12 12:51:06 PM PDT 24
Finished May 12 12:51:10 PM PDT 24
Peak memory 232604 kb
Host smart-b26bbdb0-90f8-4040-8f19-99c6174b75e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288338199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4288338199
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3997633165
Short name T660
Test name
Test status
Simulation time 345753978 ps
CPU time 3.71 seconds
Started May 12 12:51:08 PM PDT 24
Finished May 12 12:51:12 PM PDT 24
Peak memory 219564 kb
Host smart-639e849a-8aec-4d65-9797-48f90e134d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997633165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3997633165
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3684058141
Short name T38
Test name
Test status
Simulation time 34083034231 ps
CPU time 80.39 seconds
Started May 12 12:51:05 PM PDT 24
Finished May 12 12:52:26 PM PDT 24
Peak memory 219652 kb
Host smart-7886bacd-5aa7-4742-ab3e-696e48cd36f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684058141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3684058141
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1269454010
Short name T792
Test name
Test status
Simulation time 112998058 ps
CPU time 0.97 seconds
Started May 12 12:51:02 PM PDT 24
Finished May 12 12:51:04 PM PDT 24
Peak memory 217912 kb
Host smart-ba13fc70-f748-4327-8ce9-c14c60952b54
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269454010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1269454010
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1478463907
Short name T809
Test name
Test status
Simulation time 7035295218 ps
CPU time 6.83 seconds
Started May 12 12:51:07 PM PDT 24
Finished May 12 12:51:14 PM PDT 24
Peak memory 223688 kb
Host smart-1aa9b02c-5ee2-4f2f-9ce8-7d9802c021f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478463907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1478463907
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2298539511
Short name T431
Test name
Test status
Simulation time 106708969 ps
CPU time 2.63 seconds
Started May 12 12:51:07 PM PDT 24
Finished May 12 12:51:10 PM PDT 24
Peak memory 233660 kb
Host smart-c33aaf68-24db-4d5f-90b0-1fdd2cacd72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298539511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2298539511
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.240767800
Short name T584
Test name
Test status
Simulation time 698534411 ps
CPU time 5.67 seconds
Started May 12 12:51:15 PM PDT 24
Finished May 12 12:51:23 PM PDT 24
Peak memory 218976 kb
Host smart-1096192b-1a49-420a-bfb9-39f110258c3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=240767800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.240767800
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3940301797
Short name T83
Test name
Test status
Simulation time 225754336 ps
CPU time 1.09 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:19 PM PDT 24
Peak memory 235136 kb
Host smart-903322a3-35c3-4d58-b863-b2b8cc9b7f97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940301797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3940301797
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1473624677
Short name T164
Test name
Test status
Simulation time 25037741846 ps
CPU time 244.67 seconds
Started May 12 12:51:15 PM PDT 24
Finished May 12 12:55:21 PM PDT 24
Peak memory 265736 kb
Host smart-1088cfcc-f220-4780-90b4-87308fd0048d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473624677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1473624677
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3146679968
Short name T669
Test name
Test status
Simulation time 5553798769 ps
CPU time 22.06 seconds
Started May 12 12:51:09 PM PDT 24
Finished May 12 12:51:32 PM PDT 24
Peak memory 216740 kb
Host smart-4c725a05-61a5-4777-bb92-1d090c9a8345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146679968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3146679968
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4131324094
Short name T887
Test name
Test status
Simulation time 64386901149 ps
CPU time 21.66 seconds
Started May 12 12:51:15 PM PDT 24
Finished May 12 12:51:38 PM PDT 24
Peak memory 216388 kb
Host smart-a0201056-2637-4131-9552-c73a4b19302c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131324094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4131324094
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3778771531
Short name T774
Test name
Test status
Simulation time 69338935 ps
CPU time 1.15 seconds
Started May 12 12:51:07 PM PDT 24
Finished May 12 12:51:09 PM PDT 24
Peak memory 207852 kb
Host smart-ccb2d341-ef14-4ea6-90d4-57b3058d4f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778771531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3778771531
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2156356534
Short name T903
Test name
Test status
Simulation time 14435101 ps
CPU time 0.69 seconds
Started May 12 12:51:03 PM PDT 24
Finished May 12 12:51:04 PM PDT 24
Peak memory 205756 kb
Host smart-4c41a0e5-3db9-4f1b-820a-cea0b3a932dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156356534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2156356534
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3315025375
Short name T767
Test name
Test status
Simulation time 1012171987 ps
CPU time 7.69 seconds
Started May 12 12:51:07 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 236532 kb
Host smart-25280c5f-74f4-46c4-9f4a-4199735e2692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315025375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3315025375
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2577651963
Short name T559
Test name
Test status
Simulation time 15413262 ps
CPU time 0.81 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:53:59 PM PDT 24
Peak memory 205540 kb
Host smart-9920c28c-8d03-45a6-9d0f-36e8251825d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577651963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2577651963
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.457450170
Short name T383
Test name
Test status
Simulation time 249635299 ps
CPU time 3.03 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:14 PM PDT 24
Peak memory 233852 kb
Host smart-99e967e7-d4bf-49e3-be22-55c4f6bb7a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457450170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.457450170
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1695746055
Short name T914
Test name
Test status
Simulation time 31070344 ps
CPU time 0.84 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:53:58 PM PDT 24
Peak memory 206360 kb
Host smart-a7f172d0-370a-4cc7-b3de-cc9aa3d88b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695746055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1695746055
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3996040208
Short name T174
Test name
Test status
Simulation time 63338050571 ps
CPU time 229.83 seconds
Started May 12 12:54:00 PM PDT 24
Finished May 12 12:57:50 PM PDT 24
Peak memory 249392 kb
Host smart-d370399f-b047-4c3d-9da5-08eeba3122a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996040208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3996040208
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2211532587
Short name T187
Test name
Test status
Simulation time 170429388172 ps
CPU time 247.95 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:58:07 PM PDT 24
Peak memory 257256 kb
Host smart-033935bc-4d84-4e48-aefd-2bf06533edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211532587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2211532587
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1020634256
Short name T673
Test name
Test status
Simulation time 3049965506 ps
CPU time 65.84 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:55:03 PM PDT 24
Peak memory 249384 kb
Host smart-1b983b38-cef8-4ad1-a211-8fc128145aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020634256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1020634256
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3889066663
Short name T404
Test name
Test status
Simulation time 1073636043 ps
CPU time 7.29 seconds
Started May 12 12:54:05 PM PDT 24
Finished May 12 12:54:13 PM PDT 24
Peak memory 240820 kb
Host smart-12155e05-4d4f-4ab7-92b2-13b1499b4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889066663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3889066663
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4006523532
Short name T274
Test name
Test status
Simulation time 5582800882 ps
CPU time 29.26 seconds
Started May 12 12:53:54 PM PDT 24
Finished May 12 12:54:24 PM PDT 24
Peak memory 219304 kb
Host smart-1bbdfebc-5a28-407a-a718-d99084ad7cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006523532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4006523532
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4211897459
Short name T923
Test name
Test status
Simulation time 1191243119 ps
CPU time 14.08 seconds
Started May 12 12:54:14 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 234160 kb
Host smart-068b8172-f4c8-48c8-8466-bc58f3f6f1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211897459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4211897459
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1204453209
Short name T386
Test name
Test status
Simulation time 1069188551 ps
CPU time 7.75 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:54:19 PM PDT 24
Peak memory 233552 kb
Host smart-c86b7d83-50c0-4521-9803-e7877ec65362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204453209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1204453209
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.606603260
Short name T294
Test name
Test status
Simulation time 11105225331 ps
CPU time 11.03 seconds
Started May 12 12:53:57 PM PDT 24
Finished May 12 12:54:09 PM PDT 24
Peak memory 233884 kb
Host smart-d0e4268a-f5bb-494c-bec4-a980bbaa2593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606603260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.606603260
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3341133350
Short name T149
Test name
Test status
Simulation time 459241426 ps
CPU time 3.88 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:09 PM PDT 24
Peak memory 223000 kb
Host smart-0e2065fe-fc7c-4db1-944a-1574120fc3bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3341133350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3341133350
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3742481303
Short name T860
Test name
Test status
Simulation time 31066715685 ps
CPU time 236.38 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:57:54 PM PDT 24
Peak memory 249280 kb
Host smart-4ebb7f6e-f3f1-4db9-8ebc-a33d4d069967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742481303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3742481303
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3779708948
Short name T489
Test name
Test status
Simulation time 75890672913 ps
CPU time 50.92 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:47 PM PDT 24
Peak memory 216388 kb
Host smart-02013c58-b83c-45d9-84e8-9856f6c036dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779708948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3779708948
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1134962031
Short name T409
Test name
Test status
Simulation time 17465635781 ps
CPU time 14.19 seconds
Started May 12 12:53:57 PM PDT 24
Finished May 12 12:54:12 PM PDT 24
Peak memory 216344 kb
Host smart-1439d56e-1ced-42fd-b00d-cde89c2f4cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134962031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1134962031
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.347697103
Short name T540
Test name
Test status
Simulation time 340312277 ps
CPU time 1.13 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 216248 kb
Host smart-ec69243a-dfc1-4745-ad96-433cbd3eec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347697103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.347697103
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3681440227
Short name T711
Test name
Test status
Simulation time 21458817 ps
CPU time 0.69 seconds
Started May 12 12:53:55 PM PDT 24
Finished May 12 12:53:56 PM PDT 24
Peak memory 205360 kb
Host smart-a19cb41e-72f6-423c-a727-fccd9558738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681440227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3681440227
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.4134163661
Short name T50
Test name
Test status
Simulation time 19904757140 ps
CPU time 11.81 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:10 PM PDT 24
Peak memory 228932 kb
Host smart-232aa4da-b7f8-47d6-8db3-46398ddb574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134163661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4134163661
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1437537058
Short name T547
Test name
Test status
Simulation time 20591793 ps
CPU time 0.75 seconds
Started May 12 12:54:00 PM PDT 24
Finished May 12 12:54:02 PM PDT 24
Peak memory 205320 kb
Host smart-d3bed122-3a65-4fa2-9f67-29bd8c43bb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437537058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1437537058
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3183804701
Short name T492
Test name
Test status
Simulation time 461491787 ps
CPU time 7.82 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:12 PM PDT 24
Peak memory 224480 kb
Host smart-ed24a4ac-1d58-4b74-9255-69d4a3bf3316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183804701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3183804701
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3275044081
Short name T960
Test name
Test status
Simulation time 27667612 ps
CPU time 0.74 seconds
Started May 12 12:54:05 PM PDT 24
Finished May 12 12:54:06 PM PDT 24
Peak memory 205332 kb
Host smart-f505dc63-bac8-4092-89c3-c1cb9251b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275044081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3275044081
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3550195644
Short name T872
Test name
Test status
Simulation time 19699171240 ps
CPU time 178.09 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:57:09 PM PDT 24
Peak memory 252932 kb
Host smart-c4e8ad57-168a-41d1-bbf6-61ccbd23c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550195644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3550195644
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3189378843
Short name T280
Test name
Test status
Simulation time 383778145817 ps
CPU time 836.44 seconds
Started May 12 12:54:08 PM PDT 24
Finished May 12 01:08:05 PM PDT 24
Peak memory 252444 kb
Host smart-85e6f81d-5d98-4ce6-acf2-95c9b581055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189378843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3189378843
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.12482799
Short name T603
Test name
Test status
Simulation time 256198811 ps
CPU time 3.34 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 224496 kb
Host smart-8afb3d16-545c-4c20-b8a3-7776be664e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12482799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.12482799
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2865168995
Short name T932
Test name
Test status
Simulation time 1739556183 ps
CPU time 6.16 seconds
Started May 12 12:54:12 PM PDT 24
Finished May 12 12:54:19 PM PDT 24
Peak memory 232672 kb
Host smart-18c5254f-9100-45c8-a575-ee3995729cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865168995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2865168995
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4205870401
Short name T416
Test name
Test status
Simulation time 101409487 ps
CPU time 3.36 seconds
Started May 12 12:54:02 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 218616 kb
Host smart-2fc3ffee-3923-410b-8642-203bd7a98720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205870401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4205870401
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2080484629
Short name T230
Test name
Test status
Simulation time 2738954731 ps
CPU time 4.28 seconds
Started May 12 12:53:55 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 219524 kb
Host smart-1ca37b46-b7de-47fb-967a-f4b7bd9fe755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080484629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2080484629
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1210599100
Short name T668
Test name
Test status
Simulation time 489518418 ps
CPU time 2.55 seconds
Started May 12 12:54:02 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 224400 kb
Host smart-28f8df56-eec0-4db2-b110-ddba7bae90f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210599100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1210599100
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3307723513
Short name T676
Test name
Test status
Simulation time 285106119 ps
CPU time 3.34 seconds
Started May 12 12:53:57 PM PDT 24
Finished May 12 12:54:01 PM PDT 24
Peak memory 222892 kb
Host smart-cf376c9e-0273-4823-87df-db97e0816f65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3307723513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3307723513
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3051655097
Short name T773
Test name
Test status
Simulation time 80116575 ps
CPU time 0.98 seconds
Started May 12 12:54:00 PM PDT 24
Finished May 12 12:54:01 PM PDT 24
Peak memory 206672 kb
Host smart-d84088d8-7099-4eea-a96f-075ef25c43f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051655097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3051655097
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1855633683
Short name T320
Test name
Test status
Simulation time 661306934 ps
CPU time 9.34 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:08 PM PDT 24
Peak memory 216344 kb
Host smart-cf312db6-917f-4690-8f94-a1d893ed6f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855633683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1855633683
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3897914872
Short name T341
Test name
Test status
Simulation time 4320009262 ps
CPU time 4.12 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:54:04 PM PDT 24
Peak memory 216488 kb
Host smart-c7aa565c-735a-4be2-938c-931258090392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897914872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3897914872
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3336976558
Short name T428
Test name
Test status
Simulation time 55561619 ps
CPU time 1.27 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 216368 kb
Host smart-ec22e542-7123-443d-a0c1-07b27cbb6c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336976558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3336976558
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1832889005
Short name T85
Test name
Test status
Simulation time 73273693 ps
CPU time 0.92 seconds
Started May 12 12:54:05 PM PDT 24
Finished May 12 12:54:06 PM PDT 24
Peak memory 205780 kb
Host smart-90939b4f-0667-4070-9ed0-3db54d5cf526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832889005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1832889005
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.961158906
Short name T353
Test name
Test status
Simulation time 37923969 ps
CPU time 0.75 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:54:00 PM PDT 24
Peak memory 204692 kb
Host smart-6f857dfd-a903-4894-a3df-32a52e95c178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961158906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.961158906
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.670535870
Short name T757
Test name
Test status
Simulation time 7838826292 ps
CPU time 9.74 seconds
Started May 12 12:54:07 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 235168 kb
Host smart-ef4d2593-b799-42e0-987b-34a38138006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670535870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.670535870
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4212484506
Short name T859
Test name
Test status
Simulation time 26003916 ps
CPU time 0.75 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:10 PM PDT 24
Peak memory 205328 kb
Host smart-7c0cc88d-abc7-495a-80f8-24030d8af224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212484506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4212484506
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2035414411
Short name T73
Test name
Test status
Simulation time 30526982775 ps
CPU time 31.41 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 237216 kb
Host smart-d5d0fd5a-1ca0-4094-a33b-43e80108843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035414411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2035414411
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.576523199
Short name T555
Test name
Test status
Simulation time 2517302004 ps
CPU time 38.51 seconds
Started May 12 12:54:01 PM PDT 24
Finished May 12 12:54:40 PM PDT 24
Peak memory 249344 kb
Host smart-c2e12e08-caa4-40c1-9f51-15055b8b77ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576523199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.576523199
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1224370430
Short name T955
Test name
Test status
Simulation time 4095910924 ps
CPU time 50.22 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:55 PM PDT 24
Peak memory 232796 kb
Host smart-832ea982-4e87-4f02-abfd-1c51b39ec17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224370430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1224370430
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2239533760
Short name T840
Test name
Test status
Simulation time 645392522 ps
CPU time 2.81 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:54:02 PM PDT 24
Peak memory 232968 kb
Host smart-cd64680b-79f5-49e0-8a3d-b6b1ae1ac2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239533760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2239533760
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4163335752
Short name T283
Test name
Test status
Simulation time 15183597708 ps
CPU time 153.2 seconds
Started May 12 12:54:01 PM PDT 24
Finished May 12 12:56:35 PM PDT 24
Peak memory 232500 kb
Host smart-6a00a6e8-3bf8-4f6e-b730-8d9e28956fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163335752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4163335752
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.537775071
Short name T831
Test name
Test status
Simulation time 65639115 ps
CPU time 2.48 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:54:02 PM PDT 24
Peak memory 221100 kb
Host smart-6012b43e-bc59-44f4-a2eb-4d0af804b0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537775071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.537775071
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.183776453
Short name T662
Test name
Test status
Simulation time 4571900859 ps
CPU time 14.38 seconds
Started May 12 12:54:02 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 233284 kb
Host smart-e55274be-017c-4e72-8e34-a805fccc5ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183776453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.183776453
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3400369685
Short name T406
Test name
Test status
Simulation time 2584405578 ps
CPU time 8.5 seconds
Started May 12 12:54:12 PM PDT 24
Finished May 12 12:54:21 PM PDT 24
Peak memory 221896 kb
Host smart-87efce18-42bd-4e89-82d2-fce487ba3995
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3400369685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3400369685
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3506580733
Short name T247
Test name
Test status
Simulation time 70747045944 ps
CPU time 98.18 seconds
Started May 12 12:53:58 PM PDT 24
Finished May 12 12:55:36 PM PDT 24
Peak memory 241008 kb
Host smart-8b8edc5d-5e73-4445-aa32-6856f8f8bb1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506580733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3506580733
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1568133463
Short name T700
Test name
Test status
Simulation time 2052506867 ps
CPU time 21.3 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:31 PM PDT 24
Peak memory 216560 kb
Host smart-75ab37fa-58eb-420d-90aa-ec00c0f8e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568133463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1568133463
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1797278426
Short name T623
Test name
Test status
Simulation time 4826456703 ps
CPU time 17 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:26 PM PDT 24
Peak memory 216480 kb
Host smart-9992629c-a132-41a1-8472-c4a0c1c9b6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797278426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1797278426
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3622487536
Short name T929
Test name
Test status
Simulation time 45222039 ps
CPU time 0.73 seconds
Started May 12 12:54:14 PM PDT 24
Finished May 12 12:54:15 PM PDT 24
Peak memory 205752 kb
Host smart-fe12c952-5696-4da4-93c2-dd8834a148e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622487536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3622487536
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3978582357
Short name T881
Test name
Test status
Simulation time 136669536 ps
CPU time 0.91 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:54:01 PM PDT 24
Peak memory 205776 kb
Host smart-2cbe9fb4-4a7e-4882-b184-5bf6aa7f762b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978582357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3978582357
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1023153865
Short name T574
Test name
Test status
Simulation time 1569486620 ps
CPU time 8.47 seconds
Started May 12 12:53:56 PM PDT 24
Finished May 12 12:54:05 PM PDT 24
Peak memory 219384 kb
Host smart-9e61bb11-8174-4fee-9449-601541d73355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023153865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1023153865
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1325782942
Short name T342
Test name
Test status
Simulation time 21565162 ps
CPU time 0.79 seconds
Started May 12 12:54:05 PM PDT 24
Finished May 12 12:54:06 PM PDT 24
Peak memory 204960 kb
Host smart-0e58ff68-8c22-430a-8377-37fd3d0d4918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325782942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1325782942
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3094193771
Short name T513
Test name
Test status
Simulation time 426272151 ps
CPU time 4.8 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:15 PM PDT 24
Peak memory 233636 kb
Host smart-71ce86c3-be95-4239-ad64-35d8b8578ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094193771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3094193771
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.563700985
Short name T586
Test name
Test status
Simulation time 50397618 ps
CPU time 0.77 seconds
Started May 12 12:53:59 PM PDT 24
Finished May 12 12:54:01 PM PDT 24
Peak memory 206628 kb
Host smart-6383b429-8f47-42bd-adcd-53b7bf6422b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563700985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.563700985
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1286305987
Short name T215
Test name
Test status
Simulation time 8491074045 ps
CPU time 30.06 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:54:41 PM PDT 24
Peak memory 236728 kb
Host smart-5f809853-11e6-474e-a3fd-8c26d1b4dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286305987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1286305987
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3225714774
Short name T629
Test name
Test status
Simulation time 11723092458 ps
CPU time 116.9 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:56:07 PM PDT 24
Peak memory 241116 kb
Host smart-cd3baffe-4811-440e-a0d8-e4ae50fff985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225714774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3225714774
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3264549621
Short name T255
Test name
Test status
Simulation time 795405002 ps
CPU time 12.86 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:23 PM PDT 24
Peak memory 232788 kb
Host smart-0d7b253c-44c3-4e03-adf6-2e71e936f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264549621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3264549621
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.541077221
Short name T788
Test name
Test status
Simulation time 317497119 ps
CPU time 6.97 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:16 PM PDT 24
Peak memory 232664 kb
Host smart-f9c6f5ec-a081-4684-88fa-f8b3d11904e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541077221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.541077221
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3315704697
Short name T202
Test name
Test status
Simulation time 9500880580 ps
CPU time 40.09 seconds
Started May 12 12:54:14 PM PDT 24
Finished May 12 12:54:54 PM PDT 24
Peak memory 234168 kb
Host smart-0ea41ba7-159d-4a92-b4f4-463fb8a2c7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315704697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3315704697
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1013967589
Short name T866
Test name
Test status
Simulation time 14725567796 ps
CPU time 26.83 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 236080 kb
Host smart-157ef7e2-05a8-4d34-8c7e-99132a0665c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013967589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1013967589
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4252649793
Short name T518
Test name
Test status
Simulation time 1478799419 ps
CPU time 3.16 seconds
Started May 12 12:54:13 PM PDT 24
Finished May 12 12:54:16 PM PDT 24
Peak memory 233904 kb
Host smart-23d2843d-ad06-4319-9fb3-37adede8418c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252649793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4252649793
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3528395918
Short name T6
Test name
Test status
Simulation time 165479232 ps
CPU time 3.81 seconds
Started May 12 12:54:14 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 224384 kb
Host smart-f4394ff8-6c96-4e36-a876-2abc26d3333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528395918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3528395918
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1743952288
Short name T485
Test name
Test status
Simulation time 120708393 ps
CPU time 4.04 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:54:16 PM PDT 24
Peak memory 222856 kb
Host smart-489ee5a4-6190-417d-9d68-7f3119da8959
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1743952288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1743952288
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.487792695
Short name T752
Test name
Test status
Simulation time 34752142321 ps
CPU time 65.82 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:55:18 PM PDT 24
Peak memory 233400 kb
Host smart-79330a4c-8400-4c40-b2eb-5f97600e2406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487792695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.487792695
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4285843868
Short name T832
Test name
Test status
Simulation time 9205350632 ps
CPU time 24.82 seconds
Started May 12 12:54:02 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 216584 kb
Host smart-0b2f870d-9544-492d-b80e-8547339e5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285843868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4285843868
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.339067271
Short name T417
Test name
Test status
Simulation time 673312805 ps
CPU time 4.72 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:15 PM PDT 24
Peak memory 216308 kb
Host smart-ba49c02e-6695-4cd5-b325-f32200286cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339067271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.339067271
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3607852466
Short name T968
Test name
Test status
Simulation time 1359135977 ps
CPU time 5.29 seconds
Started May 12 12:54:27 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 216424 kb
Host smart-0625f688-ef1d-4c99-9eaa-6189ce2c6c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607852466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3607852466
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3815604929
Short name T876
Test name
Test status
Simulation time 814016952 ps
CPU time 0.95 seconds
Started May 12 12:54:16 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 206732 kb
Host smart-8afa6f78-59db-4f50-894d-dd3aa54224d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815604929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3815604929
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3973460131
Short name T190
Test name
Test status
Simulation time 5681688022 ps
CPU time 14.42 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:25 PM PDT 24
Peak memory 227240 kb
Host smart-4e90d6dd-10ab-42c4-8fb7-5dbf385c2665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973460131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3973460131
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2639709483
Short name T450
Test name
Test status
Simulation time 27419013 ps
CPU time 0.69 seconds
Started May 12 12:54:12 PM PDT 24
Finished May 12 12:54:14 PM PDT 24
Peak memory 205756 kb
Host smart-d8e2092a-b891-4a77-aca9-39cf7945e89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639709483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2639709483
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3428231764
Short name T683
Test name
Test status
Simulation time 296103044 ps
CPU time 4.25 seconds
Started May 12 12:54:12 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 218500 kb
Host smart-a5f4619b-2433-47e3-bc56-65ee78c5ebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428231764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3428231764
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2201093011
Short name T615
Test name
Test status
Simulation time 63187686 ps
CPU time 0.74 seconds
Started May 12 12:54:09 PM PDT 24
Finished May 12 12:54:10 PM PDT 24
Peak memory 206444 kb
Host smart-baefe6a5-3607-4b3f-a911-4418cb9b65c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201093011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2201093011
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2133910237
Short name T765
Test name
Test status
Simulation time 1686416943 ps
CPU time 23.35 seconds
Started May 12 12:54:05 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 235896 kb
Host smart-44606749-78ee-41b8-98d4-12b5cd445654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133910237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2133910237
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1645274356
Short name T804
Test name
Test status
Simulation time 15750212341 ps
CPU time 168.27 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:57:00 PM PDT 24
Peak memory 239748 kb
Host smart-619921cf-9c8a-4d45-b90d-f6cb12789333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645274356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1645274356
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2311876291
Short name T142
Test name
Test status
Simulation time 7690154061 ps
CPU time 55.99 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:55:18 PM PDT 24
Peak memory 255400 kb
Host smart-41bb6a33-badd-40cb-b9d7-62e12f7b2d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311876291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2311876291
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3595074228
Short name T502
Test name
Test status
Simulation time 2127786143 ps
CPU time 11.62 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 240856 kb
Host smart-e4a3ad9d-9d5e-4ef5-b67d-408aef29eb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595074228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3595074228
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2499605977
Short name T281
Test name
Test status
Simulation time 7412182906 ps
CPU time 12.46 seconds
Started May 12 12:54:18 PM PDT 24
Finished May 12 12:54:31 PM PDT 24
Peak memory 233980 kb
Host smart-d5632517-4b00-4310-ad12-d9b7ad8e48c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499605977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2499605977
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3075683847
Short name T567
Test name
Test status
Simulation time 1031628140 ps
CPU time 8.07 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:13 PM PDT 24
Peak memory 231724 kb
Host smart-31342dfa-4216-4810-a968-07ef8587ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075683847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3075683847
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.506027384
Short name T11
Test name
Test status
Simulation time 1327221904 ps
CPU time 4.73 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:09 PM PDT 24
Peak memory 233712 kb
Host smart-98fda393-64e6-490a-9934-7c84b7204932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506027384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.506027384
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1878924055
Short name T619
Test name
Test status
Simulation time 5666019003 ps
CPU time 11.32 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:54:15 PM PDT 24
Peak memory 226860 kb
Host smart-833c6a1e-64df-4f3f-a97f-a0ef73502898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878924055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1878924055
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1821211929
Short name T56
Test name
Test status
Simulation time 154329235 ps
CPU time 3.78 seconds
Started May 12 12:54:12 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 219220 kb
Host smart-7a0ef882-c7df-4ba9-81d5-4eacd363d5e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1821211929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1821211929
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.68064386
Short name T97
Test name
Test status
Simulation time 3201149033 ps
CPU time 23.71 seconds
Started May 12 12:54:05 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 216492 kb
Host smart-bb252604-0535-4471-b047-fbee46dcddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68064386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.68064386
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.732043833
Short name T579
Test name
Test status
Simulation time 1987667763 ps
CPU time 4.66 seconds
Started May 12 12:54:13 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 216268 kb
Host smart-dddd8419-c59d-444f-8211-e19b90ea1364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732043833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.732043833
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1551975796
Short name T628
Test name
Test status
Simulation time 350140763 ps
CPU time 3 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 216372 kb
Host smart-4a240848-3e13-4445-a00f-79ac7743d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551975796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1551975796
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2176442054
Short name T361
Test name
Test status
Simulation time 81611844 ps
CPU time 0.94 seconds
Started May 12 12:54:08 PM PDT 24
Finished May 12 12:54:10 PM PDT 24
Peak memory 206268 kb
Host smart-68441c98-6d62-4331-8857-4d7fb89eef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176442054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2176442054
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3584328696
Short name T284
Test name
Test status
Simulation time 3120418210 ps
CPU time 14.59 seconds
Started May 12 12:54:21 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 217740 kb
Host smart-3e246bd6-8146-4f09-995f-0eaa7331a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584328696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3584328696
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4260117220
Short name T905
Test name
Test status
Simulation time 21729673 ps
CPU time 0.69 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 205264 kb
Host smart-f4b7f24d-3c3f-4b87-822d-8e4f061c0238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260117220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4260117220
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2500813130
Short name T74
Test name
Test status
Simulation time 3466405940 ps
CPU time 10.89 seconds
Started May 12 12:54:18 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 219656 kb
Host smart-cd9633d1-2071-4773-89fc-af65cb6fd2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500813130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2500813130
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.80691892
Short name T624
Test name
Test status
Simulation time 30621110 ps
CPU time 0.83 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:54:13 PM PDT 24
Peak memory 206372 kb
Host smart-3e85fd2b-27ad-4ccf-9b94-7fd6a18ecfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80691892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.80691892
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1784000562
Short name T745
Test name
Test status
Simulation time 198462973 ps
CPU time 4.17 seconds
Started May 12 12:54:04 PM PDT 24
Finished May 12 12:54:09 PM PDT 24
Peak memory 240812 kb
Host smart-2d555653-24a6-4005-acfa-5fa09b35f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784000562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1784000562
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3323189944
Short name T906
Test name
Test status
Simulation time 30730173229 ps
CPU time 268.16 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:58:51 PM PDT 24
Peak memory 249232 kb
Host smart-969d2eb0-14d4-46cb-a9e9-0b7aa5744ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323189944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3323189944
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3918402343
Short name T501
Test name
Test status
Simulation time 37546259807 ps
CPU time 62.02 seconds
Started May 12 12:54:19 PM PDT 24
Finished May 12 12:55:22 PM PDT 24
Peak memory 238300 kb
Host smart-7560fb19-cc20-4d0c-8bdb-f7d7efa77797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918402343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3918402343
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1949004830
Short name T919
Test name
Test status
Simulation time 4239698356 ps
CPU time 15.24 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:54:19 PM PDT 24
Peak memory 240896 kb
Host smart-38faa25f-3391-45c5-ab79-fddfdea8ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949004830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1949004830
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1901591387
Short name T105
Test name
Test status
Simulation time 600272048 ps
CPU time 3.3 seconds
Started May 12 12:54:19 PM PDT 24
Finished May 12 12:54:23 PM PDT 24
Peak memory 233592 kb
Host smart-d7816cae-1161-45d2-bf0d-7fcca930ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901591387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1901591387
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.323800433
Short name T192
Test name
Test status
Simulation time 2490923153 ps
CPU time 12.48 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 220000 kb
Host smart-42d50f71-aa9f-4a5b-9ed8-61464da07525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323800433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.323800433
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.590513773
Short name T68
Test name
Test status
Simulation time 11867880325 ps
CPU time 18.35 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 232960 kb
Host smart-5501f529-6ed2-43dc-a720-bbc0baa14d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590513773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.590513773
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1105940906
Short name T631
Test name
Test status
Simulation time 2902296994 ps
CPU time 6.73 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:17 PM PDT 24
Peak memory 217420 kb
Host smart-6d5567af-8688-4c60-99f1-8306583230a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105940906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1105940906
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1579210140
Short name T764
Test name
Test status
Simulation time 11772383619 ps
CPU time 10.46 seconds
Started May 12 12:54:12 PM PDT 24
Finished May 12 12:54:23 PM PDT 24
Peak memory 219200 kb
Host smart-90f86578-ee08-4a88-8d5d-88535af941ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1579210140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1579210140
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3947754454
Short name T411
Test name
Test status
Simulation time 33514956 ps
CPU time 0.72 seconds
Started May 12 12:54:10 PM PDT 24
Finished May 12 12:54:12 PM PDT 24
Peak memory 205496 kb
Host smart-cd402477-5dc3-40ce-9caa-1454b94bde90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947754454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3947754454
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.124765760
Short name T337
Test name
Test status
Simulation time 3824760700 ps
CPU time 5.77 seconds
Started May 12 12:54:13 PM PDT 24
Finished May 12 12:54:19 PM PDT 24
Peak memory 216332 kb
Host smart-f098a52f-a20e-485c-8bb9-595d45690061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124765760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.124765760
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4237785610
Short name T847
Test name
Test status
Simulation time 259770673 ps
CPU time 3.45 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:21 PM PDT 24
Peak memory 216388 kb
Host smart-a96b7e9e-b3eb-417b-88f9-578ea80fde6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237785610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4237785610
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.622329592
Short name T517
Test name
Test status
Simulation time 49649546 ps
CPU time 0.72 seconds
Started May 12 12:54:11 PM PDT 24
Finished May 12 12:54:12 PM PDT 24
Peak memory 205752 kb
Host smart-fe8862b1-c18e-4abf-b2c3-2800577ce71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622329592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.622329592
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.480545989
Short name T288
Test name
Test status
Simulation time 786410290 ps
CPU time 3.33 seconds
Started May 12 12:54:03 PM PDT 24
Finished May 12 12:54:07 PM PDT 24
Peak memory 233676 kb
Host smart-8b63292a-4ebe-4ef7-9ca2-795651925038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480545989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.480545989
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3841896355
Short name T468
Test name
Test status
Simulation time 49023899 ps
CPU time 0.75 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:39 PM PDT 24
Peak memory 204652 kb
Host smart-54512f6e-1ded-4656-96a7-0b9e94356065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841896355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3841896355
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1446794373
Short name T888
Test name
Test status
Simulation time 2682003765 ps
CPU time 14.82 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:54:31 PM PDT 24
Peak memory 235336 kb
Host smart-ee9d7553-9fb6-4665-a48e-c4f5fe8b89c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446794373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1446794373
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2405082103
Short name T323
Test name
Test status
Simulation time 21103417 ps
CPU time 0.75 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 206684 kb
Host smart-02502003-ed5f-4d67-b7e1-bdf5760176e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405082103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2405082103
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1866388662
Short name T868
Test name
Test status
Simulation time 43866370466 ps
CPU time 335.08 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:59:50 PM PDT 24
Peak memory 266512 kb
Host smart-f25da28e-b608-4311-a670-a4e5d3add4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866388662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1866388662
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.96593548
Short name T210
Test name
Test status
Simulation time 54104383092 ps
CPU time 542.92 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 01:03:25 PM PDT 24
Peak memory 265620 kb
Host smart-854a0f6d-1316-4756-a926-b340a6d701ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96593548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.96593548
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.439204003
Short name T596
Test name
Test status
Simulation time 6738733237 ps
CPU time 38.13 seconds
Started May 12 12:54:19 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 241192 kb
Host smart-cb6085af-eb4d-4478-9fe5-582d7afcbc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439204003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.439204003
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.770768138
Short name T939
Test name
Test status
Simulation time 778500476 ps
CPU time 3.2 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:54:19 PM PDT 24
Peak memory 232600 kb
Host smart-9523a4ca-2056-4bbb-87df-0577cb57ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770768138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.770768138
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.697174932
Short name T101
Test name
Test status
Simulation time 3377288522 ps
CPU time 8.27 seconds
Started May 12 12:54:20 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 218540 kb
Host smart-4e151aba-98f1-482a-b3c1-9a1349e65cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697174932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.697174932
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1418225702
Short name T704
Test name
Test status
Simulation time 115421007 ps
CPU time 2.56 seconds
Started May 12 12:54:19 PM PDT 24
Finished May 12 12:54:22 PM PDT 24
Peak memory 221696 kb
Host smart-4e455620-20fe-4188-baa4-02383c8b9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418225702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1418225702
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1554100599
Short name T875
Test name
Test status
Simulation time 344446886 ps
CPU time 3.9 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:22 PM PDT 24
Peak memory 216660 kb
Host smart-92baaf0c-4c84-4c54-833d-8ec2ced5899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554100599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1554100599
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1244565424
Short name T956
Test name
Test status
Simulation time 2367431360 ps
CPU time 6.52 seconds
Started May 12 12:54:28 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 226192 kb
Host smart-46699dfa-5c02-4d04-8aad-d43f4e0c2be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244565424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1244565424
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1382993726
Short name T777
Test name
Test status
Simulation time 1090242618 ps
CPU time 15.03 seconds
Started May 12 12:54:19 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 219068 kb
Host smart-0c98e21b-768b-4f58-8706-3368d8fa68ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1382993726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1382993726
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3377374931
Short name T71
Test name
Test status
Simulation time 91837962147 ps
CPU time 137.25 seconds
Started May 12 12:54:16 PM PDT 24
Finished May 12 12:56:34 PM PDT 24
Peak memory 237408 kb
Host smart-efc1a017-d7ee-4c7e-956b-1cc784424164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377374931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3377374931
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.896818369
Short name T29
Test name
Test status
Simulation time 3169455636 ps
CPU time 2.34 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:20 PM PDT 24
Peak memory 216652 kb
Host smart-1ed139f7-51d8-464c-8980-4c468f46f020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896818369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.896818369
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3805882041
Short name T486
Test name
Test status
Simulation time 3321599680 ps
CPU time 14.56 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 216300 kb
Host smart-f5ec35ba-e83b-486e-a2b3-6f12e2c5397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805882041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3805882041
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3536142670
Short name T607
Test name
Test status
Simulation time 651679298 ps
CPU time 3.92 seconds
Started May 12 12:54:29 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 216348 kb
Host smart-e0f0b97b-0290-43e0-bb75-33c338687ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536142670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3536142670
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.444897748
Short name T387
Test name
Test status
Simulation time 250724490 ps
CPU time 1 seconds
Started May 12 12:54:29 PM PDT 24
Finished May 12 12:54:30 PM PDT 24
Peak memory 205804 kb
Host smart-60cb9b14-a3e5-4abb-907d-a516010959da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444897748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.444897748
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1325061156
Short name T408
Test name
Test status
Simulation time 298960657 ps
CPU time 4.51 seconds
Started May 12 12:54:08 PM PDT 24
Finished May 12 12:54:13 PM PDT 24
Peak memory 218904 kb
Host smart-be77056d-cdf8-42d8-a094-b559eaaf416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325061156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1325061156
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1945314995
Short name T373
Test name
Test status
Simulation time 34479156 ps
CPU time 0.73 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 205296 kb
Host smart-41a52554-9043-4064-8918-1b0a326000ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945314995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1945314995
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2205840488
Short name T191
Test name
Test status
Simulation time 1646006082 ps
CPU time 7.61 seconds
Started May 12 12:54:17 PM PDT 24
Finished May 12 12:54:26 PM PDT 24
Peak memory 224380 kb
Host smart-a83c8224-f5b3-4129-95c8-c68c59fa9a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205840488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2205840488
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3203821474
Short name T834
Test name
Test status
Simulation time 30100480 ps
CPU time 0.79 seconds
Started May 12 12:54:13 PM PDT 24
Finished May 12 12:54:14 PM PDT 24
Peak memory 206404 kb
Host smart-7f9ea0d4-98b1-49e4-bd92-8178ac2cf44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203821474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3203821474
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.300610321
Short name T744
Test name
Test status
Simulation time 37055533 ps
CPU time 0.76 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 215856 kb
Host smart-e0be6ef2-12d1-4f02-80b3-88fbfbe1b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300610321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.300610321
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3651984033
Short name T943
Test name
Test status
Simulation time 16690192369 ps
CPU time 173.12 seconds
Started May 12 12:54:23 PM PDT 24
Finished May 12 12:57:16 PM PDT 24
Peak memory 255592 kb
Host smart-25bac0bc-1549-4104-9472-59edd71c72c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651984033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3651984033
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3378717548
Short name T732
Test name
Test status
Simulation time 132387694157 ps
CPU time 279.66 seconds
Started May 12 12:54:29 PM PDT 24
Finished May 12 12:59:09 PM PDT 24
Peak memory 249364 kb
Host smart-ba09b804-1eea-42a0-9cb2-49b96b8c0892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378717548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3378717548
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2205919693
Short name T560
Test name
Test status
Simulation time 13010881965 ps
CPU time 36.77 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 232788 kb
Host smart-128545ab-6e38-4477-a57a-324135489b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205919693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2205919693
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4124835155
Short name T572
Test name
Test status
Simulation time 2278936111 ps
CPU time 20.36 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 220116 kb
Host smart-34cfdf8a-c0a9-443e-8a5d-a2f40239c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124835155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4124835155
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4159155752
Short name T701
Test name
Test status
Simulation time 5052077725 ps
CPU time 41.85 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:55:13 PM PDT 24
Peak memory 222612 kb
Host smart-2169e3c3-a884-4d09-8a42-4bdaebf2da91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159155752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4159155752
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3561305566
Short name T475
Test name
Test status
Simulation time 8056427157 ps
CPU time 11.3 seconds
Started May 12 12:54:37 PM PDT 24
Finished May 12 12:54:50 PM PDT 24
Peak memory 241980 kb
Host smart-27df28df-aecc-4da9-abbd-215f4ce1b5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561305566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3561305566
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3434952237
Short name T293
Test name
Test status
Simulation time 9264007514 ps
CPU time 8.74 seconds
Started May 12 12:54:21 PM PDT 24
Finished May 12 12:54:31 PM PDT 24
Peak memory 234008 kb
Host smart-f8994ce1-ddf9-4090-94b9-63bbe9ade40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434952237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3434952237
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3967283465
Short name T608
Test name
Test status
Simulation time 400261435 ps
CPU time 5.92 seconds
Started May 12 12:54:24 PM PDT 24
Finished May 12 12:54:30 PM PDT 24
Peak memory 218956 kb
Host smart-baf6f2a9-8b20-44a4-ab9b-3879824763c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967283465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3967283465
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1939377278
Short name T412
Test name
Test status
Simulation time 12521457907 ps
CPU time 34.62 seconds
Started May 12 12:54:27 PM PDT 24
Finished May 12 12:55:02 PM PDT 24
Peak memory 219748 kb
Host smart-f726af5e-c52a-4d83-af55-7c761be846cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939377278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1939377278
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2834812299
Short name T949
Test name
Test status
Simulation time 7117702009 ps
CPU time 4.46 seconds
Started May 12 12:54:20 PM PDT 24
Finished May 12 12:54:25 PM PDT 24
Peak memory 216492 kb
Host smart-8db03554-6f09-43c2-b500-1b1f402f290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834812299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2834812299
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2447347006
Short name T681
Test name
Test status
Simulation time 654962382 ps
CPU time 2.16 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:54:18 PM PDT 24
Peak memory 216316 kb
Host smart-274491bc-0caa-4d9b-99cc-f226136b20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447347006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2447347006
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1669535004
Short name T452
Test name
Test status
Simulation time 51874302 ps
CPU time 0.76 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:26 PM PDT 24
Peak memory 205736 kb
Host smart-ccfb605f-1522-419f-ae49-5ca2d25a36b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669535004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1669535004
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3724133451
Short name T613
Test name
Test status
Simulation time 45286061 ps
CPU time 2.17 seconds
Started May 12 12:54:29 PM PDT 24
Finished May 12 12:54:31 PM PDT 24
Peak memory 221444 kb
Host smart-f144f6d4-6a17-42c3-85df-c31331189486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724133451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3724133451
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1263447516
Short name T813
Test name
Test status
Simulation time 15131519 ps
CPU time 0.74 seconds
Started May 12 12:54:33 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 204668 kb
Host smart-fd6c6fab-33cc-4ddd-8c1b-dc58da64adbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263447516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1263447516
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2131712488
Short name T375
Test name
Test status
Simulation time 2726093921 ps
CPU time 9 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:40 PM PDT 24
Peak memory 218444 kb
Host smart-b5c2d9ac-19a7-496f-8e27-9e4c9024fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131712488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2131712488
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.883178044
Short name T332
Test name
Test status
Simulation time 13836130 ps
CPU time 0.74 seconds
Started May 12 12:54:19 PM PDT 24
Finished May 12 12:54:20 PM PDT 24
Peak memory 205732 kb
Host smart-73728718-4c76-49a2-ae4e-8a9b54739dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883178044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.883178044
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2669392812
Short name T400
Test name
Test status
Simulation time 24601209 ps
CPU time 0.75 seconds
Started May 12 12:54:31 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 215848 kb
Host smart-da284120-b83b-49f8-90ec-c0445b9b25fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669392812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2669392812
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3024604611
Short name T173
Test name
Test status
Simulation time 14332811151 ps
CPU time 127.41 seconds
Started May 12 12:54:29 PM PDT 24
Finished May 12 12:56:37 PM PDT 24
Peak memory 239232 kb
Host smart-ed651946-a99c-4a68-9531-d76709676cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024604611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3024604611
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2381771955
Short name T17
Test name
Test status
Simulation time 6279399203 ps
CPU time 29.5 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:54:52 PM PDT 24
Peak memory 217752 kb
Host smart-b32456de-e899-4e7e-9f33-db58dbe74519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381771955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2381771955
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.376883090
Short name T451
Test name
Test status
Simulation time 73389070 ps
CPU time 4.53 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 232992 kb
Host smart-55081ed0-f659-442e-b675-bb3185c2f57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376883090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.376883090
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.471135835
Short name T953
Test name
Test status
Simulation time 3415437479 ps
CPU time 3.99 seconds
Started May 12 12:54:27 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 218924 kb
Host smart-3d9a273c-ff9e-4aa2-a03b-a2abe8ac7116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471135835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.471135835
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3377975479
Short name T782
Test name
Test status
Simulation time 1165170070 ps
CPU time 17.63 seconds
Started May 12 12:54:39 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 237780 kb
Host smart-26f38f6d-5f7c-4eea-af86-33fba88295e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377975479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3377975479
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3339178842
Short name T254
Test name
Test status
Simulation time 10070927991 ps
CPU time 16.11 seconds
Started May 12 12:54:15 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 234880 kb
Host smart-2d6ad593-fa53-4242-8e28-8d0bb5c54c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339178842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3339178842
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1987697543
Short name T825
Test name
Test status
Simulation time 1861435522 ps
CPU time 4.95 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:54:28 PM PDT 24
Peak memory 234316 kb
Host smart-77e6a331-844f-4e72-a856-b09e071c24b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987697543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1987697543
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2078372681
Short name T684
Test name
Test status
Simulation time 963967335 ps
CPU time 5.72 seconds
Started May 12 12:54:29 PM PDT 24
Finished May 12 12:54:35 PM PDT 24
Peak memory 219916 kb
Host smart-d3396410-9dda-4fe1-85e9-ad6840861f3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2078372681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2078372681
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2602646479
Short name T588
Test name
Test status
Simulation time 2935091008 ps
CPU time 47.5 seconds
Started May 12 12:54:38 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 241440 kb
Host smart-c78544b3-2ab9-4aba-bea1-96aac819730f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602646479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2602646479
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1966721040
Short name T100
Test name
Test status
Simulation time 5690094511 ps
CPU time 28.32 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:55:00 PM PDT 24
Peak memory 216384 kb
Host smart-39de4be6-1612-4665-93b5-57bf9102e29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966721040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1966721040
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.23150540
Short name T345
Test name
Test status
Simulation time 1070635068 ps
CPU time 4.88 seconds
Started May 12 12:54:30 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 216236 kb
Host smart-acf2c436-3e60-4b03-8704-2bb92736d224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23150540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.23150540
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3125119851
Short name T851
Test name
Test status
Simulation time 34581309 ps
CPU time 0.67 seconds
Started May 12 12:54:22 PM PDT 24
Finished May 12 12:54:23 PM PDT 24
Peak memory 205424 kb
Host smart-c9f6a2bc-595e-4979-aa8d-eef1daca3835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125119851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3125119851
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.149822334
Short name T730
Test name
Test status
Simulation time 536930256 ps
CPU time 0.9 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:27 PM PDT 24
Peak memory 205700 kb
Host smart-a74f2e47-8f74-496e-af40-c53034716f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149822334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.149822334
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3236221140
Short name T802
Test name
Test status
Simulation time 853746439 ps
CPU time 3.03 seconds
Started May 12 12:54:39 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 218268 kb
Host smart-9bac8ce2-209b-4bc5-908e-f7739b2b1951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236221140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3236221140
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4281447663
Short name T659
Test name
Test status
Simulation time 38168513 ps
CPU time 0.73 seconds
Started May 12 12:54:42 PM PDT 24
Finished May 12 12:54:44 PM PDT 24
Peak memory 205656 kb
Host smart-20e203e9-7624-46dd-b47b-3f7deabcda6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281447663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4281447663
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.45628973
Short name T657
Test name
Test status
Simulation time 530922478 ps
CPU time 7.55 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:33 PM PDT 24
Peak memory 234224 kb
Host smart-2be9da22-2595-48b5-836d-44d3b1b42c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45628973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.45628973
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1295133533
Short name T460
Test name
Test status
Simulation time 166740403 ps
CPU time 0.83 seconds
Started May 12 12:54:41 PM PDT 24
Finished May 12 12:54:43 PM PDT 24
Peak memory 206332 kb
Host smart-b6a454e2-52a5-4493-92e7-58dada85450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295133533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1295133533
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2109376442
Short name T922
Test name
Test status
Simulation time 16766232200 ps
CPU time 118.04 seconds
Started May 12 12:54:23 PM PDT 24
Finished May 12 12:56:21 PM PDT 24
Peak memory 240996 kb
Host smart-c31e2bdb-fbea-4b83-b900-2fb4f93f24e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109376442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2109376442
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.615588739
Short name T62
Test name
Test status
Simulation time 23416991945 ps
CPU time 53.89 seconds
Started May 12 12:54:31 PM PDT 24
Finished May 12 12:55:25 PM PDT 24
Peak memory 249288 kb
Host smart-01227b1c-3694-4e95-b23b-83762e0ed5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615588739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.615588739
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.716986622
Short name T436
Test name
Test status
Simulation time 51468770809 ps
CPU time 163.72 seconds
Started May 12 12:54:36 PM PDT 24
Finished May 12 12:57:22 PM PDT 24
Peak memory 257288 kb
Host smart-c7f48f1f-b0e0-4431-95ee-290f5bf4ada6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716986622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.716986622
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2917426303
Short name T664
Test name
Test status
Simulation time 1111584453 ps
CPU time 6.53 seconds
Started May 12 12:54:21 PM PDT 24
Finished May 12 12:54:28 PM PDT 24
Peak memory 232676 kb
Host smart-aee6da78-801c-4810-afa7-644f7fe71953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917426303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2917426303
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3100433702
Short name T455
Test name
Test status
Simulation time 7035491324 ps
CPU time 17.37 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:45 PM PDT 24
Peak memory 233608 kb
Host smart-bc7e65e5-85eb-4696-a6e4-f8cc0a9dafed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100433702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3100433702
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3446504580
Short name T275
Test name
Test status
Simulation time 26628115671 ps
CPU time 35.74 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:55:01 PM PDT 24
Peak memory 236908 kb
Host smart-933147bb-c895-49f3-bc36-0bc3cf1adb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446504580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3446504580
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3942092340
Short name T278
Test name
Test status
Simulation time 7982253300 ps
CPU time 7.85 seconds
Started May 12 12:54:32 PM PDT 24
Finished May 12 12:54:41 PM PDT 24
Peak memory 224540 kb
Host smart-2f3dc82c-d806-4e1a-8015-0172e5644d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942092340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3942092340
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1669534948
Short name T52
Test name
Test status
Simulation time 846668286 ps
CPU time 7.99 seconds
Started May 12 12:54:25 PM PDT 24
Finished May 12 12:54:34 PM PDT 24
Peak memory 228300 kb
Host smart-f26ee65f-a2b4-4d03-8906-361d7f645745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669534948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1669534948
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2206556849
Short name T907
Test name
Test status
Simulation time 65126194 ps
CPU time 3.24 seconds
Started May 12 12:54:32 PM PDT 24
Finished May 12 12:54:36 PM PDT 24
Peak memory 220492 kb
Host smart-0a525fd2-f991-483a-97a8-8a670af4b69d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206556849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2206556849
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2245775503
Short name T805
Test name
Test status
Simulation time 18128584481 ps
CPU time 61.53 seconds
Started May 12 12:54:24 PM PDT 24
Finished May 12 12:55:26 PM PDT 24
Peak memory 232988 kb
Host smart-471367d7-3a82-4599-b89b-9acca371ca33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245775503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2245775503
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2615985214
Short name T66
Test name
Test status
Simulation time 23162851254 ps
CPU time 31.26 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:58 PM PDT 24
Peak memory 216476 kb
Host smart-4bc9c9e4-9060-41de-80ca-685b8380751a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615985214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2615985214
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3091729249
Short name T771
Test name
Test status
Simulation time 410479654 ps
CPU time 1.54 seconds
Started May 12 12:54:34 PM PDT 24
Finished May 12 12:54:37 PM PDT 24
Peak memory 206840 kb
Host smart-60013850-0269-4955-8769-e5d828944f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091729249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3091729249
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1377205879
Short name T432
Test name
Test status
Simulation time 792570682 ps
CPU time 4.95 seconds
Started May 12 12:54:26 PM PDT 24
Finished May 12 12:54:32 PM PDT 24
Peak memory 216452 kb
Host smart-65c66b8e-dbf6-4cc1-9fec-e33ce7516258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377205879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1377205879
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.436275897
Short name T789
Test name
Test status
Simulation time 107729038 ps
CPU time 0.93 seconds
Started May 12 12:54:28 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 206040 kb
Host smart-7471872e-8168-4aed-9e2a-2abdc57fbc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436275897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.436275897
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1933756674
Short name T186
Test name
Test status
Simulation time 1081374605 ps
CPU time 8.26 seconds
Started May 12 12:54:21 PM PDT 24
Finished May 12 12:54:29 PM PDT 24
Peak memory 234420 kb
Host smart-48d0b2cd-2105-4bb6-ba98-56e76c5e6565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933756674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1933756674
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4050835993
Short name T599
Test name
Test status
Simulation time 35279945 ps
CPU time 0.7 seconds
Started May 12 12:51:22 PM PDT 24
Finished May 12 12:51:24 PM PDT 24
Peak memory 204776 kb
Host smart-7e84fed2-6c46-40b0-ab7f-9fd4b482cc84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050835993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
050835993
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4156733626
Short name T183
Test name
Test status
Simulation time 167891310 ps
CPU time 2.49 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:20 PM PDT 24
Peak memory 218548 kb
Host smart-6b94889d-193a-4fff-90b3-dfe82fcbdd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156733626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4156733626
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.575496032
Short name T509
Test name
Test status
Simulation time 21805495 ps
CPU time 0.8 seconds
Started May 12 12:51:14 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 206376 kb
Host smart-0abae510-a110-44db-a9cc-d507d2da3b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575496032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.575496032
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3026015504
Short name T265
Test name
Test status
Simulation time 4288723809 ps
CPU time 37.93 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:49 PM PDT 24
Peak memory 237896 kb
Host smart-88702724-20fc-4a96-8e81-e3d45d2a1ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026015504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3026015504
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.228417168
Short name T285
Test name
Test status
Simulation time 2905767412 ps
CPU time 37.81 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:55 PM PDT 24
Peak memory 237400 kb
Host smart-c295d029-63a3-4b1d-9034-f2b31a042aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228417168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.228417168
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3532608292
Short name T705
Test name
Test status
Simulation time 27127216531 ps
CPU time 282.04 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:55:56 PM PDT 24
Peak memory 249296 kb
Host smart-018830ed-9440-4e80-bb4a-ab68011bdc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532608292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3532608292
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1187502507
Short name T306
Test name
Test status
Simulation time 761601451 ps
CPU time 9.43 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:27 PM PDT 24
Peak memory 240804 kb
Host smart-d7f3d6a3-332e-489b-ad49-beccae7ec115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187502507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1187502507
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2720929989
Short name T577
Test name
Test status
Simulation time 286075350 ps
CPU time 3.9 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:19 PM PDT 24
Peak memory 233672 kb
Host smart-3bea0baa-e4c8-4675-820a-cfbb1cb79b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720929989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2720929989
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2646229484
Short name T456
Test name
Test status
Simulation time 21311147842 ps
CPU time 49.06 seconds
Started May 12 12:51:20 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 234008 kb
Host smart-26ea7ec9-23b9-45a5-91ae-9e5b853a6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646229484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2646229484
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1221219674
Short name T641
Test name
Test status
Simulation time 29024795 ps
CPU time 1.13 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:15 PM PDT 24
Peak memory 217892 kb
Host smart-4d969325-eac1-4ad5-a2fa-0386a9361b58
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221219674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1221219674
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1308761704
Short name T735
Test name
Test status
Simulation time 183800274 ps
CPU time 2.4 seconds
Started May 12 12:51:22 PM PDT 24
Finished May 12 12:51:25 PM PDT 24
Peak memory 233408 kb
Host smart-ad05ef8d-65f0-4cac-ad19-0a3d5cc7b496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308761704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1308761704
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3579394755
Short name T742
Test name
Test status
Simulation time 2465134511 ps
CPU time 12.22 seconds
Started May 12 12:51:09 PM PDT 24
Finished May 12 12:51:22 PM PDT 24
Peak memory 240532 kb
Host smart-b3697392-6b9f-4ffa-9c59-a9353299ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579394755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3579394755
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.933103616
Short name T707
Test name
Test status
Simulation time 1208379893 ps
CPU time 10.67 seconds
Started May 12 12:51:18 PM PDT 24
Finished May 12 12:51:29 PM PDT 24
Peak memory 222512 kb
Host smart-0de65481-77c9-4529-b12b-84e2766f6202
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933103616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.933103616
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2320956993
Short name T77
Test name
Test status
Simulation time 249526488 ps
CPU time 1.14 seconds
Started May 12 12:51:14 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 215096 kb
Host smart-9cbda502-a06f-4749-b484-d7ed608c3777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320956993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2320956993
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2410058784
Short name T931
Test name
Test status
Simulation time 3862531674 ps
CPU time 15.48 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:30 PM PDT 24
Peak memory 216688 kb
Host smart-1c2f4c82-fa64-4d45-bed0-783678844546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410058784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2410058784
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2180910068
Short name T826
Test name
Test status
Simulation time 5983395781 ps
CPU time 17.04 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:29 PM PDT 24
Peak memory 216340 kb
Host smart-9e8bfb61-6768-481c-84ff-e897ddd8190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180910068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2180910068
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3489240458
Short name T961
Test name
Test status
Simulation time 546327587 ps
CPU time 2.42 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:14 PM PDT 24
Peak memory 216280 kb
Host smart-14448c1a-b7f6-43c2-a3f5-fa53c7eed6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489240458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3489240458
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4038148134
Short name T533
Test name
Test status
Simulation time 25660239 ps
CPU time 0.81 seconds
Started May 12 12:51:20 PM PDT 24
Finished May 12 12:51:21 PM PDT 24
Peak memory 206020 kb
Host smart-72cf4b76-d95a-422e-a981-ab8f331be5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038148134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4038148134
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2807006091
Short name T576
Test name
Test status
Simulation time 8985810441 ps
CPU time 17.29 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 218632 kb
Host smart-1a241377-fb2f-481d-a49a-9ee12ad95a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807006091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2807006091
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1422236854
Short name T703
Test name
Test status
Simulation time 12529880 ps
CPU time 0.7 seconds
Started May 12 12:51:17 PM PDT 24
Finished May 12 12:51:24 PM PDT 24
Peak memory 204640 kb
Host smart-8d3cd95b-9577-4dab-b3c9-1ccccc2f4b22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422236854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
422236854
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3106984017
Short name T214
Test name
Test status
Simulation time 1565578423 ps
CPU time 5.85 seconds
Started May 12 12:51:19 PM PDT 24
Finished May 12 12:51:25 PM PDT 24
Peak memory 218720 kb
Host smart-21294cd1-d2c1-473a-907d-3a83d15b3c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106984017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3106984017
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2048394997
Short name T91
Test name
Test status
Simulation time 25101519 ps
CPU time 0.78 seconds
Started May 12 12:51:21 PM PDT 24
Finished May 12 12:51:22 PM PDT 24
Peak memory 206356 kb
Host smart-19d858a5-d608-4bf4-ab72-c68e7a6655bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048394997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2048394997
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3406892234
Short name T59
Test name
Test status
Simulation time 3406967897 ps
CPU time 19.16 seconds
Started May 12 12:51:18 PM PDT 24
Finished May 12 12:51:38 PM PDT 24
Peak memory 234944 kb
Host smart-268b5837-d881-4660-8b2d-313edd7e7e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406892234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3406892234
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3554304643
Short name T242
Test name
Test status
Simulation time 44418563171 ps
CPU time 436.81 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:58:34 PM PDT 24
Peak memory 253204 kb
Host smart-7c93fb47-2f6c-47da-b205-d3066bdd3453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554304643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3554304643
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.401170772
Short name T245
Test name
Test status
Simulation time 10263821607 ps
CPU time 154.05 seconds
Started May 12 12:51:20 PM PDT 24
Finished May 12 12:53:54 PM PDT 24
Peak memory 249344 kb
Host smart-833f7185-5403-46b3-a009-36d2d2a20e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401170772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
401170772
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3055230586
Short name T379
Test name
Test status
Simulation time 1455999277 ps
CPU time 21.7 seconds
Started May 12 12:51:20 PM PDT 24
Finished May 12 12:51:43 PM PDT 24
Peak memory 224416 kb
Host smart-f638c68e-b873-4c20-8a84-a7fd22e106a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055230586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3055230586
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1653277577
Short name T539
Test name
Test status
Simulation time 98303381 ps
CPU time 2.08 seconds
Started May 12 12:51:13 PM PDT 24
Finished May 12 12:51:16 PM PDT 24
Peak memory 216116 kb
Host smart-e1dd4b17-9a43-429d-bb4c-f42acc0400ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653277577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1653277577
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3919769782
Short name T743
Test name
Test status
Simulation time 3513814695 ps
CPU time 32.52 seconds
Started May 12 12:51:11 PM PDT 24
Finished May 12 12:51:45 PM PDT 24
Peak memory 234744 kb
Host smart-f4f9ba50-c416-4a4e-a7be-3df51e86b2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919769782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3919769782
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4283036092
Short name T934
Test name
Test status
Simulation time 61166688 ps
CPU time 1.05 seconds
Started May 12 12:51:29 PM PDT 24
Finished May 12 12:51:30 PM PDT 24
Peak memory 216764 kb
Host smart-3e2111f1-5050-4f83-8fd7-2e4e326d0e51
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283036092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4283036092
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4166657304
Short name T546
Test name
Test status
Simulation time 451373393 ps
CPU time 3.54 seconds
Started May 12 12:51:18 PM PDT 24
Finished May 12 12:51:22 PM PDT 24
Peak memory 218556 kb
Host smart-c55d449c-4ac1-4275-bc5e-85e8cf7778cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166657304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4166657304
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1062995456
Short name T816
Test name
Test status
Simulation time 12328226354 ps
CPU time 11.53 seconds
Started May 12 12:51:16 PM PDT 24
Finished May 12 12:51:29 PM PDT 24
Peak memory 233708 kb
Host smart-66917e77-1693-416f-92a6-a6df4c852fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062995456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1062995456
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1265923801
Short name T682
Test name
Test status
Simulation time 136096143 ps
CPU time 4.41 seconds
Started May 12 12:51:23 PM PDT 24
Finished May 12 12:51:28 PM PDT 24
Peak memory 220216 kb
Host smart-86e7177d-586e-4ea5-bbda-11e3936044ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265923801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1265923801
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3678789489
Short name T262
Test name
Test status
Simulation time 167368886223 ps
CPU time 412.11 seconds
Started May 12 12:51:37 PM PDT 24
Finished May 12 12:58:29 PM PDT 24
Peak memory 264592 kb
Host smart-4831327e-be77-46b3-88f2-7374a14d94d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678789489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3678789489
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3082748367
Short name T798
Test name
Test status
Simulation time 12122185440 ps
CPU time 36.93 seconds
Started May 12 12:51:32 PM PDT 24
Finished May 12 12:52:09 PM PDT 24
Peak memory 216436 kb
Host smart-954298ee-e9e6-4515-b230-52ca7d218a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082748367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3082748367
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1276028988
Short name T708
Test name
Test status
Simulation time 606275219 ps
CPU time 4.63 seconds
Started May 12 12:51:12 PM PDT 24
Finished May 12 12:51:18 PM PDT 24
Peak memory 216180 kb
Host smart-2874b9bf-8699-4d44-bfce-889f3041755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276028988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1276028988
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3834021390
Short name T347
Test name
Test status
Simulation time 445987007 ps
CPU time 2.69 seconds
Started May 12 12:51:21 PM PDT 24
Finished May 12 12:51:24 PM PDT 24
Peak memory 216356 kb
Host smart-b20314b9-5cdc-4b6c-bec9-4dc37551ab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834021390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3834021390
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3437444749
Short name T69
Test name
Test status
Simulation time 46327947 ps
CPU time 0.86 seconds
Started May 12 12:51:21 PM PDT 24
Finished May 12 12:51:22 PM PDT 24
Peak memory 205692 kb
Host smart-730b8f31-bf8c-4e35-ac6c-42158643d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437444749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3437444749
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1760382099
Short name T959
Test name
Test status
Simulation time 12492303939 ps
CPU time 14.59 seconds
Started May 12 12:51:19 PM PDT 24
Finished May 12 12:51:34 PM PDT 24
Peak memory 233696 kb
Host smart-72af60e5-e8f1-4bf3-8f9e-f8ec0fbee6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760382099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1760382099
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2941255709
Short name T622
Test name
Test status
Simulation time 13614106 ps
CPU time 0.74 seconds
Started May 12 12:51:32 PM PDT 24
Finished May 12 12:51:34 PM PDT 24
Peak memory 205492 kb
Host smart-9564dc33-71d8-42b0-a9dd-0b2fa947a2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941255709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
941255709
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3211221243
Short name T749
Test name
Test status
Simulation time 801045343 ps
CPU time 7.83 seconds
Started May 12 12:51:27 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 220280 kb
Host smart-b66ef2db-234a-486b-b580-76b9e63279a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211221243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3211221243
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3483438710
Short name T950
Test name
Test status
Simulation time 118827821 ps
CPU time 0.73 seconds
Started May 12 12:51:15 PM PDT 24
Finished May 12 12:51:17 PM PDT 24
Peak memory 205320 kb
Host smart-8c89373d-0af4-4a90-b850-27fb6a044c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483438710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3483438710
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3954343635
Short name T597
Test name
Test status
Simulation time 33475682202 ps
CPU time 233.56 seconds
Started May 12 12:51:33 PM PDT 24
Finished May 12 12:55:27 PM PDT 24
Peak memory 249056 kb
Host smart-fe1f9b22-eca6-457e-9292-a251312a3569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954343635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3954343635
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.259321559
Short name T516
Test name
Test status
Simulation time 14974792087 ps
CPU time 94.41 seconds
Started May 12 12:51:28 PM PDT 24
Finished May 12 12:53:03 PM PDT 24
Peak memory 249316 kb
Host smart-ffa78c5b-5dc5-4ebe-a5f8-df88e12a1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259321559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.259321559
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4137823453
Short name T626
Test name
Test status
Simulation time 713799503760 ps
CPU time 644.75 seconds
Started May 12 12:51:30 PM PDT 24
Finished May 12 01:02:21 PM PDT 24
Peak memory 257736 kb
Host smart-6e5a7d43-b887-40ce-bd54-23437cb7f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137823453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4137823453
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4142616993
Short name T686
Test name
Test status
Simulation time 2551099905 ps
CPU time 20.94 seconds
Started May 12 12:51:37 PM PDT 24
Finished May 12 12:51:58 PM PDT 24
Peak memory 240944 kb
Host smart-5fe1de0f-5c1d-43f9-80e4-ee89c79ce799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142616993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4142616993
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.473547761
Short name T295
Test name
Test status
Simulation time 1978392499 ps
CPU time 9.21 seconds
Started May 12 12:51:32 PM PDT 24
Finished May 12 12:51:42 PM PDT 24
Peak memory 234176 kb
Host smart-8cec2a4e-31ab-4379-a76a-fdeb87389aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473547761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.473547761
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1361287298
Short name T595
Test name
Test status
Simulation time 396468011 ps
CPU time 3.29 seconds
Started May 12 12:51:28 PM PDT 24
Finished May 12 12:51:32 PM PDT 24
Peak memory 233996 kb
Host smart-3c60fae7-6e8e-4d83-a329-58542364d73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361287298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1361287298
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2375080684
Short name T494
Test name
Test status
Simulation time 91725642 ps
CPU time 1.01 seconds
Started May 12 12:51:22 PM PDT 24
Finished May 12 12:51:23 PM PDT 24
Peak memory 217948 kb
Host smart-c23f36cd-73de-41d2-a525-59343ca68392
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375080684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2375080684
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4183376968
Short name T199
Test name
Test status
Simulation time 337815337 ps
CPU time 4.16 seconds
Started May 12 12:51:28 PM PDT 24
Finished May 12 12:51:33 PM PDT 24
Peak memory 233868 kb
Host smart-94e9e245-1a66-4474-8586-4448e41e3950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183376968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4183376968
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.545106016
Short name T748
Test name
Test status
Simulation time 201793254 ps
CPU time 3.28 seconds
Started May 12 12:51:25 PM PDT 24
Finished May 12 12:51:29 PM PDT 24
Peak memory 233012 kb
Host smart-8b13c78d-45f2-4a0a-bcee-afbcb3683008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545106016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.545106016
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.345077795
Short name T446
Test name
Test status
Simulation time 1385204274 ps
CPU time 6.29 seconds
Started May 12 12:51:24 PM PDT 24
Finished May 12 12:51:31 PM PDT 24
Peak memory 219048 kb
Host smart-f47d7b2b-eb6b-4fe9-8399-0fa654a415d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=345077795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.345077795
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3634643475
Short name T368
Test name
Test status
Simulation time 3947178670 ps
CPU time 19.4 seconds
Started May 12 12:51:22 PM PDT 24
Finished May 12 12:51:42 PM PDT 24
Peak memory 216496 kb
Host smart-243ca1e2-934a-4121-b97a-330408238727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634643475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3634643475
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2323500734
Short name T781
Test name
Test status
Simulation time 4163936282 ps
CPU time 8.85 seconds
Started May 12 12:51:29 PM PDT 24
Finished May 12 12:51:38 PM PDT 24
Peak memory 216496 kb
Host smart-6ed6741c-9cf1-44a9-af0f-831c4546d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323500734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2323500734
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.718422461
Short name T335
Test name
Test status
Simulation time 11535366 ps
CPU time 0.68 seconds
Started May 12 12:51:29 PM PDT 24
Finished May 12 12:51:30 PM PDT 24
Peak memory 205392 kb
Host smart-63bcc588-03c7-488e-afa9-32da9e068d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718422461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.718422461
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2233387971
Short name T422
Test name
Test status
Simulation time 95909239 ps
CPU time 0.81 seconds
Started May 12 12:51:32 PM PDT 24
Finished May 12 12:51:33 PM PDT 24
Peak memory 205740 kb
Host smart-c4c3f6e8-dae9-4e63-abe6-af780e81b938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233387971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2233387971
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.371674948
Short name T867
Test name
Test status
Simulation time 36175726996 ps
CPU time 31.24 seconds
Started May 12 12:51:29 PM PDT 24
Finished May 12 12:52:01 PM PDT 24
Peak memory 241860 kb
Host smart-4dda82fe-fcf3-442e-8557-a79e2da04561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371674948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.371674948
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.131411639
Short name T424
Test name
Test status
Simulation time 37214946 ps
CPU time 0.72 seconds
Started May 12 12:51:39 PM PDT 24
Finished May 12 12:51:40 PM PDT 24
Peak memory 205644 kb
Host smart-da8e92b0-9fd5-4a42-817a-a6399c8936c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131411639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.131411639
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3099726886
Short name T16
Test name
Test status
Simulation time 1472705414 ps
CPU time 6.29 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:41 PM PDT 24
Peak memory 233828 kb
Host smart-e9353cf1-b242-4e90-bab9-ab416989bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099726886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3099726886
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3922086758
Short name T536
Test name
Test status
Simulation time 16504492 ps
CPU time 0.81 seconds
Started May 12 12:51:36 PM PDT 24
Finished May 12 12:51:37 PM PDT 24
Peak memory 206244 kb
Host smart-c5471fb0-2d3a-406f-955d-236701c5e795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922086758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3922086758
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4147452752
Short name T818
Test name
Test status
Simulation time 22442187668 ps
CPU time 51.13 seconds
Started May 12 12:51:45 PM PDT 24
Finished May 12 12:52:36 PM PDT 24
Peak memory 241012 kb
Host smart-db1722a4-de2a-464d-b5e3-1430434d380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147452752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4147452752
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.152528115
Short name T140
Test name
Test status
Simulation time 14889149909 ps
CPU time 239.47 seconds
Started May 12 12:51:35 PM PDT 24
Finished May 12 12:55:35 PM PDT 24
Peak memory 265408 kb
Host smart-69ac7157-056e-43ef-833e-fa4adb11c58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152528115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.152528115
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.727030502
Short name T784
Test name
Test status
Simulation time 9231116346 ps
CPU time 64.43 seconds
Started May 12 12:51:37 PM PDT 24
Finished May 12 12:52:42 PM PDT 24
Peak memory 238456 kb
Host smart-b791ef9b-a1fb-43a5-829b-6b6e82bd5f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727030502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
727030502
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2275166586
Short name T463
Test name
Test status
Simulation time 1872255621 ps
CPU time 10.2 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:45 PM PDT 24
Peak memory 240712 kb
Host smart-6dd25589-b6e8-40a3-82da-b3742bd0d296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275166586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2275166586
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1254226623
Short name T585
Test name
Test status
Simulation time 1955090664 ps
CPU time 8.58 seconds
Started May 12 12:51:42 PM PDT 24
Finished May 12 12:51:51 PM PDT 24
Peak memory 233064 kb
Host smart-132b5a7b-edaf-450c-ba52-52234938d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254226623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1254226623
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.472788128
Short name T558
Test name
Test status
Simulation time 1236550737 ps
CPU time 15.99 seconds
Started May 12 12:51:33 PM PDT 24
Finished May 12 12:51:50 PM PDT 24
Peak memory 250572 kb
Host smart-162676fa-3397-4396-9af2-59119aaf0f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472788128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.472788128
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3382615732
Short name T741
Test name
Test status
Simulation time 25984493 ps
CPU time 1.02 seconds
Started May 12 12:51:29 PM PDT 24
Finished May 12 12:51:30 PM PDT 24
Peak memory 217988 kb
Host smart-833e30da-5883-4ae1-8d54-e3c7255ee0cf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382615732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3382615732
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1647804081
Short name T304
Test name
Test status
Simulation time 1767824077 ps
CPU time 7.05 seconds
Started May 12 12:51:30 PM PDT 24
Finished May 12 12:51:37 PM PDT 24
Peak memory 218624 kb
Host smart-d3142357-98bc-4476-9bec-08b9917c78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647804081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1647804081
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2340707048
Short name T388
Test name
Test status
Simulation time 4715831870 ps
CPU time 8.32 seconds
Started May 12 12:51:30 PM PDT 24
Finished May 12 12:51:39 PM PDT 24
Peak memory 238012 kb
Host smart-38a8cb16-7863-49b7-9961-8c083c437225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340707048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2340707048
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2200437701
Short name T360
Test name
Test status
Simulation time 8603961153 ps
CPU time 17.29 seconds
Started May 12 12:51:41 PM PDT 24
Finished May 12 12:51:59 PM PDT 24
Peak memory 219144 kb
Host smart-e4475420-5f7c-487c-a284-11d7ca7969c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2200437701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2200437701
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4236696085
Short name T722
Test name
Test status
Simulation time 41711639018 ps
CPU time 343.25 seconds
Started May 12 12:51:41 PM PDT 24
Finished May 12 12:57:25 PM PDT 24
Peak memory 256572 kb
Host smart-7fbf4545-3f7b-43dc-9fb6-922e723403e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236696085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4236696085
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1183349439
Short name T391
Test name
Test status
Simulation time 1556290865 ps
CPU time 19.93 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:55 PM PDT 24
Peak memory 219920 kb
Host smart-701e5726-2849-4d7a-9d50-c652777ed3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183349439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1183349439
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.7621786
Short name T779
Test name
Test status
Simulation time 2562301844 ps
CPU time 5.15 seconds
Started May 12 12:51:35 PM PDT 24
Finished May 12 12:51:41 PM PDT 24
Peak memory 216356 kb
Host smart-97072ebd-1605-4166-849b-e47a14d3152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7621786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.7621786
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3519124944
Short name T737
Test name
Test status
Simulation time 228064028 ps
CPU time 2.33 seconds
Started May 12 12:51:35 PM PDT 24
Finished May 12 12:51:38 PM PDT 24
Peak memory 216320 kb
Host smart-00e0923b-98ae-4000-92b2-cfee96254090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519124944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3519124944
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2001108240
Short name T370
Test name
Test status
Simulation time 1734828807 ps
CPU time 0.99 seconds
Started May 12 12:51:33 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 206772 kb
Host smart-3ff979a1-fe9e-47dc-9863-e6b6659aa7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001108240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2001108240
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.51572034
Short name T24
Test name
Test status
Simulation time 729443024 ps
CPU time 4.84 seconds
Started May 12 12:51:30 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 234208 kb
Host smart-efb8f15a-5e58-4ec8-a6c6-15d8ea1301a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51572034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.51572034
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3049282676
Short name T458
Test name
Test status
Simulation time 27378566 ps
CPU time 0.72 seconds
Started May 12 12:51:45 PM PDT 24
Finished May 12 12:51:47 PM PDT 24
Peak memory 204696 kb
Host smart-f61a7696-25a0-43b2-99f8-e3ffa620112a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049282676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
049282676
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2533634127
Short name T356
Test name
Test status
Simulation time 302479807 ps
CPU time 2.44 seconds
Started May 12 12:51:42 PM PDT 24
Finished May 12 12:51:46 PM PDT 24
Peak memory 233736 kb
Host smart-e013bcda-1c05-422c-8c23-59c34083bb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533634127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2533634127
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2710647029
Short name T882
Test name
Test status
Simulation time 24025536 ps
CPU time 0.76 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 205628 kb
Host smart-e0fe19c4-177d-457d-87b7-0c5c40db4fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710647029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2710647029
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4044027358
Short name T389
Test name
Test status
Simulation time 218544287 ps
CPU time 5.31 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:40 PM PDT 24
Peak memory 232704 kb
Host smart-db75c4be-be62-42b9-be19-a2dd7ac0949f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044027358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4044027358
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3486037355
Short name T301
Test name
Test status
Simulation time 21510657442 ps
CPU time 211.33 seconds
Started May 12 12:51:42 PM PDT 24
Finished May 12 12:55:15 PM PDT 24
Peak memory 238596 kb
Host smart-387d547d-fb17-4c63-a9c1-b7f8fc9c70af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486037355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3486037355
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2574901391
Short name T289
Test name
Test status
Simulation time 114031380865 ps
CPU time 203.18 seconds
Started May 12 12:51:52 PM PDT 24
Finished May 12 12:55:16 PM PDT 24
Peak memory 251284 kb
Host smart-b3d459f0-9392-4864-8780-397dd53e4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574901391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2574901391
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3062936376
Short name T636
Test name
Test status
Simulation time 1343878586 ps
CPU time 19.4 seconds
Started May 12 12:51:37 PM PDT 24
Finished May 12 12:51:57 PM PDT 24
Peak memory 226820 kb
Host smart-a2c7abd8-ced1-4da5-bc31-56c1f7248bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062936376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3062936376
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4181939379
Short name T727
Test name
Test status
Simulation time 1143689912 ps
CPU time 5.54 seconds
Started May 12 12:51:35 PM PDT 24
Finished May 12 12:51:42 PM PDT 24
Peak memory 221612 kb
Host smart-c87ba5f6-23ba-433a-a060-6f394a97280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181939379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4181939379
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1248787530
Short name T797
Test name
Test status
Simulation time 1535616203 ps
CPU time 10.53 seconds
Started May 12 12:51:33 PM PDT 24
Finished May 12 12:51:44 PM PDT 24
Peak memory 233692 kb
Host smart-21ce51a3-727c-4d48-acb8-2bb6e7965417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248787530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1248787530
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1573691670
Short name T570
Test name
Test status
Simulation time 130932752 ps
CPU time 1.13 seconds
Started May 12 12:51:47 PM PDT 24
Finished May 12 12:51:49 PM PDT 24
Peak memory 216776 kb
Host smart-1a14654f-bd6c-49b2-84ec-865f835d9b11
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573691670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1573691670
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1618720262
Short name T421
Test name
Test status
Simulation time 32229397 ps
CPU time 2.45 seconds
Started May 12 12:51:42 PM PDT 24
Finished May 12 12:51:46 PM PDT 24
Peak memory 221012 kb
Host smart-bc7c4cce-660c-4d03-a9ab-05fc92f96fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618720262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1618720262
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.269283183
Short name T723
Test name
Test status
Simulation time 11138535787 ps
CPU time 11.29 seconds
Started May 12 12:51:35 PM PDT 24
Finished May 12 12:51:47 PM PDT 24
Peak memory 239240 kb
Host smart-18166fbb-420f-4f78-a54f-ed8dabeee886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269283183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.269283183
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2925725355
Short name T634
Test name
Test status
Simulation time 14226273680 ps
CPU time 17.54 seconds
Started May 12 12:51:36 PM PDT 24
Finished May 12 12:51:54 PM PDT 24
Peak memory 218524 kb
Host smart-72963c79-ca87-49c9-917c-b9365ca93772
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2925725355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2925725355
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1128865211
Short name T593
Test name
Test status
Simulation time 2193931913 ps
CPU time 7.28 seconds
Started May 12 12:51:59 PM PDT 24
Finished May 12 12:52:07 PM PDT 24
Peak memory 224152 kb
Host smart-a3c0b68d-f5b1-48f9-92fa-69b5eef2e958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128865211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1128865211
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1741748494
Short name T911
Test name
Test status
Simulation time 23797730368 ps
CPU time 29.27 seconds
Started May 12 12:51:36 PM PDT 24
Finished May 12 12:52:06 PM PDT 24
Peak memory 216364 kb
Host smart-9d5a6c98-d57d-4b70-9f17-66667f1d43bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741748494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1741748494
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1845597560
Short name T476
Test name
Test status
Simulation time 1679914409 ps
CPU time 4.79 seconds
Started May 12 12:51:39 PM PDT 24
Finished May 12 12:51:44 PM PDT 24
Peak memory 216312 kb
Host smart-cbef4418-38ec-4128-948f-5a53313b15a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845597560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1845597560
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2779766615
Short name T319
Test name
Test status
Simulation time 76493950 ps
CPU time 1.49 seconds
Started May 12 12:51:33 PM PDT 24
Finished May 12 12:51:35 PM PDT 24
Peak memory 216376 kb
Host smart-9b9183b6-6a1e-4d95-a749-766cca4586fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779766615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2779766615
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4088344261
Short name T495
Test name
Test status
Simulation time 15177688 ps
CPU time 0.72 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:36 PM PDT 24
Peak memory 205812 kb
Host smart-da01cd5d-715a-4a85-9a45-fb9281833b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088344261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4088344261
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.39574184
Short name T305
Test name
Test status
Simulation time 3141309025 ps
CPU time 9.94 seconds
Started May 12 12:51:34 PM PDT 24
Finished May 12 12:51:44 PM PDT 24
Peak memory 226432 kb
Host smart-34e90902-24ea-42c3-808f-6f0f76b36a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39574184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.39574184
Directory /workspace/9.spi_device_upload/latest
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