Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3410424	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3819589

1

T1

928

T2

893

T4

10426

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4056208	1			T1	131		T2	5		T3	1
values[0x0]	1584858	1			T1	453		T2	467		T3	1
values[0x1]	1588947	1			T1	426		T2	426		T4	5496

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2418177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4811836

1

T1

937

T2

894

T4

16734

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28684	1			T2	4		T4	80		T5	14
valid_sources[0x01]	30855	1			T2	1		T4	287		T5	16
valid_sources[0x02]	28942	1			T2	4		T4	79		T5	3
valid_sources[0x03]	30676	1			T4	690		T5	14		T8	27
valid_sources[0x04]	27163	1			T2	4		T4	6		T5	5
valid_sources[0x05]	27899	1			T2	1		T4	147		T5	15
valid_sources[0x06]	28942	1			T2	9		T4	106		T5	21
valid_sources[0x07]	24867	1			T2	1		T4	22		T5	7
valid_sources[0x08]	27411	1			T2	2		T4	6		T5	31
valid_sources[0x09]	26474	1			T2	4		T4	255		T5	1
valid_sources[0x0a]	30725	1			T2	7		T4	6		T5	4
valid_sources[0x0b]	40022	1			T2	1		T4	22		T5	10
valid_sources[0x0c]	27530	1			T2	2		T4	71		T5	14
valid_sources[0x0d]	37221	1			T2	5		T4	280		T5	7
valid_sources[0x0e]	27992	1			T2	4		T4	2		T5	8
valid_sources[0x0f]	30602	1			T2	2		T4	103		T5	10
valid_sources[0x10]	29654	1			T2	4		T4	24		T5	10
valid_sources[0x11]	29650	1			T2	2		T4	19		T5	6
valid_sources[0x12]	26395	1			T2	4		T4	192		T5	12
valid_sources[0x13]	31163	1			T2	4		T4	2		T5	17
valid_sources[0x14]	30290	1			T2	4		T4	310		T5	20
valid_sources[0x15]	27465	1			T2	4		T4	154		T5	11
valid_sources[0x16]	30785	1			T2	1		T4	103		T5	14
valid_sources[0x17]	41325	1			T2	6		T4	2		T5	10
valid_sources[0x18]	26754	1			T2	7		T4	204		T5	28
valid_sources[0x19]	28286	1			T2	6		T5	19		T8	33
valid_sources[0x1a]	28624	1			T2	2		T4	361		T5	19
valid_sources[0x1b]	29130	1			T2	9		T4	19		T5	24
valid_sources[0x1c]	24311	1			T2	4		T4	37		T5	20
valid_sources[0x1d]	28104	1			T2	3		T4	224		T5	5
valid_sources[0x1e]	26020	1			T2	2		T5	14		T7	2
valid_sources[0x1f]	26268	1			T2	7		T4	179		T5	8
valid_sources[0x20]	27053	1			T2	7		T4	5		T5	12
valid_sources[0x21]	27172	1			T2	2		T4	120		T5	22
valid_sources[0x22]	28732	1			T2	8		T4	21		T5	5
valid_sources[0x23]	30151	1			T2	4		T4	1		T5	9
valid_sources[0x24]	25954	1			T2	1		T5	22		T8	29
valid_sources[0x25]	28150	1			T2	5		T4	25		T5	11
valid_sources[0x26]	26021	1			T2	2		T4	16		T5	12
valid_sources[0x27]	25410	1			T4	124		T5	10		T8	30
valid_sources[0x28]	28669	1			T2	1		T4	41		T5	6
valid_sources[0x29]	28152	1			T2	5		T4	31		T5	12
valid_sources[0x2a]	26567	1			T2	1		T4	47		T5	23
valid_sources[0x2b]	26886	1			T2	6		T4	38		T5	7
valid_sources[0x2c]	27945	1			T2	9		T4	63		T5	8
valid_sources[0x2d]	25887	1			T2	3		T5	15		T8	29
valid_sources[0x2e]	30480	1			T4	29		T5	8		T8	26
valid_sources[0x2f]	29553	1			T2	6		T4	45		T5	9
valid_sources[0x30]	27596	1			T2	3		T4	54		T5	49
valid_sources[0x31]	29470	1			T2	5		T4	279		T5	10
valid_sources[0x32]	25534	1			T2	2		T4	3		T5	5
valid_sources[0x33]	28413	1			T2	5		T4	15		T5	15
valid_sources[0x34]	25641	1			T2	1		T4	1		T5	9
valid_sources[0x35]	31735	1			T2	5		T4	1		T5	8
valid_sources[0x36]	27605	1			T2	2		T5	3		T8	34
valid_sources[0x37]	25897	1			T2	3		T4	32		T5	33
valid_sources[0x38]	26139	1			T2	2		T5	3		T8	28
valid_sources[0x39]	26706	1			T2	3		T4	15		T5	20
valid_sources[0x3a]	29809	1			T2	3		T4	25		T5	5
valid_sources[0x3b]	28748	1			T2	1		T4	9		T5	7
valid_sources[0x3c]	28912	1			T2	3		T4	171		T5	2
valid_sources[0x3d]	36989	1			T2	2		T4	666		T5	24
valid_sources[0x3e]	26312	1			T2	3		T4	471		T5	30
valid_sources[0x3f]	28646	1			T2	3		T4	300		T5	19
valid_sources[0x40]	29051	1			T2	1		T4	158		T5	5
valid_sources[0x41]	27390	1			T2	3		T4	18		T5	24
valid_sources[0x42]	29240	1			T2	1		T4	181		T5	6
valid_sources[0x43]	25863	1			T2	2		T4	162		T5	3
valid_sources[0x44]	26306	1			T2	4		T5	15		T8	41
valid_sources[0x45]	27615	1			T2	4		T5	6		T8	29
valid_sources[0x46]	26829	1			T2	4		T4	160		T5	11
valid_sources[0x47]	26837	1			T2	3		T4	118		T5	11
valid_sources[0x48]	26778	1			T2	5		T4	772		T5	12
valid_sources[0x49]	25744	1			T2	9		T4	232		T5	25
valid_sources[0x4a]	25866	1			T2	2		T4	68		T5	25
valid_sources[0x4b]	28998	1			T2	10		T4	322		T5	15
valid_sources[0x4c]	26760	1			T2	6		T4	4		T5	25
valid_sources[0x4d]	28923	1			T2	1		T4	137		T5	23
valid_sources[0x4e]	28675	1			T2	6		T4	57		T5	17
valid_sources[0x4f]	26736	1			T2	2		T4	3		T5	18
valid_sources[0x50]	26318	1			T2	1		T4	98		T5	18
valid_sources[0x51]	29614	1			T2	5		T4	1		T5	22
valid_sources[0x52]	27113	1			T2	2		T4	1		T5	9
valid_sources[0x53]	27550	1			T2	2		T5	11		T8	33
valid_sources[0x54]	26403	1			T2	2		T4	109		T5	6
valid_sources[0x55]	26087	1			T2	1		T5	26		T8	32
valid_sources[0x56]	26650	1			T2	3		T4	15		T5	5
valid_sources[0x57]	27144	1			T2	2		T4	4		T5	22
valid_sources[0x58]	25113	1			T2	11		T4	1		T5	20
valid_sources[0x59]	27845	1			T2	5		T4	174		T5	14
valid_sources[0x5a]	25319	1			T2	5		T4	733		T5	3
valid_sources[0x5b]	26668	1			T2	5		T4	1		T5	16
valid_sources[0x5c]	25484	1			T2	4		T4	185		T5	2
valid_sources[0x5d]	26466	1			T2	7		T4	147		T5	15
valid_sources[0x5e]	27558	1			T2	4		T4	47		T5	3
valid_sources[0x5f]	27554	1			T2	2		T4	12		T5	9
valid_sources[0x60]	27564	1			T2	6		T4	2		T5	9
valid_sources[0x61]	31246	1			T2	2		T4	295		T5	5
valid_sources[0x62]	27542	1			T5	21		T8	37		T9	2
valid_sources[0x63]	27441	1			T2	5		T4	159		T5	13
valid_sources[0x64]	31344	1			T2	2		T4	8		T5	11
valid_sources[0x65]	27007	1			T2	7		T4	24		T5	26
valid_sources[0x66]	28843	1			T2	9		T4	3		T5	15
valid_sources[0x67]	25361	1			T2	1		T4	174		T5	9
valid_sources[0x68]	26447	1			T4	6		T5	9		T8	25
valid_sources[0x69]	24930	1			T2	7		T4	2		T5	13
valid_sources[0x6a]	33692	1			T2	2		T4	649		T5	15
valid_sources[0x6b]	29605	1			T2	3		T4	2		T5	10
valid_sources[0x6c]	26723	1			T2	4		T4	20		T5	13
valid_sources[0x6d]	26748	1			T2	6		T4	61		T5	3
valid_sources[0x6e]	26680	1			T2	5		T4	34		T5	20
valid_sources[0x6f]	25508	1			T2	2		T4	107		T5	8
valid_sources[0x70]	26821	1			T2	3		T5	9		T8	32
valid_sources[0x71]	25622	1			T2	7		T4	2		T5	18
valid_sources[0x72]	27327	1			T2	3		T4	2		T5	8
valid_sources[0x73]	31328	1			T2	2		T4	81		T5	15
valid_sources[0x74]	24711	1			T2	3		T4	1		T5	11
valid_sources[0x75]	27273	1			T2	2		T4	7		T5	22
valid_sources[0x76]	29314	1			T2	3		T4	88		T5	18
valid_sources[0x77]	29381	1			T2	2		T4	31		T5	23
valid_sources[0x78]	34773	1			T2	3		T4	91		T5	6
valid_sources[0x79]	33187	1			T2	2		T4	899		T5	17
valid_sources[0x7a]	28909	1			T2	1		T4	3		T5	14
valid_sources[0x7b]	36525	1			T2	2		T4	2		T5	13
valid_sources[0x7c]	26768	1			T2	3		T4	22		T5	9
valid_sources[0x7d]	25471	1			T2	2		T4	102		T5	15
valid_sources[0x7e]	28222	1			T2	5		T4	516		T5	23
valid_sources[0x7f]	27111	1			T2	3		T4	3		T5	4
valid_sources[0x80]	39441	1			T2	1		T4	33		T5	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

967513

1

T1

52

T2

1

T4

1884

values[0x0]

all_enables

biggest_size

1436494

1

T1

451

T2

466

T4

4338

values[0x1]

all_enables

biggest_size

1415582

1

T1

425

T2

426

T4

4204