Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3429429

1

T1

82

T2

5

T3

2

full_word

3818583

1

T1

928

T2

893

T4

10426

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7247572	1			T1	1010		T2	898		T3	2
auto[TlIntgErrCmd]	137	1			T98	4		T101	5		T102	11
auto[TlIntgErrData]	161	1			T98	1		T101	11		T102	12
auto[TlIntgErrBoth]	142	1			T98	5		T101	14		T102	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4057538

1

T1

131

T2

5

T3

1

auto[1]

3190474

1

T1

879

T2

893

T3

1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3089799	1			T1	79		T2	4		T3	1
auto[TlIntgErrNone]	partial	auto[1]	339225	1			T1	3		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	967542	1			T1	52		T2	1		T4	1884
auto[TlIntgErrNone]	full_word	auto[1]	2851006	1			T1	876		T2	892		T4	8542
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T98	2		T101	1		T102	6
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T98	2		T101	4		T102	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T255	1		T256	1		T257	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T102	1		T253	1		T258	1
auto[TlIntgErrData]	partial	auto[0]	76	1			T101	3		T102	2		T253	3
auto[TlIntgErrData]	partial	auto[1]	73	1			T98	1		T101	7		T102	8
auto[TlIntgErrData]	full_word	auto[0]	7	1			T102	1		T253	1		T255	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T101	1		T102	1		T255	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T98	1		T101	5		T102	4
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T98	3		T101	8		T102	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T101	1		T259	1		T250	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T98	1		T249	1		T258	1