Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T4,T5,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T4,T5,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T4,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	614908202	485296888	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	614908202	3092411	0	0
GntImpliesValid_A	614908202	3092411	0	0
GrantKnown_A	614908202	485296888	0	0
IdxKnown_A	614908202	485296888	0	0
IndexIsCorrect_A	614908202	3092411	0	0
LockArbDecision_A	614908202	0	0	0
NoReadyValidNoGrant_A	614908202	0	0	0
ReadyAndValidImplyGrant_A	614908202	3092411	0	0
ReqAndReadyImplyGrant_A	614908202	3092411	0	0
ReqImpliesValid_A	614908202	3092411	0	0
ReqStaysHighUntilGranted0_M	614908202	0	0	0
RoundRobin_A	614908202	2	0	926
ValidKnown_A	614908202	485296888	0	0
gen_data_port_assertion.DataFlow_A	614908202	3092411	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	485296888	0	0
T1	12131	12037	0	0
T2	407605	406324	0	0
T3	660	585	0	0
T4	697894	420487	0	0
T5	241247	205591	0	0
T6	4502	3938	0	0
T7	701	605	0	0
T8	299413	239811	0	0
T9	2861	2795	0	0
T10	74187	47301	0	0
T11	225236	1108371	0	0
T12	7664	3832	0	0
T13	43872	21501	0	0
T14	96	96	0	0
T15	267008	263631	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	485296888	0	0
T1	12131	12037	0	0
T2	407605	406324	0	0
T3	660	585	0	0
T4	697894	420487	0	0
T5	241247	205591	0	0
T6	4502	3938	0	0
T7	701	605	0	0
T8	299413	239811	0	0
T9	2861	2795	0	0
T10	74187	47301	0	0
T11	225236	1108371	0	0
T12	7664	3832	0	0
T13	43872	21501	0	0
T14	96	96	0	0
T15	267008	263631	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	485296888	0	0
T1	12131	12037	0	0
T2	407605	406324	0	0
T3	660	585	0	0
T4	697894	420487	0	0
T5	241247	205591	0	0
T6	4502	3938	0	0
T7	701	605	0	0
T8	299413	239811	0	0
T9	2861	2795	0	0
T10	74187	47301	0	0
T11	225236	1108371	0	0
T12	7664	3832	0	0
T13	43872	21501	0	0
T14	96	96	0	0
T15	267008	263631	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	2	0	926
T41	122365	1	0	1
T45	0	1	0	0
T46	1714	0	0	1
T47	9890	0	0	1
T48	35564	0	0	1
T49	211856	0	0	1
T50	6916	0	0	1
T51	1691	0	0	1
T52	144061	0	0	1
T53	6918	0	0	1
T54	592183	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	485296888	0	0
T1	12131	12037	0	0
T2	407605	406324	0	0
T3	660	585	0	0
T4	697894	420487	0	0
T5	241247	205591	0	0
T6	4502	3938	0	0
T7	701	605	0	0
T8	299413	239811	0	0
T9	2861	2795	0	0
T10	74187	47301	0	0
T11	225236	1108371	0	0
T12	7664	3832	0	0
T13	43872	21501	0	0
T14	96	96	0	0
T15	267008	263631	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614908202	3092411	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	697894	11103	0	0
T5	241247	2137	0	0
T6	4502	0	0	0
T7	701	0	0	0
T8	299413	832	0	0
T9	2861	832	0	0
T10	74187	832	0	0
T11	225236	31678	0	0
T12	7664	832	0	0
T13	43872	832	0	0
T14	192	0	0	0
T15	534016	1799	0	0
T16	0	2126	0	0
T18	0	160	0	0
T19	0	8148	0	0
T20	0	9	0	0
T27	0	15670	0	0
T28	0	10134	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T4,T5,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T4,T5,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T11
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128241506	29286062	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	128241506	655228	0	0
GntImpliesValid_A	128241506	655228	0	0
GrantKnown_A	128241506	29286062	0	0
IdxKnown_A	128241506	29286062	0	0
IndexIsCorrect_A	128241506	655228	0	0
LockArbDecision_A	128241506	0	0	0
NoReadyValidNoGrant_A	128241506	0	0	0
ReadyAndValidImplyGrant_A	128241506	655228	0	0
ReqAndReadyImplyGrant_A	128241506	655228	0	0
ReqImpliesValid_A	128241506	655228	0	0
ReqStaysHighUntilGranted0_M	128241506	0	0	0
RoundRobin_A	128241506	0	0	0
ValidKnown_A	128241506	29286062	0	0
gen_data_port_assertion.DataFlow_A	128241506	655228	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	29286062	0	0
T4	269574	131560	0	0
T5	33975	32352	0	0
T6	504	504	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	352072	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	107680	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	29286062	0	0
T4	269574	131560	0	0
T5	33975	32352	0	0
T6	504	504	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	352072	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	107680	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	29286062	0	0
T4	269574	131560	0	0
T5	33975	32352	0	0
T6	504	504	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	352072	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	107680	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	29286062	0	0
T4	269574	131560	0	0
T5	33975	32352	0	0
T6	504	504	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	352072	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	107680	0	0
T16	0	49760	0	0
T17	0	648	0	0
T18	0	2872	0	0
T19	0	443576	0	0
T20	0	152	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	655228	0	0
T4	269574	5914	0	0
T5	33975	1452	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	10352	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	1273	0	0
T16	0	2118	0	0
T18	0	160	0	0
T19	0	4617	0	0
T20	0	9	0	0
T27	0	4895	0	0
T28	0	1931	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T15
1	0	Covered	T4,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T4,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T11,T15
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128241506	97668861	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	128241506	479357	0	0
GntImpliesValid_A	128241506	479357	0	0
GrantKnown_A	128241506	97668861	0	0
IdxKnown_A	128241506	97668861	0	0
IndexIsCorrect_A	128241506	479357	0	0
LockArbDecision_A	128241506	0	0	0
NoReadyValidNoGrant_A	128241506	0	0	0
ReadyAndValidImplyGrant_A	128241506	479357	0	0
ReqAndReadyImplyGrant_A	128241506	479357	0	0
ReqImpliesValid_A	128241506	479357	0	0
ReqStaysHighUntilGranted0_M	128241506	0	0	0
RoundRobin_A	128241506	0	0	0
ValidKnown_A	128241506	97668861	0	0
gen_data_port_assertion.DataFlow_A	128241506	479357	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	97668861	0	0
T1	4568	4568	0	0
T2	131646	130460	0	0
T4	269574	130189	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	58000	0	0
T10	26816	26816	0	0
T11	112618	756299	0	0
T12	3832	3832	0	0
T13	21936	21501	0	0
T14	0	96	0	0
T15	0	155951	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	97668861	0	0
T1	4568	4568	0	0
T2	131646	130460	0	0
T4	269574	130189	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	58000	0	0
T10	26816	26816	0	0
T11	112618	756299	0	0
T12	3832	3832	0	0
T13	21936	21501	0	0
T14	0	96	0	0
T15	0	155951	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	97668861	0	0
T1	4568	4568	0	0
T2	131646	130460	0	0
T4	269574	130189	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	58000	0	0
T10	26816	26816	0	0
T11	112618	756299	0	0
T12	3832	3832	0	0
T13	21936	21501	0	0
T14	0	96	0	0
T15	0	155951	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	97668861	0	0
T1	4568	4568	0	0
T2	131646	130460	0	0
T4	269574	130189	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	58000	0	0
T10	26816	26816	0	0
T11	112618	756299	0	0
T12	3832	3832	0	0
T13	21936	21501	0	0
T14	0	96	0	0
T15	0	155951	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128241506	479357	0	0
T4	269574	513	0	0
T5	33975	0	0	0
T6	504	0	0	0
T8	58755	0	0	0
T10	26816	0	0	0
T11	112618	551	0	0
T12	3832	0	0	0
T13	21936	0	0	0
T14	96	0	0	0
T15	267008	526	0	0
T16	0	8	0	0
T19	0	3531	0	0
T27	0	10775	0	0
T28	0	8203	0	0
T34	0	2422	0	0
T39	0	2	0	0
T44	0	14	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T11
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	358425190	358341965	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	358425190	1957826	0	0
GntImpliesValid_A	358425190	1957826	0	0
GrantKnown_A	358425190	358341965	0	0
IdxKnown_A	358425190	358341965	0	0
IndexIsCorrect_A	358425190	1957826	0	0
LockArbDecision_A	358425190	0	0	0
NoReadyValidNoGrant_A	358425190	0	0	0
ReadyAndValidImplyGrant_A	358425190	1957826	0	0
ReqAndReadyImplyGrant_A	358425190	1957826	0	0
ReqImpliesValid_A	358425190	1957826	0	0
ReqStaysHighUntilGranted0_M	358425190	0	0	0
RoundRobin_A	358425190	2	0	926
ValidKnown_A	358425190	358341965	0	0
gen_data_port_assertion.DataFlow_A	358425190	1957826	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	358341965	0	0
T1	7563	7469	0	0
T2	275959	275864	0	0
T3	660	585	0	0
T4	158746	158738	0	0
T5	173297	173239	0	0
T6	3494	3434	0	0
T7	701	605	0	0
T8	181903	181811	0	0
T9	2861	2795	0	0
T10	20555	20485	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	358341965	0	0
T1	7563	7469	0	0
T2	275959	275864	0	0
T3	660	585	0	0
T4	158746	158738	0	0
T5	173297	173239	0	0
T6	3494	3434	0	0
T7	701	605	0	0
T8	181903	181811	0	0
T9	2861	2795	0	0
T10	20555	20485	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	358341965	0	0
T1	7563	7469	0	0
T2	275959	275864	0	0
T3	660	585	0	0
T4	158746	158738	0	0
T5	173297	173239	0	0
T6	3494	3434	0	0
T7	701	605	0	0
T8	181903	181811	0	0
T9	2861	2795	0	0
T10	20555	20485	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	2	0	926
T41	122365	1	0	1
T45	0	1	0	0
T46	1714	0	0	1
T47	9890	0	0	1
T48	35564	0	0	1
T49	211856	0	0	1
T50	6916	0	0	1
T51	1691	0	0	1
T52	144061	0	0	1
T53	6918	0	0	1
T54	592183	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	358341965	0	0
T1	7563	7469	0	0
T2	275959	275864	0	0
T3	660	585	0	0
T4	158746	158738	0	0
T5	173297	173239	0	0
T6	3494	3434	0	0
T7	701	605	0	0
T8	181903	181811	0	0
T9	2861	2795	0	0
T10	20555	20485	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358425190	1957826	0	0
T1	7563	832	0	0
T2	275959	832	0	0
T3	660	0	0	0
T4	158746	4676	0	0
T5	173297	685	0	0
T6	3494	0	0	0
T7	701	0	0	0
T8	181903	832	0	0
T9	2861	832	0	0
T10	20555	832	0	0
T11	0	20775	0	0
T12	0	832	0	0
T13	0	832	0	0