Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	360750010	3311	0	0
addr_swap_data_rd_A	360750010	2947	0	0
addr_swap_mask_rd_A	360750010	2897	0	0
cfg_rd_A	360750010	3498	0	0
cmd_filter_0_rd_A	360750010	8947	0	0
cmd_filter_1_rd_A	360750010	9064	0	0
cmd_filter_2_rd_A	360750010	9214	0	0
cmd_filter_3_rd_A	360750010	10221	0	0
cmd_filter_4_rd_A	360750010	8875	0	0
cmd_filter_5_rd_A	360750010	9095	0	0
cmd_filter_6_rd_A	360750010	8982	0	0
cmd_filter_7_rd_A	360750010	8569	0	0
cmd_info_0_rd_A	360750010	5520	0	0
cmd_info_10_rd_A	360750010	5807	0	0
cmd_info_11_rd_A	360750010	5499	0	0
cmd_info_12_rd_A	360750010	5619	0	0
cmd_info_13_rd_A	360750010	6086	0	0
cmd_info_14_rd_A	360750010	5535	0	0
cmd_info_15_rd_A	360750010	5275	0	0
cmd_info_16_rd_A	360750010	6229	0	0
cmd_info_17_rd_A	360750010	5435	0	0
cmd_info_18_rd_A	360750010	5259	0	0
cmd_info_19_rd_A	360750010	5172	0	0
cmd_info_1_rd_A	360750010	5152	0	0
cmd_info_20_rd_A	360750010	5018	0	0
cmd_info_21_rd_A	360750010	5610	0	0
cmd_info_22_rd_A	360750010	5276	0	0
cmd_info_23_rd_A	360750010	5472	0	0
cmd_info_2_rd_A	360750010	5680	0	0
cmd_info_3_rd_A	360750010	5920	0	0
cmd_info_4_rd_A	360750010	5497	0	0
cmd_info_5_rd_A	360750010	5362	0	0
cmd_info_6_rd_A	360750010	5634	0	0
cmd_info_7_rd_A	360750010	5481	0	0
cmd_info_8_rd_A	360750010	5309	0	0
cmd_info_9_rd_A	360750010	5447	0	0
cmd_info_en4b_rd_A	360750010	3276	0	0
cmd_info_ex4b_rd_A	360750010	3134	0	0
cmd_info_wrdi_rd_A	360750010	3232	0	0
cmd_info_wren_rd_A	360750010	3206	0	0
intercept_en_rd_A	360750010	3514	0	0
intr_enable_rd_A	360750010	5069	0	0
jedec_cc_rd_A	360750010	3260	0	0
jedec_id_rd_A	360750010	3051	0	0
mailbox_addr_rd_A	360750010	3011	0	0
payload_swap_data_rd_A	360750010	3040	0	0
payload_swap_mask_rd_A	360750010	3009	0	0
read_threshold_rd_A	360750010	3089	0	0
tpm_access_0_rd_A	360750010	3638	0	0
tpm_access_1_rd_A	360750010	2886	0	0
tpm_cfg_rd_A	360750010	3696	0	0
tpm_did_vid_rd_A	360750010	3115	0	0
tpm_int_enable_rd_A	360750010	2896	0	0
tpm_int_status_rd_A	360750010	2989	0	0
tpm_int_vector_rd_A	360750010	2809	0	0
tpm_intf_capability_rd_A	360750010	2957	0	0
tpm_rid_rd_A	360750010	2962	0	0
tpm_sts_rd_A	360750010	2995	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3311	0	0
T93	2596	2	0	0
T94	4248	5	0	0
T95	14390	8	0	0
T96	7809	338	0	0
T97	7022	211	0	0
T98	10033	3	0	0
T99	5423	8	0	0
T100	5086	5	0	0
T101	28640	5	0	0
T103	4815	138	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2947	0	0
T78	4508	19	0	0
T80	1971	8	0	0
T95	14390	16	0	0
T102	91189	12	0	0
T117	3574	2	0	0
T118	103144	434	0	0
T120	7934	12	0	0
T150	13785	16	0	0
T151	7958	14	0	0
T152	19685	87	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2897	0	0
T78	4508	13	0	0
T80	1971	7	0	0
T95	14390	37	0	0
T102	91189	68	0	0
T117	3574	3	0	0
T118	103144	380	0	0
T120	7934	4	0	0
T150	13785	48	0	0
T151	7958	2	0	0
T152	19685	61	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3498	0	0
T78	4508	10	0	0
T80	1971	1	0	0
T95	14390	38	0	0
T102	91189	158	0	0
T117	3574	2	0	0
T118	103144	412	0	0
T120	7934	13	0	0
T150	13785	47	0	0
T151	7958	46	0	0
T152	19685	103	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	8947	0	0
T78	4508	18	0	0
T95	14390	124	0	0
T102	91189	974	0	0
T117	3574	5	0	0
T118	103144	438	0	0
T120	7934	268	0	0
T150	13785	61	0	0
T151	7958	22	0	0
T152	19685	60	0	0
T153	4314	4	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	9064	0	0
T78	4508	14	0	0
T95	14390	17	0	0
T102	91189	937	0	0
T117	3574	2	0	0
T118	103144	375	0	0
T120	7934	15	0	0
T150	13785	16	0	0
T151	7958	4	0	0
T152	19685	96	0	0
T153	4314	72	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	9214	0	0
T78	4508	4	0	0
T80	1971	1	0	0
T95	14390	232	0	0
T102	91189	1097	0	0
T118	103144	421	0	0
T120	7934	252	0	0
T150	13785	34	0	0
T151	7958	1	0	0
T152	19685	93	0	0
T153	4314	69	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	10221	0	0
T78	4508	13	0	0
T95	14390	130	0	0
T102	91189	868	0	0
T117	3574	141	0	0
T118	103144	408	0	0
T120	7934	140	0	0
T150	13785	42	0	0
T151	7958	24	0	0
T152	19685	67	0	0
T153	4314	43	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	8875	0	0
T78	4508	6	0	0
T95	14390	13	0	0
T102	91189	990	0	0
T117	3574	134	0	0
T118	103144	376	0	0
T120	7934	9	0	0
T122	269081	655	0	0
T150	13785	33	0	0
T151	7958	26	0	0
T152	19685	28	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	9095	0	0
T78	4508	12	0	0
T95	14390	123	0	0
T102	91189	1114	0	0
T117	3574	7	0	0
T118	103144	455	0	0
T120	7934	123	0	0
T150	13785	40	0	0
T151	7958	36	0	0
T152	19685	80	0	0
T153	4314	1	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	8982	0	0
T78	4508	9	0	0
T95	14390	151	0	0
T102	91189	1096	0	0
T117	3574	151	0	0
T118	103144	404	0	0
T120	7934	280	0	0
T150	13785	37	0	0
T151	7958	24	0	0
T152	19685	71	0	0
T153	4314	66	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	8569	0	0
T78	4508	9	0	0
T80	1971	4	0	0
T95	14390	258	0	0
T102	91189	927	0	0
T118	103144	445	0	0
T120	7934	132	0	0
T150	13785	38	0	0
T151	7958	32	0	0
T152	19685	61	0	0
T153	4314	56	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5520	0	0
T78	4508	8	0	0
T80	1971	4	0	0
T95	14390	133	0	0
T102	91189	324	0	0
T117	3574	43	0	0
T118	103144	457	0	0
T120	7934	68	0	0
T150	13785	61	0	0
T151	7958	17	0	0
T152	19685	58	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5807	0	0
T78	4508	6	0	0
T95	14390	135	0	0
T102	91189	380	0	0
T117	3574	8	0	0
T118	103144	390	0	0
T120	7934	103	0	0
T150	13785	44	0	0
T151	7958	25	0	0
T152	19685	83	0	0
T153	4314	27	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5499	0	0
T78	4508	14	0	0
T95	14390	29	0	0
T102	91189	453	0	0
T117	3574	4	0	0
T118	103144	448	0	0
T120	7934	52	0	0
T150	13785	35	0	0
T151	7958	12	0	0
T152	19685	119	0	0
T153	4314	23	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5619	0	0
T78	4508	10	0	0
T80	1971	2	0	0
T95	14390	175	0	0
T102	91189	300	0	0
T117	3574	63	0	0
T118	103144	414	0	0
T120	7934	71	0	0
T150	13785	57	0	0
T151	7958	9	0	0
T152	19685	51	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	6086	0	0
T78	4508	8	0	0
T95	14390	96	0	0
T102	91189	399	0	0
T117	3574	65	0	0
T118	103144	469	0	0
T120	7934	55	0	0
T150	13785	26	0	0
T151	7958	39	0	0
T152	19685	57	0	0
T153	4314	18	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5535	0	0
T78	4508	12	0	0
T95	14390	25	0	0
T102	91189	365	0	0
T117	3574	6	0	0
T118	103144	465	0	0
T120	7934	47	0	0
T150	13785	15	0	0
T151	7958	8	0	0
T152	19685	42	0	0
T153	4314	28	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5275	0	0
T78	4508	10	0	0
T80	1971	8	0	0
T95	14390	98	0	0
T102	91189	357	0	0
T118	103144	422	0	0
T120	7934	109	0	0
T122	269081	617	0	0
T150	13785	77	0	0
T151	7958	21	0	0
T152	19685	17	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	6229	0	0
T78	4508	15	0	0
T95	14390	124	0	0
T102	91189	550	0	0
T117	3574	46	0	0
T118	103144	499	0	0
T120	7934	63	0	0
T150	13785	95	0	0
T151	7958	38	0	0
T152	19685	99	0	0
T153	4314	35	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5435	0	0
T78	4508	13	0	0
T95	14390	120	0	0
T102	91189	400	0	0
T117	3574	3	0	0
T118	103144	387	0	0
T120	7934	59	0	0
T150	13785	30	0	0
T151	7958	55	0	0
T152	19685	99	0	0
T153	4314	4	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5259	0	0
T78	4508	2	0	0
T80	1971	7	0	0
T95	14390	110	0	0
T102	91189	502	0	0
T117	3574	2	0	0
T118	103144	457	0	0
T120	7934	63	0	0
T150	13785	59	0	0
T151	7958	28	0	0
T152	19685	83	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5172	0	0
T78	4508	25	0	0
T95	14390	16	0	0
T102	91189	312	0	0
T117	3574	45	0	0
T118	103144	405	0	0
T120	7934	94	0	0
T150	13785	68	0	0
T151	7958	3	0	0
T152	19685	65	0	0
T153	4314	31	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5152	0	0
T78	4508	14	0	0
T80	1971	9	0	0
T95	14390	59	0	0
T102	91189	403	0	0
T117	3574	9	0	0
T118	103144	408	0	0
T120	7934	13	0	0
T150	13785	39	0	0
T151	7958	41	0	0
T152	19685	43	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5018	0	0
T78	4508	15	0	0
T95	14390	108	0	0
T102	91189	347	0	0
T117	3574	3	0	0
T118	103144	421	0	0
T120	7934	59	0	0
T150	13785	10	0	0
T151	7958	29	0	0
T152	19685	50	0	0
T153	4314	4	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5610	0	0
T78	4508	14	0	0
T95	14390	68	0	0
T102	91189	461	0	0
T117	3574	37	0	0
T118	103144	403	0	0
T120	7934	59	0	0
T150	13785	27	0	0
T151	7958	33	0	0
T152	19685	72	0	0
T153	4314	28	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5276	0	0
T78	4508	15	0	0
T95	14390	82	0	0
T102	91189	565	0	0
T117	3574	37	0	0
T118	103144	468	0	0
T120	7934	72	0	0
T150	13785	57	0	0
T151	7958	3	0	0
T152	19685	106	0	0
T153	4314	13	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5472	0	0
T78	4508	16	0	0
T80	1971	4	0	0
T95	14390	86	0	0
T102	91189	393	0	0
T117	3574	47	0	0
T118	103144	483	0	0
T120	7934	5	0	0
T150	13785	50	0	0
T151	7958	16	0	0
T152	19685	88	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5680	0	0
T78	4508	10	0	0
T95	14390	69	0	0
T102	91189	452	0	0
T117	3574	35	0	0
T118	103144	395	0	0
T120	7934	120	0	0
T150	13785	66	0	0
T151	7958	20	0	0
T152	19685	73	0	0
T153	4314	8	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5920	0	0
T78	4508	11	0	0
T95	14390	160	0	0
T102	91189	444	0	0
T117	3574	7	0	0
T118	103144	443	0	0
T120	7934	73	0	0
T150	13785	89	0	0
T151	7958	8	0	0
T152	19685	71	0	0
T153	4314	8	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5497	0	0
T78	4508	6	0	0
T95	14390	120	0	0
T102	91189	248	0	0
T117	3574	50	0	0
T118	103144	352	0	0
T120	7934	51	0	0
T150	13785	11	0	0
T151	7958	20	0	0
T152	19685	64	0	0
T153	4314	46	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5362	0	0
T78	4508	12	0	0
T95	14390	69	0	0
T102	91189	397	0	0
T117	3574	2	0	0
T118	103144	452	0	0
T120	7934	118	0	0
T150	13785	59	0	0
T151	7958	10	0	0
T152	19685	114	0	0
T153	4314	27	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5634	0	0
T78	4508	16	0	0
T95	14390	67	0	0
T102	91189	469	0	0
T117	3574	29	0	0
T118	103144	382	0	0
T120	7934	52	0	0
T150	13785	68	0	0
T151	7958	27	0	0
T152	19685	67	0	0
T153	4314	21	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5481	0	0
T78	4508	7	0	0
T95	14390	20	0	0
T102	91189	415	0	0
T117	3574	3	0	0
T118	103144	431	0	0
T120	7934	63	0	0
T150	13785	36	0	0
T151	7958	36	0	0
T152	19685	62	0	0
T153	4314	23	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5309	0	0
T78	4508	11	0	0
T80	1971	6	0	0
T95	14390	26	0	0
T102	91189	397	0	0
T117	3574	9	0	0
T118	103144	319	0	0
T120	7934	71	0	0
T150	13785	49	0	0
T151	7958	18	0	0
T152	19685	53	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5447	0	0
T78	4508	18	0	0
T80	1971	8	0	0
T95	14390	50	0	0
T102	91189	433	0	0
T117	3574	9	0	0
T118	103144	444	0	0
T120	7934	9	0	0
T150	13785	67	0	0
T151	7958	15	0	0
T152	19685	34	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3276	0	0
T78	4508	8	0	0
T95	14390	30	0	0
T102	91189	103	0	0
T117	3574	1	0	0
T118	103144	441	0	0
T120	7934	11	0	0
T150	13785	54	0	0
T151	7958	19	0	0
T152	19685	33	0	0
T153	4314	3	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3134	0	0
T78	4508	11	0	0
T95	14390	16	0	0
T102	91189	96	0	0
T117	3574	1	0	0
T118	103144	448	0	0
T120	7934	16	0	0
T150	13785	56	0	0
T151	7958	20	0	0
T152	19685	86	0	0
T153	4314	10	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3232	0	0
T78	4508	8	0	0
T80	1971	7	0	0
T95	14390	19	0	0
T102	91189	103	0	0
T117	3574	2	0	0
T118	103144	441	0	0
T120	7934	5	0	0
T150	13785	44	0	0
T151	7958	37	0	0
T152	19685	94	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3206	0	0
T78	4508	15	0	0
T80	1971	2	0	0
T95	14390	34	0	0
T102	91189	116	0	0
T117	3574	1	0	0
T118	103144	465	0	0
T120	7934	1	0	0
T150	13785	70	0	0
T151	7958	3	0	0
T152	19685	38	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3514	0	0
T78	4508	3	0	0
T80	1971	9	0	0
T95	14390	33	0	0
T102	91189	124	0	0
T118	103144	367	0	0
T120	7934	19	0	0
T150	13785	19	0	0
T151	7958	43	0	0
T152	19685	33	0	0
T153	4314	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	5069	0	0
T22	0	6	0	0
T27	331486	37	0	0
T28	772263	0	0	0
T33	442796	0	0	0
T34	753754	5	0	0
T36	0	13	0	0
T41	0	16	0	0
T42	14383	0	0	0
T44	330619	0	0	0
T81	52133	0	0	0
T86	138829	0	0	0
T114	199699	0	0	0
T137	0	16	0	0
T141	0	4	0	0
T154	0	23	0	0
T155	0	54	0	0
T156	0	7	0	0
T157	27212	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3260	0	0
T78	4508	15	0	0
T95	14390	29	0	0
T102	91189	94	0	0
T117	3574	1	0	0
T118	103144	397	0	0
T120	7934	10	0	0
T122	269081	676	0	0
T150	13785	55	0	0
T151	7958	32	0	0
T152	19685	53	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3051	0	0
T78	4508	6	0	0
T80	1971	2	0	0
T95	14390	15	0	0
T102	91189	111	0	0
T117	3574	2	0	0
T118	103144	376	0	0
T120	7934	12	0	0
T150	13785	26	0	0
T151	7958	1	0	0
T152	19685	67	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3011	0	0
T78	4508	15	0	0
T80	1971	8	0	0
T95	14390	15	0	0
T102	91189	40	0	0
T117	3574	10	0	0
T118	103144	458	0	0
T120	7934	5	0	0
T150	13785	27	0	0
T152	19685	69	0	0
T153	4314	4	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3040	0	0
T78	4508	18	0	0
T95	14390	23	0	0
T102	91189	89	0	0
T117	3574	9	0	0
T118	103144	427	0	0
T120	7934	8	0	0
T150	13785	59	0	0
T151	7958	17	0	0
T152	19685	61	0	0
T153	4314	10	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3009	0	0
T78	4508	18	0	0
T95	14390	27	0	0
T102	91189	62	0	0
T117	3574	5	0	0
T118	103144	420	0	0
T120	7934	6	0	0
T150	13785	22	0	0
T151	7958	42	0	0
T152	19685	66	0	0
T153	4314	4	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3089	0	0
T78	4508	7	0	0
T95	14390	23	0	0
T102	91189	60	0	0
T117	3574	4	0	0
T118	103144	422	0	0
T120	7934	4	0	0
T150	13785	48	0	0
T151	7958	17	0	0
T152	19685	56	0	0
T153	4314	4	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3638	0	0
T78	4508	11	0	0
T80	1971	5	0	0
T95	14390	35	0	0
T102	91189	151	0	0
T117	3574	8	0	0
T118	103144	375	0	0
T120	7934	41	0	0
T150	13785	43	0	0
T151	7958	13	0	0
T152	19685	68	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2886	0	0
T78	4508	8	0	0
T95	14390	33	0	0
T102	91189	35	0	0
T117	3574	3	0	0
T118	103144	416	0	0
T120	7934	12	0	0
T150	13785	27	0	0
T151	7958	21	0	0
T152	19685	106	0	0
T153	4314	1	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3696	0	0
T78	4508	14	0	0
T95	14390	27	0	0
T102	91189	177	0	0
T117	3574	3	0	0
T118	103144	449	0	0
T120	7934	8	0	0
T150	13785	69	0	0
T151	7958	33	0	0
T152	19685	62	0	0
T153	4314	16	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	3115	0	0
T78	4508	9	0	0
T80	1971	7	0	0
T95	14390	45	0	0
T102	91189	95	0	0
T117	3574	6	0	0
T118	103144	472	0	0
T150	13785	23	0	0
T151	7958	14	0	0
T152	19685	69	0	0
T153	4314	7	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2896	0	0
T78	4508	10	0	0
T80	1971	1	0	0
T95	14390	18	0	0
T102	91189	75	0	0
T118	103144	504	0	0
T120	7934	5	0	0
T150	13785	42	0	0
T151	7958	6	0	0
T152	19685	69	0	0
T153	4314	2	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2989	0	0
T78	4508	6	0	0
T95	14390	11	0	0
T102	91189	54	0	0
T117	3574	2	0	0
T118	103144	468	0	0
T120	7934	13	0	0
T150	13785	35	0	0
T151	7958	25	0	0
T152	19685	90	0	0
T153	4314	4	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2809	0	0
T78	4508	8	0	0
T95	14390	33	0	0
T102	91189	22	0	0
T117	3574	7	0	0
T118	103144	355	0	0
T120	7934	4	0	0
T150	13785	47	0	0
T151	7958	43	0	0
T152	19685	42	0	0
T153	4314	10	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2957	0	0
T78	4508	6	0	0
T95	14390	27	0	0
T102	91189	100	0	0
T117	3574	3	0	0
T118	103144	415	0	0
T120	7934	13	0	0
T150	13785	83	0	0
T151	7958	37	0	0
T152	19685	70	0	0
T153	4314	1	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2962	0	0
T78	4508	11	0	0
T95	14390	30	0	0
T102	91189	69	0	0
T117	3574	3	0	0
T118	103144	434	0	0
T120	7934	16	0	0
T150	13785	31	0	0
T151	7958	34	0	0
T152	19685	62	0	0
T153	4314	2	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	360750010	2995	0	0
T78	4508	5	0	0
T95	14390	19	0	0
T102	91189	56	0	0
T117	3574	6	0	0
T118	103144	420	0	0
T120	7934	8	0	0
T150	13785	49	0	0
T151	7958	8	0	0
T152	19685	50	0	0
T153	4314	8	0	0