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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.93 98.36 94.20 98.61 89.36 97.16 95.81 98.02


Total test records in report: 1101
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T810 /workspace/coverage/default/46.spi_device_flash_all.3644615267 May 14 01:07:56 PM PDT 24 May 14 01:08:02 PM PDT 24 34545035 ps
T811 /workspace/coverage/default/46.spi_device_tpm_sts_read.3884053263 May 14 01:07:52 PM PDT 24 May 14 01:07:56 PM PDT 24 13012666 ps
T812 /workspace/coverage/default/36.spi_device_csb_read.1219495897 May 14 01:07:29 PM PDT 24 May 14 01:07:34 PM PDT 24 13792980 ps
T813 /workspace/coverage/default/23.spi_device_read_buffer_direct.2560119382 May 14 01:06:25 PM PDT 24 May 14 01:07:00 PM PDT 24 142712963 ps
T814 /workspace/coverage/default/24.spi_device_mailbox.2523049940 May 14 01:06:26 PM PDT 24 May 14 01:07:05 PM PDT 24 1657670745 ps
T815 /workspace/coverage/default/46.spi_device_tpm_all.4283496918 May 14 01:08:06 PM PDT 24 May 14 01:08:38 PM PDT 24 14672440716 ps
T816 /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3570174105 May 14 01:07:47 PM PDT 24 May 14 01:07:56 PM PDT 24 411267364 ps
T817 /workspace/coverage/default/22.spi_device_flash_all.3314303691 May 14 01:06:18 PM PDT 24 May 14 01:09:06 PM PDT 24 15496880747 ps
T818 /workspace/coverage/default/10.spi_device_intercept.2940728644 May 14 01:05:36 PM PDT 24 May 14 01:05:52 PM PDT 24 417461076 ps
T819 /workspace/coverage/default/8.spi_device_read_buffer_direct.1713263694 May 14 01:05:23 PM PDT 24 May 14 01:05:48 PM PDT 24 1417878827 ps
T820 /workspace/coverage/default/12.spi_device_tpm_sts_read.164975254 May 14 01:05:41 PM PDT 24 May 14 01:05:58 PM PDT 24 158447920 ps
T821 /workspace/coverage/default/47.spi_device_flash_and_tpm.1135638698 May 14 01:08:05 PM PDT 24 May 14 01:09:36 PM PDT 24 21218533874 ps
T822 /workspace/coverage/default/41.spi_device_read_buffer_direct.2240517669 May 14 01:07:45 PM PDT 24 May 14 01:07:56 PM PDT 24 839569981 ps
T823 /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1876910457 May 14 01:06:08 PM PDT 24 May 14 01:06:48 PM PDT 24 1036915579 ps
T824 /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2914683895 May 14 01:05:35 PM PDT 24 May 14 01:05:48 PM PDT 24 210930400 ps
T825 /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.412302097 May 14 01:05:17 PM PDT 24 May 14 01:05:26 PM PDT 24 1236884211 ps
T826 /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1100160620 May 14 01:07:46 PM PDT 24 May 14 01:08:06 PM PDT 24 21917922616 ps
T220 /workspace/coverage/default/12.spi_device_flash_all.662740343 May 14 01:05:38 PM PDT 24 May 14 01:12:27 PM PDT 24 219244627437 ps
T234 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1470566637 May 14 01:05:19 PM PDT 24 May 14 01:06:43 PM PDT 24 15452244419 ps
T827 /workspace/coverage/default/19.spi_device_flash_mode.4003024132 May 14 01:06:09 PM PDT 24 May 14 01:06:50 PM PDT 24 843402290 ps
T84 /workspace/coverage/default/25.spi_device_stress_all.2222845381 May 14 01:06:25 PM PDT 24 May 14 01:15:49 PM PDT 24 103601239814 ps
T828 /workspace/coverage/default/37.spi_device_flash_all.1950666166 May 14 01:07:36 PM PDT 24 May 14 01:10:33 PM PDT 24 97570975715 ps
T829 /workspace/coverage/default/24.spi_device_intercept.1933353344 May 14 01:06:25 PM PDT 24 May 14 01:07:10 PM PDT 24 5503781351 ps
T830 /workspace/coverage/default/13.spi_device_tpm_sts_read.3141695835 May 14 01:05:51 PM PDT 24 May 14 01:06:19 PM PDT 24 45547177 ps
T831 /workspace/coverage/default/28.spi_device_read_buffer_direct.4118082419 May 14 01:06:37 PM PDT 24 May 14 01:07:14 PM PDT 24 1740757812 ps
T832 /workspace/coverage/default/33.spi_device_mailbox.3559349912 May 14 01:07:25 PM PDT 24 May 14 01:08:54 PM PDT 24 10371408067 ps
T833 /workspace/coverage/default/3.spi_device_pass_cmd_filtering.905072033 May 14 01:05:04 PM PDT 24 May 14 01:05:22 PM PDT 24 6937742822 ps
T834 /workspace/coverage/default/38.spi_device_flash_and_tpm.1080023178 May 14 01:07:37 PM PDT 24 May 14 01:08:14 PM PDT 24 5797486204 ps
T835 /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3471595884 May 14 01:05:57 PM PDT 24 May 14 01:06:40 PM PDT 24 2279977951 ps
T836 /workspace/coverage/default/49.spi_device_flash_all.4145445634 May 14 01:08:03 PM PDT 24 May 14 01:08:15 PM PDT 24 419758086 ps
T837 /workspace/coverage/default/13.spi_device_upload.1934202818 May 14 01:05:50 PM PDT 24 May 14 01:06:22 PM PDT 24 331235920 ps
T838 /workspace/coverage/default/6.spi_device_mem_parity.1992600505 May 14 01:05:18 PM PDT 24 May 14 01:05:26 PM PDT 24 64344531 ps
T839 /workspace/coverage/default/4.spi_device_mem_parity.2614728576 May 14 01:05:15 PM PDT 24 May 14 01:05:19 PM PDT 24 130132128 ps
T840 /workspace/coverage/default/49.spi_device_tpm_sts_read.2933518073 May 14 01:08:04 PM PDT 24 May 14 01:08:11 PM PDT 24 74920254 ps
T841 /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2092109067 May 14 01:07:39 PM PDT 24 May 14 01:08:10 PM PDT 24 31415987529 ps
T842 /workspace/coverage/default/47.spi_device_csb_read.3225286115 May 14 01:07:58 PM PDT 24 May 14 01:08:03 PM PDT 24 64670951 ps
T843 /workspace/coverage/default/43.spi_device_upload.3785826197 May 14 01:07:49 PM PDT 24 May 14 01:08:23 PM PDT 24 8724862897 ps
T844 /workspace/coverage/default/49.spi_device_flash_and_tpm.2740839561 May 14 01:08:05 PM PDT 24 May 14 01:10:46 PM PDT 24 48041671068 ps
T845 /workspace/coverage/default/17.spi_device_tpm_rw.2274932752 May 14 01:05:54 PM PDT 24 May 14 01:06:26 PM PDT 24 176547407 ps
T846 /workspace/coverage/default/38.spi_device_intercept.2821248893 May 14 01:07:40 PM PDT 24 May 14 01:07:46 PM PDT 24 124248934 ps
T847 /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1981658748 May 14 01:04:43 PM PDT 24 May 14 01:04:50 PM PDT 24 4869917636 ps
T65 /workspace/coverage/default/4.spi_device_sec_cm.1791716524 May 14 01:05:15 PM PDT 24 May 14 01:05:19 PM PDT 24 62017519 ps
T848 /workspace/coverage/default/12.spi_device_tpm_rw.2915663219 May 14 01:05:35 PM PDT 24 May 14 01:05:47 PM PDT 24 39421853 ps
T849 /workspace/coverage/default/36.spi_device_mailbox.4217583253 May 14 01:07:35 PM PDT 24 May 14 01:07:48 PM PDT 24 1262880414 ps
T850 /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1705758828 May 14 01:07:09 PM PDT 24 May 14 01:07:17 PM PDT 24 3354322760 ps
T851 /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.566371314 May 14 01:05:48 PM PDT 24 May 14 01:06:24 PM PDT 24 1896838668 ps
T852 /workspace/coverage/default/3.spi_device_intercept.1432728882 May 14 01:05:07 PM PDT 24 May 14 01:05:11 PM PDT 24 443596768 ps
T853 /workspace/coverage/default/24.spi_device_cfg_cmd.2455204893 May 14 01:06:27 PM PDT 24 May 14 01:07:00 PM PDT 24 69892056 ps
T854 /workspace/coverage/default/18.spi_device_cfg_cmd.143151154 May 14 01:06:05 PM PDT 24 May 14 01:06:46 PM PDT 24 3276723410 ps
T855 /workspace/coverage/default/46.spi_device_mailbox.876667265 May 14 01:08:02 PM PDT 24 May 14 01:08:14 PM PDT 24 6173611286 ps
T856 /workspace/coverage/default/4.spi_device_upload.3731996392 May 14 01:05:16 PM PDT 24 May 14 01:05:36 PM PDT 24 4853714212 ps
T857 /workspace/coverage/default/38.spi_device_mailbox.906183942 May 14 01:07:39 PM PDT 24 May 14 01:08:10 PM PDT 24 7239402987 ps
T858 /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3369441785 May 14 01:04:32 PM PDT 24 May 14 01:04:35 PM PDT 24 12417228 ps
T859 /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3385089831 May 14 01:07:56 PM PDT 24 May 14 01:08:04 PM PDT 24 92213043 ps
T860 /workspace/coverage/default/4.spi_device_read_buffer_direct.811456179 May 14 01:05:20 PM PDT 24 May 14 01:05:41 PM PDT 24 14074736291 ps
T861 /workspace/coverage/default/40.spi_device_read_buffer_direct.250252487 May 14 01:07:39 PM PDT 24 May 14 01:07:48 PM PDT 24 139216870 ps
T862 /workspace/coverage/default/38.spi_device_stress_all.3308625412 May 14 01:07:39 PM PDT 24 May 14 01:08:20 PM PDT 24 11402255232 ps
T863 /workspace/coverage/default/25.spi_device_mailbox.3537854353 May 14 01:06:26 PM PDT 24 May 14 01:07:11 PM PDT 24 639245787 ps
T864 /workspace/coverage/default/21.spi_device_tpm_sts_read.2766017744 May 14 01:06:07 PM PDT 24 May 14 01:06:45 PM PDT 24 63134965 ps
T865 /workspace/coverage/default/14.spi_device_read_buffer_direct.3147885608 May 14 01:05:53 PM PDT 24 May 14 01:06:34 PM PDT 24 3643070938 ps
T866 /workspace/coverage/default/1.spi_device_stress_all.1645569674 May 14 01:04:45 PM PDT 24 May 14 01:09:35 PM PDT 24 120127335914 ps
T867 /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3179984611 May 14 01:06:10 PM PDT 24 May 14 01:06:52 PM PDT 24 2390988536 ps
T868 /workspace/coverage/default/15.spi_device_intercept.1464807011 May 14 01:05:57 PM PDT 24 May 14 01:06:46 PM PDT 24 6081264213 ps
T869 /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2179186486 May 14 01:07:41 PM PDT 24 May 14 01:07:55 PM PDT 24 31698504082 ps
T870 /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.60811993 May 14 01:05:53 PM PDT 24 May 14 01:06:29 PM PDT 24 1234754332 ps
T871 /workspace/coverage/default/5.spi_device_tpm_sts_read.3340041244 May 14 01:05:15 PM PDT 24 May 14 01:05:18 PM PDT 24 25284298 ps
T872 /workspace/coverage/default/43.spi_device_flash_mode.47190007 May 14 01:07:51 PM PDT 24 May 14 01:08:09 PM PDT 24 5466911470 ps
T873 /workspace/coverage/default/36.spi_device_tpm_sts_read.3093928520 May 14 01:07:35 PM PDT 24 May 14 01:07:37 PM PDT 24 41715870 ps
T144 /workspace/coverage/default/13.spi_device_flash_and_tpm.341981197 May 14 01:05:45 PM PDT 24 May 14 01:09:48 PM PDT 24 49205320823 ps
T874 /workspace/coverage/default/48.spi_device_csb_read.2643315447 May 14 01:08:07 PM PDT 24 May 14 01:08:14 PM PDT 24 18207296 ps
T875 /workspace/coverage/default/40.spi_device_intercept.3662797644 May 14 01:07:42 PM PDT 24 May 14 01:07:49 PM PDT 24 746513895 ps
T876 /workspace/coverage/default/46.spi_device_upload.34501419 May 14 01:08:02 PM PDT 24 May 14 01:08:26 PM PDT 24 17820893842 ps
T877 /workspace/coverage/default/40.spi_device_flash_mode.1329827056 May 14 01:07:42 PM PDT 24 May 14 01:07:56 PM PDT 24 3697887250 ps
T878 /workspace/coverage/default/23.spi_device_intercept.782649405 May 14 01:06:15 PM PDT 24 May 14 01:07:21 PM PDT 24 5705903248 ps
T879 /workspace/coverage/default/22.spi_device_tpm_sts_read.2348243264 May 14 01:06:13 PM PDT 24 May 14 01:06:49 PM PDT 24 342681821 ps
T880 /workspace/coverage/default/8.spi_device_tpm_all.3232240864 May 14 01:05:26 PM PDT 24 May 14 01:06:07 PM PDT 24 13256363126 ps
T881 /workspace/coverage/default/12.spi_device_tpm_all.1777503855 May 14 01:05:41 PM PDT 24 May 14 01:06:34 PM PDT 24 30860347276 ps
T882 /workspace/coverage/default/48.spi_device_tpm_all.1589749771 May 14 01:07:55 PM PDT 24 May 14 01:08:09 PM PDT 24 1018332515 ps
T883 /workspace/coverage/default/10.spi_device_flash_mode.2920553581 May 14 01:05:36 PM PDT 24 May 14 01:05:59 PM PDT 24 767846819 ps
T884 /workspace/coverage/default/26.spi_device_tpm_sts_read.3443901297 May 14 01:06:34 PM PDT 24 May 14 01:07:00 PM PDT 24 28652470 ps
T885 /workspace/coverage/default/10.spi_device_tpm_rw.428447571 May 14 01:05:35 PM PDT 24 May 14 01:05:49 PM PDT 24 169152391 ps
T886 /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1934820593 May 14 01:07:27 PM PDT 24 May 14 01:07:45 PM PDT 24 24005674007 ps
T213 /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2957384538 May 14 01:06:25 PM PDT 24 May 14 01:08:17 PM PDT 24 15788499605 ps
T887 /workspace/coverage/default/29.spi_device_pass_cmd_filtering.376390784 May 14 01:06:37 PM PDT 24 May 14 01:07:06 PM PDT 24 297435329 ps
T888 /workspace/coverage/default/23.spi_device_alert_test.4056424079 May 14 01:06:24 PM PDT 24 May 14 01:06:56 PM PDT 24 13933388 ps
T889 /workspace/coverage/default/27.spi_device_read_buffer_direct.2258558573 May 14 01:06:33 PM PDT 24 May 14 01:07:14 PM PDT 24 4514635986 ps
T890 /workspace/coverage/default/29.spi_device_mailbox.3079491362 May 14 01:06:47 PM PDT 24 May 14 01:07:38 PM PDT 24 11663310371 ps
T891 /workspace/coverage/default/30.spi_device_tpm_all.408240558 May 14 01:06:47 PM PDT 24 May 14 01:07:09 PM PDT 24 5996955675 ps
T231 /workspace/coverage/default/15.spi_device_flash_all.3765127676 May 14 01:05:58 PM PDT 24 May 14 01:11:44 PM PDT 24 162628091960 ps
T892 /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1447826718 May 14 01:07:52 PM PDT 24 May 14 01:08:18 PM PDT 24 30536807575 ps
T893 /workspace/coverage/default/24.spi_device_flash_mode.4162360705 May 14 01:06:26 PM PDT 24 May 14 01:07:29 PM PDT 24 8196963051 ps
T894 /workspace/coverage/default/26.spi_device_read_buffer_direct.738089664 May 14 01:06:28 PM PDT 24 May 14 01:07:08 PM PDT 24 9736748438 ps
T895 /workspace/coverage/default/37.spi_device_tpm_all.3817089200 May 14 01:07:36 PM PDT 24 May 14 01:07:48 PM PDT 24 1175156533 ps
T896 /workspace/coverage/default/26.spi_device_cfg_cmd.2022852877 May 14 01:06:27 PM PDT 24 May 14 01:07:07 PM PDT 24 1156105078 ps
T897 /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2459920098 May 14 01:06:37 PM PDT 24 May 14 01:07:17 PM PDT 24 29870548680 ps
T898 /workspace/coverage/default/32.spi_device_read_buffer_direct.67820531 May 14 01:07:26 PM PDT 24 May 14 01:07:39 PM PDT 24 3768864800 ps
T899 /workspace/coverage/default/27.spi_device_tpm_sts_read.1183386126 May 14 01:06:37 PM PDT 24 May 14 01:07:02 PM PDT 24 130316242 ps
T900 /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3466887264 May 14 01:06:16 PM PDT 24 May 14 01:07:01 PM PDT 24 1499987869 ps
T901 /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3303453061 May 14 01:05:18 PM PDT 24 May 14 01:05:27 PM PDT 24 299554565 ps
T902 /workspace/coverage/default/33.spi_device_flash_mode.78284878 May 14 01:07:24 PM PDT 24 May 14 01:07:40 PM PDT 24 4017796613 ps
T903 /workspace/coverage/default/13.spi_device_pass_cmd_filtering.257446974 May 14 01:05:51 PM PDT 24 May 14 01:06:32 PM PDT 24 10991022785 ps
T904 /workspace/coverage/default/12.spi_device_read_buffer_direct.740225417 May 14 01:05:43 PM PDT 24 May 14 01:06:07 PM PDT 24 282267108 ps
T905 /workspace/coverage/default/3.spi_device_tpm_rw.175106356 May 14 01:05:05 PM PDT 24 May 14 01:05:19 PM PDT 24 1595285855 ps
T906 /workspace/coverage/default/42.spi_device_read_buffer_direct.233336432 May 14 01:07:49 PM PDT 24 May 14 01:07:59 PM PDT 24 231408973 ps
T907 /workspace/coverage/default/0.spi_device_tpm_rw.2040210164 May 14 01:04:37 PM PDT 24 May 14 01:04:39 PM PDT 24 60123264 ps
T908 /workspace/coverage/default/29.spi_device_intercept.1257346360 May 14 01:06:48 PM PDT 24 May 14 01:07:09 PM PDT 24 944766935 ps
T909 /workspace/coverage/default/43.spi_device_tpm_sts_read.4071887829 May 14 01:07:47 PM PDT 24 May 14 01:07:52 PM PDT 24 131497306 ps
T910 /workspace/coverage/default/46.spi_device_stress_all.3108434500 May 14 01:08:07 PM PDT 24 May 14 01:08:14 PM PDT 24 64903397 ps
T911 /workspace/coverage/default/47.spi_device_flash_mode.1093231609 May 14 01:08:07 PM PDT 24 May 14 01:08:20 PM PDT 24 648728916 ps
T912 /workspace/coverage/default/40.spi_device_upload.2293748658 May 14 01:07:39 PM PDT 24 May 14 01:08:12 PM PDT 24 34271063617 ps
T913 /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1187035378 May 14 01:07:28 PM PDT 24 May 14 01:07:34 PM PDT 24 133903747 ps
T914 /workspace/coverage/default/3.spi_device_flash_and_tpm.603525108 May 14 01:05:14 PM PDT 24 May 14 01:07:43 PM PDT 24 43611928467 ps
T915 /workspace/coverage/default/9.spi_device_read_buffer_direct.154042060 May 14 01:05:35 PM PDT 24 May 14 01:05:52 PM PDT 24 639866359 ps
T916 /workspace/coverage/default/11.spi_device_csb_read.2843485120 May 14 01:05:33 PM PDT 24 May 14 01:05:43 PM PDT 24 52140484 ps
T917 /workspace/coverage/default/25.spi_device_read_buffer_direct.1009080822 May 14 01:06:26 PM PDT 24 May 14 01:07:09 PM PDT 24 5672918031 ps
T918 /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2502961918 May 14 01:08:02 PM PDT 24 May 14 01:08:17 PM PDT 24 7321453486 ps
T66 /workspace/coverage/default/0.spi_device_sec_cm.1801404051 May 14 01:04:44 PM PDT 24 May 14 01:04:47 PM PDT 24 122376146 ps
T919 /workspace/coverage/default/46.spi_device_csb_read.1523860015 May 14 01:08:02 PM PDT 24 May 14 01:08:08 PM PDT 24 18260372 ps
T920 /workspace/coverage/default/20.spi_device_alert_test.3325715878 May 14 01:06:10 PM PDT 24 May 14 01:06:48 PM PDT 24 21949005 ps
T921 /workspace/coverage/default/17.spi_device_intercept.1407502613 May 14 01:05:56 PM PDT 24 May 14 01:06:35 PM PDT 24 1400059770 ps
T922 /workspace/coverage/default/2.spi_device_alert_test.3488181532 May 14 01:05:06 PM PDT 24 May 14 01:05:08 PM PDT 24 14288613 ps
T923 /workspace/coverage/default/16.spi_device_csb_read.2069377204 May 14 01:05:55 PM PDT 24 May 14 01:06:28 PM PDT 24 54130283 ps
T924 /workspace/coverage/default/45.spi_device_tpm_sts_read.3089504620 May 14 01:07:48 PM PDT 24 May 14 01:07:53 PM PDT 24 23974727 ps
T925 /workspace/coverage/default/19.spi_device_upload.910902686 May 14 01:06:06 PM PDT 24 May 14 01:06:46 PM PDT 24 77562712 ps
T926 /workspace/coverage/default/43.spi_device_read_buffer_direct.3635816009 May 14 01:07:46 PM PDT 24 May 14 01:07:58 PM PDT 24 3634738412 ps
T927 /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3989917634 May 14 01:07:26 PM PDT 24 May 14 01:07:30 PM PDT 24 12396664 ps
T928 /workspace/coverage/default/39.spi_device_alert_test.1726542434 May 14 01:07:40 PM PDT 24 May 14 01:07:44 PM PDT 24 43053361 ps
T929 /workspace/coverage/default/27.spi_device_tpm_all.2464778552 May 14 01:06:37 PM PDT 24 May 14 01:07:04 PM PDT 24 2693745558 ps
T930 /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3253883521 May 14 01:06:35 PM PDT 24 May 14 01:07:17 PM PDT 24 3259610438 ps
T931 /workspace/coverage/default/38.spi_device_tpm_all.3186945518 May 14 01:07:40 PM PDT 24 May 14 01:08:12 PM PDT 24 14777035647 ps
T932 /workspace/coverage/default/19.spi_device_stress_all.154870030 May 14 01:06:06 PM PDT 24 May 14 01:07:10 PM PDT 24 1788096129 ps
T933 /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1626169923 May 14 01:05:43 PM PDT 24 May 14 01:06:17 PM PDT 24 4086822517 ps
T934 /workspace/coverage/default/19.spi_device_mailbox.2426310569 May 14 01:06:06 PM PDT 24 May 14 01:06:54 PM PDT 24 996685859 ps
T935 /workspace/coverage/default/9.spi_device_stress_all.3957665241 May 14 01:05:34 PM PDT 24 May 14 01:12:27 PM PDT 24 37743854216 ps
T936 /workspace/coverage/default/37.spi_device_flash_mode.1148796008 May 14 01:07:36 PM PDT 24 May 14 01:07:54 PM PDT 24 1672863557 ps
T230 /workspace/coverage/default/20.spi_device_stress_all.486704749 May 14 01:06:11 PM PDT 24 May 14 01:10:56 PM PDT 24 18853433403 ps
T937 /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1888598755 May 14 01:08:06 PM PDT 24 May 14 01:08:21 PM PDT 24 1482869366 ps
T938 /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3786239745 May 14 01:06:00 PM PDT 24 May 14 01:10:22 PM PDT 24 44946955039 ps
T939 /workspace/coverage/default/35.spi_device_upload.3028223238 May 14 01:07:27 PM PDT 24 May 14 01:07:42 PM PDT 24 9432279764 ps
T940 /workspace/coverage/default/30.spi_device_csb_read.4003127814 May 14 01:06:47 PM PDT 24 May 14 01:07:05 PM PDT 24 66568068 ps
T941 /workspace/coverage/default/18.spi_device_flash_mode.3672588823 May 14 01:06:07 PM PDT 24 May 14 01:07:04 PM PDT 24 5990677768 ps
T942 /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2142022349 May 14 01:05:31 PM PDT 24 May 14 01:05:44 PM PDT 24 3550162324 ps
T943 /workspace/coverage/default/40.spi_device_csb_read.2372858731 May 14 01:07:38 PM PDT 24 May 14 01:07:42 PM PDT 24 33730781 ps
T944 /workspace/coverage/default/33.spi_device_read_buffer_direct.3072737089 May 14 01:07:26 PM PDT 24 May 14 01:07:38 PM PDT 24 493051596 ps
T945 /workspace/coverage/default/9.spi_device_flash_mode.1311337671 May 14 01:05:33 PM PDT 24 May 14 01:05:56 PM PDT 24 2526886495 ps
T946 /workspace/coverage/default/12.spi_device_flash_and_tpm.1835455647 May 14 01:05:39 PM PDT 24 May 14 01:07:36 PM PDT 24 39278512084 ps
T947 /workspace/coverage/default/18.spi_device_stress_all.1094108300 May 14 01:06:08 PM PDT 24 May 14 01:06:46 PM PDT 24 129062921 ps
T948 /workspace/coverage/default/48.spi_device_flash_and_tpm.798211634 May 14 01:08:05 PM PDT 24 May 14 01:10:57 PM PDT 24 79932095883 ps
T949 /workspace/coverage/default/4.spi_device_flash_all.3360702426 May 14 01:05:19 PM PDT 24 May 14 01:06:28 PM PDT 24 4901014460 ps
T950 /workspace/coverage/default/8.spi_device_mem_parity.1815066056 May 14 01:05:27 PM PDT 24 May 14 01:05:37 PM PDT 24 24852284 ps
T951 /workspace/coverage/default/49.spi_device_flash_mode.2774100593 May 14 01:08:02 PM PDT 24 May 14 01:08:10 PM PDT 24 213466999 ps
T952 /workspace/coverage/default/17.spi_device_upload.2603661821 May 14 01:05:56 PM PDT 24 May 14 01:06:39 PM PDT 24 11154037304 ps
T953 /workspace/coverage/default/1.spi_device_mailbox.224166711 May 14 01:04:45 PM PDT 24 May 14 01:05:00 PM PDT 24 1365585639 ps
T954 /workspace/coverage/default/11.spi_device_mailbox.3553981168 May 14 01:05:36 PM PDT 24 May 14 01:06:13 PM PDT 24 3335280673 ps
T955 /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2600465893 May 14 01:07:26 PM PDT 24 May 14 01:09:05 PM PDT 24 4950078757 ps
T956 /workspace/coverage/default/12.spi_device_upload.2046117762 May 14 01:05:41 PM PDT 24 May 14 01:06:17 PM PDT 24 13740671553 ps
T957 /workspace/coverage/default/7.spi_device_cfg_cmd.940658255 May 14 01:05:27 PM PDT 24 May 14 01:05:38 PM PDT 24 438138364 ps
T958 /workspace/coverage/default/15.spi_device_cfg_cmd.2010386976 May 14 01:05:53 PM PDT 24 May 14 01:06:25 PM PDT 24 497146378 ps
T959 /workspace/coverage/default/40.spi_device_flash_and_tpm.4205498438 May 14 01:07:37 PM PDT 24 May 14 01:08:58 PM PDT 24 3331559989 ps
T960 /workspace/coverage/default/9.spi_device_upload.1467685907 May 14 01:05:37 PM PDT 24 May 14 01:06:04 PM PDT 24 1856507153 ps
T961 /workspace/coverage/default/31.spi_device_upload.1830484813 May 14 01:07:09 PM PDT 24 May 14 01:07:21 PM PDT 24 4814642386 ps
T962 /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4262169263 May 14 01:06:47 PM PDT 24 May 14 01:08:50 PM PDT 24 9496422206 ps
T963 /workspace/coverage/default/45.spi_device_pass_cmd_filtering.16930828 May 14 01:07:58 PM PDT 24 May 14 01:08:10 PM PDT 24 794047117 ps
T964 /workspace/coverage/default/33.spi_device_tpm_sts_read.2750404684 May 14 01:07:26 PM PDT 24 May 14 01:07:30 PM PDT 24 60402803 ps
T965 /workspace/coverage/default/23.spi_device_tpm_all.3189703915 May 14 01:06:18 PM PDT 24 May 14 01:06:56 PM PDT 24 206252752 ps
T966 /workspace/coverage/default/22.spi_device_tpm_rw.2244023294 May 14 01:06:16 PM PDT 24 May 14 01:06:52 PM PDT 24 443386620 ps
T967 /workspace/coverage/default/42.spi_device_tpm_sts_read.2302829656 May 14 01:07:46 PM PDT 24 May 14 01:07:50 PM PDT 24 48335432 ps
T968 /workspace/coverage/default/35.spi_device_mailbox.1909608032 May 14 01:07:27 PM PDT 24 May 14 01:07:50 PM PDT 24 1320029192 ps
T969 /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1778988812 May 14 01:07:27 PM PDT 24 May 14 01:07:43 PM PDT 24 2678144124 ps
T970 /workspace/coverage/default/32.spi_device_csb_read.3833353607 May 14 01:07:10 PM PDT 24 May 14 01:07:14 PM PDT 24 78934331 ps
T971 /workspace/coverage/default/15.spi_device_csb_read.3618500699 May 14 01:05:46 PM PDT 24 May 14 01:06:10 PM PDT 24 66570913 ps
T972 /workspace/coverage/default/6.spi_device_tpm_rw.764648327 May 14 01:05:18 PM PDT 24 May 14 01:05:27 PM PDT 24 171070116 ps
T973 /workspace/coverage/default/23.spi_device_stress_all.3776437656 May 14 01:06:25 PM PDT 24 May 14 01:16:13 PM PDT 24 49719856655 ps
T974 /workspace/coverage/default/31.spi_device_tpm_all.1046555999 May 14 01:07:10 PM PDT 24 May 14 01:07:18 PM PDT 24 1614907191 ps
T975 /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2475952372 May 14 01:07:40 PM PDT 24 May 14 01:07:59 PM PDT 24 24564069181 ps
T976 /workspace/coverage/default/47.spi_device_mailbox.82453476 May 14 01:08:07 PM PDT 24 May 14 01:08:51 PM PDT 24 16291692902 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1617608277 May 14 01:23:06 PM PDT 24 May 14 01:23:09 PM PDT 24 187954826 ps
T150 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4237659261 May 14 01:23:22 PM PDT 24 May 14 01:23:27 PM PDT 24 551512629 ps
T977 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4082116009 May 14 01:23:07 PM PDT 24 May 14 01:23:12 PM PDT 24 29910362 ps
T93 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1973576317 May 14 01:23:29 PM PDT 24 May 14 01:23:33 PM PDT 24 26245099 ps
T94 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.324027090 May 14 01:23:18 PM PDT 24 May 14 01:23:21 PM PDT 24 44281014 ps
T978 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2925926688 May 14 01:23:12 PM PDT 24 May 14 01:23:48 PM PDT 24 1044206021 ps
T979 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1007084770 May 14 01:23:01 PM PDT 24 May 14 01:23:03 PM PDT 24 11962789 ps
T95 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3790826541 May 14 01:23:26 PM PDT 24 May 14 01:23:32 PM PDT 24 846579770 ps
T99 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.693225460 May 14 01:23:23 PM PDT 24 May 14 01:23:30 PM PDT 24 112998574 ps
T115 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3547471457 May 14 01:23:07 PM PDT 24 May 14 01:23:12 PM PDT 24 41369225 ps
T116 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1562166106 May 14 01:23:05 PM PDT 24 May 14 01:23:08 PM PDT 24 22166857 ps
T980 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1883088491 May 14 01:23:03 PM PDT 24 May 14 01:23:05 PM PDT 24 10844980 ps
T153 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.868017266 May 14 01:23:22 PM PDT 24 May 14 01:23:26 PM PDT 24 172662970 ps
T117 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2976289059 May 14 01:23:11 PM PDT 24 May 14 01:23:14 PM PDT 24 149026044 ps
T100 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1335084690 May 14 01:23:04 PM PDT 24 May 14 01:23:08 PM PDT 24 211969149 ps
T151 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2448289390 May 14 01:23:28 PM PDT 24 May 14 01:23:32 PM PDT 24 159193500 ps
T96 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1964681551 May 14 01:23:03 PM PDT 24 May 14 01:23:10 PM PDT 24 390534532 ps
T97 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.725831079 May 14 01:23:11 PM PDT 24 May 14 01:23:18 PM PDT 24 77186953 ps
T981 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3694509010 May 14 01:23:27 PM PDT 24 May 14 01:23:32 PM PDT 24 67343702 ps
T79 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1930655257 May 14 01:23:04 PM PDT 24 May 14 01:23:07 PM PDT 24 153358752 ps
T98 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2551245958 May 14 01:23:23 PM PDT 24 May 14 01:23:32 PM PDT 24 1003502993 ps
T982 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1140965227 May 14 01:23:08 PM PDT 24 May 14 01:23:12 PM PDT 24 20340803 ps
T101 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4210790419 May 14 01:23:22 PM PDT 24 May 14 01:23:45 PM PDT 24 1507525148 ps
T118 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3613294573 May 14 01:23:06 PM PDT 24 May 14 01:23:31 PM PDT 24 1097270122 ps
T119 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2045749019 May 14 01:23:08 PM PDT 24 May 14 01:23:13 PM PDT 24 26959437 ps
T983 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3724391132 May 14 01:23:26 PM PDT 24 May 14 01:23:30 PM PDT 24 60955530 ps
T984 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.15463803 May 14 01:23:24 PM PDT 24 May 14 01:23:27 PM PDT 24 19995163 ps
T103 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1339441886 May 14 01:23:22 PM PDT 24 May 14 01:23:28 PM PDT 24 218963036 ps
T152 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2946549195 May 14 01:23:24 PM PDT 24 May 14 01:23:31 PM PDT 24 757185680 ps
T985 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2875386011 May 14 01:23:29 PM PDT 24 May 14 01:23:32 PM PDT 24 17728576 ps
T120 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3843007158 May 14 01:23:29 PM PDT 24 May 14 01:23:34 PM PDT 24 345001286 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3919014304 May 14 01:23:28 PM PDT 24 May 14 01:23:34 PM PDT 24 121740096 ps
T986 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3323909767 May 14 01:23:26 PM PDT 24 May 14 01:23:30 PM PDT 24 75151559 ps
T987 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3168576200 May 14 01:23:22 PM PDT 24 May 14 01:23:27 PM PDT 24 248511761 ps
T111 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.621597411 May 14 01:23:24 PM PDT 24 May 14 01:23:28 PM PDT 24 128637873 ps
T102 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.602630749 May 14 01:23:30 PM PDT 24 May 14 01:23:53 PM PDT 24 949945955 ps
T121 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3997472529 May 14 01:23:05 PM PDT 24 May 14 01:23:08 PM PDT 24 54762009 ps
T988 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4293214383 May 14 01:23:11 PM PDT 24 May 14 01:23:14 PM PDT 24 13796234 ps
T989 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4040477826 May 14 01:23:07 PM PDT 24 May 14 01:23:13 PM PDT 24 60652881 ps
T990 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3161411675 May 14 01:23:34 PM PDT 24 May 14 01:23:39 PM PDT 24 256286530 ps
T991 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.7685867 May 14 01:23:34 PM PDT 24 May 14 01:23:38 PM PDT 24 38303174 ps
T992 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1497050349 May 14 01:23:23 PM PDT 24 May 14 01:23:27 PM PDT 24 99202549 ps
T80 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.518227222 May 14 01:23:14 PM PDT 24 May 14 01:23:16 PM PDT 24 78953901 ps
T253 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2599039588 May 14 01:23:21 PM PDT 24 May 14 01:23:29 PM PDT 24 426102453 ps
T993 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.653817478 May 14 01:23:28 PM PDT 24 May 14 01:23:31 PM PDT 24 18104005 ps
T994 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.984012374 May 14 01:23:26 PM PDT 24 May 14 01:23:30 PM PDT 24 51276115 ps
T122 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1312707765 May 14 01:23:05 PM PDT 24 May 14 01:23:48 PM PDT 24 5491422305 ps
T249 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1661691560 May 14 01:23:10 PM PDT 24 May 14 01:23:20 PM PDT 24 336391274 ps
T995 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1500093528 May 14 01:23:13 PM PDT 24 May 14 01:23:15 PM PDT 24 53299696 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1158280813 May 14 01:23:10 PM PDT 24 May 14 01:23:14 PM PDT 24 124308088 ps
T996 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3487742846 May 14 01:23:24 PM PDT 24 May 14 01:23:29 PM PDT 24 268024709 ps
T997 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2967858789 May 14 01:23:04 PM PDT 24 May 14 01:23:08 PM PDT 24 100924171 ps
T255 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1652977694 May 14 01:23:32 PM PDT 24 May 14 01:23:53 PM PDT 24 1232032598 ps
T108 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4224086695 May 14 01:23:09 PM PDT 24 May 14 01:23:15 PM PDT 24 343718736 ps
T110 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2333396397 May 14 01:23:11 PM PDT 24 May 14 01:23:16 PM PDT 24 157242245 ps
T998 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3387758548 May 14 01:23:24 PM PDT 24 May 14 01:23:29 PM PDT 24 96692118 ps
T999 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2329059002 May 14 01:23:28 PM PDT 24 May 14 01:23:32 PM PDT 24 25168080 ps
T1000 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3810575700 May 14 01:23:14 PM PDT 24 May 14 01:23:19 PM PDT 24 350964159 ps
T1001 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1043872269 May 14 01:23:32 PM PDT 24 May 14 01:23:34 PM PDT 24 10848213 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3800186127 May 14 01:23:08 PM PDT 24 May 14 01:23:35 PM PDT 24 3925139649 ps
T107 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1389823996 May 14 01:23:07 PM PDT 24 May 14 01:23:13 PM PDT 24 576370345 ps
T1002 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.885830782 May 14 01:23:24 PM PDT 24 May 14 01:23:31 PM PDT 24 59877431 ps
T125 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2899160751 May 14 01:23:07 PM PDT 24 May 14 01:23:32 PM PDT 24 366207095 ps
T1003 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3998875985 May 14 01:23:24 PM PDT 24 May 14 01:23:29 PM PDT 24 163741190 ps
T112 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4278247070 May 14 01:23:26 PM PDT 24 May 14 01:23:32 PM PDT 24 478591960 ps
T1004 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1433412603 May 14 01:23:28 PM PDT 24 May 14 01:23:31 PM PDT 24 15877814 ps
T258 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2301681664 May 14 01:23:06 PM PDT 24 May 14 01:23:23 PM PDT 24 1346174944 ps
T1005 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.552935716 May 14 01:23:34 PM PDT 24 May 14 01:23:37 PM PDT 24 31662448 ps
T1006 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3070115329 May 14 01:23:24 PM PDT 24 May 14 01:23:28 PM PDT 24 40790266 ps
T1007 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1566539750 May 14 01:23:02 PM PDT 24 May 14 01:23:05 PM PDT 24 39070075 ps
T1008 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4258615031 May 14 01:23:23 PM PDT 24 May 14 01:23:45 PM PDT 24 1254388697 ps
T1009 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.279578390 May 14 01:23:20 PM PDT 24 May 14 01:23:23 PM PDT 24 62380095 ps
T1010 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2865812901 May 14 01:23:39 PM PDT 24 May 14 01:23:42 PM PDT 24 12874402 ps
T1011 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3452286116 May 14 01:23:09 PM PDT 24 May 14 01:23:13 PM PDT 24 103399210 ps
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