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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.93 98.36 94.20 98.61 89.36 97.16 95.81 98.02


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T126 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2485475065 May 14 01:23:07 PM PDT 24 May 14 01:23:11 PM PDT 24 45405033 ps
T127 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.721958221 May 14 01:23:26 PM PDT 24 May 14 01:23:31 PM PDT 24 148373228 ps
T1012 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1050928087 May 14 01:23:36 PM PDT 24 May 14 01:23:40 PM PDT 24 16932850 ps
T1013 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2493013468 May 14 01:23:36 PM PDT 24 May 14 01:23:40 PM PDT 24 76017824 ps
T1014 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.650261267 May 14 01:23:34 PM PDT 24 May 14 01:23:38 PM PDT 24 16182628 ps
T1015 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1461068415 May 14 01:23:19 PM PDT 24 May 14 01:23:20 PM PDT 24 48508029 ps
T1016 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4030533579 May 14 01:23:12 PM PDT 24 May 14 01:23:19 PM PDT 24 401804063 ps
T109 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1805595856 May 14 01:23:29 PM PDT 24 May 14 01:23:36 PM PDT 24 781127561 ps
T1017 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4289644240 May 14 01:23:21 PM PDT 24 May 14 01:23:26 PM PDT 24 114355492 ps
T1018 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1902842799 May 14 01:23:21 PM PDT 24 May 14 01:23:23 PM PDT 24 18995983 ps
T1019 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1721686599 May 14 01:23:25 PM PDT 24 May 14 01:23:32 PM PDT 24 509122693 ps
T1020 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3536062335 May 14 01:23:22 PM PDT 24 May 14 01:23:26 PM PDT 24 31001070 ps
T1021 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1903914606 May 14 01:23:35 PM PDT 24 May 14 01:23:38 PM PDT 24 11764935 ps
T1022 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2399308185 May 14 01:23:03 PM PDT 24 May 14 01:23:06 PM PDT 24 35039001 ps
T1023 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1584156410 May 14 01:23:29 PM PDT 24 May 14 01:23:35 PM PDT 24 58970231 ps
T1024 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.518105420 May 14 01:23:06 PM PDT 24 May 14 01:23:16 PM PDT 24 777795008 ps
T1025 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2141199770 May 14 01:23:06 PM PDT 24 May 14 01:23:11 PM PDT 24 113174891 ps
T1026 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3334289929 May 14 01:23:21 PM PDT 24 May 14 01:23:23 PM PDT 24 30798823 ps
T1027 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2596186642 May 14 01:23:12 PM PDT 24 May 14 01:23:17 PM PDT 24 45882658 ps
T1028 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1984567782 May 14 01:23:13 PM PDT 24 May 14 01:23:18 PM PDT 24 171406953 ps
T1029 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3317746306 May 14 01:23:29 PM PDT 24 May 14 01:23:32 PM PDT 24 60142671 ps
T1030 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.915068459 May 14 01:23:03 PM PDT 24 May 14 01:23:07 PM PDT 24 103039315 ps
T1031 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1421155048 May 14 01:23:27 PM PDT 24 May 14 01:23:30 PM PDT 24 101107430 ps
T1032 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1300077012 May 14 01:23:24 PM PDT 24 May 14 01:23:28 PM PDT 24 252448823 ps
T1033 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4153540488 May 14 01:23:10 PM PDT 24 May 14 01:23:14 PM PDT 24 52482792 ps
T1034 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3453260945 May 14 01:23:37 PM PDT 24 May 14 01:23:41 PM PDT 24 14367945 ps
T259 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.256376517 May 14 01:23:22 PM PDT 24 May 14 01:23:32 PM PDT 24 3922164574 ps
T1035 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1817768260 May 14 01:23:25 PM PDT 24 May 14 01:23:33 PM PDT 24 823242891 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1333906628 May 14 01:23:02 PM PDT 24 May 14 01:23:05 PM PDT 24 76162048 ps
T1037 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1527172422 May 14 01:23:24 PM PDT 24 May 14 01:23:30 PM PDT 24 44426038 ps
T1038 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2843338888 May 14 01:23:25 PM PDT 24 May 14 01:23:31 PM PDT 24 222972867 ps
T1039 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2111254312 May 14 01:23:21 PM PDT 24 May 14 01:23:23 PM PDT 24 56257233 ps
T1040 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.192003548 May 14 01:23:37 PM PDT 24 May 14 01:23:40 PM PDT 24 15355950 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4045273452 May 14 01:23:07 PM PDT 24 May 14 01:23:34 PM PDT 24 2894667333 ps
T1042 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.274643674 May 14 01:23:32 PM PDT 24 May 14 01:23:34 PM PDT 24 33518837 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3807434903 May 14 01:23:07 PM PDT 24 May 14 01:23:12 PM PDT 24 56642980 ps
T1044 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4198521030 May 14 01:23:22 PM PDT 24 May 14 01:23:25 PM PDT 24 22306821 ps
T1045 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3879557161 May 14 01:23:23 PM PDT 24 May 14 01:23:29 PM PDT 24 126301356 ps
T1046 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2072544281 May 14 01:23:07 PM PDT 24 May 14 01:23:10 PM PDT 24 29728934 ps
T1047 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1876331441 May 14 01:23:18 PM PDT 24 May 14 01:23:35 PM PDT 24 1545685181 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2066642540 May 14 01:23:06 PM PDT 24 May 14 01:23:10 PM PDT 24 77874534 ps
T256 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2792642372 May 14 01:23:19 PM PDT 24 May 14 01:23:27 PM PDT 24 587254541 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1462369118 May 14 01:23:12 PM PDT 24 May 14 01:23:15 PM PDT 24 29595397 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.647866591 May 14 01:23:29 PM PDT 24 May 14 01:23:33 PM PDT 24 185131347 ps
T1051 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3498696480 May 14 01:23:27 PM PDT 24 May 14 01:23:30 PM PDT 24 24880803 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.183222688 May 14 01:23:07 PM PDT 24 May 14 01:23:13 PM PDT 24 99525522 ps
T1053 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2282199916 May 14 01:23:28 PM PDT 24 May 14 01:23:32 PM PDT 24 57140122 ps
T1054 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.703000814 May 14 01:23:25 PM PDT 24 May 14 01:23:30 PM PDT 24 59779123 ps
T248 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1562723549 May 14 01:23:28 PM PDT 24 May 14 01:23:34 PM PDT 24 107426539 ps
T1055 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.5950824 May 14 01:23:26 PM PDT 24 May 14 01:23:30 PM PDT 24 42710940 ps
T1056 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2558457420 May 14 01:23:07 PM PDT 24 May 14 01:23:23 PM PDT 24 188028366 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.931100978 May 14 01:23:22 PM PDT 24 May 14 01:23:39 PM PDT 24 819298050 ps
T1058 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1259429867 May 14 01:23:34 PM PDT 24 May 14 01:23:38 PM PDT 24 202200177 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.423142487 May 14 01:23:12 PM PDT 24 May 14 01:23:36 PM PDT 24 415571806 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1186848805 May 14 01:23:02 PM PDT 24 May 14 01:23:09 PM PDT 24 124349383 ps
T1061 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.414572141 May 14 01:23:22 PM PDT 24 May 14 01:23:27 PM PDT 24 189827708 ps
T1062 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2165120882 May 14 01:23:24 PM PDT 24 May 14 01:23:30 PM PDT 24 119038272 ps
T1063 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2362735052 May 14 01:23:22 PM PDT 24 May 14 01:23:27 PM PDT 24 143130517 ps
T1064 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.90726387 May 14 01:23:29 PM PDT 24 May 14 01:23:32 PM PDT 24 24076387 ps
T1065 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.927718585 May 14 01:23:32 PM PDT 24 May 14 01:23:34 PM PDT 24 44163414 ps
T1066 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.512128817 May 14 01:23:22 PM PDT 24 May 14 01:23:39 PM PDT 24 12472579801 ps
T1067 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2878707037 May 14 01:23:42 PM PDT 24 May 14 01:23:44 PM PDT 24 27225479 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4155613200 May 14 01:23:11 PM PDT 24 May 14 01:23:17 PM PDT 24 266412981 ps
T1069 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.303512703 May 14 01:23:23 PM PDT 24 May 14 01:23:27 PM PDT 24 18299026 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1853254631 May 14 01:23:07 PM PDT 24 May 14 01:23:14 PM PDT 24 275967346 ps
T250 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4068535168 May 14 01:23:03 PM PDT 24 May 14 01:23:26 PM PDT 24 14930956414 ps
T1071 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3626666258 May 14 01:23:27 PM PDT 24 May 14 01:23:32 PM PDT 24 310962196 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1475917365 May 14 01:23:07 PM PDT 24 May 14 01:23:11 PM PDT 24 39015867 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.298980253 May 14 01:23:12 PM PDT 24 May 14 01:23:17 PM PDT 24 180573011 ps
T257 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1753800063 May 14 01:23:05 PM PDT 24 May 14 01:23:24 PM PDT 24 1119111217 ps
T1074 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1052959326 May 14 01:23:32 PM PDT 24 May 14 01:23:35 PM PDT 24 48381556 ps
T254 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3111445192 May 14 01:23:26 PM PDT 24 May 14 01:23:49 PM PDT 24 833310477 ps
T1075 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.890564042 May 14 01:23:35 PM PDT 24 May 14 01:23:39 PM PDT 24 15672790 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1367604094 May 14 01:23:05 PM PDT 24 May 14 01:23:07 PM PDT 24 11688544 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2355594548 May 14 01:23:25 PM PDT 24 May 14 01:23:29 PM PDT 24 55174078 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1104431304 May 14 01:23:24 PM PDT 24 May 14 01:23:28 PM PDT 24 59820933 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.155631763 May 14 01:23:23 PM PDT 24 May 14 01:23:48 PM PDT 24 4609932774 ps
T1080 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2684909971 May 14 01:23:34 PM PDT 24 May 14 01:23:38 PM PDT 24 49440656 ps
T1081 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4287138433 May 14 01:23:25 PM PDT 24 May 14 01:23:30 PM PDT 24 75501847 ps
T1082 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.464948934 May 14 01:23:24 PM PDT 24 May 14 01:23:29 PM PDT 24 25435564 ps
T1083 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2172589431 May 14 01:23:37 PM PDT 24 May 14 01:23:40 PM PDT 24 64561828 ps
T1084 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4160974262 May 14 01:23:10 PM PDT 24 May 14 01:23:15 PM PDT 24 168996288 ps
T1085 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3570476705 May 14 01:23:23 PM PDT 24 May 14 01:23:30 PM PDT 24 186747620 ps
T1086 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.196162358 May 14 01:23:29 PM PDT 24 May 14 01:23:32 PM PDT 24 41398088 ps
T251 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.425620122 May 14 01:23:03 PM PDT 24 May 14 01:23:24 PM PDT 24 1654475991 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3697261587 May 14 01:23:26 PM PDT 24 May 14 01:23:34 PM PDT 24 1565687395 ps
T1088 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2306394697 May 14 01:23:10 PM PDT 24 May 14 01:23:37 PM PDT 24 4165031355 ps
T1089 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.821053246 May 14 01:23:06 PM PDT 24 May 14 01:23:08 PM PDT 24 18578891 ps
T1090 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.129762009 May 14 01:23:25 PM PDT 24 May 14 01:23:29 PM PDT 24 11490082 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3146592824 May 14 01:23:26 PM PDT 24 May 14 01:23:30 PM PDT 24 22804321 ps
T1092 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3153250884 May 14 01:23:32 PM PDT 24 May 14 01:23:34 PM PDT 24 36918246 ps
T1093 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.449654494 May 14 01:23:23 PM PDT 24 May 14 01:23:32 PM PDT 24 101986626 ps
T1094 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.222130738 May 14 01:23:35 PM PDT 24 May 14 01:23:39 PM PDT 24 87256340 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3841842870 May 14 01:23:28 PM PDT 24 May 14 01:23:34 PM PDT 24 61679024 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.462140377 May 14 01:23:03 PM PDT 24 May 14 01:23:07 PM PDT 24 74297368 ps
T252 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.178203483 May 14 01:23:22 PM PDT 24 May 14 01:23:38 PM PDT 24 203466899 ps
T1097 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2440057637 May 14 01:23:23 PM PDT 24 May 14 01:23:26 PM PDT 24 53950907 ps
T1098 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2844809220 May 14 01:23:31 PM PDT 24 May 14 01:23:34 PM PDT 24 11033125 ps
T1099 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.712373932 May 14 01:23:32 PM PDT 24 May 14 01:23:34 PM PDT 24 49994823 ps
T1100 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3775197215 May 14 01:23:24 PM PDT 24 May 14 01:23:28 PM PDT 24 19017144 ps
T1101 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3354051010 May 14 01:23:38 PM PDT 24 May 14 01:23:42 PM PDT 24 16406273 ps

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.202037549
Short name T4
Test name
Test status
Simulation time 176385035304 ps
CPU time 129.46 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:09:41 PM PDT 24
Peak memory 233008 kb
Host smart-d813d850-2fa0-464d-adbc-ec1145a85fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202037549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.202037549
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3539540175
Short name T11
Test name
Test status
Simulation time 17049834414 ps
CPU time 218.53 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:10:05 PM PDT 24
Peak memory 257584 kb
Host smart-6d1a912c-ec4b-4cd6-8438-4afb46f45def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539540175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3539540175
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3112170844
Short name T34
Test name
Test status
Simulation time 15702977784 ps
CPU time 122.7 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:07:29 PM PDT 24
Peak memory 258488 kb
Host smart-a37c50a0-a9e4-4eb3-8d5c-400d89d81a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112170844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3112170844
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3790826541
Short name T95
Test name
Test status
Simulation time 846579770 ps
CPU time 3.78 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 218500 kb
Host smart-193ca416-b788-4cc5-bbd0-98031dbe5667
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790826541 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3790826541
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.82546679
Short name T41
Test name
Test status
Simulation time 407881623958 ps
CPU time 1254.47 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:27:54 PM PDT 24
Peak memory 282080 kb
Host smart-f5f430b6-1ae5-4cbd-9c14-5ab7594bbc7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82546679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress
_all.82546679
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3285788516
Short name T61
Test name
Test status
Simulation time 46712258 ps
CPU time 0.72 seconds
Started May 14 01:04:31 PM PDT 24
Finished May 14 01:04:34 PM PDT 24
Peak memory 216236 kb
Host smart-a8f48c30-1871-4d2a-b119-8acd7671d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285788516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3285788516
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2650601791
Short name T36
Test name
Test status
Simulation time 55265952472 ps
CPU time 524.47 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 257452 kb
Host smart-725df4c6-5451-4e3b-bf7c-22aa6042a5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650601791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2650601791
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1051079914
Short name T180
Test name
Test status
Simulation time 644143978154 ps
CPU time 380.01 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 254728 kb
Host smart-bbea3f3a-7b0b-4d96-afe8-6fdb8d13085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051079914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1051079914
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2211509480
Short name T62
Test name
Test status
Simulation time 104193424 ps
CPU time 0.96 seconds
Started May 14 01:04:54 PM PDT 24
Finished May 14 01:04:56 PM PDT 24
Peak memory 234952 kb
Host smart-6387ace5-ab47-4212-a85a-a2a645e2a6b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211509480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2211509480
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.40552229
Short name T163
Test name
Test status
Simulation time 408178440503 ps
CPU time 356.01 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:11:29 PM PDT 24
Peak memory 273836 kb
Host smart-b653fb34-fd61-4fd2-971b-ded62d2d988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40552229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.40552229
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1262442013
Short name T145
Test name
Test status
Simulation time 1332639711 ps
CPU time 25.36 seconds
Started May 14 01:07:59 PM PDT 24
Finished May 14 01:08:29 PM PDT 24
Peak memory 240924 kb
Host smart-ea3ede72-cad4-4ac5-834a-00cf69978d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262442013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1262442013
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3650651364
Short name T27
Test name
Test status
Simulation time 67649866318 ps
CPU time 358.75 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 282180 kb
Host smart-737a7085-efb1-4e33-88dc-dcf47d9f160a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650651364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3650651364
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3680656859
Short name T186
Test name
Test status
Simulation time 14137795157 ps
CPU time 119.7 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 256860 kb
Host smart-fe21f754-cf6a-4582-842e-b48ee55d2836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680656859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3680656859
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.602630749
Short name T102
Test name
Test status
Simulation time 949945955 ps
CPU time 21.43 seconds
Started May 14 01:23:30 PM PDT 24
Finished May 14 01:23:53 PM PDT 24
Peak memory 215892 kb
Host smart-cc28239a-abf5-4dfc-a307-af98eefa3440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602630749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.602630749
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.723178887
Short name T174
Test name
Test status
Simulation time 13553949889 ps
CPU time 209.39 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:09:21 PM PDT 24
Peak memory 256284 kb
Host smart-79656d97-2a9f-44e1-be3a-05bd552fc791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723178887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.723178887
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1312707765
Short name T122
Test name
Test status
Simulation time 5491422305 ps
CPU time 40.95 seconds
Started May 14 01:23:05 PM PDT 24
Finished May 14 01:23:48 PM PDT 24
Peak memory 215852 kb
Host smart-f73ccae6-022a-4cd6-a33e-a9584462ea5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312707765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1312707765
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1964681551
Short name T96
Test name
Test status
Simulation time 390534532 ps
CPU time 5.31 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:10 PM PDT 24
Peak memory 215868 kb
Host smart-dd3fdc31-6683-4ffb-8dcd-941df5dfb293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964681551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
964681551
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2265985282
Short name T28
Test name
Test status
Simulation time 321779166660 ps
CPU time 671.45 seconds
Started May 14 01:06:24 PM PDT 24
Finished May 14 01:18:07 PM PDT 24
Peak memory 253084 kb
Host smart-0adbae73-1491-439c-8f33-7de3fb3b0682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265985282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2265985282
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3460743341
Short name T168
Test name
Test status
Simulation time 204679367697 ps
CPU time 429.27 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 265076 kb
Host smart-87ba432b-636b-428e-9d75-14f235b8e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460743341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3460743341
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2839797457
Short name T71
Test name
Test status
Simulation time 3849652559 ps
CPU time 103.72 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:08:30 PM PDT 24
Peak memory 267248 kb
Host smart-fcf0dccb-d68e-4e44-a870-0080249aabdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839797457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2839797457
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.405519964
Short name T441
Test name
Test status
Simulation time 67104949 ps
CPU time 1.04 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:48 PM PDT 24
Peak memory 216716 kb
Host smart-a68a6bb8-c3ac-4ef4-b3e6-da86bbdb6266
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405519964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.405519964
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1237313657
Short name T141
Test name
Test status
Simulation time 30429378096 ps
CPU time 197.63 seconds
Started May 14 01:07:45 PM PDT 24
Finished May 14 01:11:04 PM PDT 24
Peak memory 249308 kb
Host smart-7737e7b2-1f0e-43bb-bdc2-123f221348cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237313657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1237313657
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.894388538
Short name T38
Test name
Test status
Simulation time 427169365439 ps
CPU time 667.25 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:16:46 PM PDT 24
Peak memory 265732 kb
Host smart-2f38adf0-ebf2-4ca1-9e74-3c30b852f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894388538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
894388538
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2744850983
Short name T77
Test name
Test status
Simulation time 30226760000 ps
CPU time 267.51 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:12:28 PM PDT 24
Peak memory 270748 kb
Host smart-03009ee4-8d81-4472-96aa-a75423a752b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744850983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2744850983
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.633402559
Short name T210
Test name
Test status
Simulation time 5403603212 ps
CPU time 36 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:57 PM PDT 24
Peak memory 246496 kb
Host smart-8ab83762-6dde-4599-ae87-cb52b21c750b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633402559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.633402559
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4153130973
Short name T393
Test name
Test status
Simulation time 27597561 ps
CPU time 0.71 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 205740 kb
Host smart-d1521d94-9aaa-4ce5-9c24-6185ac28ee7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153130973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4153130973
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.178203483
Short name T252
Test name
Test status
Simulation time 203466899 ps
CPU time 13.91 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:38 PM PDT 24
Peak memory 215700 kb
Host smart-fdd6601c-caf8-4398-85c0-3264f93aa074
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178203483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.178203483
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1740935530
Short name T29
Test name
Test status
Simulation time 503730897 ps
CPU time 5.04 seconds
Started May 14 01:05:27 PM PDT 24
Finished May 14 01:05:41 PM PDT 24
Peak memory 219980 kb
Host smart-c011cbcc-0864-45c1-906b-fb98795c5806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740935530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1740935530
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2222845381
Short name T84
Test name
Test status
Simulation time 103601239814 ps
CPU time 532.68 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 273948 kb
Host smart-ef463a94-d499-4b0e-949f-360f0be9a3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222845381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2222845381
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4278247070
Short name T112
Test name
Test status
Simulation time 478591960 ps
CPU time 3.45 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 215872 kb
Host smart-2714fe81-015a-4d70-9254-bc8cfdb0ae25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278247070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
278247070
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3447224471
Short name T304
Test name
Test status
Simulation time 6024868781 ps
CPU time 32.12 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:39 PM PDT 24
Peak memory 241060 kb
Host smart-fbf214e7-8fdc-4424-9921-14458fa7e932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447224471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3447224471
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3581676368
Short name T165
Test name
Test status
Simulation time 16541249073 ps
CPU time 139.98 seconds
Started May 14 01:05:58 PM PDT 24
Finished May 14 01:08:53 PM PDT 24
Peak memory 255344 kb
Host smart-290ad107-7085-4943-98b9-d8e3b6fd34f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581676368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3581676368
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3800231991
Short name T246
Test name
Test status
Simulation time 81879865470 ps
CPU time 378.92 seconds
Started May 14 01:05:42 PM PDT 24
Finished May 14 01:12:18 PM PDT 24
Peak memory 255928 kb
Host smart-73c27fa3-22d5-4962-85db-6a7d8be6269e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800231991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3800231991
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.662740343
Short name T220
Test name
Test status
Simulation time 219244627437 ps
CPU time 396.19 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:12:27 PM PDT 24
Peak memory 249548 kb
Host smart-c885283f-510c-4b8b-8d5b-b27392f77ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662740343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.662740343
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.63774444
Short name T241
Test name
Test status
Simulation time 6773992051 ps
CPU time 33.28 seconds
Started May 14 01:06:17 PM PDT 24
Finished May 14 01:07:25 PM PDT 24
Peak memory 250024 kb
Host smart-a962e46d-e95f-4045-994d-bba12c4332b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63774444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.63774444
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2032659437
Short name T225
Test name
Test status
Simulation time 82338587020 ps
CPU time 179.55 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:09:50 PM PDT 24
Peak memory 259312 kb
Host smart-e01ac21f-81a7-41e6-a4bf-76067e962e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032659437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2032659437
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.635649295
Short name T242
Test name
Test status
Simulation time 32748454725 ps
CPU time 123.68 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 251336 kb
Host smart-4c8511bb-8f32-4b09-850d-785922833bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635649295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.635649295
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1470566637
Short name T234
Test name
Test status
Simulation time 15452244419 ps
CPU time 77.07 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:06:43 PM PDT 24
Peak memory 250328 kb
Host smart-5ace74b9-cbd6-4468-a0e0-51ddb9608428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470566637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1470566637
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2402692192
Short name T301
Test name
Test status
Simulation time 272668599 ps
CPU time 6.27 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 224408 kb
Host smart-822d0a26-d6a4-4fc2-921e-b75cc9694beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402692192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2402692192
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2522468852
Short name T215
Test name
Test status
Simulation time 65445072302 ps
CPU time 120.96 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:09:44 PM PDT 24
Peak memory 241044 kb
Host smart-7804a892-efed-416d-b472-73d48a78c14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522468852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2522468852
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1013564775
Short name T520
Test name
Test status
Simulation time 4202886938 ps
CPU time 13.3 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:06:04 PM PDT 24
Peak memory 233748 kb
Host smart-40591b48-9cff-4937-af01-94ef17e17e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013564775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1013564775
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3857585582
Short name T30
Test name
Test status
Simulation time 2979206159 ps
CPU time 7.69 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:06:51 PM PDT 24
Peak memory 235460 kb
Host smart-9f6eeddd-9b80-479f-b034-a0f37b9affc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857585582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3857585582
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2551245958
Short name T98
Test name
Test status
Simulation time 1003502993 ps
CPU time 6.87 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 215856 kb
Host smart-c07c13d2-c630-4afe-baea-8309c5b16ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551245958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2551245958
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2157096159
Short name T222
Test name
Test status
Simulation time 14514154300 ps
CPU time 213.4 seconds
Started May 14 01:05:46 PM PDT 24
Finished May 14 01:09:42 PM PDT 24
Peak memory 263524 kb
Host smart-1f8ec4d3-6308-4bb5-9bf0-ecb9e2e49e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157096159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2157096159
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3765127676
Short name T231
Test name
Test status
Simulation time 162628091960 ps
CPU time 312.08 seconds
Started May 14 01:05:58 PM PDT 24
Finished May 14 01:11:44 PM PDT 24
Peak memory 272436 kb
Host smart-28e5e26c-e4fd-4f0b-a9d2-53a777fb7303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765127676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3765127676
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.167842093
Short name T17
Test name
Test status
Simulation time 175812687 ps
CPU time 0.77 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:30 PM PDT 24
Peak memory 205760 kb
Host smart-5a8190c9-dab0-4d08-bc8c-224226a471fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167842093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.167842093
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3314303691
Short name T817
Test name
Test status
Simulation time 15496880747 ps
CPU time 133.93 seconds
Started May 14 01:06:18 PM PDT 24
Finished May 14 01:09:06 PM PDT 24
Peak memory 249284 kb
Host smart-2c70770d-24d6-4768-97a5-cd99392c8e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314303691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3314303691
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3295560502
Short name T218
Test name
Test status
Simulation time 227386343688 ps
CPU time 432.41 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:14:39 PM PDT 24
Peak memory 263436 kb
Host smart-c10106f5-c336-4c21-874c-02a8132ff47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295560502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3295560502
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1387973112
Short name T175
Test name
Test status
Simulation time 37272002421 ps
CPU time 230.92 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:09:08 PM PDT 24
Peak memory 265084 kb
Host smart-77ebc64a-b940-41ef-b18e-4f0e1d2d338b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387973112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1387973112
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1837572531
Short name T85
Test name
Test status
Simulation time 2474905279 ps
CPU time 5.41 seconds
Started May 14 01:06:23 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 233844 kb
Host smart-8e7e42fb-80cc-46ce-abd1-2c2f64a1e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837572531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1837572531
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1617608277
Short name T78
Test name
Test status
Simulation time 187954826 ps
CPU time 1.51 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:09 PM PDT 24
Peak memory 207516 kb
Host smart-67b8be62-25c5-4090-b452-582bfb357c09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617608277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1617608277
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1186848805
Short name T1060
Test name
Test status
Simulation time 124349383 ps
CPU time 4.5 seconds
Started May 14 01:23:02 PM PDT 24
Finished May 14 01:23:09 PM PDT 24
Peak memory 215776 kb
Host smart-334fe435-0c33-45c1-b73d-b712f7659114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186848805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
186848805
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3600989328
Short name T159
Test name
Test status
Simulation time 2407807229 ps
CPU time 30.02 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:06:20 PM PDT 24
Peak memory 232772 kb
Host smart-537f2655-fc6e-4059-9f13-d145cf821528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600989328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3600989328
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3390093586
Short name T329
Test name
Test status
Simulation time 165141154 ps
CPU time 0.74 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 205744 kb
Host smart-2518ff3f-0373-454e-89ff-65abed0ca470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390093586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3390093586
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4243069395
Short name T21
Test name
Test status
Simulation time 46391276795 ps
CPU time 204.17 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:10:20 PM PDT 24
Peak memory 255384 kb
Host smart-53ff70a8-0cca-4c47-bef7-ee0b8da8cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243069395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4243069395
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4045273452
Short name T1041
Test name
Test status
Simulation time 2894667333 ps
CPU time 24.57 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 215864 kb
Host smart-dd6fdb39-cff3-40e9-a77e-6f3f22a2a5b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045273452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4045273452
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1333906628
Short name T1036
Test name
Test status
Simulation time 76162048 ps
CPU time 1.02 seconds
Started May 14 01:23:02 PM PDT 24
Finished May 14 01:23:05 PM PDT 24
Peak memory 207232 kb
Host smart-27cfb098-5ecf-49b3-b0ef-207cbfd12950
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333906628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1333906628
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1335084690
Short name T100
Test name
Test status
Simulation time 211969149 ps
CPU time 1.87 seconds
Started May 14 01:23:04 PM PDT 24
Finished May 14 01:23:08 PM PDT 24
Peak memory 215776 kb
Host smart-9e7db2ed-37b3-451b-8169-74f23dd2642c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335084690 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1335084690
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1562166106
Short name T116
Test name
Test status
Simulation time 22166857 ps
CPU time 1.4 seconds
Started May 14 01:23:05 PM PDT 24
Finished May 14 01:23:08 PM PDT 24
Peak memory 215732 kb
Host smart-cd4687af-f94e-4cc6-a380-ceb68b305620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562166106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
562166106
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2399308185
Short name T1022
Test name
Test status
Simulation time 35039001 ps
CPU time 0.83 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:06 PM PDT 24
Peak memory 204248 kb
Host smart-a5c33b60-8109-4df0-bfe6-85cea259d93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399308185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
399308185
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2066642540
Short name T1048
Test name
Test status
Simulation time 77874534 ps
CPU time 1.53 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:10 PM PDT 24
Peak memory 215800 kb
Host smart-9711e6b4-8d34-4f60-8f5c-bdc7f3425a90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066642540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2066642540
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1883088491
Short name T980
Test name
Test status
Simulation time 10844980 ps
CPU time 0.66 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:05 PM PDT 24
Peak memory 203824 kb
Host smart-eb54beac-7419-46a9-91e6-fea51d0486b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883088491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1883088491
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3807434903
Short name T1043
Test name
Test status
Simulation time 56642980 ps
CPU time 1.91 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:12 PM PDT 24
Peak memory 215764 kb
Host smart-f26bbc13-d41d-4731-ade6-cb8ee9a4f603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807434903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3807434903
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1753800063
Short name T257
Test name
Test status
Simulation time 1119111217 ps
CPU time 17.97 seconds
Started May 14 01:23:05 PM PDT 24
Finished May 14 01:23:24 PM PDT 24
Peak memory 216084 kb
Host smart-d916b6ad-b713-470d-8594-fb55517a20ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753800063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1753800063
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3800186127
Short name T124
Test name
Test status
Simulation time 3925139649 ps
CPU time 24.5 seconds
Started May 14 01:23:08 PM PDT 24
Finished May 14 01:23:35 PM PDT 24
Peak memory 216892 kb
Host smart-860ecd43-3252-4549-ae8d-9478daf58544
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800186127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3800186127
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2925926688
Short name T978
Test name
Test status
Simulation time 1044206021 ps
CPU time 34.12 seconds
Started May 14 01:23:12 PM PDT 24
Finished May 14 01:23:48 PM PDT 24
Peak memory 207584 kb
Host smart-c73e08e8-b555-4ad0-9064-736d489d4f02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925926688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2925926688
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2141199770
Short name T1025
Test name
Test status
Simulation time 113174891 ps
CPU time 4.1 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:11 PM PDT 24
Peak memory 218272 kb
Host smart-b155b4bb-95a6-4114-95a1-728aadb37279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141199770 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2141199770
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.915068459
Short name T1030
Test name
Test status
Simulation time 103039315 ps
CPU time 2 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:07 PM PDT 24
Peak memory 215776 kb
Host smart-4ee70146-a7c1-46c2-b835-17da3e7c7603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915068459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.915068459
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.821053246
Short name T1089
Test name
Test status
Simulation time 18578891 ps
CPU time 0.73 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:08 PM PDT 24
Peak memory 204280 kb
Host smart-14651297-e21b-4e55-bd85-24b00be8734a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821053246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.821053246
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.462140377
Short name T1096
Test name
Test status
Simulation time 74297368 ps
CPU time 1.3 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:07 PM PDT 24
Peak memory 216052 kb
Host smart-88bca5ed-2e81-451a-a12b-d2e768104fbd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462140377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.462140377
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1566539750
Short name T1007
Test name
Test status
Simulation time 39070075 ps
CPU time 0.69 seconds
Started May 14 01:23:02 PM PDT 24
Finished May 14 01:23:05 PM PDT 24
Peak memory 203852 kb
Host smart-1fe62603-82cb-4a21-b1c2-8b24ca138109
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566539750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1566539750
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4040477826
Short name T989
Test name
Test status
Simulation time 60652881 ps
CPU time 3.73 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:13 PM PDT 24
Peak memory 215760 kb
Host smart-30d72e9a-fcbd-4f4a-a6e6-f996d327bc16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040477826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4040477826
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4155613200
Short name T1068
Test name
Test status
Simulation time 266412981 ps
CPU time 3.65 seconds
Started May 14 01:23:11 PM PDT 24
Finished May 14 01:23:17 PM PDT 24
Peak memory 215844 kb
Host smart-6775c9b1-6959-45dd-93b0-5f6d18b7d0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155613200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
155613200
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4068535168
Short name T250
Test name
Test status
Simulation time 14930956414 ps
CPU time 21.59 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:26 PM PDT 24
Peak memory 215988 kb
Host smart-141b86cb-695c-4b91-971c-8a29a01d2cf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068535168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4068535168
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.868017266
Short name T153
Test name
Test status
Simulation time 172662970 ps
CPU time 1.4 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:26 PM PDT 24
Peak memory 215760 kb
Host smart-6b4ff5e8-7d88-4721-86ec-2e5e5a8d652e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868017266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.868017266
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2440057637
Short name T1097
Test name
Test status
Simulation time 53950907 ps
CPU time 0.69 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:26 PM PDT 24
Peak memory 203988 kb
Host smart-4176ea11-2036-4b73-a0f5-7eb1ee539608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440057637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2440057637
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4289644240
Short name T1017
Test name
Test status
Simulation time 114355492 ps
CPU time 4.01 seconds
Started May 14 01:23:21 PM PDT 24
Finished May 14 01:23:26 PM PDT 24
Peak memory 215760 kb
Host smart-e44d11c0-96ea-4de5-8746-404cebd520ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289644240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4289644240
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3570476705
Short name T1085
Test name
Test status
Simulation time 186747620 ps
CPU time 4.58 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 216836 kb
Host smart-40e27480-701e-4c9b-8f0c-78c5fd62e3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570476705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3570476705
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.155631763
Short name T1079
Test name
Test status
Simulation time 4609932774 ps
CPU time 22.48 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:48 PM PDT 24
Peak memory 216384 kb
Host smart-07ca7c6b-0902-42a9-b4e9-008de689ffd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155631763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.155631763
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3536062335
Short name T1020
Test name
Test status
Simulation time 31001070 ps
CPU time 2 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:26 PM PDT 24
Peak memory 216904 kb
Host smart-318ab4af-8b09-4ee1-ada2-3ecbd177591e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536062335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3536062335
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.414572141
Short name T1061
Test name
Test status
Simulation time 189827708 ps
CPU time 2.83 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 215608 kb
Host smart-519f95bd-e97e-4d6b-a78a-0fc0b07e8e16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414572141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.414572141
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4198521030
Short name T1044
Test name
Test status
Simulation time 22306821 ps
CPU time 0.71 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:25 PM PDT 24
Peak memory 204000 kb
Host smart-79523d17-3b01-410f-b5eb-3d5d12b99511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198521030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4198521030
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3168576200
Short name T987
Test name
Test status
Simulation time 248511761 ps
CPU time 2.67 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 215764 kb
Host smart-eb44427c-ae73-4c58-bbce-98e4c3bd908a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168576200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3168576200
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1562723549
Short name T248
Test name
Test status
Simulation time 107426539 ps
CPU time 3.18 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 216924 kb
Host smart-fba1709c-50ac-4f07-828d-0f502acfd2c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562723549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1562723549
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2362735052
Short name T1063
Test name
Test status
Simulation time 143130517 ps
CPU time 2.49 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 218344 kb
Host smart-7bc80614-5e21-4c44-8ca6-341e741474b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362735052 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2362735052
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1104431304
Short name T1078
Test name
Test status
Simulation time 59820933 ps
CPU time 1.39 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:28 PM PDT 24
Peak memory 207504 kb
Host smart-ec07e551-da6c-4ae1-9f14-6f816350b241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104431304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1104431304
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.129762009
Short name T1090
Test name
Test status
Simulation time 11490082 ps
CPU time 0.71 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 204004 kb
Host smart-e555d493-747b-49bd-8086-43079e1b2826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129762009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.129762009
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4237659261
Short name T150
Test name
Test status
Simulation time 551512629 ps
CPU time 3.23 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 215792 kb
Host smart-b5979757-02b9-48ef-8d42-ec0ad1bb9ad5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237659261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4237659261
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1339441886
Short name T103
Test name
Test status
Simulation time 218963036 ps
CPU time 3.48 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:28 PM PDT 24
Peak memory 215852 kb
Host smart-e131b47a-ac20-4902-8dbb-63bf8a4d5258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339441886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1339441886
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4258615031
Short name T1008
Test name
Test status
Simulation time 1254388697 ps
CPU time 19.55 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:45 PM PDT 24
Peak memory 217108 kb
Host smart-c41cac50-461e-425c-a524-72aefe061010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258615031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4258615031
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.885830782
Short name T1002
Test name
Test status
Simulation time 59877431 ps
CPU time 4.23 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 218360 kb
Host smart-c8c2ec3a-3e14-442b-8e2e-5a44a6046c63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885830782 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.885830782
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3487742846
Short name T996
Test name
Test status
Simulation time 268024709 ps
CPU time 2.12 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 215692 kb
Host smart-243e8c30-3fe1-4d8a-847d-f1a4995a194e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487742846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3487742846
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3775197215
Short name T1100
Test name
Test status
Simulation time 19017144 ps
CPU time 0.75 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:28 PM PDT 24
Peak memory 204032 kb
Host smart-4a713585-8fd3-41ba-a081-49c3daa0c921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775197215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3775197215
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2165120882
Short name T1062
Test name
Test status
Simulation time 119038272 ps
CPU time 2.09 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 215780 kb
Host smart-262bef29-c78c-412b-b23b-0f33c24ee13c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165120882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2165120882
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3697261587
Short name T1087
Test name
Test status
Simulation time 1565687395 ps
CPU time 4.47 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 215884 kb
Host smart-03991ae8-2e3f-4144-8e12-3f5572020742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697261587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3697261587
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.449654494
Short name T1093
Test name
Test status
Simulation time 101986626 ps
CPU time 6.42 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 216052 kb
Host smart-d7e4436e-16a7-4a79-8508-79be2e930e15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449654494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.449654494
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2843338888
Short name T1038
Test name
Test status
Simulation time 222972867 ps
CPU time 2.84 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 217076 kb
Host smart-8c87a286-87c7-4edd-82c4-5e7c6a557289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843338888 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2843338888
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.703000814
Short name T1054
Test name
Test status
Simulation time 59779123 ps
CPU time 2.09 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 215664 kb
Host smart-b0083b33-d3b6-46a7-8773-e659ebf0d390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703000814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.703000814
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2111254312
Short name T1039
Test name
Test status
Simulation time 56257233 ps
CPU time 0.75 seconds
Started May 14 01:23:21 PM PDT 24
Finished May 14 01:23:23 PM PDT 24
Peak memory 204264 kb
Host smart-54ffda48-f990-4d7c-a22c-843b19c978c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111254312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2111254312
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3841842870
Short name T1095
Test name
Test status
Simulation time 61679024 ps
CPU time 3.97 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 215844 kb
Host smart-8f31b34b-3ec9-44e7-a03d-c4b3aadfff95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841842870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3841842870
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2282199916
Short name T1053
Test name
Test status
Simulation time 57140122 ps
CPU time 1.98 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 216080 kb
Host smart-38f39ddb-1ca7-4700-829d-9b68d3e9ef33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282199916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2282199916
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4210790419
Short name T101
Test name
Test status
Simulation time 1507525148 ps
CPU time 20.88 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:45 PM PDT 24
Peak memory 215772 kb
Host smart-693e30f2-a060-4579-844b-869343920a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210790419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4210790419
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3879557161
Short name T1045
Test name
Test status
Simulation time 126301356 ps
CPU time 3.46 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 217796 kb
Host smart-5d2503af-0f50-4f7e-89ef-e1e8b9b1f6aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879557161 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3879557161
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1300077012
Short name T1032
Test name
Test status
Simulation time 252448823 ps
CPU time 1.88 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:28 PM PDT 24
Peak memory 215696 kb
Host smart-baf8c4ee-0d63-4c13-8cae-d6cf7648db50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300077012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1300077012
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1902842799
Short name T1018
Test name
Test status
Simulation time 18995983 ps
CPU time 0.84 seconds
Started May 14 01:23:21 PM PDT 24
Finished May 14 01:23:23 PM PDT 24
Peak memory 203948 kb
Host smart-b2970e19-24c4-4f2c-b380-23384dffd1d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902842799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1902842799
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1497050349
Short name T992
Test name
Test status
Simulation time 99202549 ps
CPU time 1.88 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 215824 kb
Host smart-9b9ccea7-4bcf-4931-a767-9137dc6f0f46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497050349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1497050349
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.621597411
Short name T111
Test name
Test status
Simulation time 128637873 ps
CPU time 2.22 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:28 PM PDT 24
Peak memory 215916 kb
Host smart-0d6f9896-175b-4451-9fb4-6a5604c15d21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621597411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.621597411
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3111445192
Short name T254
Test name
Test status
Simulation time 833310477 ps
CPU time 20.34 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:49 PM PDT 24
Peak memory 215992 kb
Host smart-dc76cfa6-5035-4656-ac0a-74e48e53f0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111445192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3111445192
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1721686599
Short name T1019
Test name
Test status
Simulation time 509122693 ps
CPU time 3.92 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 217680 kb
Host smart-8f8ead94-de39-4f05-a405-39aa81e70c33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721686599 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1721686599
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.721958221
Short name T127
Test name
Test status
Simulation time 148373228 ps
CPU time 2.04 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 207432 kb
Host smart-5845ebc3-e74d-4003-98e2-27ffa9ab5a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721958221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.721958221
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3323909767
Short name T986
Test name
Test status
Simulation time 75151559 ps
CPU time 0.84 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 204068 kb
Host smart-b7bd9001-e608-4049-80cb-bef6e49d043c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323909767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3323909767
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2448289390
Short name T151
Test name
Test status
Simulation time 159193500 ps
CPU time 2.09 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 215852 kb
Host smart-7c19127c-1e28-45f3-b373-f71247de3ef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448289390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2448289390
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4287138433
Short name T1081
Test name
Test status
Simulation time 75501847 ps
CPU time 2.31 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 215816 kb
Host smart-aef2310b-7383-4998-a788-22a5e822dc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287138433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4287138433
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.647866591
Short name T1050
Test name
Test status
Simulation time 185131347 ps
CPU time 1.65 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:33 PM PDT 24
Peak memory 215812 kb
Host smart-d71f16d1-3b94-412a-b608-25c28b376d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647866591 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.647866591
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1259429867
Short name T1058
Test name
Test status
Simulation time 202200177 ps
CPU time 1.38 seconds
Started May 14 01:23:34 PM PDT 24
Finished May 14 01:23:38 PM PDT 24
Peak memory 215760 kb
Host smart-db03a23d-7ec4-4e52-8c22-c797c512a18c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259429867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1259429867
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3724391132
Short name T983
Test name
Test status
Simulation time 60955530 ps
CPU time 0.75 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 204272 kb
Host smart-6026a615-de18-4ce7-a44d-3514f70f97be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724391132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3724391132
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1584156410
Short name T1023
Test name
Test status
Simulation time 58970231 ps
CPU time 3.95 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:35 PM PDT 24
Peak memory 215824 kb
Host smart-45e6f32c-adca-4143-9015-c08ca53e9c21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584156410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1584156410
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1817768260
Short name T1035
Test name
Test status
Simulation time 823242891 ps
CPU time 5.02 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:33 PM PDT 24
Peak memory 215872 kb
Host smart-d472ad54-3a99-45db-8ee7-e989ebb85493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817768260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1817768260
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.256376517
Short name T259
Test name
Test status
Simulation time 3922164574 ps
CPU time 7.17 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 216088 kb
Host smart-57f108ea-fbee-46c9-b51f-544c41b7cf9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256376517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.256376517
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3919014304
Short name T113
Test name
Test status
Simulation time 121740096 ps
CPU time 2.84 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 217576 kb
Host smart-f1dc6b5e-0197-4944-a410-2e2719e9ba5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919014304 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3919014304
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3843007158
Short name T120
Test name
Test status
Simulation time 345001286 ps
CPU time 2.22 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 215672 kb
Host smart-2b212755-b5fc-4f87-87ca-f7c38c460ebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843007158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3843007158
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2355594548
Short name T1077
Test name
Test status
Simulation time 55174078 ps
CPU time 0.73 seconds
Started May 14 01:23:25 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 204232 kb
Host smart-70f0da66-abd4-4922-80da-979d366f3748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355594548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2355594548
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3694509010
Short name T981
Test name
Test status
Simulation time 67343702 ps
CPU time 2.03 seconds
Started May 14 01:23:27 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 215808 kb
Host smart-4461f70d-50a4-4e52-9681-61b6692e3b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694509010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3694509010
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1052959326
Short name T1074
Test name
Test status
Simulation time 48381556 ps
CPU time 1.84 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:35 PM PDT 24
Peak memory 215896 kb
Host smart-b65ab882-9890-426a-a400-edb1854fb3c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052959326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1052959326
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1973576317
Short name T93
Test name
Test status
Simulation time 26245099 ps
CPU time 1.82 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:33 PM PDT 24
Peak memory 215944 kb
Host smart-495b144e-f86b-4131-975d-915bcb5b9d87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973576317 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1973576317
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.196162358
Short name T1086
Test name
Test status
Simulation time 41398088 ps
CPU time 1.34 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 207408 kb
Host smart-f68842b2-25bd-4138-a74f-f28d14d2d53c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196162358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.196162358
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.927718585
Short name T1065
Test name
Test status
Simulation time 44163414 ps
CPU time 0.81 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 204004 kb
Host smart-c53b5cc1-824f-445e-988c-bf4be52f52d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927718585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.927718585
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3161411675
Short name T990
Test name
Test status
Simulation time 256286530 ps
CPU time 2.09 seconds
Started May 14 01:23:34 PM PDT 24
Finished May 14 01:23:39 PM PDT 24
Peak memory 215796 kb
Host smart-1daaebb1-c272-4f7e-8a3b-8a19fb919ebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161411675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3161411675
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1805595856
Short name T109
Test name
Test status
Simulation time 781127561 ps
CPU time 4.44 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:36 PM PDT 24
Peak memory 215864 kb
Host smart-dd8813f4-a992-4a5b-80bf-9b05901fb52a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805595856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1805595856
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1652977694
Short name T255
Test name
Test status
Simulation time 1232032598 ps
CPU time 19.24 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:53 PM PDT 24
Peak memory 215836 kb
Host smart-82fba674-4c87-4f65-aad5-e3c880489f49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652977694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1652977694
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3613294573
Short name T118
Test name
Test status
Simulation time 1097270122 ps
CPU time 22.28 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 215764 kb
Host smart-e0f80d0a-4cf6-47db-9626-5e2da1d73358
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613294573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3613294573
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2899160751
Short name T125
Test name
Test status
Simulation time 366207095 ps
CPU time 23.48 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 215736 kb
Host smart-90d7310b-376a-43a8-acd7-03ae0e9c750b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899160751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2899160751
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1930655257
Short name T79
Test name
Test status
Simulation time 153358752 ps
CPU time 1.49 seconds
Started May 14 01:23:04 PM PDT 24
Finished May 14 01:23:07 PM PDT 24
Peak memory 216688 kb
Host smart-93708a3b-60e7-417d-89a8-aade36427bd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930655257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1930655257
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1853254631
Short name T1070
Test name
Test status
Simulation time 275967346 ps
CPU time 4.26 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:14 PM PDT 24
Peak memory 218804 kb
Host smart-23a3e16a-56ca-4f53-bb22-41ee1d7728ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853254631 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1853254631
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1475917365
Short name T1072
Test name
Test status
Simulation time 39015867 ps
CPU time 1.4 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:11 PM PDT 24
Peak memory 215788 kb
Host smart-e117af5d-8799-4443-ae90-c67140cc9948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475917365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
475917365
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1140965227
Short name T982
Test name
Test status
Simulation time 20340803 ps
CPU time 0.74 seconds
Started May 14 01:23:08 PM PDT 24
Finished May 14 01:23:12 PM PDT 24
Peak memory 203888 kb
Host smart-4b59c106-9746-427a-b84f-0c5ce182f893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140965227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
140965227
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3997472529
Short name T121
Test name
Test status
Simulation time 54762009 ps
CPU time 1.24 seconds
Started May 14 01:23:05 PM PDT 24
Finished May 14 01:23:08 PM PDT 24
Peak memory 215640 kb
Host smart-328082a9-ffd0-4f08-90a7-fdf378c29522
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997472529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3997472529
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1367604094
Short name T1076
Test name
Test status
Simulation time 11688544 ps
CPU time 0.68 seconds
Started May 14 01:23:05 PM PDT 24
Finished May 14 01:23:07 PM PDT 24
Peak memory 203780 kb
Host smart-d5f36c97-daef-4c96-bb09-9f00838de198
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367604094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1367604094
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4082116009
Short name T977
Test name
Test status
Simulation time 29910362 ps
CPU time 1.87 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:12 PM PDT 24
Peak memory 215772 kb
Host smart-5a410766-601f-49c1-9a64-e35b110f12bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082116009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4082116009
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.425620122
Short name T251
Test name
Test status
Simulation time 1654475991 ps
CPU time 18.81 seconds
Started May 14 01:23:03 PM PDT 24
Finished May 14 01:23:24 PM PDT 24
Peak memory 215792 kb
Host smart-073255f2-a00e-4595-8578-8c29809ef344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425620122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.425620122
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3153250884
Short name T1092
Test name
Test status
Simulation time 36918246 ps
CPU time 0.73 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 203996 kb
Host smart-9895329a-e5b7-4090-9d5f-fa40d11b8d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153250884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3153250884
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2329059002
Short name T999
Test name
Test status
Simulation time 25168080 ps
CPU time 0.79 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 204248 kb
Host smart-ac64e8bc-00a1-41b8-8c39-0ef67e732a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329059002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2329059002
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.274643674
Short name T1042
Test name
Test status
Simulation time 33518837 ps
CPU time 0.75 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 204004 kb
Host smart-8bb5296d-7157-48d2-a3b7-dbcf62538356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274643674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.274643674
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1421155048
Short name T1031
Test name
Test status
Simulation time 101107430 ps
CPU time 0.73 seconds
Started May 14 01:23:27 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 203924 kb
Host smart-b5702605-4866-4016-a3d6-ebff3a816fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421155048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1421155048
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.653817478
Short name T993
Test name
Test status
Simulation time 18104005 ps
CPU time 0.78 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 204504 kb
Host smart-d2271a4a-8bfd-4104-afb3-3a6c1c6115b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653817478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.653817478
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3498696480
Short name T1051
Test name
Test status
Simulation time 24880803 ps
CPU time 0.78 seconds
Started May 14 01:23:27 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 204276 kb
Host smart-5db96c82-d538-4424-be3c-eb71c6db7d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498696480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3498696480
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1043872269
Short name T1001
Test name
Test status
Simulation time 10848213 ps
CPU time 0.72 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 203920 kb
Host smart-28478db8-d6a9-48a8-bde0-3e73930f6e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043872269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1043872269
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.7685867
Short name T991
Test name
Test status
Simulation time 38303174 ps
CPU time 0.77 seconds
Started May 14 01:23:34 PM PDT 24
Finished May 14 01:23:38 PM PDT 24
Peak memory 204228 kb
Host smart-62ec36ce-5396-4711-a9b8-d68d2dec1160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7685867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.7685867
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2844809220
Short name T1098
Test name
Test status
Simulation time 11033125 ps
CPU time 0.74 seconds
Started May 14 01:23:31 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 204256 kb
Host smart-9e04fb02-f364-47bd-9405-c026404850cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844809220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2844809220
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1433412603
Short name T1004
Test name
Test status
Simulation time 15877814 ps
CPU time 0.72 seconds
Started May 14 01:23:28 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 203892 kb
Host smart-734f5ba7-8ec7-4964-aba6-5511aa6c4518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433412603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1433412603
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.518105420
Short name T1024
Test name
Test status
Simulation time 777795008 ps
CPU time 8.85 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:16 PM PDT 24
Peak memory 215680 kb
Host smart-931146ef-6bb7-4a7b-b7fc-88b414a49921
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518105420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.518105420
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2558457420
Short name T1056
Test name
Test status
Simulation time 188028366 ps
CPU time 13.01 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:23 PM PDT 24
Peak memory 207468 kb
Host smart-87adec7e-014e-4096-a1d6-e5008d93ea8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558457420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2558457420
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2485475065
Short name T126
Test name
Test status
Simulation time 45405033 ps
CPU time 0.94 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:11 PM PDT 24
Peak memory 207312 kb
Host smart-55b2af0e-9d9c-4802-bf46-4a400ba76092
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485475065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2485475065
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2967858789
Short name T997
Test name
Test status
Simulation time 100924171 ps
CPU time 1.63 seconds
Started May 14 01:23:04 PM PDT 24
Finished May 14 01:23:08 PM PDT 24
Peak memory 215848 kb
Host smart-6b90ea3f-f81f-4682-8776-2a98522a5bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967858789 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2967858789
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2045749019
Short name T119
Test name
Test status
Simulation time 26959437 ps
CPU time 1.83 seconds
Started May 14 01:23:08 PM PDT 24
Finished May 14 01:23:13 PM PDT 24
Peak memory 215652 kb
Host smart-084b68bf-e8e4-4cec-8b54-5db750232b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045749019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
045749019
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2072544281
Short name T1046
Test name
Test status
Simulation time 29728934 ps
CPU time 0.86 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:10 PM PDT 24
Peak memory 204336 kb
Host smart-78cf1fa4-6cdc-40cb-844a-431b310d2d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072544281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
072544281
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3547471457
Short name T115
Test name
Test status
Simulation time 41369225 ps
CPU time 1.88 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:12 PM PDT 24
Peak memory 215740 kb
Host smart-a263ccd5-7323-46f8-9ff4-e92b3b0cac07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547471457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3547471457
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1007084770
Short name T979
Test name
Test status
Simulation time 11962789 ps
CPU time 0.7 seconds
Started May 14 01:23:01 PM PDT 24
Finished May 14 01:23:03 PM PDT 24
Peak memory 203844 kb
Host smart-465bf7e6-750f-4933-bde5-9317f38dd8d1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007084770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1007084770
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.183222688
Short name T1052
Test name
Test status
Simulation time 99525522 ps
CPU time 3.03 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:13 PM PDT 24
Peak memory 215748 kb
Host smart-53a7faa7-20b4-427f-9907-6eb0ca9e444f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183222688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.183222688
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1389823996
Short name T107
Test name
Test status
Simulation time 576370345 ps
CPU time 2.81 seconds
Started May 14 01:23:07 PM PDT 24
Finished May 14 01:23:13 PM PDT 24
Peak memory 215844 kb
Host smart-36541cbd-b7f9-4b58-bc91-4ef37ccc6498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389823996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
389823996
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2301681664
Short name T258
Test name
Test status
Simulation time 1346174944 ps
CPU time 14.72 seconds
Started May 14 01:23:06 PM PDT 24
Finished May 14 01:23:23 PM PDT 24
Peak memory 215856 kb
Host smart-1b427d65-1dd4-40b2-acba-3eb5205ce41f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301681664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2301681664
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.90726387
Short name T1064
Test name
Test status
Simulation time 24076387 ps
CPU time 0.74 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 204168 kb
Host smart-6bf9960b-7536-4f95-93cf-0115aad9cf62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90726387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.90726387
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.5950824
Short name T1055
Test name
Test status
Simulation time 42710940 ps
CPU time 0.73 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 203940 kb
Host smart-d0557667-6990-4b8b-aec8-8918f434bfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5950824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.5950824
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2875386011
Short name T985
Test name
Test status
Simulation time 17728576 ps
CPU time 0.71 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 204232 kb
Host smart-ad3209ae-9dd9-443c-a0ff-01933883cf8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875386011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2875386011
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.650261267
Short name T1014
Test name
Test status
Simulation time 16182628 ps
CPU time 0.75 seconds
Started May 14 01:23:34 PM PDT 24
Finished May 14 01:23:38 PM PDT 24
Peak memory 203992 kb
Host smart-1515c9eb-a394-4bfd-8598-67d5f855093e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650261267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.650261267
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.984012374
Short name T994
Test name
Test status
Simulation time 51276115 ps
CPU time 0.69 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 203968 kb
Host smart-28480da9-132e-4136-b4f2-aa854415fb34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984012374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.984012374
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3317746306
Short name T1029
Test name
Test status
Simulation time 60142671 ps
CPU time 0.75 seconds
Started May 14 01:23:29 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 204256 kb
Host smart-cc5ffea4-bd3b-4721-b50a-fb66460482cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317746306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3317746306
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.712373932
Short name T1099
Test name
Test status
Simulation time 49994823 ps
CPU time 0.78 seconds
Started May 14 01:23:32 PM PDT 24
Finished May 14 01:23:34 PM PDT 24
Peak memory 204004 kb
Host smart-7260aaca-36a4-4b9e-b452-93dbf0bd9a2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712373932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.712373932
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.552935716
Short name T1005
Test name
Test status
Simulation time 31662448 ps
CPU time 0.73 seconds
Started May 14 01:23:34 PM PDT 24
Finished May 14 01:23:37 PM PDT 24
Peak memory 204244 kb
Host smart-cc88fdbc-d8ca-4451-bd0c-d42baa2ef2d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552935716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.552935716
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3354051010
Short name T1101
Test name
Test status
Simulation time 16406273 ps
CPU time 0.78 seconds
Started May 14 01:23:38 PM PDT 24
Finished May 14 01:23:42 PM PDT 24
Peak memory 204272 kb
Host smart-13ba2da1-af9d-420c-990c-64c70b0e5a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354051010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3354051010
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.222130738
Short name T1094
Test name
Test status
Simulation time 87256340 ps
CPU time 0.73 seconds
Started May 14 01:23:35 PM PDT 24
Finished May 14 01:23:39 PM PDT 24
Peak memory 203920 kb
Host smart-70657f25-18b5-43b7-946b-84b242d9da2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222130738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.222130738
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1876331441
Short name T1047
Test name
Test status
Simulation time 1545685181 ps
CPU time 16.48 seconds
Started May 14 01:23:18 PM PDT 24
Finished May 14 01:23:35 PM PDT 24
Peak memory 215704 kb
Host smart-45070c49-63c2-4c7e-ac81-907722370116
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876331441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1876331441
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.423142487
Short name T1059
Test name
Test status
Simulation time 415571806 ps
CPU time 21.9 seconds
Started May 14 01:23:12 PM PDT 24
Finished May 14 01:23:36 PM PDT 24
Peak memory 215676 kb
Host smart-63cc461a-9315-41e1-be5a-459d9fcd27bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423142487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.423142487
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.518227222
Short name T80
Test name
Test status
Simulation time 78953901 ps
CPU time 1.02 seconds
Started May 14 01:23:14 PM PDT 24
Finished May 14 01:23:16 PM PDT 24
Peak memory 207316 kb
Host smart-0567998c-af1a-4bd8-b07c-7a55c6acbc5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518227222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.518227222
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.324027090
Short name T94
Test name
Test status
Simulation time 44281014 ps
CPU time 2.69 seconds
Started May 14 01:23:18 PM PDT 24
Finished May 14 01:23:21 PM PDT 24
Peak memory 218072 kb
Host smart-a1a64fcb-fe21-45b3-944f-f78908fdf86c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324027090 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.324027090
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2976289059
Short name T117
Test name
Test status
Simulation time 149026044 ps
CPU time 1.29 seconds
Started May 14 01:23:11 PM PDT 24
Finished May 14 01:23:14 PM PDT 24
Peak memory 215752 kb
Host smart-274d934a-5b7a-4040-b9d4-e312c7db424e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976289059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
976289059
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1462369118
Short name T1049
Test name
Test status
Simulation time 29595397 ps
CPU time 0.73 seconds
Started May 14 01:23:12 PM PDT 24
Finished May 14 01:23:15 PM PDT 24
Peak memory 204004 kb
Host smart-3f9cf0a2-0bf8-41d9-a975-187cd03ed1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462369118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
462369118
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1158280813
Short name T123
Test name
Test status
Simulation time 124308088 ps
CPU time 2.08 seconds
Started May 14 01:23:10 PM PDT 24
Finished May 14 01:23:14 PM PDT 24
Peak memory 215816 kb
Host smart-3fa03a60-b26f-4479-af07-045a6f155cc3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158280813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1158280813
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1500093528
Short name T995
Test name
Test status
Simulation time 53299696 ps
CPU time 0.66 seconds
Started May 14 01:23:13 PM PDT 24
Finished May 14 01:23:15 PM PDT 24
Peak memory 203844 kb
Host smart-31903584-4ace-441d-b490-ab3cab3b28c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500093528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1500093528
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2596186642
Short name T1027
Test name
Test status
Simulation time 45882658 ps
CPU time 2.88 seconds
Started May 14 01:23:12 PM PDT 24
Finished May 14 01:23:17 PM PDT 24
Peak memory 215992 kb
Host smart-7e6c2868-4bd1-41f9-a648-5e0051c77be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596186642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2596186642
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2333396397
Short name T110
Test name
Test status
Simulation time 157242245 ps
CPU time 2.18 seconds
Started May 14 01:23:11 PM PDT 24
Finished May 14 01:23:16 PM PDT 24
Peak memory 215928 kb
Host smart-257019f6-1b02-411d-a566-9732af309d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333396397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
333396397
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2792642372
Short name T256
Test name
Test status
Simulation time 587254541 ps
CPU time 7.44 seconds
Started May 14 01:23:19 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 215856 kb
Host smart-e6340691-2bd0-48ba-90aa-18fd77a29d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792642372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2792642372
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.890564042
Short name T1075
Test name
Test status
Simulation time 15672790 ps
CPU time 0.76 seconds
Started May 14 01:23:35 PM PDT 24
Finished May 14 01:23:39 PM PDT 24
Peak memory 203996 kb
Host smart-4506d0ff-16f6-400e-b33e-d354751e7760
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890564042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.890564042
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2684909971
Short name T1080
Test name
Test status
Simulation time 49440656 ps
CPU time 0.78 seconds
Started May 14 01:23:34 PM PDT 24
Finished May 14 01:23:38 PM PDT 24
Peak memory 203992 kb
Host smart-f981a860-c9df-4f9a-8a80-08577745fa56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684909971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2684909971
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3453260945
Short name T1034
Test name
Test status
Simulation time 14367945 ps
CPU time 0.75 seconds
Started May 14 01:23:37 PM PDT 24
Finished May 14 01:23:41 PM PDT 24
Peak memory 203992 kb
Host smart-6cdbde06-e783-4179-8ed0-bb029d32a347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453260945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3453260945
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2172589431
Short name T1083
Test name
Test status
Simulation time 64561828 ps
CPU time 0.77 seconds
Started May 14 01:23:37 PM PDT 24
Finished May 14 01:23:40 PM PDT 24
Peak memory 204000 kb
Host smart-7819bb9e-b926-4ec0-a385-f4386b99adf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172589431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2172589431
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1050928087
Short name T1012
Test name
Test status
Simulation time 16932850 ps
CPU time 0.77 seconds
Started May 14 01:23:36 PM PDT 24
Finished May 14 01:23:40 PM PDT 24
Peak memory 204000 kb
Host smart-6b473eca-b8ec-436f-8c4c-8898748ea574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050928087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1050928087
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1903914606
Short name T1021
Test name
Test status
Simulation time 11764935 ps
CPU time 0.72 seconds
Started May 14 01:23:35 PM PDT 24
Finished May 14 01:23:38 PM PDT 24
Peak memory 204264 kb
Host smart-02a0bedd-4582-4779-b9f1-cd9342276fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903914606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1903914606
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2493013468
Short name T1013
Test name
Test status
Simulation time 76017824 ps
CPU time 0.75 seconds
Started May 14 01:23:36 PM PDT 24
Finished May 14 01:23:40 PM PDT 24
Peak memory 203976 kb
Host smart-a442da1b-5bc1-4a4d-adf2-de0980cce819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493013468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2493013468
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.192003548
Short name T1040
Test name
Test status
Simulation time 15355950 ps
CPU time 0.8 seconds
Started May 14 01:23:37 PM PDT 24
Finished May 14 01:23:40 PM PDT 24
Peak memory 203936 kb
Host smart-dd807408-9443-4bc4-873f-4b1724ed6521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192003548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.192003548
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2878707037
Short name T1067
Test name
Test status
Simulation time 27225479 ps
CPU time 0.71 seconds
Started May 14 01:23:42 PM PDT 24
Finished May 14 01:23:44 PM PDT 24
Peak memory 203944 kb
Host smart-c81a8ddd-c8a9-45c2-8e6e-6f12ca3c8783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878707037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2878707037
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2865812901
Short name T1010
Test name
Test status
Simulation time 12874402 ps
CPU time 0.76 seconds
Started May 14 01:23:39 PM PDT 24
Finished May 14 01:23:42 PM PDT 24
Peak memory 204244 kb
Host smart-1b56ac1e-fb74-4a90-9e2b-d915d423a157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865812901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2865812901
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.298980253
Short name T1073
Test name
Test status
Simulation time 180573011 ps
CPU time 2.52 seconds
Started May 14 01:23:12 PM PDT 24
Finished May 14 01:23:17 PM PDT 24
Peak memory 216860 kb
Host smart-a298a354-fac9-4c0e-8366-013e8baba09b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298980253 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.298980253
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3452286116
Short name T1011
Test name
Test status
Simulation time 103399210 ps
CPU time 1.85 seconds
Started May 14 01:23:09 PM PDT 24
Finished May 14 01:23:13 PM PDT 24
Peak memory 215736 kb
Host smart-00ef4357-d24a-43dc-a087-111e712dc774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452286116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
452286116
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1461068415
Short name T1015
Test name
Test status
Simulation time 48508029 ps
CPU time 0.7 seconds
Started May 14 01:23:19 PM PDT 24
Finished May 14 01:23:20 PM PDT 24
Peak memory 203916 kb
Host smart-11bcf30f-efb0-4e9d-a54d-6ef7e960d8e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461068415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
461068415
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4030533579
Short name T1016
Test name
Test status
Simulation time 401804063 ps
CPU time 4.32 seconds
Started May 14 01:23:12 PM PDT 24
Finished May 14 01:23:19 PM PDT 24
Peak memory 215796 kb
Host smart-b40ddbc8-bee5-403f-aa2f-209fca8cec32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030533579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4030533579
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4224086695
Short name T108
Test name
Test status
Simulation time 343718736 ps
CPU time 2.89 seconds
Started May 14 01:23:09 PM PDT 24
Finished May 14 01:23:15 PM PDT 24
Peak memory 215840 kb
Host smart-cb0503f7-aaa6-4a79-a83b-2992667f44e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224086695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
224086695
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1661691560
Short name T249
Test name
Test status
Simulation time 336391274 ps
CPU time 8.08 seconds
Started May 14 01:23:10 PM PDT 24
Finished May 14 01:23:20 PM PDT 24
Peak memory 215916 kb
Host smart-f5add237-4ef8-4944-81bd-b357707f63a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661691560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1661691560
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3810575700
Short name T1000
Test name
Test status
Simulation time 350964159 ps
CPU time 3.43 seconds
Started May 14 01:23:14 PM PDT 24
Finished May 14 01:23:19 PM PDT 24
Peak memory 218456 kb
Host smart-21741fd8-bbbb-41ca-b0ff-592ed87d1c32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810575700 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3810575700
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4160974262
Short name T1084
Test name
Test status
Simulation time 168996288 ps
CPU time 2.69 seconds
Started May 14 01:23:10 PM PDT 24
Finished May 14 01:23:15 PM PDT 24
Peak memory 215796 kb
Host smart-8dd8641d-abf8-4a82-b196-95046c5b9f0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160974262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
160974262
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4293214383
Short name T988
Test name
Test status
Simulation time 13796234 ps
CPU time 0.8 seconds
Started May 14 01:23:11 PM PDT 24
Finished May 14 01:23:14 PM PDT 24
Peak memory 203964 kb
Host smart-0719e4a1-04c3-4498-8c64-277ddbaa7193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293214383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
293214383
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1984567782
Short name T1028
Test name
Test status
Simulation time 171406953 ps
CPU time 2.8 seconds
Started May 14 01:23:13 PM PDT 24
Finished May 14 01:23:18 PM PDT 24
Peak memory 215744 kb
Host smart-9bdd3969-47c7-4e7c-887f-cdfb7c8e645a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984567782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1984567782
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4153540488
Short name T1033
Test name
Test status
Simulation time 52482792 ps
CPU time 1.5 seconds
Started May 14 01:23:10 PM PDT 24
Finished May 14 01:23:14 PM PDT 24
Peak memory 215800 kb
Host smart-808c935a-b1a4-46c0-bb4b-85f989999e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153540488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
153540488
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2306394697
Short name T1088
Test name
Test status
Simulation time 4165031355 ps
CPU time 24.33 seconds
Started May 14 01:23:10 PM PDT 24
Finished May 14 01:23:37 PM PDT 24
Peak memory 216108 kb
Host smart-ad4ad0ec-ac85-42e8-a630-f775a8073ace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306394697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2306394697
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3387758548
Short name T998
Test name
Test status
Simulation time 96692118 ps
CPU time 1.65 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 215844 kb
Host smart-aaa9c183-fcf8-4fa2-95f8-c86f323fd0c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387758548 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3387758548
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.303512703
Short name T1069
Test name
Test status
Simulation time 18299026 ps
CPU time 1.27 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 215564 kb
Host smart-1190152c-88b1-4448-8845-d8392a33dd76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303512703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.303512703
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3334289929
Short name T1026
Test name
Test status
Simulation time 30798823 ps
CPU time 0.73 seconds
Started May 14 01:23:21 PM PDT 24
Finished May 14 01:23:23 PM PDT 24
Peak memory 204216 kb
Host smart-cf9f0103-9ae2-422b-b31b-514433362361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334289929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
334289929
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3998875985
Short name T1003
Test name
Test status
Simulation time 163741190 ps
CPU time 1.57 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 215712 kb
Host smart-177eec77-b97b-4967-ab29-b846bb0b34a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998875985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3998875985
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.725831079
Short name T97
Test name
Test status
Simulation time 77186953 ps
CPU time 4.75 seconds
Started May 14 01:23:11 PM PDT 24
Finished May 14 01:23:18 PM PDT 24
Peak memory 215984 kb
Host smart-a0685bea-b503-4a0e-8c0e-91dee9cc4c83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725831079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.725831079
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.512128817
Short name T1066
Test name
Test status
Simulation time 12472579801 ps
CPU time 14.42 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:39 PM PDT 24
Peak memory 215852 kb
Host smart-d09edd8d-a1db-49e7-b374-4d2bf461b0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512128817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.512128817
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1527172422
Short name T1037
Test name
Test status
Simulation time 44426038 ps
CPU time 3.03 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 217556 kb
Host smart-0cbf8b7d-dd02-47bd-9e91-56f01778d8d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527172422 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1527172422
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3626666258
Short name T1071
Test name
Test status
Simulation time 310962196 ps
CPU time 2.07 seconds
Started May 14 01:23:27 PM PDT 24
Finished May 14 01:23:32 PM PDT 24
Peak memory 207528 kb
Host smart-6e7070e8-467c-4426-ad03-d5d611f07794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626666258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
626666258
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3070115329
Short name T1006
Test name
Test status
Simulation time 40790266 ps
CPU time 0.77 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:28 PM PDT 24
Peak memory 203984 kb
Host smart-ade98326-4a6e-4790-b9f5-edc8027a0d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070115329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
070115329
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.464948934
Short name T1082
Test name
Test status
Simulation time 25435564 ps
CPU time 1.85 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 207592 kb
Host smart-19b47831-694b-4c70-9e18-c82350374d91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464948934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.464948934
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.279578390
Short name T1009
Test name
Test status
Simulation time 62380095 ps
CPU time 1.68 seconds
Started May 14 01:23:20 PM PDT 24
Finished May 14 01:23:23 PM PDT 24
Peak memory 215916 kb
Host smart-f754ed79-8734-45cc-96d9-026731d0ad71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279578390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.279578390
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2599039588
Short name T253
Test name
Test status
Simulation time 426102453 ps
CPU time 6.54 seconds
Started May 14 01:23:21 PM PDT 24
Finished May 14 01:23:29 PM PDT 24
Peak memory 216052 kb
Host smart-2a9ea51a-22a4-4cb7-ad39-77f758e1ab27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599039588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2599039588
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.693225460
Short name T99
Test name
Test status
Simulation time 112998574 ps
CPU time 3.9 seconds
Started May 14 01:23:23 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 217764 kb
Host smart-ee9fd834-5548-4faf-b4ff-560462293f1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693225460 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.693225460
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3146592824
Short name T1091
Test name
Test status
Simulation time 22804321 ps
CPU time 1.33 seconds
Started May 14 01:23:26 PM PDT 24
Finished May 14 01:23:30 PM PDT 24
Peak memory 215768 kb
Host smart-a5487e54-3869-4d49-958f-bd293e1b054c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146592824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
146592824
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.15463803
Short name T984
Test name
Test status
Simulation time 19995163 ps
CPU time 0.75 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:27 PM PDT 24
Peak memory 204196 kb
Host smart-8020e312-0431-4c7e-a024-f257757171f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15463803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.15463803
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2946549195
Short name T152
Test name
Test status
Simulation time 757185680 ps
CPU time 4.72 seconds
Started May 14 01:23:24 PM PDT 24
Finished May 14 01:23:31 PM PDT 24
Peak memory 215764 kb
Host smart-0764f3e3-9b79-4f29-b221-f92455f30196
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946549195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2946549195
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.931100978
Short name T1057
Test name
Test status
Simulation time 819298050 ps
CPU time 14.09 seconds
Started May 14 01:23:22 PM PDT 24
Finished May 14 01:23:39 PM PDT 24
Peak memory 216460 kb
Host smart-dd3a354d-7e9a-493e-a8c0-b68f10cfb724
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931100978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.931100978
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.65210098
Short name T462
Test name
Test status
Simulation time 16130847 ps
CPU time 0.7 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:47 PM PDT 24
Peak memory 204736 kb
Host smart-9533681e-f807-41e6-af42-56a45779ba7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65210098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.65210098
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4246045706
Short name T434
Test name
Test status
Simulation time 938393956 ps
CPU time 10.71 seconds
Started May 14 01:04:37 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 234864 kb
Host smart-6f443429-1118-4a73-a0f7-ec9c82b58779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246045706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4246045706
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.123262848
Short name T523
Test name
Test status
Simulation time 71460685 ps
CPU time 0.76 seconds
Started May 14 01:04:30 PM PDT 24
Finished May 14 01:04:31 PM PDT 24
Peak memory 206392 kb
Host smart-07b12c7e-1141-45bc-ac0c-4d09f5307a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123262848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.123262848
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.4085525064
Short name T807
Test name
Test status
Simulation time 15639473087 ps
CPU time 73.95 seconds
Started May 14 01:04:43 PM PDT 24
Finished May 14 01:05:59 PM PDT 24
Peak memory 249476 kb
Host smart-6fa4242b-246e-42cc-9a1a-0116d82abbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085525064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.4085525064
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1485893523
Short name T438
Test name
Test status
Simulation time 7806014337 ps
CPU time 30.61 seconds
Started May 14 01:04:43 PM PDT 24
Finished May 14 01:05:17 PM PDT 24
Peak memory 224680 kb
Host smart-55a03281-e680-4bce-8f66-d2db7e302998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485893523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1485893523
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.507247823
Short name T510
Test name
Test status
Simulation time 1717076298 ps
CPU time 23.51 seconds
Started May 14 01:04:42 PM PDT 24
Finished May 14 01:05:06 PM PDT 24
Peak memory 217464 kb
Host smart-73a07b31-a8d5-4da5-a66e-5312c7ebca3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507247823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
507247823
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4237489936
Short name T307
Test name
Test status
Simulation time 4696819001 ps
CPU time 22.33 seconds
Started May 14 01:04:47 PM PDT 24
Finished May 14 01:05:12 PM PDT 24
Peak memory 241000 kb
Host smart-04e181fc-1585-4b4a-bd5e-92745874ca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237489936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4237489936
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3814830964
Short name T413
Test name
Test status
Simulation time 55673576 ps
CPU time 2.5 seconds
Started May 14 01:04:34 PM PDT 24
Finished May 14 01:04:38 PM PDT 24
Peak memory 221512 kb
Host smart-a3e89b0c-a070-43b8-b072-c260667884ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814830964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3814830964
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.328473603
Short name T184
Test name
Test status
Simulation time 622757583 ps
CPU time 5.08 seconds
Started May 14 01:04:35 PM PDT 24
Finished May 14 01:04:41 PM PDT 24
Peak memory 232684 kb
Host smart-535711a5-1d1f-4221-a9bd-266ac10192cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328473603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.328473603
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1177200702
Short name T512
Test name
Test status
Simulation time 15440249 ps
CPU time 1.01 seconds
Started May 14 01:04:38 PM PDT 24
Finished May 14 01:04:40 PM PDT 24
Peak memory 216728 kb
Host smart-5117a83f-10fb-4d35-bd6a-5ceea0a9cbbf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177200702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1177200702
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.611870720
Short name T243
Test name
Test status
Simulation time 218439438 ps
CPU time 3.21 seconds
Started May 14 01:04:35 PM PDT 24
Finished May 14 01:04:40 PM PDT 24
Peak memory 218692 kb
Host smart-73cc40d6-ada7-4879-a92c-96227acb9fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611870720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
611870720
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.908338208
Short name T743
Test name
Test status
Simulation time 106929317 ps
CPU time 2.72 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:04:37 PM PDT 24
Peak memory 232668 kb
Host smart-485865f8-ce98-4d33-8bb3-5a0cd4f40e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908338208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.908338208
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1500883546
Short name T610
Test name
Test status
Simulation time 473007711 ps
CPU time 6.29 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:53 PM PDT 24
Peak memory 222756 kb
Host smart-b0717391-8abb-4a4a-8ea2-4ad0161de196
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1500883546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1500883546
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1801404051
Short name T66
Test name
Test status
Simulation time 122376146 ps
CPU time 1.1 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:47 PM PDT 24
Peak memory 235120 kb
Host smart-1bad0a67-3e6d-4b70-94d0-05e3773e2bcf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801404051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1801404051
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1070220229
Short name T485
Test name
Test status
Simulation time 13199735867 ps
CPU time 118.29 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:06:45 PM PDT 24
Peak memory 252516 kb
Host smart-e71cb9ad-d4b5-4085-96a3-8cc60f13e650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070220229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1070220229
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.886927185
Short name T552
Test name
Test status
Simulation time 2586783819 ps
CPU time 22.81 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:04:57 PM PDT 24
Peak memory 216584 kb
Host smart-1f28ad4c-34ca-4683-8b4d-efa413f1f333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886927185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.886927185
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3369441785
Short name T858
Test name
Test status
Simulation time 12417228 ps
CPU time 0.76 seconds
Started May 14 01:04:32 PM PDT 24
Finished May 14 01:04:35 PM PDT 24
Peak memory 205472 kb
Host smart-f78a3742-133c-49df-977a-d0a771477600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369441785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3369441785
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2040210164
Short name T907
Test name
Test status
Simulation time 60123264 ps
CPU time 1.04 seconds
Started May 14 01:04:37 PM PDT 24
Finished May 14 01:04:39 PM PDT 24
Peak memory 216176 kb
Host smart-537f49c0-7ca4-400f-b10e-04971efe1c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040210164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2040210164
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1682574032
Short name T415
Test name
Test status
Simulation time 26496200 ps
CPU time 0.81 seconds
Started May 14 01:04:33 PM PDT 24
Finished May 14 01:04:36 PM PDT 24
Peak memory 205844 kb
Host smart-23daec0c-b29d-4b90-8a5e-e91e5ec859e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682574032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1682574032
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.175203798
Short name T613
Test name
Test status
Simulation time 9338388213 ps
CPU time 9.74 seconds
Started May 14 01:04:34 PM PDT 24
Finished May 14 01:04:46 PM PDT 24
Peak memory 225680 kb
Host smart-4bd7ca0f-a49d-46df-ab09-4c9669987fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175203798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.175203798
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3017435246
Short name T541
Test name
Test status
Simulation time 37381294 ps
CPU time 0.72 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:48 PM PDT 24
Peak memory 205304 kb
Host smart-9cb0636a-bcae-4ba1-a289-e503a5cd6d0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017435246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
017435246
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.982647143
Short name T200
Test name
Test status
Simulation time 36517767 ps
CPU time 2.55 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 232636 kb
Host smart-dafdb2a2-1e91-426d-8565-7bebc9bf3b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982647143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.982647143
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2533915421
Short name T700
Test name
Test status
Simulation time 43091782 ps
CPU time 0.75 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:48 PM PDT 24
Peak memory 206768 kb
Host smart-21f4b936-d77f-4b30-891f-1dd4e76e7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533915421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2533915421
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2770525503
Short name T239
Test name
Test status
Simulation time 14005085983 ps
CPU time 72.03 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:06:00 PM PDT 24
Peak memory 237368 kb
Host smart-70fc5949-135f-4d1f-b5b7-bb12dfe212d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770525503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2770525503
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1849611680
Short name T227
Test name
Test status
Simulation time 1453702512 ps
CPU time 30.43 seconds
Started May 14 01:04:49 PM PDT 24
Finished May 14 01:05:20 PM PDT 24
Peak memory 240976 kb
Host smart-6773958a-1e5e-464d-91fb-421fe881ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849611680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1849611680
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3852385004
Short name T750
Test name
Test status
Simulation time 47207077688 ps
CPU time 203.16 seconds
Started May 14 01:04:43 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 240228 kb
Host smart-4f38b03a-2178-41ca-8f2f-27432bb4c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852385004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3852385004
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3926992806
Short name T544
Test name
Test status
Simulation time 119709999 ps
CPU time 3.52 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:51 PM PDT 24
Peak memory 229524 kb
Host smart-1f4d17b9-026a-4005-9d16-4b6b59ba65e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926992806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3926992806
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2816861998
Short name T782
Test name
Test status
Simulation time 670904140 ps
CPU time 4.72 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:51 PM PDT 24
Peak memory 218688 kb
Host smart-ebcd010b-1bfb-4976-9553-ce91df050865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816861998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2816861998
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.224166711
Short name T953
Test name
Test status
Simulation time 1365585639 ps
CPU time 13.16 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:05:00 PM PDT 24
Peak memory 236060 kb
Host smart-07c88e3f-dc14-4d78-b795-493130169d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224166711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.224166711
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2353491630
Short name T561
Test name
Test status
Simulation time 26872467 ps
CPU time 1.06 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:48 PM PDT 24
Peak memory 217888 kb
Host smart-053df864-425a-4147-9b7c-e3295d0453fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353491630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2353491630
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4220654389
Short name T294
Test name
Test status
Simulation time 7848295684 ps
CPU time 17.8 seconds
Started May 14 01:04:49 PM PDT 24
Finished May 14 01:05:08 PM PDT 24
Peak memory 218500 kb
Host smart-8317ca18-a004-44b5-b423-5366022cea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220654389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4220654389
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3192419703
Short name T292
Test name
Test status
Simulation time 4906457687 ps
CPU time 5.13 seconds
Started May 14 01:04:43 PM PDT 24
Finished May 14 01:04:51 PM PDT 24
Peak memory 219064 kb
Host smart-7e4739c5-7ad4-4e74-9d4c-df723c149b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192419703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3192419703
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3459159477
Short name T582
Test name
Test status
Simulation time 8690815204 ps
CPU time 12.34 seconds
Started May 14 01:04:47 PM PDT 24
Finished May 14 01:05:02 PM PDT 24
Peak memory 223184 kb
Host smart-a1b2375a-8773-472c-9adb-5d76bcc9df96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459159477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3459159477
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1539720520
Short name T63
Test name
Test status
Simulation time 78749752 ps
CPU time 0.95 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:49 PM PDT 24
Peak memory 234328 kb
Host smart-3c636ece-6add-4ec5-8f84-56866910187a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539720520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1539720520
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1645569674
Short name T866
Test name
Test status
Simulation time 120127335914 ps
CPU time 288 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:09:35 PM PDT 24
Peak memory 249380 kb
Host smart-51723597-9fcd-40d6-81b2-d0ae5c99b073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645569674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1645569674
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2151090635
Short name T465
Test name
Test status
Simulation time 5458030025 ps
CPU time 35.3 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:05:21 PM PDT 24
Peak memory 220216 kb
Host smart-bca59ccb-2911-4307-bd16-fc800bfdd177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151090635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2151090635
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1981658748
Short name T847
Test name
Test status
Simulation time 4869917636 ps
CPU time 5.72 seconds
Started May 14 01:04:43 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 216508 kb
Host smart-78816026-60d9-4518-a64c-05239ee5194d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981658748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1981658748
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.327637659
Short name T389
Test name
Test status
Simulation time 258935551 ps
CPU time 1.04 seconds
Started May 14 01:04:42 PM PDT 24
Finished May 14 01:04:44 PM PDT 24
Peak memory 206884 kb
Host smart-df142296-6c25-48e2-aadf-f79ed38e0d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327637659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.327637659
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3618270066
Short name T798
Test name
Test status
Simulation time 40406393 ps
CPU time 0.73 seconds
Started May 14 01:04:43 PM PDT 24
Finished May 14 01:04:45 PM PDT 24
Peak memory 205816 kb
Host smart-41b00155-0f2d-445f-a013-b64a786bcf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618270066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3618270066
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2872554031
Short name T653
Test name
Test status
Simulation time 13794554425 ps
CPU time 43.22 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:05:30 PM PDT 24
Peak memory 238852 kb
Host smart-68f9842d-0438-4281-a3a0-dca117f7eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872554031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2872554031
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3223599441
Short name T793
Test name
Test status
Simulation time 78008756 ps
CPU time 0.74 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:42 PM PDT 24
Peak memory 205296 kb
Host smart-c197f4e1-db53-4e30-89d5-f2e42e71fcc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223599441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3223599441
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3207776066
Short name T756
Test name
Test status
Simulation time 16381772 ps
CPU time 0.74 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:48 PM PDT 24
Peak memory 205388 kb
Host smart-d7d4a44b-5b3e-418a-8abf-b2d9ea7ec4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207776066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3207776066
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1582487032
Short name T479
Test name
Test status
Simulation time 11569970 ps
CPU time 0.74 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:49 PM PDT 24
Peak memory 215860 kb
Host smart-6f8ed499-2b33-4e21-af5b-ddd99bec7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582487032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1582487032
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.453541595
Short name T238
Test name
Test status
Simulation time 53782719397 ps
CPU time 103.19 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:07:27 PM PDT 24
Peak memory 255728 kb
Host smart-0ce87e92-e035-4212-8235-fca08f683a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453541595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.453541595
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2920553581
Short name T883
Test name
Test status
Simulation time 767846819 ps
CPU time 11.99 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:59 PM PDT 24
Peak memory 235916 kb
Host smart-526b0031-1cd8-464b-a790-dbbafd2f2bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920553581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2920553581
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2940728644
Short name T818
Test name
Test status
Simulation time 417461076 ps
CPU time 3.86 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 233760 kb
Host smart-45757076-82be-441f-aba7-3943e1e86907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940728644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2940728644
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3068377655
Short name T205
Test name
Test status
Simulation time 309745339 ps
CPU time 9.91 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:57 PM PDT 24
Peak memory 227272 kb
Host smart-06220b85-4db5-4166-bba8-edc577c532ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068377655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3068377655
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.542547347
Short name T748
Test name
Test status
Simulation time 3328907090 ps
CPU time 6.59 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:05:59 PM PDT 24
Peak memory 233824 kb
Host smart-d3f72904-f001-4aa5-8383-7680c675d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542547347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.542547347
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4155477138
Short name T801
Test name
Test status
Simulation time 1658275703 ps
CPU time 5.39 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:05:54 PM PDT 24
Peak memory 233640 kb
Host smart-0b168967-eb40-4ba9-bf8f-57ff9b3c76c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155477138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4155477138
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1461002757
Short name T533
Test name
Test status
Simulation time 6701445811 ps
CPU time 20.68 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:06:08 PM PDT 24
Peak memory 219296 kb
Host smart-b50bdf9b-e3ba-444f-9b40-2e998ee1f3c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1461002757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1461002757
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1671413983
Short name T785
Test name
Test status
Simulation time 47222128026 ps
CPU time 208.06 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:09:14 PM PDT 24
Peak memory 255756 kb
Host smart-50f4291e-f78a-4547-85f1-b49fe382329e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671413983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1671413983
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1032718635
Short name T378
Test name
Test status
Simulation time 1555334502 ps
CPU time 14.82 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:06:01 PM PDT 24
Peak memory 216276 kb
Host smart-f9a979b0-64e4-4b48-990d-31dca345e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032718635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1032718635
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.967374952
Short name T659
Test name
Test status
Simulation time 8632061153 ps
CPU time 6.64 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:05:50 PM PDT 24
Peak memory 216420 kb
Host smart-8e9422e2-712d-4947-a056-ce3cc843edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967374952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.967374952
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.428447571
Short name T885
Test name
Test status
Simulation time 169152391 ps
CPU time 2.84 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:49 PM PDT 24
Peak memory 216396 kb
Host smart-339b8c18-504e-4667-866c-b0c8492889bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428447571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.428447571
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4284088937
Short name T435
Test name
Test status
Simulation time 78604382 ps
CPU time 0.83 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:05:44 PM PDT 24
Peak memory 205788 kb
Host smart-bd38a646-49a5-4caa-8f11-0033f3e4c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284088937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4284088937
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1633387480
Short name T193
Test name
Test status
Simulation time 419231643 ps
CPU time 4.69 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 233864 kb
Host smart-02976347-0ab2-4692-ab13-88df4e839677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633387480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1633387480
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1504164599
Short name T594
Test name
Test status
Simulation time 67909693 ps
CPU time 0.7 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:05:44 PM PDT 24
Peak memory 205292 kb
Host smart-dc5214ba-3fb9-4dbb-9816-10b69a06277a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504164599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1504164599
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1948248940
Short name T715
Test name
Test status
Simulation time 762525806 ps
CPU time 9.5 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:05:59 PM PDT 24
Peak memory 218628 kb
Host smart-ba5ce4c4-9080-4606-93ed-8987e6ddfccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948248940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1948248940
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2843485120
Short name T916
Test name
Test status
Simulation time 52140484 ps
CPU time 0.83 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 205328 kb
Host smart-747f1202-56db-4214-a3b9-f50fcf649d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843485120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2843485120
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1161980119
Short name T191
Test name
Test status
Simulation time 10368346986 ps
CPU time 45.81 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:06:38 PM PDT 24
Peak memory 236392 kb
Host smart-00a57462-3391-4bdb-baac-4d15369975ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161980119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1161980119
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.378225831
Short name T229
Test name
Test status
Simulation time 581127713894 ps
CPU time 552.91 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:15:05 PM PDT 24
Peak memory 257500 kb
Host smart-a378070c-99ca-4772-9ada-1c39095fbf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378225831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.378225831
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.221872152
Short name T578
Test name
Test status
Simulation time 184606474 ps
CPU time 6.04 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:50 PM PDT 24
Peak memory 232796 kb
Host smart-d6a874f2-1d13-4fa4-a333-837a79ecb928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221872152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.221872152
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1354432041
Short name T289
Test name
Test status
Simulation time 1586529603 ps
CPU time 6.35 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:54 PM PDT 24
Peak memory 233328 kb
Host smart-cedc01bf-4dcb-47c1-9b0a-02b6acd9bf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354432041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1354432041
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3553981168
Short name T954
Test name
Test status
Simulation time 3335280673 ps
CPU time 24.89 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:06:13 PM PDT 24
Peak memory 239604 kb
Host smart-454d1051-f2ff-4652-8018-873924b72085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553981168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3553981168
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1968592482
Short name T428
Test name
Test status
Simulation time 37912839 ps
CPU time 1.01 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 217916 kb
Host smart-debf16df-f9c9-496b-a103-16bd1be0ec2c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968592482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1968592482
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3564154906
Short name T660
Test name
Test status
Simulation time 4177290845 ps
CPU time 12.54 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:06:00 PM PDT 24
Peak memory 218132 kb
Host smart-fed7143f-86bc-4c4a-95fb-b3d69575ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564154906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3564154906
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1117543551
Short name T283
Test name
Test status
Simulation time 112046560 ps
CPU time 2.44 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:48 PM PDT 24
Peak memory 232788 kb
Host smart-68ea8ffa-bb93-44df-88ef-3d86a4eae2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117543551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1117543551
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3095118264
Short name T644
Test name
Test status
Simulation time 678121736 ps
CPU time 3.65 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:05:55 PM PDT 24
Peak memory 219208 kb
Host smart-79df05d9-ca92-46db-a989-48f04bcd2b8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095118264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3095118264
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3703237258
Short name T440
Test name
Test status
Simulation time 364177674 ps
CPU time 2.39 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:05:55 PM PDT 24
Peak memory 216356 kb
Host smart-71075e4c-be03-4d33-86d5-1e4f8bc39484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703237258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3703237258
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2490582758
Short name T522
Test name
Test status
Simulation time 661832811 ps
CPU time 4.49 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:05:48 PM PDT 24
Peak memory 216372 kb
Host smart-cd474583-63c0-4aed-b5ff-8c594bdede6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490582758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2490582758
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3455189876
Short name T786
Test name
Test status
Simulation time 61515065 ps
CPU time 0.78 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:05:51 PM PDT 24
Peak memory 205844 kb
Host smart-eb2bb722-f1c4-4a69-88d3-6f9b3c822cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455189876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3455189876
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1595102792
Short name T399
Test name
Test status
Simulation time 77076017 ps
CPU time 1.08 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 206080 kb
Host smart-ec7ffe76-a3e4-427a-afa6-4098f4e334c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595102792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1595102792
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2691876963
Short name T198
Test name
Test status
Simulation time 1940539881 ps
CPU time 6.79 seconds
Started May 14 01:05:39 PM PDT 24
Finished May 14 01:06:00 PM PDT 24
Peak memory 232700 kb
Host smart-7284dfc0-7188-4cbe-8991-07db2bf076a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691876963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2691876963
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2417387453
Short name T401
Test name
Test status
Simulation time 2526860686 ps
CPU time 5.94 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:54 PM PDT 24
Peak memory 234372 kb
Host smart-cdfd7744-e637-408b-9b33-42321ca40c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417387453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2417387453
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1491556321
Short name T714
Test name
Test status
Simulation time 33165576 ps
CPU time 0.82 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:05:50 PM PDT 24
Peak memory 206520 kb
Host smart-4dc10d13-ec70-4bea-b7a9-f01e223f83aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491556321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1491556321
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1835455647
Short name T946
Test name
Test status
Simulation time 39278512084 ps
CPU time 101.05 seconds
Started May 14 01:05:39 PM PDT 24
Finished May 14 01:07:36 PM PDT 24
Peak memory 254424 kb
Host smart-14d05255-ded8-4864-ac3e-ef9504426bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835455647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1835455647
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2630394082
Short name T49
Test name
Test status
Simulation time 22299999107 ps
CPU time 155.03 seconds
Started May 14 01:05:42 PM PDT 24
Finished May 14 01:08:36 PM PDT 24
Peak memory 235836 kb
Host smart-ab048f4c-2e9e-4647-994b-bd1e8ee1acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630394082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2630394082
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2458341825
Short name T371
Test name
Test status
Simulation time 159480725 ps
CPU time 4.64 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 232752 kb
Host smart-41ccc7e2-3854-4768-a1db-d402b2e580c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458341825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2458341825
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1342009358
Short name T581
Test name
Test status
Simulation time 1060499444 ps
CPU time 8.45 seconds
Started May 14 01:05:39 PM PDT 24
Finished May 14 01:06:01 PM PDT 24
Peak memory 233840 kb
Host smart-e52f1d20-c63d-40ef-9757-4a5adee2d562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342009358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1342009358
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3616308764
Short name T400
Test name
Test status
Simulation time 46133460 ps
CPU time 0.97 seconds
Started May 14 01:05:39 PM PDT 24
Finished May 14 01:05:54 PM PDT 24
Peak memory 217920 kb
Host smart-eb65c06c-67fb-4b3a-9d46-21a60410f12e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616308764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3616308764
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3839465854
Short name T587
Test name
Test status
Simulation time 29435760359 ps
CPU time 21.26 seconds
Started May 14 01:05:43 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 224644 kb
Host smart-fd8ad65c-735b-4fe4-b054-d4c6665e6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839465854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3839465854
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2363471131
Short name T643
Test name
Test status
Simulation time 585458623 ps
CPU time 5.06 seconds
Started May 14 01:05:39 PM PDT 24
Finished May 14 01:05:58 PM PDT 24
Peak memory 219532 kb
Host smart-8cec2d86-69bc-4726-8c32-7c34fe5bfbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363471131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2363471131
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.740225417
Short name T904
Test name
Test status
Simulation time 282267108 ps
CPU time 3.7 seconds
Started May 14 01:05:43 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 222940 kb
Host smart-642e179e-d0dc-47b2-8bb3-8e1e81ef3921
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=740225417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.740225417
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.353916305
Short name T799
Test name
Test status
Simulation time 185546829 ps
CPU time 1.02 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:05:53 PM PDT 24
Peak memory 215184 kb
Host smart-f552f5d2-123f-4a26-b137-d0818508a515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353916305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.353916305
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1777503855
Short name T881
Test name
Test status
Simulation time 30860347276 ps
CPU time 35.67 seconds
Started May 14 01:05:41 PM PDT 24
Finished May 14 01:06:34 PM PDT 24
Peak memory 216492 kb
Host smart-3e96d0ae-964f-44a0-ad9b-95b35f78c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777503855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1777503855
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3651277744
Short name T664
Test name
Test status
Simulation time 30976713430 ps
CPU time 21.92 seconds
Started May 14 01:05:36 PM PDT 24
Finished May 14 01:06:09 PM PDT 24
Peak memory 216516 kb
Host smart-9cebee52-3e1b-4a7c-9161-8716cf7712c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651277744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3651277744
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2915663219
Short name T848
Test name
Test status
Simulation time 39421853 ps
CPU time 1.12 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:47 PM PDT 24
Peak memory 216448 kb
Host smart-d4798fd6-9dd4-4e65-a3ef-55ffffa64904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915663219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2915663219
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.164975254
Short name T820
Test name
Test status
Simulation time 158447920 ps
CPU time 0.8 seconds
Started May 14 01:05:41 PM PDT 24
Finished May 14 01:05:58 PM PDT 24
Peak memory 205840 kb
Host smart-c558a46d-f151-45a5-a825-981ad89d26f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164975254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.164975254
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2046117762
Short name T956
Test name
Test status
Simulation time 13740671553 ps
CPU time 18.45 seconds
Started May 14 01:05:41 PM PDT 24
Finished May 14 01:06:17 PM PDT 24
Peak memory 229848 kb
Host smart-050016f8-2799-4174-8439-bbf10913516b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046117762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2046117762
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1796523149
Short name T478
Test name
Test status
Simulation time 30121090 ps
CPU time 0.71 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 205648 kb
Host smart-6f8f19b3-b612-46dd-977a-ceac13caef93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796523149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1796523149
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.251143514
Short name T598
Test name
Test status
Simulation time 1155652852 ps
CPU time 10.18 seconds
Started May 14 01:05:48 PM PDT 24
Finished May 14 01:06:23 PM PDT 24
Peak memory 219668 kb
Host smart-c31294d0-8231-4bd1-8023-5fc5ce9d7bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251143514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.251143514
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1426156642
Short name T35
Test name
Test status
Simulation time 8382913492 ps
CPU time 85.99 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 262348 kb
Host smart-07aaa603-930d-4ec3-87a1-332985329142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426156642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1426156642
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.341981197
Short name T144
Test name
Test status
Simulation time 49205320823 ps
CPU time 221.27 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:09:48 PM PDT 24
Peak memory 249408 kb
Host smart-f30c61d6-a511-4f41-bab2-64dc342c55d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341981197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.341981197
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3402653537
Short name T54
Test name
Test status
Simulation time 61687767808 ps
CPU time 563.38 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 262960 kb
Host smart-f5b145cf-ede4-48e0-9f70-2f20812857fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402653537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3402653537
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3315227384
Short name T354
Test name
Test status
Simulation time 1082407622 ps
CPU time 8.71 seconds
Started May 14 01:05:43 PM PDT 24
Finished May 14 01:06:11 PM PDT 24
Peak memory 218420 kb
Host smart-aa9b4767-cb5d-4984-963d-17dd9f4e1c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315227384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3315227384
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1224650687
Short name T592
Test name
Test status
Simulation time 213692910 ps
CPU time 2.51 seconds
Started May 14 01:05:51 PM PDT 24
Finished May 14 01:06:22 PM PDT 24
Peak memory 221460 kb
Host smart-a11def88-9b6e-458f-bf06-1018ae2c5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224650687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1224650687
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2135137999
Short name T387
Test name
Test status
Simulation time 114699586 ps
CPU time 0.98 seconds
Started May 14 01:05:47 PM PDT 24
Finished May 14 01:06:11 PM PDT 24
Peak memory 217944 kb
Host smart-09cfaa63-25d6-46a5-8a3c-6cd7e149c1b1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135137999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2135137999
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.566371314
Short name T851
Test name
Test status
Simulation time 1896838668 ps
CPU time 12.32 seconds
Started May 14 01:05:48 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 230396 kb
Host smart-fa469bf0-af9e-42db-80e8-09ce4fb39f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566371314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.566371314
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.257446974
Short name T903
Test name
Test status
Simulation time 10991022785 ps
CPU time 12.05 seconds
Started May 14 01:05:51 PM PDT 24
Finished May 14 01:06:32 PM PDT 24
Peak memory 238884 kb
Host smart-ccd634f7-51ca-475f-b947-affb5406fabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257446974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.257446974
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1049881243
Short name T488
Test name
Test status
Simulation time 430723987 ps
CPU time 3.9 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:11 PM PDT 24
Peak memory 222280 kb
Host smart-bf5f85d0-8dd1-4d5b-ba88-ea5db4eb2c9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1049881243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1049881243
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1474881117
Short name T773
Test name
Test status
Simulation time 49786366 ps
CPU time 1.14 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 206752 kb
Host smart-30c517fd-dccc-4cdf-a78f-186cdfeb361b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474881117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1474881117
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4179984420
Short name T665
Test name
Test status
Simulation time 21953071524 ps
CPU time 23.97 seconds
Started May 14 01:05:48 PM PDT 24
Finished May 14 01:06:37 PM PDT 24
Peak memory 216456 kb
Host smart-f76e26eb-2e8e-433b-9493-b388518f359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179984420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4179984420
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1626169923
Short name T933
Test name
Test status
Simulation time 4086822517 ps
CPU time 13.19 seconds
Started May 14 01:05:43 PM PDT 24
Finished May 14 01:06:17 PM PDT 24
Peak memory 216492 kb
Host smart-4750b117-2c94-437b-b12e-f2f6d6d6126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626169923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1626169923
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.209698364
Short name T572
Test name
Test status
Simulation time 24166723 ps
CPU time 0.9 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:08 PM PDT 24
Peak memory 206976 kb
Host smart-3bbc7d39-32f7-432d-9a50-575fc12196e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209698364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.209698364
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3141695835
Short name T830
Test name
Test status
Simulation time 45547177 ps
CPU time 0.83 seconds
Started May 14 01:05:51 PM PDT 24
Finished May 14 01:06:19 PM PDT 24
Peak memory 206212 kb
Host smart-b07a767b-ec4b-48bb-8c91-66c776b43298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141695835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3141695835
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1934202818
Short name T837
Test name
Test status
Simulation time 331235920 ps
CPU time 5.41 seconds
Started May 14 01:05:50 PM PDT 24
Finished May 14 01:06:22 PM PDT 24
Peak memory 230308 kb
Host smart-ddf5f8fb-3fb5-4764-86ef-5ab0716b708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934202818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1934202818
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4010138458
Short name T432
Test name
Test status
Simulation time 17121339 ps
CPU time 0.77 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 204688 kb
Host smart-d572ab3b-24e4-4487-a6ef-d76c791a72fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010138458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4010138458
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1904934420
Short name T353
Test name
Test status
Simulation time 290278959 ps
CPU time 3.32 seconds
Started May 14 01:05:50 PM PDT 24
Finished May 14 01:06:20 PM PDT 24
Peak memory 234416 kb
Host smart-7b442eb3-0922-4ac9-a941-9030234153e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904934420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1904934420
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4103475192
Short name T516
Test name
Test status
Simulation time 32632649 ps
CPU time 0.77 seconds
Started May 14 01:05:46 PM PDT 24
Finished May 14 01:06:08 PM PDT 24
Peak memory 205444 kb
Host smart-3ac5d25a-de9e-416d-b306-e937231202a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103475192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4103475192
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3517720161
Short name T679
Test name
Test status
Simulation time 160929955161 ps
CPU time 323.14 seconds
Started May 14 01:05:46 PM PDT 24
Finished May 14 01:11:32 PM PDT 24
Peak memory 249336 kb
Host smart-26a3c0a5-7abc-4e9f-be87-a56f5c70b699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517720161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3517720161
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1722209539
Short name T237
Test name
Test status
Simulation time 6618761243 ps
CPU time 89.12 seconds
Started May 14 01:05:48 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 252560 kb
Host smart-b00d4d99-ae76-4e80-91dd-8b65cde542bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722209539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1722209539
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2578174078
Short name T16
Test name
Test status
Simulation time 31740653476 ps
CPU time 45.14 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:51 PM PDT 24
Peak memory 240748 kb
Host smart-599e111f-6c6f-405d-8f2b-81711a19cebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578174078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2578174078
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.504109765
Short name T683
Test name
Test status
Simulation time 1923551537 ps
CPU time 26.11 seconds
Started May 14 01:05:51 PM PDT 24
Finished May 14 01:06:44 PM PDT 24
Peak memory 239600 kb
Host smart-ced7aa80-507c-4266-a915-d44969dfed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504109765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.504109765
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3517645473
Short name T204
Test name
Test status
Simulation time 1116824591 ps
CPU time 5.72 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:12 PM PDT 24
Peak memory 233864 kb
Host smart-1a0b6418-179a-4590-8201-369a723bb4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517645473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3517645473
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4064195835
Short name T475
Test name
Test status
Simulation time 17097892866 ps
CPU time 75.91 seconds
Started May 14 01:05:50 PM PDT 24
Finished May 14 01:07:33 PM PDT 24
Peak memory 231712 kb
Host smart-6b0db38a-b94b-42b6-afac-410bb679443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064195835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4064195835
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4006191690
Short name T24
Test name
Test status
Simulation time 43039378 ps
CPU time 1.06 seconds
Started May 14 01:05:52 PM PDT 24
Finished May 14 01:06:22 PM PDT 24
Peak memory 216752 kb
Host smart-22fbfe2d-b94c-4326-b2d9-2344609ea1f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006191690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4006191690
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1768908115
Short name T293
Test name
Test status
Simulation time 1232902901 ps
CPU time 4.98 seconds
Started May 14 01:05:47 PM PDT 24
Finished May 14 01:06:15 PM PDT 24
Peak memory 216656 kb
Host smart-4d1f874e-fedc-4f46-9b50-f35214e8cf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768908115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1768908115
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1601522606
Short name T192
Test name
Test status
Simulation time 914962080 ps
CPU time 7.72 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:14 PM PDT 24
Peak memory 237276 kb
Host smart-558c8324-32fa-4bfe-94e1-250095572668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601522606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1601522606
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3147885608
Short name T865
Test name
Test status
Simulation time 3643070938 ps
CPU time 10.57 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:06:34 PM PDT 24
Peak memory 222664 kb
Host smart-cac3cc4d-6305-4fb6-b444-9a7d98f4cd41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3147885608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3147885608
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1172886772
Short name T337
Test name
Test status
Simulation time 536650406 ps
CPU time 8.4 seconds
Started May 14 01:05:51 PM PDT 24
Finished May 14 01:06:27 PM PDT 24
Peak memory 216348 kb
Host smart-71799723-c136-4675-8322-0a4fee57581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172886772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1172886772
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.60811993
Short name T870
Test name
Test status
Simulation time 1234754332 ps
CPU time 5.62 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:06:29 PM PDT 24
Peak memory 216484 kb
Host smart-486c2b53-2cc4-4799-9bdc-4385a367f4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60811993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.60811993
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.418668716
Short name T641
Test name
Test status
Simulation time 143486473 ps
CPU time 1.04 seconds
Started May 14 01:05:45 PM PDT 24
Finished May 14 01:06:08 PM PDT 24
Peak memory 207956 kb
Host smart-9ceddc29-33ff-4217-aa7e-6071c50c655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418668716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.418668716
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1987201624
Short name T666
Test name
Test status
Simulation time 27704814 ps
CPU time 0.75 seconds
Started May 14 01:05:47 PM PDT 24
Finished May 14 01:06:11 PM PDT 24
Peak memory 206056 kb
Host smart-11b9ec57-3210-4c55-8279-e303b7391ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987201624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1987201624
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1301548804
Short name T573
Test name
Test status
Simulation time 9560478101 ps
CPU time 9.52 seconds
Started May 14 01:05:48 PM PDT 24
Finished May 14 01:06:22 PM PDT 24
Peak memory 233736 kb
Host smart-4d542d7d-0771-4b0a-ab70-dcaea5ea5a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301548804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1301548804
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1513459336
Short name T368
Test name
Test status
Simulation time 13562904 ps
CPU time 0.75 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:28 PM PDT 24
Peak memory 205356 kb
Host smart-e06e2dea-e999-415b-891a-550da82d82d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513459336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1513459336
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2010386976
Short name T958
Test name
Test status
Simulation time 497146378 ps
CPU time 2.08 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:06:25 PM PDT 24
Peak memory 218464 kb
Host smart-33913cf9-f5e4-4c21-b693-88fd11d52e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010386976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2010386976
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3618500699
Short name T971
Test name
Test status
Simulation time 66570913 ps
CPU time 0.77 seconds
Started May 14 01:05:46 PM PDT 24
Finished May 14 01:06:10 PM PDT 24
Peak memory 206748 kb
Host smart-ac54c05e-40c7-40f1-a7c8-392c655eb86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618500699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3618500699
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3786239745
Short name T938
Test name
Test status
Simulation time 44946955039 ps
CPU time 226.19 seconds
Started May 14 01:06:00 PM PDT 24
Finished May 14 01:10:22 PM PDT 24
Peak memory 259252 kb
Host smart-ca24365b-5fe1-439c-933d-0e64a1710f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786239745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3786239745
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2086637274
Short name T575
Test name
Test status
Simulation time 352251966 ps
CPU time 6.85 seconds
Started May 14 01:06:01 PM PDT 24
Finished May 14 01:06:43 PM PDT 24
Peak memory 224568 kb
Host smart-25ff48b0-2b7d-4d6d-a424-1d3f0f606fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086637274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2086637274
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1464807011
Short name T868
Test name
Test status
Simulation time 6081264213 ps
CPU time 15.98 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 219748 kb
Host smart-9c1bb60c-c60b-4e67-ad79-7e776f204f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464807011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1464807011
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2153183937
Short name T284
Test name
Test status
Simulation time 532868235 ps
CPU time 2.97 seconds
Started May 14 01:05:58 PM PDT 24
Finished May 14 01:06:35 PM PDT 24
Peak memory 218416 kb
Host smart-b273aaf5-6721-4594-ab32-6389aa6f8883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153183937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2153183937
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3391592458
Short name T425
Test name
Test status
Simulation time 53374688 ps
CPU time 1.05 seconds
Started May 14 01:05:53 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 216716 kb
Host smart-684c4921-3463-4ca6-9f24-8328bc1a8093
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391592458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3391592458
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2096015674
Short name T777
Test name
Test status
Simulation time 441075559 ps
CPU time 2.5 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:29 PM PDT 24
Peak memory 232760 kb
Host smart-2901473e-7e50-409a-a149-e9280dee06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096015674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2096015674
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.708550909
Short name T755
Test name
Test status
Simulation time 2899313627 ps
CPU time 14.57 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:42 PM PDT 24
Peak memory 237564 kb
Host smart-29a04d66-55f8-4de7-894f-940658514583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708550909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.708550909
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1384250567
Short name T146
Test name
Test status
Simulation time 240320256 ps
CPU time 4.21 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:35 PM PDT 24
Peak memory 219156 kb
Host smart-f0af2570-9b22-4f21-a758-d33b81311608
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1384250567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1384250567
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.875660499
Short name T458
Test name
Test status
Simulation time 123089782 ps
CPU time 0.91 seconds
Started May 14 01:05:58 PM PDT 24
Finished May 14 01:06:33 PM PDT 24
Peak memory 206820 kb
Host smart-17ede1f2-8d04-4c9b-889e-9b0071f83a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875660499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.875660499
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3071923947
Short name T341
Test name
Test status
Simulation time 7150881269 ps
CPU time 24.98 seconds
Started May 14 01:05:54 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 216536 kb
Host smart-70d35a79-c175-48b6-b2cc-581b8970b344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071923947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3071923947
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1140793527
Short name T741
Test name
Test status
Simulation time 19765759 ps
CPU time 0.69 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:28 PM PDT 24
Peak memory 205560 kb
Host smart-05794878-b5ff-41c4-abfd-89e04b73ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140793527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1140793527
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1676520167
Short name T437
Test name
Test status
Simulation time 23013550 ps
CPU time 0.97 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:30 PM PDT 24
Peak memory 207184 kb
Host smart-f09d9325-9dab-4f83-aae4-96d94614b925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676520167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1676520167
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1856629222
Short name T559
Test name
Test status
Simulation time 42890400 ps
CPU time 0.75 seconds
Started May 14 01:05:54 PM PDT 24
Finished May 14 01:06:24 PM PDT 24
Peak memory 205792 kb
Host smart-7f6e2b46-6a55-43f2-bb64-192068d739e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856629222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1856629222
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1394420032
Short name T114
Test name
Test status
Simulation time 2037750338 ps
CPU time 11.81 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:37 PM PDT 24
Peak memory 240292 kb
Host smart-d0c80ca5-28cd-4f9a-a8a8-91793a9d1321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394420032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1394420032
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3011913207
Short name T571
Test name
Test status
Simulation time 22769010 ps
CPU time 0.69 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:31 PM PDT 24
Peak memory 204716 kb
Host smart-b3fa7e31-d777-43b7-a31a-8d7d9b70bbbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011913207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3011913207
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3792761247
Short name T160
Test name
Test status
Simulation time 113238694 ps
CPU time 2.41 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:31 PM PDT 24
Peak memory 233164 kb
Host smart-f34092ef-d992-4723-95dc-be666fff5f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792761247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3792761247
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2069377204
Short name T923
Test name
Test status
Simulation time 54130283 ps
CPU time 0.75 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:28 PM PDT 24
Peak memory 206448 kb
Host smart-82301cdf-9aef-46d0-8b6f-a3b8cd22d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069377204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2069377204
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1235738994
Short name T276
Test name
Test status
Simulation time 1761989640 ps
CPU time 5.88 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:36 PM PDT 24
Peak memory 224408 kb
Host smart-02812f14-f8af-4b3a-8533-0a2bcdd3e9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235738994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1235738994
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1934805245
Short name T67
Test name
Test status
Simulation time 7763842117 ps
CPU time 59.64 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:07:27 PM PDT 24
Peak memory 241160 kb
Host smart-29378a1b-93f0-4e8c-8f16-67f41ef8aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934805245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1934805245
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1590759901
Short name T681
Test name
Test status
Simulation time 1868728626 ps
CPU time 41.09 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 239712 kb
Host smart-c602a43d-ff82-47c9-89fe-117c118740c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590759901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1590759901
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1184631643
Short name T310
Test name
Test status
Simulation time 1713520152 ps
CPU time 13.3 seconds
Started May 14 01:05:54 PM PDT 24
Finished May 14 01:06:38 PM PDT 24
Peak memory 232708 kb
Host smart-f4a5f708-785c-470d-afe6-b4be73eb63e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184631643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1184631643
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1621683493
Short name T417
Test name
Test status
Simulation time 206389965 ps
CPU time 3.96 seconds
Started May 14 01:05:58 PM PDT 24
Finished May 14 01:06:36 PM PDT 24
Peak memory 234328 kb
Host smart-2a4b5ca4-493c-498d-912d-07f30abaa4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621683493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1621683493
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3291776520
Short name T261
Test name
Test status
Simulation time 2457459723 ps
CPU time 26.97 seconds
Started May 14 01:05:59 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 235076 kb
Host smart-9dfd7ef2-b595-45bf-95cb-95ff733c6995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291776520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3291776520
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1766570998
Short name T599
Test name
Test status
Simulation time 139449119 ps
CPU time 1 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:31 PM PDT 24
Peak memory 217976 kb
Host smart-cc48c653-b224-4712-9bd6-53b7dda9db1b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766570998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1766570998
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1251259963
Short name T295
Test name
Test status
Simulation time 1524049383 ps
CPU time 11.56 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:38 PM PDT 24
Peak memory 238116 kb
Host smart-0338ee7a-4054-4304-8b29-b759453ef660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251259963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1251259963
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1871935762
Short name T752
Test name
Test status
Simulation time 56924492 ps
CPU time 2.37 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:31 PM PDT 24
Peak memory 221280 kb
Host smart-17f25d1c-0ffc-4c83-9be9-573f93dc5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871935762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1871935762
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.64107282
Short name T148
Test name
Test status
Simulation time 1824337838 ps
CPU time 14.66 seconds
Started May 14 01:05:59 PM PDT 24
Finished May 14 01:06:49 PM PDT 24
Peak memory 220152 kb
Host smart-cf4ad590-4c8d-452e-89a6-5ca2bf4ea130
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=64107282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.64107282
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1559703404
Short name T316
Test name
Test status
Simulation time 5963271131 ps
CPU time 12.02 seconds
Started May 14 01:06:00 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 216488 kb
Host smart-a695f8cf-e03b-4997-9019-7babab03df8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559703404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1559703404
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3573063761
Short name T332
Test name
Test status
Simulation time 1317378455 ps
CPU time 7.09 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:36 PM PDT 24
Peak memory 216400 kb
Host smart-f17a15b1-66a9-4206-a0c2-80a6d9ee6001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573063761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3573063761
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2465788778
Short name T336
Test name
Test status
Simulation time 47256610 ps
CPU time 1.78 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:31 PM PDT 24
Peak memory 216316 kb
Host smart-964a63cf-16e2-4493-b037-40cad3e20469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465788778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2465788778
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.606445158
Short name T504
Test name
Test status
Simulation time 84527817 ps
CPU time 0.79 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:32 PM PDT 24
Peak memory 205808 kb
Host smart-d9156dca-2ef3-49af-a03b-4f45823980eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606445158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.606445158
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3131056329
Short name T604
Test name
Test status
Simulation time 133434017 ps
CPU time 2.5 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:29 PM PDT 24
Peak memory 218676 kb
Host smart-36f81583-2760-4d1a-8204-aba4b4da10d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131056329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3131056329
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.468955430
Short name T577
Test name
Test status
Simulation time 37377756 ps
CPU time 0.67 seconds
Started May 14 01:06:12 PM PDT 24
Finished May 14 01:06:49 PM PDT 24
Peak memory 205364 kb
Host smart-996c366f-796b-4b9c-8dfb-9c09587ca771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468955430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.468955430
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.367953837
Short name T550
Test name
Test status
Simulation time 732923248 ps
CPU time 2.8 seconds
Started May 14 01:05:54 PM PDT 24
Finished May 14 01:06:27 PM PDT 24
Peak memory 233724 kb
Host smart-74834e47-0dc7-4b0c-804a-075a67328e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367953837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.367953837
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3471973136
Short name T57
Test name
Test status
Simulation time 17225584 ps
CPU time 0.75 seconds
Started May 14 01:05:58 PM PDT 24
Finished May 14 01:06:33 PM PDT 24
Peak memory 205440 kb
Host smart-b2d4b48d-c53a-4011-882b-985e2dc0e662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471973136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3471973136
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.260677793
Short name T219
Test name
Test status
Simulation time 16378180793 ps
CPU time 59.97 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 249392 kb
Host smart-5b6cf697-39d4-4b5f-a111-1fc5b3496e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260677793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.260677793
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2029677361
Short name T619
Test name
Test status
Simulation time 4891290787 ps
CPU time 12.81 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 217688 kb
Host smart-d7c5be31-ce81-4e6d-a763-5502476b2b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029677361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2029677361
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4086513366
Short name T672
Test name
Test status
Simulation time 2694269037 ps
CPU time 14.06 seconds
Started May 14 01:06:03 PM PDT 24
Finished May 14 01:06:54 PM PDT 24
Peak memory 217596 kb
Host smart-aa0af54f-494d-4450-8b4c-71519b57d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086513366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4086513366
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3355322516
Short name T306
Test name
Test status
Simulation time 512068936 ps
CPU time 13.69 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:55 PM PDT 24
Peak memory 240948 kb
Host smart-84e8c36b-fe9e-4ccc-8ae4-04ead37a423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355322516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3355322516
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1407502613
Short name T921
Test name
Test status
Simulation time 1400059770 ps
CPU time 5.55 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:35 PM PDT 24
Peak memory 237408 kb
Host smart-111afe6d-d6d4-47e3-9acf-6b4aaada48df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407502613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1407502613
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.595759197
Short name T426
Test name
Test status
Simulation time 102761895 ps
CPU time 2.05 seconds
Started May 14 01:05:55 PM PDT 24
Finished May 14 01:06:28 PM PDT 24
Peak memory 216120 kb
Host smart-6bdae1f0-4440-43bb-9e24-d7b108d3beb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595759197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.595759197
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2601214304
Short name T502
Test name
Test status
Simulation time 34666035 ps
CPU time 1.08 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:30 PM PDT 24
Peak memory 216696 kb
Host smart-6e9fb10f-059d-473c-9b9d-92e200d810de
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601214304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2601214304
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3980811997
Short name T694
Test name
Test status
Simulation time 114686658 ps
CPU time 2.93 seconds
Started May 14 01:05:59 PM PDT 24
Finished May 14 01:06:38 PM PDT 24
Peak memory 218536 kb
Host smart-40f81b8a-97ce-4ead-8e94-cd3f550ea4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980811997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3980811997
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3471595884
Short name T835
Test name
Test status
Simulation time 2279977951 ps
CPU time 8.23 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:40 PM PDT 24
Peak memory 229560 kb
Host smart-7594894b-d504-4001-b78f-d336d84c7dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471595884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3471595884
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.727330955
Short name T136
Test name
Test status
Simulation time 3780707980 ps
CPU time 9.87 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 222300 kb
Host smart-cc8dcbda-a28c-46c1-954a-72b8984c3aa1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=727330955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.727330955
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2260606613
Short name T158
Test name
Test status
Simulation time 39713990 ps
CPU time 0.91 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:42 PM PDT 24
Peak memory 206560 kb
Host smart-cfa55fc2-59a0-4429-a36e-3efb481c7242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260606613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2260606613
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.110363155
Short name T461
Test name
Test status
Simulation time 827130326 ps
CPU time 8.02 seconds
Started May 14 01:05:57 PM PDT 24
Finished May 14 01:06:38 PM PDT 24
Peak memory 216332 kb
Host smart-1d9f21b2-5c2e-4dc5-9068-2d6634ebd3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110363155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.110363155
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3195858090
Short name T728
Test name
Test status
Simulation time 18543735 ps
CPU time 0.68 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:30 PM PDT 24
Peak memory 205508 kb
Host smart-fbda03c6-5f96-4154-8aa5-a3687c13309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195858090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3195858090
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2274932752
Short name T845
Test name
Test status
Simulation time 176547407 ps
CPU time 1.24 seconds
Started May 14 01:05:54 PM PDT 24
Finished May 14 01:06:26 PM PDT 24
Peak memory 216344 kb
Host smart-53316574-9822-4f02-96bc-5cde89dfa663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274932752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2274932752
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_upload.2603661821
Short name T952
Test name
Test status
Simulation time 11154037304 ps
CPU time 10.26 seconds
Started May 14 01:05:56 PM PDT 24
Finished May 14 01:06:39 PM PDT 24
Peak memory 218516 kb
Host smart-9322aff4-9490-4fb0-94ed-cad06c3bb510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603661821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2603661821
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.796372996
Short name T464
Test name
Test status
Simulation time 41649861 ps
CPU time 0.71 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:06:45 PM PDT 24
Peak memory 205288 kb
Host smart-b4c3553a-2635-49dd-ab27-95cc1086edf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796372996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.796372996
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.143151154
Short name T854
Test name
Test status
Simulation time 3276723410 ps
CPU time 4.41 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 218792 kb
Host smart-a0aa96d0-17f5-422b-a8e4-f9cda9bd9710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143151154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.143151154
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2833462260
Short name T655
Test name
Test status
Simulation time 35191415 ps
CPU time 0.78 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 206420 kb
Host smart-85d2805d-9247-485d-a5a5-d7501c5347c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833462260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2833462260
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3517105595
Short name T44
Test name
Test status
Simulation time 3444087876 ps
CPU time 41.24 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:07:26 PM PDT 24
Peak memory 239776 kb
Host smart-6025f1e3-1cdd-4b73-b0ab-8662734061e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517105595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3517105595
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1944548018
Short name T89
Test name
Test status
Simulation time 1260904319 ps
CPU time 33.07 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 249188 kb
Host smart-bebbfc43-40cd-4b4c-8682-7277ed9d8716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944548018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1944548018
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2374252867
Short name T540
Test name
Test status
Simulation time 6269358110 ps
CPU time 37.17 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:07:19 PM PDT 24
Peak memory 236736 kb
Host smart-77249625-1e39-43f7-8b88-0fff24fc4c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374252867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2374252867
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3672588823
Short name T941
Test name
Test status
Simulation time 5990677768 ps
CPU time 19.69 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:07:04 PM PDT 24
Peak memory 235456 kb
Host smart-6a5f3fa6-8764-4f48-ae56-ff3b82469a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672588823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3672588823
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.134960682
Short name T265
Test name
Test status
Simulation time 62235872 ps
CPU time 2.99 seconds
Started May 14 01:06:03 PM PDT 24
Finished May 14 01:06:43 PM PDT 24
Peak memory 234724 kb
Host smart-e456f8ec-f6d1-4678-b221-1266eb2f6a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134960682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.134960682
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1874095767
Short name T185
Test name
Test status
Simulation time 179275711752 ps
CPU time 92.68 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:08:18 PM PDT 24
Peak memory 249992 kb
Host smart-000e2f31-9b68-490e-993f-5b21c47ac7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874095767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1874095767
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.585424620
Short name T678
Test name
Test status
Simulation time 105922270 ps
CPU time 1 seconds
Started May 14 01:06:03 PM PDT 24
Finished May 14 01:06:41 PM PDT 24
Peak memory 218196 kb
Host smart-feb28240-c17a-4484-b2c7-ff6f3eba6cb6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585424620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.585424620
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.89723867
Short name T106
Test name
Test status
Simulation time 279652022 ps
CPU time 3.41 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 233288 kb
Host smart-11213bb4-accb-420b-85eb-637a6371c687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89723867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.89723867
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.286704876
Short name T376
Test name
Test status
Simulation time 423738256 ps
CPU time 6.46 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:47 PM PDT 24
Peak memory 223028 kb
Host smart-bfb81f62-5f61-4f5a-9c48-a0a29a94e8be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=286704876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.286704876
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1094108300
Short name T947
Test name
Test status
Simulation time 129062921 ps
CPU time 1.18 seconds
Started May 14 01:06:08 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 206964 kb
Host smart-c3730c96-c6a1-4e8d-bad2-9edff146fd2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094108300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1094108300
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1636810815
Short name T638
Test name
Test status
Simulation time 9557580659 ps
CPU time 47.65 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 216540 kb
Host smart-617c375c-edec-4296-8753-119bd1bcdc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636810815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1636810815
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2756809597
Short name T754
Test name
Test status
Simulation time 4328242228 ps
CPU time 4.77 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 216288 kb
Host smart-ee378459-6fb3-408d-91a3-36e07d460325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756809597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2756809597
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3621400420
Short name T535
Test name
Test status
Simulation time 145889488 ps
CPU time 1.23 seconds
Started May 14 01:06:03 PM PDT 24
Finished May 14 01:06:41 PM PDT 24
Peak memory 208116 kb
Host smart-76381d44-a6b3-4972-947c-5d60420e2b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621400420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3621400420
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2083707992
Short name T692
Test name
Test status
Simulation time 96019696 ps
CPU time 0.84 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:06:45 PM PDT 24
Peak memory 205752 kb
Host smart-0b0ec41a-b75f-4624-a3c6-34ecc694dbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083707992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2083707992
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3491233365
Short name T618
Test name
Test status
Simulation time 78244261841 ps
CPU time 15.09 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 234288 kb
Host smart-3802e889-9d01-45b7-8cca-3f54d48d8c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491233365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3491233365
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3121380659
Short name T690
Test name
Test status
Simulation time 55109809 ps
CPU time 0.7 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:06:47 PM PDT 24
Peak memory 205396 kb
Host smart-105b9732-5451-4088-8a9a-9a4163da0000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121380659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3121380659
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2975198551
Short name T360
Test name
Test status
Simulation time 141864850 ps
CPU time 3.18 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:44 PM PDT 24
Peak memory 219576 kb
Host smart-23e647cc-1b67-490c-aba5-feba4e71abf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975198551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2975198551
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2000871984
Short name T408
Test name
Test status
Simulation time 29494931 ps
CPU time 0.85 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:47 PM PDT 24
Peak memory 206456 kb
Host smart-b1430bd8-bedf-44a3-8145-7a8266347425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000871984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2000871984
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1234516791
Short name T203
Test name
Test status
Simulation time 89949999983 ps
CPU time 86.89 seconds
Started May 14 01:06:03 PM PDT 24
Finished May 14 01:08:07 PM PDT 24
Peak memory 249272 kb
Host smart-2ddb5135-ad85-4eab-86d6-88bdea429d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234516791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1234516791
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2735678381
Short name T188
Test name
Test status
Simulation time 13258892200 ps
CPU time 149.64 seconds
Started May 14 01:06:12 PM PDT 24
Finished May 14 01:09:18 PM PDT 24
Peak memory 249888 kb
Host smart-bf798d17-441a-48c3-aa0e-5000cb7834b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735678381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2735678381
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1477808939
Short name T671
Test name
Test status
Simulation time 6099718669 ps
CPU time 104.21 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:08:26 PM PDT 24
Peak memory 249440 kb
Host smart-2033a45a-07df-43db-9acf-12ce57badea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477808939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1477808939
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4003024132
Short name T827
Test name
Test status
Simulation time 843402290 ps
CPU time 3.75 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:06:50 PM PDT 24
Peak memory 232724 kb
Host smart-8e75d789-7327-495b-97b4-b1ed96edd028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003024132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4003024132
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2221122682
Short name T171
Test name
Test status
Simulation time 10520310243 ps
CPU time 16.11 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 220264 kb
Host smart-6427e919-a9d0-4797-8d06-7b8dedeafd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221122682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2221122682
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2426310569
Short name T934
Test name
Test status
Simulation time 996685859 ps
CPU time 11.34 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:06:54 PM PDT 24
Peak memory 238760 kb
Host smart-de31f5b6-0887-4d61-a9a2-6d5a3b8659d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426310569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2426310569
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.501199919
Short name T534
Test name
Test status
Simulation time 52654264 ps
CPU time 1 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:42 PM PDT 24
Peak memory 216756 kb
Host smart-fbda026f-8151-47bc-866c-73c25b6ca78e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501199919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.501199919
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4182119120
Short name T771
Test name
Test status
Simulation time 1482199670 ps
CPU time 3.02 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:45 PM PDT 24
Peak memory 224508 kb
Host smart-903e717a-d834-425e-acce-dee4f5a7406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182119120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4182119120
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2236965104
Short name T751
Test name
Test status
Simulation time 739304950 ps
CPU time 4.9 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 234936 kb
Host smart-891139a8-cd36-4ea9-803b-ab7a9fde11a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236965104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2236965104
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3309446274
Short name T419
Test name
Test status
Simulation time 101301768 ps
CPU time 3.77 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 222368 kb
Host smart-69517578-e72f-4308-baec-5fa3c77464ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3309446274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3309446274
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.154870030
Short name T932
Test name
Test status
Simulation time 1788096129 ps
CPU time 26.84 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:07:10 PM PDT 24
Peak memory 238884 kb
Host smart-ee30cdef-7bc8-4ac9-b831-06797f1d6c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154870030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.154870030
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3474717509
Short name T527
Test name
Test status
Simulation time 37084129694 ps
CPU time 21.81 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 216480 kb
Host smart-6b2180fa-928d-4681-821e-dafdd993e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474717509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3474717509
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2738732358
Short name T707
Test name
Test status
Simulation time 1137406558 ps
CPU time 6.89 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:06:51 PM PDT 24
Peak memory 216328 kb
Host smart-0862e122-8b49-419a-a0d5-50d6b60e9d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738732358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2738732358
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2544662883
Short name T351
Test name
Test status
Simulation time 23992674 ps
CPU time 0.96 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:43 PM PDT 24
Peak memory 207220 kb
Host smart-b91f85a8-40ff-477d-9420-9b0ce98ad7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544662883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2544662883
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2345540642
Short name T492
Test name
Test status
Simulation time 86535757 ps
CPU time 0.95 seconds
Started May 14 01:06:08 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 205752 kb
Host smart-2eb353cb-c4ab-44ab-a8e2-b798a96e88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345540642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2345540642
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.910902686
Short name T925
Test name
Test status
Simulation time 77562712 ps
CPU time 2.57 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 232776 kb
Host smart-0918cced-3f81-4236-87ae-efc3adf4cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910902686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.910902686
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3488181532
Short name T922
Test name
Test status
Simulation time 14288613 ps
CPU time 0.71 seconds
Started May 14 01:05:06 PM PDT 24
Finished May 14 01:05:08 PM PDT 24
Peak memory 205684 kb
Host smart-2967f135-0fbe-40ec-a928-4471133ad5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488181532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
488181532
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3261170355
Short name T281
Test name
Test status
Simulation time 763752340 ps
CPU time 6.61 seconds
Started May 14 01:04:42 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 219676 kb
Host smart-e86fc29b-3c4d-40b1-abe7-191fc8761f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261170355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3261170355
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3860045483
Short name T762
Test name
Test status
Simulation time 17236583 ps
CPU time 0.74 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:48 PM PDT 24
Peak memory 206716 kb
Host smart-c95d8318-4416-45e1-9c2c-777f59175f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860045483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3860045483
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.611089309
Short name T369
Test name
Test status
Simulation time 1016128422 ps
CPU time 7.66 seconds
Started May 14 01:04:55 PM PDT 24
Finished May 14 01:05:04 PM PDT 24
Peak memory 233844 kb
Host smart-684996f5-9ea5-4766-b103-bd65db7c6fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611089309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.611089309
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2959218736
Short name T539
Test name
Test status
Simulation time 2815677272 ps
CPU time 11.22 seconds
Started May 14 01:04:56 PM PDT 24
Finished May 14 01:05:10 PM PDT 24
Peak memory 224764 kb
Host smart-c13d1b0a-25a4-4d2f-bf05-1bc4e9070e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959218736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2959218736
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3832378667
Short name T226
Test name
Test status
Simulation time 212634000789 ps
CPU time 500.76 seconds
Started May 14 01:04:56 PM PDT 24
Finished May 14 01:13:19 PM PDT 24
Peak memory 252964 kb
Host smart-1cc13e0a-5622-4332-b619-a07805b809c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832378667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3832378667
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3539500799
Short name T40
Test name
Test status
Simulation time 177463664 ps
CPU time 3.54 seconds
Started May 14 01:04:46 PM PDT 24
Finished May 14 01:04:52 PM PDT 24
Peak memory 224552 kb
Host smart-0ba07551-a0cc-4ada-aa5d-0bfd56b8ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539500799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3539500799
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2751939075
Short name T624
Test name
Test status
Simulation time 14562166806 ps
CPU time 14.13 seconds
Started May 14 01:04:47 PM PDT 24
Finished May 14 01:05:03 PM PDT 24
Peak memory 218828 kb
Host smart-890d9945-6821-4ade-8033-3b031372129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751939075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2751939075
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2179768187
Short name T287
Test name
Test status
Simulation time 23353716060 ps
CPU time 49.23 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 226888 kb
Host smart-c0d6817c-2986-40ac-8b05-86968ce9f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179768187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2179768187
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.431979819
Short name T727
Test name
Test status
Simulation time 67305908 ps
CPU time 1.04 seconds
Started May 14 01:04:49 PM PDT 24
Finished May 14 01:04:51 PM PDT 24
Peak memory 216680 kb
Host smart-623145b0-442b-4c03-97d4-4fdb786e0cb3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431979819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.431979819
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.742416563
Short name T662
Test name
Test status
Simulation time 236721958 ps
CPU time 2.99 seconds
Started May 14 01:04:42 PM PDT 24
Finished May 14 01:04:46 PM PDT 24
Peak memory 216892 kb
Host smart-7370b0b1-4a3f-4834-be84-443b1a40d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742416563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
742416563
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1850853393
Short name T262
Test name
Test status
Simulation time 24145300087 ps
CPU time 36.8 seconds
Started May 14 01:04:48 PM PDT 24
Finished May 14 01:05:26 PM PDT 24
Peak memory 240980 kb
Host smart-19610e82-3a91-4cff-acd4-b290ff7429f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850853393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1850853393
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.943574029
Short name T603
Test name
Test status
Simulation time 410858791 ps
CPU time 7.53 seconds
Started May 14 01:04:56 PM PDT 24
Finished May 14 01:05:06 PM PDT 24
Peak memory 220288 kb
Host smart-e988b4e2-424f-4594-b248-dcd5e8a1c383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=943574029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.943574029
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.264196845
Short name T648
Test name
Test status
Simulation time 138658096310 ps
CPU time 353.34 seconds
Started May 14 01:04:55 PM PDT 24
Finished May 14 01:10:50 PM PDT 24
Peak memory 249384 kb
Host smart-70de0308-322d-4117-b08b-693670fe1d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264196845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.264196845
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2476946956
Short name T636
Test name
Test status
Simulation time 444080587 ps
CPU time 6.93 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:54 PM PDT 24
Peak memory 216520 kb
Host smart-2c4dd680-2174-460f-88b6-9a5ad897e34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476946956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2476946956
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2606050221
Short name T383
Test name
Test status
Simulation time 15901143664 ps
CPU time 9.99 seconds
Started May 14 01:04:47 PM PDT 24
Finished May 14 01:04:59 PM PDT 24
Peak memory 216436 kb
Host smart-442667b8-bcdf-4c13-ad95-390d4bcd7646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606050221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2606050221
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2813341299
Short name T431
Test name
Test status
Simulation time 174294207 ps
CPU time 1.36 seconds
Started May 14 01:04:45 PM PDT 24
Finished May 14 01:04:49 PM PDT 24
Peak memory 216376 kb
Host smart-dd472f98-b303-47eb-90ca-bbb48dba2995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813341299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2813341299
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.120721299
Short name T474
Test name
Test status
Simulation time 74381403 ps
CPU time 0.76 seconds
Started May 14 01:04:47 PM PDT 24
Finished May 14 01:04:50 PM PDT 24
Peak memory 205780 kb
Host smart-91256205-16aa-4269-8ade-c061e44fb9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120721299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.120721299
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3375425478
Short name T723
Test name
Test status
Simulation time 2978382450 ps
CPU time 10.36 seconds
Started May 14 01:04:44 PM PDT 24
Finished May 14 01:04:57 PM PDT 24
Peak memory 218904 kb
Host smart-9c143374-60f3-4228-acd8-62265970d505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375425478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3375425478
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3325715878
Short name T920
Test name
Test status
Simulation time 21949005 ps
CPU time 0.74 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 204760 kb
Host smart-c2509129-019d-44ae-aa1d-c5b867e245cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325715878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3325715878
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.383781775
Short name T285
Test name
Test status
Simulation time 1141874546 ps
CPU time 5.23 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:52 PM PDT 24
Peak memory 218772 kb
Host smart-29b20276-0f3f-4e61-af61-0391d2afd762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383781775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.383781775
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.472727387
Short name T642
Test name
Test status
Simulation time 20666406 ps
CPU time 0.79 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 206412 kb
Host smart-c523695e-c4e1-4dbf-ae6d-fde692fec013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472727387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.472727387
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4145083321
Short name T379
Test name
Test status
Simulation time 24572238 ps
CPU time 0.8 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:06:47 PM PDT 24
Peak memory 216120 kb
Host smart-30f0663f-d60e-4924-b8fb-6c74be158e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145083321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4145083321
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1332235680
Short name T374
Test name
Test status
Simulation time 72557987 ps
CPU time 0.84 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 217012 kb
Host smart-9f43a958-014c-404b-8e57-23fa35d3c938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332235680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1332235680
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1163561189
Short name T693
Test name
Test status
Simulation time 439761899 ps
CPU time 8.83 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:06:55 PM PDT 24
Peak memory 224480 kb
Host smart-8e07b06b-174e-47be-b68b-c1d0121f49fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163561189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1163561189
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2518676208
Short name T469
Test name
Test status
Simulation time 1210834562 ps
CPU time 7.2 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:54 PM PDT 24
Peak memory 217784 kb
Host smart-a1be3f76-3775-444f-ad18-a2c09ab74c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518676208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2518676208
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4152890466
Short name T667
Test name
Test status
Simulation time 1101051380 ps
CPU time 12.07 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:06:55 PM PDT 24
Peak memory 235804 kb
Host smart-29cba524-98f6-4173-a59c-2c970dbf2595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152890466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4152890466
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1795996548
Short name T217
Test name
Test status
Simulation time 909920290 ps
CPU time 7.21 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:49 PM PDT 24
Peak memory 218572 kb
Host smart-a0189e1c-7767-48ec-bb67-ea63ca39e98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795996548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1795996548
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1876910457
Short name T823
Test name
Test status
Simulation time 1036915579 ps
CPU time 2.77 seconds
Started May 14 01:06:08 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 233596 kb
Host smart-20023f62-a312-432f-ad95-01b5de131e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876910457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1876910457
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2503471026
Short name T796
Test name
Test status
Simulation time 271540247 ps
CPU time 4.72 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:46 PM PDT 24
Peak memory 220260 kb
Host smart-fdc2b889-2c1f-4ae4-8bdb-19adad862e6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503471026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2503471026
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.486704749
Short name T230
Test name
Test status
Simulation time 18853433403 ps
CPU time 248.75 seconds
Started May 14 01:06:11 PM PDT 24
Finished May 14 01:10:56 PM PDT 24
Peak memory 281192 kb
Host smart-625aeded-f036-4f68-be94-d0cdb7e0a63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486704749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.486704749
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3914451384
Short name T318
Test name
Test status
Simulation time 18705642669 ps
CPU time 45.01 seconds
Started May 14 01:06:08 PM PDT 24
Finished May 14 01:07:30 PM PDT 24
Peak memory 216460 kb
Host smart-27708e9a-5a93-446c-a2fd-a01fec66ae89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914451384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3914451384
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1690913748
Short name T402
Test name
Test status
Simulation time 2774546204 ps
CPU time 3.98 seconds
Started May 14 01:06:04 PM PDT 24
Finished May 14 01:06:45 PM PDT 24
Peak memory 216536 kb
Host smart-a0c716a6-70d4-4cc4-8a29-cd9db951e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690913748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1690913748
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2824020534
Short name T454
Test name
Test status
Simulation time 781214515 ps
CPU time 3.39 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 216296 kb
Host smart-2e81da95-f426-423d-9c92-c73496c140f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824020534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2824020534
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3566514947
Short name T392
Test name
Test status
Simulation time 39466501 ps
CPU time 0.81 seconds
Started May 14 01:06:11 PM PDT 24
Finished May 14 01:06:48 PM PDT 24
Peak memory 205836 kb
Host smart-b593d295-bfc6-490b-8000-c900e359382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566514947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3566514947
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3001441460
Short name T589
Test name
Test status
Simulation time 11544308106 ps
CPU time 19.65 seconds
Started May 14 01:06:09 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 233968 kb
Host smart-e65aaca4-465a-4e62-9425-d00fc2b6ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001441460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3001441460
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4092364227
Short name T457
Test name
Test status
Simulation time 55192687 ps
CPU time 0.71 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:06:51 PM PDT 24
Peak memory 205308 kb
Host smart-a6604811-90f8-452f-b6ea-e8557f924a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092364227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4092364227
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.366698140
Short name T682
Test name
Test status
Simulation time 25751769535 ps
CPU time 21.06 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 234432 kb
Host smart-ae51f455-7413-440c-9761-8148a01fe4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366698140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.366698140
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3966613775
Short name T51
Test name
Test status
Simulation time 33190366 ps
CPU time 0.79 seconds
Started May 14 01:06:06 PM PDT 24
Finished May 14 01:06:44 PM PDT 24
Peak memory 206476 kb
Host smart-0f691a85-035a-4802-9289-3e2c2902db49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966613775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3966613775
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3637566880
Short name T82
Test name
Test status
Simulation time 6918112951 ps
CPU time 112.17 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:08:42 PM PDT 24
Peak memory 253440 kb
Host smart-255cbe39-12d8-410c-a82f-aab1b394c67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637566880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3637566880
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.88366497
Short name T228
Test name
Test status
Simulation time 87498924228 ps
CPU time 169.09 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:09:40 PM PDT 24
Peak memory 235372 kb
Host smart-817f7194-3d46-4bef-b472-8444d5a5cfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88366497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.88366497
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.912791959
Short name T308
Test name
Test status
Simulation time 161910997 ps
CPU time 6.49 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 224464 kb
Host smart-8ac11b9e-f6b2-419e-a042-55d23d93c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912791959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.912791959
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2569646410
Short name T616
Test name
Test status
Simulation time 9406101398 ps
CPU time 20 seconds
Started May 14 01:06:17 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 233552 kb
Host smart-b282cdf0-bd51-455c-8531-ea13d7af67bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569646410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2569646410
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.309636550
Short name T658
Test name
Test status
Simulation time 1392611278 ps
CPU time 2.58 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:06:53 PM PDT 24
Peak memory 232776 kb
Host smart-74b8d36f-e9e3-4102-8ab2-044826d1f675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309636550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.309636550
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2950814782
Short name T453
Test name
Test status
Simulation time 24340090175 ps
CPU time 16.41 seconds
Started May 14 01:06:17 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 232356 kb
Host smart-00abe08f-8ff1-44a8-9808-0c67c29bf0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950814782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2950814782
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3466887264
Short name T900
Test name
Test status
Simulation time 1499987869 ps
CPU time 10.85 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:07:01 PM PDT 24
Peak memory 249144 kb
Host smart-3bacd56e-ab59-431b-b877-8ed5a30b791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466887264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3466887264
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1019290297
Short name T134
Test name
Test status
Simulation time 492725266 ps
CPU time 6.25 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 221684 kb
Host smart-f43f9de6-135a-4a26-b532-a5f75c8d4d3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1019290297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1019290297
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.865222064
Short name T585
Test name
Test status
Simulation time 59895697 ps
CPU time 1.2 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:06:51 PM PDT 24
Peak memory 207084 kb
Host smart-587c0636-d433-41a2-8f84-2879fbcff5eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865222064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.865222064
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2761519754
Short name T765
Test name
Test status
Simulation time 9312030508 ps
CPU time 27.31 seconds
Started May 14 01:06:08 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 216464 kb
Host smart-1dde9178-cccd-4ce9-a074-7a7c1226d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761519754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2761519754
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3179984611
Short name T867
Test name
Test status
Simulation time 2390988536 ps
CPU time 5.73 seconds
Started May 14 01:06:10 PM PDT 24
Finished May 14 01:06:52 PM PDT 24
Peak memory 216472 kb
Host smart-57b26b6e-eb98-4d3f-ab9f-b16adb653b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179984611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3179984611
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3215022837
Short name T509
Test name
Test status
Simulation time 58800585 ps
CPU time 1.41 seconds
Started May 14 01:06:05 PM PDT 24
Finished May 14 01:06:42 PM PDT 24
Peak memory 216364 kb
Host smart-1bce1466-d875-492f-a6bf-daae7ffea9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215022837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3215022837
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2766017744
Short name T864
Test name
Test status
Simulation time 63134965 ps
CPU time 0.79 seconds
Started May 14 01:06:07 PM PDT 24
Finished May 14 01:06:45 PM PDT 24
Peak memory 205768 kb
Host smart-6270c047-da5a-4da8-934f-c91ce7851cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766017744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2766017744
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.209764682
Short name T278
Test name
Test status
Simulation time 31593295 ps
CPU time 2.11 seconds
Started May 14 01:06:18 PM PDT 24
Finished May 14 01:06:54 PM PDT 24
Peak memory 216212 kb
Host smart-ea730922-14e5-4f57-b47c-bcd8637518f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209764682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.209764682
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1130618281
Short name T58
Test name
Test status
Simulation time 27081990 ps
CPU time 0.69 seconds
Started May 14 01:06:17 PM PDT 24
Finished May 14 01:06:52 PM PDT 24
Peak memory 205284 kb
Host smart-6f7a17bb-51e6-41d6-b72c-7841397cebd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130618281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1130618281
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3518100361
Short name T530
Test name
Test status
Simulation time 860126512 ps
CPU time 4.35 seconds
Started May 14 01:06:17 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 234396 kb
Host smart-9148c4d0-27fc-43be-b7b6-5123ca6a3425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518100361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3518100361
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3464567456
Short name T677
Test name
Test status
Simulation time 50261194 ps
CPU time 0.74 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:06:50 PM PDT 24
Peak memory 205772 kb
Host smart-136a8b74-0404-4caa-aeb9-a13a9b5a004e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464567456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3464567456
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3386871993
Short name T702
Test name
Test status
Simulation time 27952367736 ps
CPU time 64.35 seconds
Started May 14 01:06:18 PM PDT 24
Finished May 14 01:07:57 PM PDT 24
Peak memory 249388 kb
Host smart-51d50fb7-52e7-419e-bb32-4673f8c4cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386871993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3386871993
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1975943681
Short name T736
Test name
Test status
Simulation time 1703880975 ps
CPU time 21.77 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 232780 kb
Host smart-8347c7fd-91c4-4c8c-813a-17577e58656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975943681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1975943681
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1427433363
Short name T201
Test name
Test status
Simulation time 4367727185 ps
CPU time 11.28 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 233880 kb
Host smart-37dd5b20-1f07-4d8f-80eb-4c85a1ddeabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427433363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1427433363
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3386747693
Short name T375
Test name
Test status
Simulation time 762763845 ps
CPU time 4.08 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:06:53 PM PDT 24
Peak memory 232708 kb
Host smart-e9bfc720-d5d5-474f-ab68-743472709adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386747693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3386747693
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1208943069
Short name T177
Test name
Test status
Simulation time 188113749 ps
CPU time 2.75 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:06:53 PM PDT 24
Peak memory 233272 kb
Host smart-8df63ef6-2b68-4efd-8562-200eb1d0a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208943069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1208943069
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3150582730
Short name T52
Test name
Test status
Simulation time 1455181032 ps
CPU time 6.75 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 222408 kb
Host smart-f03e4458-5571-4ea8-8da2-10c5c788bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150582730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3150582730
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3044260585
Short name T706
Test name
Test status
Simulation time 154879744 ps
CPU time 4.53 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:06:54 PM PDT 24
Peak memory 222900 kb
Host smart-22a8bb5c-2c38-4ff0-8d9a-92fdae34ace1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3044260585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3044260585
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1999758016
Short name T155
Test name
Test status
Simulation time 14742725016 ps
CPU time 104.65 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:08:34 PM PDT 24
Peak memory 238396 kb
Host smart-2bdf7463-5413-40c7-ac3a-049df87f4ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999758016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1999758016
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.759638449
Short name T398
Test name
Test status
Simulation time 22375110760 ps
CPU time 36.26 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:07:27 PM PDT 24
Peak memory 216508 kb
Host smart-d7dcd33c-14eb-4d2a-b5de-5a06eb141445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759638449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.759638449
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.938226135
Short name T459
Test name
Test status
Simulation time 473433147 ps
CPU time 2.29 seconds
Started May 14 01:06:13 PM PDT 24
Finished May 14 01:06:50 PM PDT 24
Peak memory 216328 kb
Host smart-b59a0356-4346-448e-8de4-f0b6ea83cf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938226135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.938226135
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2244023294
Short name T966
Test name
Test status
Simulation time 443386620 ps
CPU time 1.78 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:06:52 PM PDT 24
Peak memory 216304 kb
Host smart-dd78ba9b-fc60-4878-b24a-8ef2edfc1376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244023294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2244023294
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2348243264
Short name T879
Test name
Test status
Simulation time 342681821 ps
CPU time 0.78 seconds
Started May 14 01:06:13 PM PDT 24
Finished May 14 01:06:49 PM PDT 24
Peak memory 205752 kb
Host smart-df14b4ac-ef83-4ccd-93b7-903cda0aef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348243264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2348243264
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.938705984
Short name T639
Test name
Test status
Simulation time 3690359125 ps
CPU time 4.33 seconds
Started May 14 01:06:17 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 216360 kb
Host smart-90f23402-3175-4376-ba9d-142c81cb982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938705984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.938705984
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4056424079
Short name T888
Test name
Test status
Simulation time 13933388 ps
CPU time 0.7 seconds
Started May 14 01:06:24 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 204776 kb
Host smart-f1dce9d1-da2d-45a2-b2f8-77690b542de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056424079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4056424079
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1358301526
Short name T640
Test name
Test status
Simulation time 190206901 ps
CPU time 2.34 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:06:53 PM PDT 24
Peak memory 218732 kb
Host smart-41501c27-b980-4989-8508-6f1887ffa62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358301526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1358301526
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1186514268
Short name T498
Test name
Test status
Simulation time 22544233 ps
CPU time 0.81 seconds
Started May 14 01:06:19 PM PDT 24
Finished May 14 01:06:53 PM PDT 24
Peak memory 206472 kb
Host smart-4e624fd3-f80f-41b5-a38b-cb02485bf5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186514268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1186514268
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3636091753
Short name T495
Test name
Test status
Simulation time 5801524527 ps
CPU time 53.73 seconds
Started May 14 01:06:24 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 249176 kb
Host smart-ca5363a4-91b5-40ec-9a77-0e531e796fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636091753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3636091753
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2772036409
Short name T211
Test name
Test status
Simulation time 53649826720 ps
CPU time 227.59 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:10:44 PM PDT 24
Peak memory 261220 kb
Host smart-07ee1676-a87e-4f86-ac5a-69c76a997b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772036409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2772036409
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2452549714
Short name T305
Test name
Test status
Simulation time 6761028944 ps
CPU time 91.85 seconds
Started May 14 01:06:24 PM PDT 24
Finished May 14 01:08:28 PM PDT 24
Peak memory 235264 kb
Host smart-5f8102ca-7349-42ab-aa15-b855717a837f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452549714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2452549714
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.782649405
Short name T878
Test name
Test status
Simulation time 5705903248 ps
CPU time 31.18 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:07:21 PM PDT 24
Peak memory 219260 kb
Host smart-71d4bc37-e1aa-49df-85d9-7f66d271b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782649405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.782649405
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1252123200
Short name T543
Test name
Test status
Simulation time 12278360446 ps
CPU time 79.5 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 232292 kb
Host smart-f4ef093f-8a1d-4d99-bc07-3c62ff182bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252123200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1252123200
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.780597972
Short name T724
Test name
Test status
Simulation time 11101946219 ps
CPU time 9.06 seconds
Started May 14 01:06:15 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 232832 kb
Host smart-ac2e6fa1-e211-47e5-b4de-910a987c92d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780597972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.780597972
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1313448623
Short name T377
Test name
Test status
Simulation time 3155154974 ps
CPU time 11.06 seconds
Started May 14 01:06:13 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 240964 kb
Host smart-817beff5-6033-4736-a9c7-1e897f4a8c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313448623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1313448623
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2560119382
Short name T813
Test name
Test status
Simulation time 142712963 ps
CPU time 4.12 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 222332 kb
Host smart-ec90789d-bcb7-460e-9f70-632c18318d23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2560119382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2560119382
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3776437656
Short name T973
Test name
Test status
Simulation time 49719856655 ps
CPU time 556.63 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 273924 kb
Host smart-a310fe4b-e0ed-4307-b315-0d3e4a774b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776437656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3776437656
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3189703915
Short name T965
Test name
Test status
Simulation time 206252752 ps
CPU time 3.74 seconds
Started May 14 01:06:18 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 216360 kb
Host smart-55d030ee-ce25-4246-8ee6-afc4d6c34c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189703915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3189703915
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4242607513
Short name T442
Test name
Test status
Simulation time 1978149789 ps
CPU time 6.04 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 216320 kb
Host smart-976e3da2-bff2-4998-a6d9-ef285c994b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242607513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4242607513
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1164927370
Short name T358
Test name
Test status
Simulation time 560964034 ps
CPU time 0.94 seconds
Started May 14 01:06:16 PM PDT 24
Finished May 14 01:06:52 PM PDT 24
Peak memory 206436 kb
Host smart-fb150fc6-edd0-4754-a452-e67e9aecb6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164927370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1164927370
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2941365206
Short name T394
Test name
Test status
Simulation time 15785460 ps
CPU time 0.71 seconds
Started May 14 01:06:14 PM PDT 24
Finished May 14 01:06:50 PM PDT 24
Peak memory 205792 kb
Host smart-a572b4e4-b576-4afb-9b06-045d39623a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941365206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2941365206
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.65318253
Short name T499
Test name
Test status
Simulation time 6449170597 ps
CPU time 19.49 seconds
Started May 14 01:06:18 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 232892 kb
Host smart-9e23a64f-38b3-4132-baef-2514aebc8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65318253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.65318253
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3971962198
Short name T59
Test name
Test status
Simulation time 44609475 ps
CPU time 0.71 seconds
Started May 14 01:06:28 PM PDT 24
Finished May 14 01:06:58 PM PDT 24
Peak memory 205588 kb
Host smart-3fa90501-fa3f-40cf-a29c-e34ead7bf304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971962198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3971962198
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2455204893
Short name T853
Test name
Test status
Simulation time 69892056 ps
CPU time 2.47 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 233772 kb
Host smart-62b32f6b-ce2b-4694-9c4a-b5abb3c6dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455204893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2455204893
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2128229666
Short name T359
Test name
Test status
Simulation time 87550406 ps
CPU time 0.77 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 206364 kb
Host smart-2cb71ed1-c920-4429-931c-86b84589a108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128229666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2128229666
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1526614856
Short name T744
Test name
Test status
Simulation time 1204826017 ps
CPU time 26.36 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:26 PM PDT 24
Peak memory 251456 kb
Host smart-5abea8ee-cae8-43c2-9f56-48420b36e89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526614856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1526614856
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2182949923
Short name T687
Test name
Test status
Simulation time 7859047655 ps
CPU time 118.59 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:08:55 PM PDT 24
Peak memory 255884 kb
Host smart-b78125d5-7705-436d-99ac-0ae3cddcf4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182949923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2182949923
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4162360705
Short name T893
Test name
Test status
Simulation time 8196963051 ps
CPU time 32.54 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:29 PM PDT 24
Peak memory 241000 kb
Host smart-82876f2e-2b7f-404b-ae94-2944ae1bf09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162360705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4162360705
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1933353344
Short name T829
Test name
Test status
Simulation time 5503781351 ps
CPU time 13.9 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:10 PM PDT 24
Peak memory 224532 kb
Host smart-35b5feb5-772d-4538-b65b-5cdb6c2631be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933353344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1933353344
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2523049940
Short name T814
Test name
Test status
Simulation time 1657670745 ps
CPU time 7.58 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 222296 kb
Host smart-8d0721ac-b5bc-46e3-8b90-39ccd4af2fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523049940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2523049940
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3887120814
Short name T791
Test name
Test status
Simulation time 2889487078 ps
CPU time 10.21 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 233684 kb
Host smart-4286f096-ca2b-4875-a07c-d66dfbda842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887120814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3887120814
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.507818185
Short name T436
Test name
Test status
Simulation time 3703220933 ps
CPU time 3.99 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 224648 kb
Host smart-b0cf0993-a0c5-402c-9375-3de1d1af295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507818185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.507818185
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3889605245
Short name T390
Test name
Test status
Simulation time 4242919170 ps
CPU time 11.33 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:07:09 PM PDT 24
Peak memory 222932 kb
Host smart-28eb9484-a0f3-4035-8061-7cdb2c1f72c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3889605245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3889605245
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3473246652
Short name T137
Test name
Test status
Simulation time 10535169277 ps
CPU time 148.07 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:09:26 PM PDT 24
Peak memory 253336 kb
Host smart-159f5d7c-abd3-4eef-a4e1-957e810382d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473246652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3473246652
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3496695988
Short name T381
Test name
Test status
Simulation time 25882175291 ps
CPU time 35.23 seconds
Started May 14 01:06:23 PM PDT 24
Finished May 14 01:07:30 PM PDT 24
Peak memory 216508 kb
Host smart-7b4592ef-2fd9-4533-bc9e-c697f7c6e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496695988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3496695988
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.759677195
Short name T471
Test name
Test status
Simulation time 11589836917 ps
CPU time 16.57 seconds
Started May 14 01:06:24 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 216528 kb
Host smart-424778a1-4b81-4de5-9df7-b1ca30d7ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759677195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.759677195
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3571092887
Short name T804
Test name
Test status
Simulation time 60170181 ps
CPU time 1.11 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 207912 kb
Host smart-bc8b5396-3588-4203-8e33-b27ee203f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571092887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3571092887
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2874319135
Short name T481
Test name
Test status
Simulation time 181058516 ps
CPU time 0.85 seconds
Started May 14 01:06:23 PM PDT 24
Finished May 14 01:06:56 PM PDT 24
Peak memory 205808 kb
Host smart-3dbb0c9e-cda4-4fca-a356-4fecc8b72102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874319135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2874319135
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1518670211
Short name T365
Test name
Test status
Simulation time 1392878213 ps
CPU time 8.24 seconds
Started May 14 01:06:28 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 218660 kb
Host smart-8813be4f-4cc4-4aa7-a425-0c1a8a13c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518670211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1518670211
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3839698021
Short name T433
Test name
Test status
Simulation time 36321909 ps
CPU time 0.72 seconds
Started May 14 01:06:24 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 204720 kb
Host smart-25ea6ba0-0b97-477d-a19c-6d5c63ba39bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839698021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3839698021
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1636217613
Short name T629
Test name
Test status
Simulation time 336185156 ps
CPU time 3.17 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 234488 kb
Host smart-425f4148-aec7-499a-af5a-5ac2b0155a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636217613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1636217613
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4041892456
Short name T56
Test name
Test status
Simulation time 15515675 ps
CPU time 0.76 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 206736 kb
Host smart-10d04df7-abf7-4b94-a97b-728b961dc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041892456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4041892456
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3971792750
Short name T247
Test name
Test status
Simulation time 27571870446 ps
CPU time 35.13 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:31 PM PDT 24
Peak memory 235400 kb
Host smart-6b3d3c46-7970-49c6-b789-a303e52de1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971792750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3971792750
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.9852950
Short name T600
Test name
Test status
Simulation time 1924346515 ps
CPU time 17.94 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:15 PM PDT 24
Peak memory 224452 kb
Host smart-0ffda350-8b2a-448d-abc3-5ecf24eac30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9852950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.9852950
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2957384538
Short name T213
Test name
Test status
Simulation time 15788499605 ps
CPU time 81.07 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 253076 kb
Host smart-6e4c19ad-9755-4910-92a7-1bc719704dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957384538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2957384538
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.438654354
Short name T403
Test name
Test status
Simulation time 622032686 ps
CPU time 4.77 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:04 PM PDT 24
Peak memory 218720 kb
Host smart-b4e1e3e6-742c-4d20-9f43-1ad2cfb53d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438654354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.438654354
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.497935799
Short name T670
Test name
Test status
Simulation time 84991595 ps
CPU time 2.86 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 235808 kb
Host smart-2b1f2671-09e9-4e8f-ab67-241f3590e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497935799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.497935799
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3537854353
Short name T863
Test name
Test status
Simulation time 639245787 ps
CPU time 14.83 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 249220 kb
Host smart-9d75e86d-bac2-4452-b008-7bf2a8533eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537854353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3537854353
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1156096863
Short name T216
Test name
Test status
Simulation time 4407136264 ps
CPU time 7.44 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:04 PM PDT 24
Peak memory 234512 kb
Host smart-72a11743-3b21-4d89-aab0-bcfbd1b4542a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156096863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1156096863
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1009080822
Short name T917
Test name
Test status
Simulation time 5672918031 ps
CPU time 12.03 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:09 PM PDT 24
Peak memory 219404 kb
Host smart-e4798015-5592-451e-bdfc-673d1760bfea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009080822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1009080822
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3869482404
Short name T317
Test name
Test status
Simulation time 2674889385 ps
CPU time 26.92 seconds
Started May 14 01:06:23 PM PDT 24
Finished May 14 01:07:22 PM PDT 24
Peak memory 216616 kb
Host smart-6d51c951-2bd4-44ec-af48-dfa81365e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869482404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3869482404
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3426475673
Short name T713
Test name
Test status
Simulation time 42395694 ps
CPU time 0.74 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 205524 kb
Host smart-a892dde4-344a-4666-8738-4969ba39b373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426475673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3426475673
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2045100839
Short name T349
Test name
Test status
Simulation time 62382890 ps
CPU time 1.48 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:58 PM PDT 24
Peak memory 208072 kb
Host smart-bfab7838-c325-4da4-9b08-bcbbad50fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045100839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2045100839
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2438029292
Short name T611
Test name
Test status
Simulation time 109816832 ps
CPU time 0.78 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 205600 kb
Host smart-9c35e5ad-fc18-4d44-9bd4-f8b744719c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438029292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2438029292
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.872510104
Short name T676
Test name
Test status
Simulation time 253411386 ps
CPU time 3.26 seconds
Started May 14 01:06:22 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 234040 kb
Host smart-e423e9ff-b70a-458f-8135-e3f8068c86f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872510104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.872510104
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2064931781
Short name T596
Test name
Test status
Simulation time 11073661 ps
CPU time 0.67 seconds
Started May 14 01:06:28 PM PDT 24
Finished May 14 01:06:58 PM PDT 24
Peak memory 205264 kb
Host smart-f2e9924a-ed56-4897-882d-0f9429fbe73a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064931781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2064931781
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2022852877
Short name T896
Test name
Test status
Simulation time 1156105078 ps
CPU time 9.25 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:07:07 PM PDT 24
Peak memory 219744 kb
Host smart-8ec79a8b-4b52-4417-9bb5-fdf3d6566d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022852877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2022852877
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3467070323
Short name T792
Test name
Test status
Simulation time 14557391 ps
CPU time 0.78 seconds
Started May 14 01:06:28 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 206392 kb
Host smart-ecc26a5b-1dfc-4bfb-8f69-de9b0fee38e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467070323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3467070323
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1691962990
Short name T397
Test name
Test status
Simulation time 6578637468 ps
CPU time 30.73 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:28 PM PDT 24
Peak memory 224636 kb
Host smart-638083ad-bf40-4c07-ac37-b353bda73bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691962990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1691962990
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1191685859
Short name T473
Test name
Test status
Simulation time 205638714649 ps
CPU time 197.13 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:10:17 PM PDT 24
Peak memory 248464 kb
Host smart-033e8269-c560-423d-8039-873cc2d904c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191685859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1191685859
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2705811255
Short name T179
Test name
Test status
Simulation time 16239581977 ps
CPU time 60.63 seconds
Started May 14 01:06:29 PM PDT 24
Finished May 14 01:07:58 PM PDT 24
Peak memory 239768 kb
Host smart-547cd079-ab53-49fd-bd4d-f3a13290e160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705811255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2705811255
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2695496808
Short name T439
Test name
Test status
Simulation time 356233305 ps
CPU time 3.85 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 232664 kb
Host smart-e3be18fd-87d1-4e04-983b-fcce4df6be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695496808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2695496808
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2612683371
Short name T494
Test name
Test status
Simulation time 41038541 ps
CPU time 2.61 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 232760 kb
Host smart-56c59872-b671-4e2a-89a3-314cfbf49145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612683371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2612683371
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1823572226
Short name T268
Test name
Test status
Simulation time 1145105437 ps
CPU time 12.75 seconds
Started May 14 01:06:26 PM PDT 24
Finished May 14 01:07:10 PM PDT 24
Peak memory 240940 kb
Host smart-454f20be-638a-4b41-bfd8-67997a9c6f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823572226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1823572226
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4076643673
Short name T615
Test name
Test status
Simulation time 437673420 ps
CPU time 2.84 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:59 PM PDT 24
Peak memory 218448 kb
Host smart-5ee55d31-1d09-4166-8870-1ca274466ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076643673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4076643673
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1230380144
Short name T668
Test name
Test status
Simulation time 5594481433 ps
CPU time 16.33 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 218776 kb
Host smart-4df2f582-2ad1-49f4-8791-1587dc6e4374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230380144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1230380144
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.738089664
Short name T894
Test name
Test status
Simulation time 9736748438 ps
CPU time 10.02 seconds
Started May 14 01:06:28 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 223132 kb
Host smart-aa583638-b620-491f-b938-027b611ac7d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738089664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.738089664
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.778869344
Short name T719
Test name
Test status
Simulation time 4723394336 ps
CPU time 21.86 seconds
Started May 14 01:06:28 PM PDT 24
Finished May 14 01:07:19 PM PDT 24
Peak memory 224604 kb
Host smart-06fd18cf-f871-4839-b187-741e6d9e7367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778869344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.778869344
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3101043422
Short name T800
Test name
Test status
Simulation time 3630720406 ps
CPU time 22.64 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:07:19 PM PDT 24
Peak memory 216532 kb
Host smart-5e6e8e73-4712-4fb9-b46f-5dc5d643d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101043422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3101043422
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.167467550
Short name T612
Test name
Test status
Simulation time 509396989 ps
CPU time 2.87 seconds
Started May 14 01:06:27 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 216340 kb
Host smart-b2468311-bc48-41ba-9ec1-c5df99982434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167467550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.167467550
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2448777111
Short name T333
Test name
Test status
Simulation time 160154880 ps
CPU time 1.14 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 207224 kb
Host smart-3818cef7-e9a6-4664-baa6-50a445fa100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448777111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2448777111
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3443901297
Short name T884
Test name
Test status
Simulation time 28652470 ps
CPU time 0.75 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:00 PM PDT 24
Peak memory 205808 kb
Host smart-196546d5-1f6e-4a6f-b296-a6581cc5a0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443901297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3443901297
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4256929145
Short name T808
Test name
Test status
Simulation time 405992372 ps
CPU time 6.5 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 234940 kb
Host smart-12c73e1f-b1a1-4e81-af77-7fec3e3fca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256929145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4256929145
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.99695411
Short name T708
Test name
Test status
Simulation time 32398851 ps
CPU time 0.71 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 204732 kb
Host smart-bb4d1aa2-f61c-410d-ae1a-1413a99b4fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99695411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.99695411
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4291708630
Short name T364
Test name
Test status
Simulation time 87305675 ps
CPU time 2.55 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:03 PM PDT 24
Peak memory 218556 kb
Host smart-d7d7c924-832b-4d4f-93e7-ed63b0810912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291708630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4291708630
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3410684215
Short name T385
Test name
Test status
Simulation time 16118345 ps
CPU time 0.72 seconds
Started May 14 01:06:25 PM PDT 24
Finished May 14 01:06:57 PM PDT 24
Peak memory 205376 kb
Host smart-a1b325c3-38a7-49a6-8d45-f6cfc7814f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410684215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3410684215
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.689750493
Short name T263
Test name
Test status
Simulation time 49582435877 ps
CPU time 184.74 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:10:04 PM PDT 24
Peak memory 250476 kb
Host smart-2a37d5a2-f3e8-454f-8f43-1e4313277e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689750493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.689750493
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3072202212
Short name T195
Test name
Test status
Simulation time 15602801677 ps
CPU time 110 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 252972 kb
Host smart-0a027d8d-6274-46f4-b755-931c0dc9cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072202212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3072202212
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3253883521
Short name T930
Test name
Test status
Simulation time 3259610438 ps
CPU time 16.3 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:17 PM PDT 24
Peak memory 237768 kb
Host smart-ce87f49b-7158-4eaa-a37a-ec9f7a9985ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253883521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3253883521
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3763450256
Short name T300
Test name
Test status
Simulation time 1468949703 ps
CPU time 22.19 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:23 PM PDT 24
Peak memory 249144 kb
Host smart-4cd17ce2-5471-41b5-bde1-3cf677b639ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763450256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3763450256
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2451436281
Short name T430
Test name
Test status
Simulation time 410280524 ps
CPU time 7.26 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 235272 kb
Host smart-f689e6cf-76c3-486c-9773-70dc0653372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451436281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2451436281
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2227832226
Short name T574
Test name
Test status
Simulation time 8746184094 ps
CPU time 11.68 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 233984 kb
Host smart-826b0040-edbe-4f96-954e-a943661f0ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227832226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2227832226
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1042719580
Short name T758
Test name
Test status
Simulation time 17656604828 ps
CPU time 4.75 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 234772 kb
Host smart-029ba4d8-a091-4035-91d7-e505cebeae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042719580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1042719580
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3421563570
Short name T557
Test name
Test status
Simulation time 79800260354 ps
CPU time 24.21 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:07:23 PM PDT 24
Peak memory 238864 kb
Host smart-42e640e7-2cf5-4124-a612-9b3ee513511a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421563570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3421563570
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2258558573
Short name T889
Test name
Test status
Simulation time 4514635986 ps
CPU time 14.51 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:07:14 PM PDT 24
Peak memory 220460 kb
Host smart-c7cfc6db-357e-4b53-8115-42893839e9ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2258558573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2258558573
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1342235918
Short name T455
Test name
Test status
Simulation time 11352318527 ps
CPU time 57.25 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:58 PM PDT 24
Peak memory 241208 kb
Host smart-449dfe30-5d51-491b-b774-be3ada61b228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342235918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1342235918
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2464778552
Short name T929
Test name
Test status
Simulation time 2693745558 ps
CPU time 2.62 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:04 PM PDT 24
Peak memory 216540 kb
Host smart-16efffd1-a73b-4a3e-8461-020a388db3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464778552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2464778552
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2060537089
Short name T794
Test name
Test status
Simulation time 5322545117 ps
CPU time 14.2 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:15 PM PDT 24
Peak memory 216556 kb
Host smart-991f6c23-5646-4195-a9ac-87d976f384b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060537089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2060537089
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.547763153
Short name T634
Test name
Test status
Simulation time 1035465838 ps
CPU time 3.06 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:03 PM PDT 24
Peak memory 216444 kb
Host smart-3d8b5af1-b4b6-4b2a-96a7-8e161d389b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547763153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.547763153
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1183386126
Short name T899
Test name
Test status
Simulation time 130316242 ps
CPU time 0.82 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 205872 kb
Host smart-3d1115bb-a697-43c6-8cbe-b86eff6d3885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183386126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1183386126
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2522557252
Short name T740
Test name
Test status
Simulation time 6415203981 ps
CPU time 7.13 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:07 PM PDT 24
Peak memory 234344 kb
Host smart-e1756140-1e1e-4949-a4ef-fbe9c8b1c2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522557252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2522557252
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1413393340
Short name T7
Test name
Test status
Simulation time 70272205 ps
CPU time 0.69 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 205692 kb
Host smart-0b077398-dd0f-465b-9fdb-9138684306e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413393340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1413393340
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3568674713
Short name T190
Test name
Test status
Simulation time 1159354214 ps
CPU time 8.12 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 233964 kb
Host smart-e36ad0cf-7e0a-424e-9207-7261fe10c837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568674713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3568674713
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2647872000
Short name T350
Test name
Test status
Simulation time 31957937 ps
CPU time 0.74 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 205424 kb
Host smart-c02ec0b3-0e95-435b-8d86-e03bb452de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647872000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2647872000
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1171948781
Short name T726
Test name
Test status
Simulation time 7015502422 ps
CPU time 23.87 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:24 PM PDT 24
Peak memory 237168 kb
Host smart-b0cf20d3-f5b8-449d-b166-f97533001306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171948781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1171948781
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.94274952
Short name T450
Test name
Test status
Simulation time 54174839691 ps
CPU time 172.48 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:09:53 PM PDT 24
Peak memory 265552 kb
Host smart-4498f18e-37ae-4c4f-b30c-0cbea9eb8735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94274952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.94274952
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.842209573
Short name T689
Test name
Test status
Simulation time 911161910 ps
CPU time 17.55 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 232748 kb
Host smart-0438c4b1-32ca-43bf-a5ff-a76264314908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842209573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.842209573
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1524332088
Short name T633
Test name
Test status
Simulation time 34445541 ps
CPU time 2.51 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 221236 kb
Host smart-5f4b0eac-412a-48c6-8621-0af4822eda9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524332088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1524332088
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.911240660
Short name T705
Test name
Test status
Simulation time 663908081 ps
CPU time 7.61 seconds
Started May 14 01:06:33 PM PDT 24
Finished May 14 01:07:07 PM PDT 24
Peak memory 240112 kb
Host smart-d037cce9-daa2-44c1-b06b-bcdce0640156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911240660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.911240660
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3841424842
Short name T720
Test name
Test status
Simulation time 4435493563 ps
CPU time 16.9 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 239408 kb
Host smart-c4c2c424-4393-43fa-8229-6e4fc3a11736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841424842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3841424842
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3260238321
Short name T429
Test name
Test status
Simulation time 3360796886 ps
CPU time 3.84 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 234736 kb
Host smart-19c2c04d-6891-4a94-bc8c-fecc4b5aac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260238321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3260238321
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4118082419
Short name T831
Test name
Test status
Simulation time 1740757812 ps
CPU time 12.76 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:14 PM PDT 24
Peak memory 218724 kb
Host smart-41b48b56-d798-4116-9a2f-b86a652d0735
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4118082419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4118082419
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3917647735
Short name T513
Test name
Test status
Simulation time 14837494359 ps
CPU time 21.31 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:21 PM PDT 24
Peak memory 216540 kb
Host smart-d290658b-fc0f-4717-b7ed-81836b20e395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917647735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3917647735
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2899924613
Short name T422
Test name
Test status
Simulation time 75196889626 ps
CPU time 12.58 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:13 PM PDT 24
Peak memory 216444 kb
Host smart-0caff784-e8ca-4817-ad3f-48214c4b2204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899924613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2899924613
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2497026356
Short name T324
Test name
Test status
Simulation time 146591439 ps
CPU time 5.87 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:07 PM PDT 24
Peak memory 216400 kb
Host smart-afc44d0c-19cf-4ddf-b238-2b3d5a414314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497026356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2497026356
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1833435671
Short name T321
Test name
Test status
Simulation time 29227251 ps
CPU time 0.73 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 205748 kb
Host smart-a8b2f4cf-07a5-4884-9c4e-90ac754b019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833435671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1833435671
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.946166191
Short name T483
Test name
Test status
Simulation time 478940361 ps
CPU time 3.32 seconds
Started May 14 01:06:34 PM PDT 24
Finished May 14 01:07:03 PM PDT 24
Peak memory 234088 kb
Host smart-e469671e-4478-4c58-b3b7-03a8a2759b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946166191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.946166191
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2523668258
Short name T470
Test name
Test status
Simulation time 16177527 ps
CPU time 0.71 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 204776 kb
Host smart-eb336f3b-764a-4244-bdb7-22bc9bc223d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523668258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2523668258
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1214347958
Short name T53
Test name
Test status
Simulation time 288338343 ps
CPU time 2.72 seconds
Started May 14 01:06:46 PM PDT 24
Finished May 14 01:07:07 PM PDT 24
Peak memory 234140 kb
Host smart-40401aea-c5e6-4fb9-8727-57deb13bb93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214347958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1214347958
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1305415260
Short name T477
Test name
Test status
Simulation time 57274573 ps
CPU time 0.78 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 206460 kb
Host smart-fd622f99-81fa-4387-95dd-d2a8ad95bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305415260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1305415260
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.819576103
Short name T595
Test name
Test status
Simulation time 16147039658 ps
CPU time 59.52 seconds
Started May 14 01:06:49 PM PDT 24
Finished May 14 01:08:05 PM PDT 24
Peak memory 241076 kb
Host smart-791d3750-18e9-4bf7-983a-bd7e97ae61b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819576103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.819576103
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4262169263
Short name T962
Test name
Test status
Simulation time 9496422206 ps
CPU time 105.75 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:08:50 PM PDT 24
Peak memory 249380 kb
Host smart-4002a476-5ffa-4f88-ae71-efbbf16b674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262169263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4262169263
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3116878137
Short name T1
Test name
Test status
Simulation time 151305414 ps
CPU time 3.42 seconds
Started May 14 01:06:48 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 232592 kb
Host smart-7fa3a193-134c-47a4-bbaf-1af3834f4184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116878137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3116878137
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1257346360
Short name T908
Test name
Test status
Simulation time 944766935 ps
CPU time 4.57 seconds
Started May 14 01:06:48 PM PDT 24
Finished May 14 01:07:09 PM PDT 24
Peak memory 237376 kb
Host smart-377acc05-790e-4f6b-bdd8-17e782691d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257346360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1257346360
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3079491362
Short name T890
Test name
Test status
Simulation time 11663310371 ps
CPU time 34.25 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:38 PM PDT 24
Peak memory 235028 kb
Host smart-6f6012c7-d30a-48c3-b8b7-263222eabbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079491362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3079491362
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2459920098
Short name T897
Test name
Test status
Simulation time 29870548680 ps
CPU time 15.83 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:17 PM PDT 24
Peak memory 217124 kb
Host smart-04e0f92e-e978-4334-b19f-0345ac4e62a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459920098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2459920098
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.376390784
Short name T887
Test name
Test status
Simulation time 297435329 ps
CPU time 5.03 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 233636 kb
Host smart-ca21feb2-b41c-4114-a03b-3640fde6a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376390784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.376390784
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2969047480
Short name T733
Test name
Test status
Simulation time 834397976 ps
CPU time 8.5 seconds
Started May 14 01:06:46 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 222520 kb
Host smart-64bceb1d-d6f0-462e-8feb-a29b1502596b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2969047480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2969047480
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1502030908
Short name T493
Test name
Test status
Simulation time 731486276 ps
CPU time 1 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 206972 kb
Host smart-9a0c9bc3-4053-4b58-9465-d704dda1bcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502030908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1502030908
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2859384219
Short name T313
Test name
Test status
Simulation time 2224730073 ps
CPU time 10.24 seconds
Started May 14 01:06:37 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 216392 kb
Host smart-4b63b9e0-be8b-4e24-bb7b-2f7d8226d250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859384219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2859384219
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3202203393
Short name T506
Test name
Test status
Simulation time 792278939 ps
CPU time 5.24 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 216256 kb
Host smart-391920b8-adc4-40c1-a934-fb7ac01a423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202203393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3202203393
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4102955664
Short name T766
Test name
Test status
Simulation time 24823766 ps
CPU time 1.46 seconds
Started May 14 01:06:36 PM PDT 24
Finished May 14 01:07:03 PM PDT 24
Peak memory 208156 kb
Host smart-de9ed861-0129-4ffb-b3ae-c8f050f51543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102955664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4102955664
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1244139385
Short name T320
Test name
Test status
Simulation time 241431989 ps
CPU time 0.9 seconds
Started May 14 01:06:35 PM PDT 24
Finished May 14 01:07:02 PM PDT 24
Peak memory 206828 kb
Host smart-5cd9ca2f-90c4-4ea6-9d8b-737d86fce220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244139385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1244139385
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.492646550
Short name T601
Test name
Test status
Simulation time 2731574663 ps
CPU time 12.54 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:17 PM PDT 24
Peak memory 220968 kb
Host smart-2ffef5fa-cc5a-4fa9-ba35-e95ec40bb119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492646550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.492646550
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3547224200
Short name T345
Test name
Test status
Simulation time 13630677 ps
CPU time 0.7 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:21 PM PDT 24
Peak memory 204736 kb
Host smart-da284296-f73d-4002-9fcb-19f445c3c7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547224200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
547224200
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2348024878
Short name T133
Test name
Test status
Simulation time 148191239 ps
CPU time 2.59 seconds
Started May 14 01:05:06 PM PDT 24
Finished May 14 01:05:09 PM PDT 24
Peak memory 233708 kb
Host smart-9d451f58-7b1a-4d1a-a8a0-71a6474bd17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348024878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2348024878
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2809361495
Short name T340
Test name
Test status
Simulation time 12905708 ps
CPU time 0.77 seconds
Started May 14 01:05:08 PM PDT 24
Finished May 14 01:05:10 PM PDT 24
Peak memory 206696 kb
Host smart-0020d51d-460d-4e72-abca-a3066be5d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809361495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2809361495
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.283793859
Short name T779
Test name
Test status
Simulation time 10176366521 ps
CPU time 39.27 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:05:57 PM PDT 24
Peak memory 249264 kb
Host smart-e5a29834-dee5-441c-bfdd-81951325a839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283793859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.283793859
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.603525108
Short name T914
Test name
Test status
Simulation time 43611928467 ps
CPU time 146.26 seconds
Started May 14 01:05:14 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 257368 kb
Host smart-a727714a-b321-4fab-ab79-20268c00a58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603525108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.603525108
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3149535447
Short name T621
Test name
Test status
Simulation time 932413995 ps
CPU time 5.42 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:31 PM PDT 24
Peak memory 232740 kb
Host smart-30390186-94a6-457e-a9a0-c39c3a60002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149535447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3149535447
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1432728882
Short name T852
Test name
Test status
Simulation time 443596768 ps
CPU time 2.34 seconds
Started May 14 01:05:07 PM PDT 24
Finished May 14 01:05:11 PM PDT 24
Peak memory 216088 kb
Host smart-d960afc9-b462-45ea-8ad7-61f6a64c11ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432728882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1432728882
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.304441196
Short name T605
Test name
Test status
Simulation time 946876612 ps
CPU time 10.05 seconds
Started May 14 01:05:07 PM PDT 24
Finished May 14 01:05:18 PM PDT 24
Peak memory 235548 kb
Host smart-28337d96-2259-450a-a302-b43ec3fbeef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304441196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.304441196
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1682490461
Short name T480
Test name
Test status
Simulation time 122218014 ps
CPU time 1.1 seconds
Started May 14 01:05:06 PM PDT 24
Finished May 14 01:05:08 PM PDT 24
Peak memory 216952 kb
Host smart-679d669f-e1dc-4c79-a763-d75cdea870d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682490461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1682490461
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.397776194
Short name T233
Test name
Test status
Simulation time 9996432568 ps
CPU time 18.66 seconds
Started May 14 01:05:04 PM PDT 24
Finished May 14 01:05:24 PM PDT 24
Peak memory 236452 kb
Host smart-67aa71c7-0633-4b26-8356-1ae614241f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397776194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
397776194
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.905072033
Short name T833
Test name
Test status
Simulation time 6937742822 ps
CPU time 16.84 seconds
Started May 14 01:05:04 PM PDT 24
Finished May 14 01:05:22 PM PDT 24
Peak memory 224512 kb
Host smart-93dc9811-6dc8-4cc2-aea9-5643367453c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905072033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.905072033
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.295075372
Short name T13
Test name
Test status
Simulation time 303583609 ps
CPU time 4.83 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:05:31 PM PDT 24
Peak memory 222568 kb
Host smart-58967e64-4cd8-439d-b74c-8fa87af04e93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=295075372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.295075372
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1080979033
Short name T64
Test name
Test status
Simulation time 438519356 ps
CPU time 0.96 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:23 PM PDT 24
Peak memory 235164 kb
Host smart-69a7906c-33bf-4835-a897-a71175a49a0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080979033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1080979033
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.648510539
Short name T584
Test name
Test status
Simulation time 34839395073 ps
CPU time 300.76 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:10:26 PM PDT 24
Peak memory 273948 kb
Host smart-6c99a262-7d40-472e-930c-e1ecccd60dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648510539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.648510539
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1438118370
Short name T356
Test name
Test status
Simulation time 1103966242 ps
CPU time 10.31 seconds
Started May 14 01:05:07 PM PDT 24
Finished May 14 01:05:19 PM PDT 24
Peak memory 219108 kb
Host smart-00786776-a393-4073-907d-1f035f4aa729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438118370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1438118370
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2646339092
Short name T331
Test name
Test status
Simulation time 1522785193 ps
CPU time 2.79 seconds
Started May 14 01:05:06 PM PDT 24
Finished May 14 01:05:10 PM PDT 24
Peak memory 216112 kb
Host smart-8e7247b1-6aea-4ab0-b89b-1a5f4fea330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646339092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2646339092
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.175106356
Short name T905
Test name
Test status
Simulation time 1595285855 ps
CPU time 12.81 seconds
Started May 14 01:05:05 PM PDT 24
Finished May 14 01:05:19 PM PDT 24
Peak memory 216436 kb
Host smart-02f4caca-4a18-487e-a226-bdb8a9cea392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175106356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.175106356
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3658160464
Short name T787
Test name
Test status
Simulation time 63978560 ps
CPU time 0.72 seconds
Started May 14 01:05:09 PM PDT 24
Finished May 14 01:05:11 PM PDT 24
Peak memory 205848 kb
Host smart-50644d84-2679-4df0-b148-29a56f4f279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658160464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3658160464
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3031344692
Short name T490
Test name
Test status
Simulation time 46468353 ps
CPU time 2.53 seconds
Started May 14 01:05:08 PM PDT 24
Finished May 14 01:05:12 PM PDT 24
Peak memory 235372 kb
Host smart-46bb9c8c-8f8b-429a-b028-4594576e8312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031344692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3031344692
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3937725361
Short name T632
Test name
Test status
Simulation time 12313571 ps
CPU time 0.75 seconds
Started May 14 01:07:11 PM PDT 24
Finished May 14 01:07:15 PM PDT 24
Peak memory 204676 kb
Host smart-0b35afe7-d339-4426-834c-7a75013b9471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937725361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3937725361
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4017558826
Short name T529
Test name
Test status
Simulation time 313436048 ps
CPU time 2.28 seconds
Started May 14 01:06:49 PM PDT 24
Finished May 14 01:07:08 PM PDT 24
Peak memory 218788 kb
Host smart-6a53be25-6d88-498c-bde2-eb873ff053d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017558826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4017558826
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4003127814
Short name T940
Test name
Test status
Simulation time 66568068 ps
CPU time 0.77 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:05 PM PDT 24
Peak memory 205420 kb
Host smart-1276a946-fb69-4c2a-ad6b-3d68f19e0e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003127814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4003127814
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2661581742
Short name T39
Test name
Test status
Simulation time 6896880666 ps
CPU time 27.75 seconds
Started May 14 01:06:48 PM PDT 24
Finished May 14 01:07:33 PM PDT 24
Peak memory 232880 kb
Host smart-042d5e98-6404-4be0-8df4-66080ed39526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661581742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2661581742
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1729762082
Short name T803
Test name
Test status
Simulation time 2010283376 ps
CPU time 20.25 seconds
Started May 14 01:06:48 PM PDT 24
Finished May 14 01:07:25 PM PDT 24
Peak memory 217444 kb
Host smart-9a7411d8-53ac-41eb-ae0e-0185b5ed9079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729762082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1729762082
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4057112394
Short name T245
Test name
Test status
Simulation time 12181426627 ps
CPU time 146.92 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:09:31 PM PDT 24
Peak memory 269556 kb
Host smart-6c06306a-c17e-4d0f-b31d-c25efdbe3076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057112394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4057112394
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3281197540
Short name T698
Test name
Test status
Simulation time 749225401 ps
CPU time 16.09 seconds
Started May 14 01:06:46 PM PDT 24
Finished May 14 01:07:20 PM PDT 24
Peak memory 232644 kb
Host smart-cefcb8b6-e92c-43b2-9b51-cf5bbdbb2c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281197540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3281197540
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1344485445
Short name T271
Test name
Test status
Simulation time 2474776711 ps
CPU time 22.82 seconds
Started May 14 01:06:49 PM PDT 24
Finished May 14 01:07:28 PM PDT 24
Peak memory 218808 kb
Host smart-111889ac-84b6-4890-b7a9-f746010a6946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344485445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1344485445
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.648485079
Short name T562
Test name
Test status
Simulation time 1086714150 ps
CPU time 14.1 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 233424 kb
Host smart-c9909870-ff25-4ac2-9842-c7324851d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648485079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.648485079
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3944910137
Short name T2
Test name
Test status
Simulation time 2874695804 ps
CPU time 13.28 seconds
Started May 14 01:06:49 PM PDT 24
Finished May 14 01:07:19 PM PDT 24
Peak memory 234192 kb
Host smart-8f587c82-7ad0-49eb-a308-30d704b71706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944910137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3944910137
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1879280706
Short name T9
Test name
Test status
Simulation time 57269744 ps
CPU time 2.46 seconds
Started May 14 01:06:46 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 221432 kb
Host smart-34f82288-44f0-4230-9d8f-941ea0ad0083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879280706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1879280706
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2921872360
Short name T789
Test name
Test status
Simulation time 5184427516 ps
CPU time 6.43 seconds
Started May 14 01:06:48 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 222628 kb
Host smart-8d6d4cb3-57bd-4b82-9f53-e743d004cca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2921872360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2921872360
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2046083114
Short name T214
Test name
Test status
Simulation time 24363779291 ps
CPU time 252.69 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:11:25 PM PDT 24
Peak memory 255012 kb
Host smart-c2e8dc3b-c077-4117-afbf-1f6954039c85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046083114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2046083114
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.408240558
Short name T891
Test name
Test status
Simulation time 5996955675 ps
CPU time 4.64 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:09 PM PDT 24
Peak memory 216372 kb
Host smart-3833e9ca-dd79-46d3-a37d-ab5516636b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408240558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.408240558
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1540840151
Short name T355
Test name
Test status
Simulation time 11692608232 ps
CPU time 10.73 seconds
Started May 14 01:06:46 PM PDT 24
Finished May 14 01:07:15 PM PDT 24
Peak memory 216504 kb
Host smart-0d6df205-e598-4071-b8ca-58caf662c365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540840151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1540840151
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3253989059
Short name T323
Test name
Test status
Simulation time 1016469732 ps
CPU time 2.99 seconds
Started May 14 01:06:47 PM PDT 24
Finished May 14 01:07:07 PM PDT 24
Peak memory 216356 kb
Host smart-e98f77a9-918b-4cf5-8d75-fd0d0a6c4dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253989059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3253989059
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3219774441
Short name T367
Test name
Test status
Simulation time 93171952 ps
CPU time 0.92 seconds
Started May 14 01:06:49 PM PDT 24
Finished May 14 01:07:06 PM PDT 24
Peak memory 205876 kb
Host smart-41662c94-6c5e-4830-94b1-92973e65469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219774441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3219774441
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.6477561
Short name T547
Test name
Test status
Simulation time 807767243 ps
CPU time 4.22 seconds
Started May 14 01:06:49 PM PDT 24
Finished May 14 01:07:09 PM PDT 24
Peak memory 234152 kb
Host smart-abfabb66-6851-44d6-96eb-bbfcedf1874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6477561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.6477561
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.882740495
Short name T456
Test name
Test status
Simulation time 35113320 ps
CPU time 0.78 seconds
Started May 14 01:07:08 PM PDT 24
Finished May 14 01:07:12 PM PDT 24
Peak memory 205340 kb
Host smart-20d0b826-8cf1-4d6c-bd48-b94685710a76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882740495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.882740495
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2508438654
Short name T325
Test name
Test status
Simulation time 57476785 ps
CPU time 2.56 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:15 PM PDT 24
Peak memory 221352 kb
Host smart-80058136-60ae-4666-b4a2-6b1dfae75db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508438654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2508438654
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3663830355
Short name T348
Test name
Test status
Simulation time 61814062 ps
CPU time 0.8 seconds
Started May 14 01:07:11 PM PDT 24
Finished May 14 01:07:15 PM PDT 24
Peak memory 206144 kb
Host smart-9ed87cb6-8311-4162-b9b2-f4c134f102e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663830355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3663830355
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1076819149
Short name T169
Test name
Test status
Simulation time 3559984601 ps
CPU time 27.98 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 224584 kb
Host smart-c11ff9ac-4bf6-46ef-a4f4-0f8506a2033a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076819149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1076819149
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3736961950
Short name T625
Test name
Test status
Simulation time 1173785166 ps
CPU time 29.12 seconds
Started May 14 01:07:05 PM PDT 24
Finished May 14 01:07:38 PM PDT 24
Peak memory 238044 kb
Host smart-ff4994df-7e90-481c-928f-a9450fd21363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736961950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3736961950
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3521960202
Short name T140
Test name
Test status
Simulation time 3003846797 ps
CPU time 42.17 seconds
Started May 14 01:07:08 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 252336 kb
Host smart-64022695-86ad-4b7e-b419-b95b90dea6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521960202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3521960202
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1803640103
Short name T302
Test name
Test status
Simulation time 2872242145 ps
CPU time 34.7 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 232896 kb
Host smart-137ac9be-953e-4f08-bd9a-cb581dc3a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803640103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1803640103
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3979387882
Short name T721
Test name
Test status
Simulation time 121541933 ps
CPU time 2.41 seconds
Started May 14 01:07:12 PM PDT 24
Finished May 14 01:07:17 PM PDT 24
Peak memory 221380 kb
Host smart-012acbad-d865-48a7-ab82-dbff083ff5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979387882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3979387882
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.951917982
Short name T208
Test name
Test status
Simulation time 18744195603 ps
CPU time 40.41 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 233928 kb
Host smart-ab040fd2-cbe5-444d-bfc5-2b6799828a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951917982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.951917982
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2195035133
Short name T519
Test name
Test status
Simulation time 27984891569 ps
CPU time 20.28 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 235792 kb
Host smart-5b7934f3-d015-4aa9-9ddc-5a73044e3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195035133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2195035133
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2270459553
Short name T701
Test name
Test status
Simulation time 8294457236 ps
CPU time 23.44 seconds
Started May 14 01:07:08 PM PDT 24
Finished May 14 01:07:35 PM PDT 24
Peak memory 249292 kb
Host smart-b40145e7-027f-48a2-a151-49d167339c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270459553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2270459553
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.650639813
Short name T617
Test name
Test status
Simulation time 443438298 ps
CPU time 3.49 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:16 PM PDT 24
Peak memory 222976 kb
Host smart-639e4eee-ed79-4e25-8413-7eb391e29109
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650639813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.650639813
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2970518907
Short name T223
Test name
Test status
Simulation time 24457383011 ps
CPU time 252.06 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:11:25 PM PDT 24
Peak memory 256800 kb
Host smart-2439d504-08a7-468f-b26b-2d5c0a25dee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970518907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2970518907
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1046555999
Short name T974
Test name
Test status
Simulation time 1614907191 ps
CPU time 4.75 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 216372 kb
Host smart-ea8b8394-2696-4784-a925-8b71e6d5f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046555999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1046555999
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3298466937
Short name T489
Test name
Test status
Simulation time 934413490 ps
CPU time 5.84 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 216376 kb
Host smart-d148824e-8dce-4c1c-b063-b7dad54363de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298466937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3298466937
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4177819874
Short name T420
Test name
Test status
Simulation time 52169809 ps
CPU time 0.9 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:13 PM PDT 24
Peak memory 206764 kb
Host smart-00470779-8e4a-43eb-a7f1-9927ac42f473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177819874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4177819874
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1163952389
Short name T496
Test name
Test status
Simulation time 80565793 ps
CPU time 0.91 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:14 PM PDT 24
Peak memory 205824 kb
Host smart-e1b4640f-a5d5-45e6-9da3-78964db5a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163952389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1163952389
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1830484813
Short name T961
Test name
Test status
Simulation time 4814642386 ps
CPU time 8.9 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:21 PM PDT 24
Peak memory 236344 kb
Host smart-f3ea2a0f-5e43-41af-807d-262e1ee98a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830484813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1830484813
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3641186937
Short name T491
Test name
Test status
Simulation time 12157577 ps
CPU time 0.72 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:07:28 PM PDT 24
Peak memory 205696 kb
Host smart-f3db56a2-905c-46c8-ab0c-fd7764dd4d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641186937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3641186937
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.464981864
Short name T673
Test name
Test status
Simulation time 6081281749 ps
CPU time 14.17 seconds
Started May 14 01:07:24 PM PDT 24
Finished May 14 01:07:40 PM PDT 24
Peak memory 219940 kb
Host smart-a126bce4-5619-45ed-a8df-50ad065d5987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464981864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.464981864
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3833353607
Short name T970
Test name
Test status
Simulation time 78934331 ps
CPU time 0.82 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:14 PM PDT 24
Peak memory 206448 kb
Host smart-879710cb-6a76-4633-a1ef-3242b5b9f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833353607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3833353607
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1075798076
Short name T651
Test name
Test status
Simulation time 19248448122 ps
CPU time 165.46 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:10:17 PM PDT 24
Peak memory 235916 kb
Host smart-68dc97ff-629e-418a-b587-41085e405655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075798076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1075798076
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.661993156
Short name T15
Test name
Test status
Simulation time 3956145426 ps
CPU time 27.35 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 241208 kb
Host smart-bdc9f27a-e6e2-4b18-9879-0db9653c2440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661993156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.661993156
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4091060647
Short name T309
Test name
Test status
Simulation time 124876398 ps
CPU time 4.79 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:07:37 PM PDT 24
Peak memory 232788 kb
Host smart-693cb2d1-2421-497b-8268-7a18cc82c4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091060647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4091060647
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1457189677
Short name T8
Test name
Test status
Simulation time 3566793486 ps
CPU time 19.55 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 234540 kb
Host smart-fa8275ae-3267-44fa-9218-fff8ba046d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457189677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1457189677
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.931278381
Short name T501
Test name
Test status
Simulation time 631656762 ps
CPU time 5.12 seconds
Started May 14 01:07:11 PM PDT 24
Finished May 14 01:07:19 PM PDT 24
Peak memory 232368 kb
Host smart-d4bd90f7-0b4e-469d-9556-852de1bb936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931278381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.931278381
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1679444032
Short name T627
Test name
Test status
Simulation time 361535227 ps
CPU time 4.67 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:18 PM PDT 24
Peak memory 216884 kb
Host smart-96db0eb4-02e0-40d8-8841-f340a6406c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679444032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1679444032
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2497355619
Short name T554
Test name
Test status
Simulation time 6673739923 ps
CPU time 7.92 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:21 PM PDT 24
Peak memory 218892 kb
Host smart-4dc9365c-3311-465f-af90-cd96786971b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497355619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2497355619
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.67820531
Short name T898
Test name
Test status
Simulation time 3768864800 ps
CPU time 10.58 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:39 PM PDT 24
Peak memory 223172 kb
Host smart-a7af5cee-3c62-42b1-bbba-b533750bc7d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=67820531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.67820531
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2321326199
Short name T759
Test name
Test status
Simulation time 18190333319 ps
CPU time 153.47 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:10:03 PM PDT 24
Peak memory 257376 kb
Host smart-f9655057-bec1-40be-bd07-d09a01bf56f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321326199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2321326199
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.848508383
Short name T130
Test name
Test status
Simulation time 4464347329 ps
CPU time 16.86 seconds
Started May 14 01:07:10 PM PDT 24
Finished May 14 01:07:30 PM PDT 24
Peak memory 216476 kb
Host smart-cb9c50d6-efe7-42a4-a90d-5126d2072780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848508383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.848508383
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1705758828
Short name T850
Test name
Test status
Simulation time 3354322760 ps
CPU time 3.99 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:17 PM PDT 24
Peak memory 216576 kb
Host smart-387e6b02-7c2c-49d1-a964-adde7f993613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705758828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1705758828
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4050115723
Short name T406
Test name
Test status
Simulation time 62308989 ps
CPU time 1.34 seconds
Started May 14 01:07:06 PM PDT 24
Finished May 14 01:07:11 PM PDT 24
Peak memory 216260 kb
Host smart-6ea56a88-1b61-4f4c-a150-120f2256ff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050115723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4050115723
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.780370182
Short name T637
Test name
Test status
Simulation time 57692664 ps
CPU time 0.73 seconds
Started May 14 01:07:09 PM PDT 24
Finished May 14 01:07:14 PM PDT 24
Peak memory 205792 kb
Host smart-dcf9b190-564b-4257-90ae-20c035391b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780370182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.780370182
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3521039586
Short name T586
Test name
Test status
Simulation time 30562016259 ps
CPU time 28.6 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 235280 kb
Host smart-a8d6a6a8-6b83-406f-98ec-01acd6095784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521039586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3521039586
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3471735352
Short name T650
Test name
Test status
Simulation time 37424405 ps
CPU time 0.7 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:31 PM PDT 24
Peak memory 205388 kb
Host smart-42a46bf6-0f96-43a8-9971-b19df027d7d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471735352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3471735352
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3580329693
Short name T449
Test name
Test status
Simulation time 175365429 ps
CPU time 4.26 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:07:36 PM PDT 24
Peak memory 233800 kb
Host smart-c44c8b6d-11f5-438f-8696-3140c2268225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580329693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3580329693
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.837595919
Short name T339
Test name
Test status
Simulation time 44156444 ps
CPU time 0.77 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:31 PM PDT 24
Peak memory 206800 kb
Host smart-e2e4f5e5-af3c-43f1-9782-650a9928a591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837595919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.837595919
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1290806161
Short name T774
Test name
Test status
Simulation time 135325861050 ps
CPU time 222.61 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:11:13 PM PDT 24
Peak memory 257248 kb
Host smart-1d31395c-3114-4720-bebf-fa9e02b68b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290806161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1290806161
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1839593044
Short name T404
Test name
Test status
Simulation time 18612721587 ps
CPU time 80.32 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 255560 kb
Host smart-6d76a12b-efee-4acc-a64e-b3cdb72aec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839593044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1839593044
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2600465893
Short name T955
Test name
Test status
Simulation time 4950078757 ps
CPU time 95.37 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:09:05 PM PDT 24
Peak memory 252572 kb
Host smart-3d13cd35-3e5c-474e-88e2-727e05f98ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600465893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2600465893
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.78284878
Short name T902
Test name
Test status
Simulation time 4017796613 ps
CPU time 14.38 seconds
Started May 14 01:07:24 PM PDT 24
Finished May 14 01:07:40 PM PDT 24
Peak memory 224648 kb
Host smart-8e3a041f-c01a-4a4a-8cd7-d83c86b67838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78284878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.78284878
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2805228950
Short name T264
Test name
Test status
Simulation time 4828777994 ps
CPU time 14.44 seconds
Started May 14 01:07:24 PM PDT 24
Finished May 14 01:07:39 PM PDT 24
Peak memory 235232 kb
Host smart-3b58a675-e369-443c-9297-bb814b5100de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805228950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2805228950
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3559349912
Short name T832
Test name
Test status
Simulation time 10371408067 ps
CPU time 88.27 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:08:54 PM PDT 24
Peak memory 233460 kb
Host smart-8f272ce6-e586-400a-8bfb-c9dbb5761c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559349912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3559349912
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.308597836
Short name T277
Test name
Test status
Simulation time 470038412 ps
CPU time 7.05 seconds
Started May 14 01:07:33 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 237708 kb
Host smart-b41fae84-3c32-4763-ba14-8fe270e2f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308597836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.308597836
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1458670612
Short name T47
Test name
Test status
Simulation time 101978477 ps
CPU time 3.22 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:34 PM PDT 24
Peak memory 224492 kb
Host smart-fcff1c9d-1006-4354-9bdb-80bff8b018a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458670612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1458670612
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3072737089
Short name T944
Test name
Test status
Simulation time 493051596 ps
CPU time 8.91 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:38 PM PDT 24
Peak memory 219180 kb
Host smart-8cda2f5a-952f-4a9e-aa10-59445344c5f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3072737089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3072737089
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.33949713
Short name T22
Test name
Test status
Simulation time 87190806285 ps
CPU time 499.84 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 270676 kb
Host smart-41d524c0-42b3-44ac-b362-d0154679ca48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress
_all.33949713
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4134772607
Short name T602
Test name
Test status
Simulation time 49515906294 ps
CPU time 42.22 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:08:13 PM PDT 24
Peak memory 216472 kb
Host smart-108df5d1-fb33-49a0-b360-09936660a809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134772607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4134772607
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1776692474
Short name T717
Test name
Test status
Simulation time 5784704274 ps
CPU time 13.66 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:45 PM PDT 24
Peak memory 216460 kb
Host smart-05c94bd8-8df9-485d-9d42-c69e08a23be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776692474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1776692474
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1192601556
Short name T684
Test name
Test status
Simulation time 897469508 ps
CPU time 2.55 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:33 PM PDT 24
Peak memory 216460 kb
Host smart-f394acac-98c8-43f0-9042-e036764d7ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192601556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1192601556
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2750404684
Short name T964
Test name
Test status
Simulation time 60402803 ps
CPU time 0.88 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:30 PM PDT 24
Peak memory 205760 kb
Host smart-0851272f-5ee4-4494-bac5-35b0430b5440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750404684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2750404684
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3524093376
Short name T797
Test name
Test status
Simulation time 339871445 ps
CPU time 4.26 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:07:37 PM PDT 24
Peak memory 234668 kb
Host smart-5ee06101-a3af-428f-9e6a-2cab58926a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524093376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3524093376
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3104457828
Short name T805
Test name
Test status
Simulation time 47482953 ps
CPU time 0.73 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:07:28 PM PDT 24
Peak memory 205672 kb
Host smart-7b8213e7-8efe-4dc3-a461-4df13c56becd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104457828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3104457828
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2797499888
Short name T525
Test name
Test status
Simulation time 157801057 ps
CPU time 2.61 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 235280 kb
Host smart-bf002d13-e07b-41ce-a359-67c7d731862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797499888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2797499888
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.459233314
Short name T593
Test name
Test status
Simulation time 47960418 ps
CPU time 0.74 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:07:27 PM PDT 24
Peak memory 205360 kb
Host smart-4e108ba0-a45d-4d96-b7f5-7211e0395363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459233314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.459233314
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1972099634
Short name T548
Test name
Test status
Simulation time 8189687659 ps
CPU time 72.32 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:08:38 PM PDT 24
Peak memory 238180 kb
Host smart-0b56ce43-0ef4-4958-ab12-77982e95f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972099634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1972099634
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.961260904
Short name T746
Test name
Test status
Simulation time 29072248599 ps
CPU time 76.44 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:08:49 PM PDT 24
Peak memory 238024 kb
Host smart-edb224bc-0870-42bb-bbca-759ec2b90392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961260904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.961260904
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4056466136
Short name T45
Test name
Test status
Simulation time 16991660608 ps
CPU time 70.14 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:08:41 PM PDT 24
Peak memory 249320 kb
Host smart-ae2bb057-8ec9-4c96-b0be-4face872a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056466136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4056466136
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.754271967
Short name T303
Test name
Test status
Simulation time 806535066 ps
CPU time 5.48 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:35 PM PDT 24
Peak memory 232792 kb
Host smart-ea2c7b35-e3af-40e5-b55f-4f67cdfdcfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754271967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.754271967
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3928892399
Short name T626
Test name
Test status
Simulation time 475658222 ps
CPU time 6.56 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:37 PM PDT 24
Peak memory 216612 kb
Host smart-1f886246-dd7c-486e-9473-16e27f7b9f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928892399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3928892399
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1810688816
Short name T48
Test name
Test status
Simulation time 2222838330 ps
CPU time 7.16 seconds
Started May 14 01:07:24 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 228736 kb
Host smart-ae2becac-b549-42a2-9628-3c81d873f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810688816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1810688816
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.567015183
Short name T730
Test name
Test status
Simulation time 1138227201 ps
CPU time 4.42 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:34 PM PDT 24
Peak memory 233092 kb
Host smart-13196d07-6f3b-47cf-aa6b-4a7eb6579b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567015183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.567015183
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1187035378
Short name T913
Test name
Test status
Simulation time 133903747 ps
CPU time 2.5 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:07:34 PM PDT 24
Peak memory 221364 kb
Host smart-c0197afb-77b4-4099-aa56-026508fd5a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187035378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1187035378
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1920379075
Short name T745
Test name
Test status
Simulation time 356122785 ps
CPU time 3.93 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:34 PM PDT 24
Peak memory 222272 kb
Host smart-8d1d15ff-8413-44d5-82a6-45f401428622
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1920379075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1920379075
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3919406867
Short name T156
Test name
Test status
Simulation time 74481494857 ps
CPU time 616.46 seconds
Started May 14 01:07:24 PM PDT 24
Finished May 14 01:17:42 PM PDT 24
Peak memory 263056 kb
Host smart-853b70e0-3afb-4eef-a4ea-c158820a0d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919406867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3919406867
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1448661890
Short name T680
Test name
Test status
Simulation time 3860476586 ps
CPU time 22.01 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:07:54 PM PDT 24
Peak memory 216428 kb
Host smart-6aa61e2d-295d-4ef2-9db0-99c4fa7c0290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448661890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1448661890
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1216717227
Short name T542
Test name
Test status
Simulation time 45677651 ps
CPU time 0.75 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 205580 kb
Host smart-589666d7-02d0-496a-a529-86cdf7bef36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216717227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1216717227
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.748548956
Short name T335
Test name
Test status
Simulation time 93415334 ps
CPU time 1.06 seconds
Started May 14 01:07:24 PM PDT 24
Finished May 14 01:07:26 PM PDT 24
Peak memory 207140 kb
Host smart-a5faee0d-5323-47a6-b1a8-e253e9d9b41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748548956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.748548956
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3237204794
Short name T656
Test name
Test status
Simulation time 135439392 ps
CPU time 0.76 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 205812 kb
Host smart-35faae40-c56f-4089-afcc-670a973728db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237204794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3237204794
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2351843591
Short name T74
Test name
Test status
Simulation time 610017904 ps
CPU time 2.87 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:31 PM PDT 24
Peak memory 217684 kb
Host smart-06858a83-4a28-4522-8fca-c443ce2b60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351843591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2351843591
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2111601338
Short name T60
Test name
Test status
Simulation time 36885904 ps
CPU time 0.67 seconds
Started May 14 01:07:29 PM PDT 24
Finished May 14 01:07:34 PM PDT 24
Peak memory 205336 kb
Host smart-1784e5ed-358a-422a-96d4-8d89009f0937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111601338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2111601338
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1652715399
Short name T90
Test name
Test status
Simulation time 237860161 ps
CPU time 2.6 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:33 PM PDT 24
Peak memory 233756 kb
Host smart-27172124-8db7-4594-b2d9-5cfeec0530b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652715399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1652715399
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.969372341
Short name T372
Test name
Test status
Simulation time 21362711 ps
CPU time 0.72 seconds
Started May 14 01:07:25 PM PDT 24
Finished May 14 01:07:28 PM PDT 24
Peak memory 205436 kb
Host smart-14a7b920-9584-4f93-ad6a-3ed4e3aa654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969372341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.969372341
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.27000078
Short name T711
Test name
Test status
Simulation time 70464910 ps
CPU time 0.81 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 215960 kb
Host smart-cf601213-0f7e-4e7c-ac44-9692c6aadc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27000078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.27000078
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.705546831
Short name T172
Test name
Test status
Simulation time 54418986376 ps
CPU time 300.4 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:12:32 PM PDT 24
Peak memory 257788 kb
Host smart-6dbf53e7-040d-4d78-9aa2-8357f76016e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705546831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.705546831
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3426821218
Short name T322
Test name
Test status
Simulation time 116676513 ps
CPU time 3.75 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:33 PM PDT 24
Peak memory 229368 kb
Host smart-9d55c06d-330e-4408-8dff-6e8f0f690168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426821218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3426821218
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3467140762
Short name T167
Test name
Test status
Simulation time 761567368 ps
CPU time 4.42 seconds
Started May 14 01:07:28 PM PDT 24
Finished May 14 01:07:36 PM PDT 24
Peak memory 234204 kb
Host smart-fcf1b4b5-70a0-4313-bc67-49956111a5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467140762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3467140762
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1909608032
Short name T968
Test name
Test status
Simulation time 1320029192 ps
CPU time 19.47 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:50 PM PDT 24
Peak memory 240924 kb
Host smart-de0031ed-caff-429f-ae27-1553e062ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909608032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1909608032
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1778988812
Short name T969
Test name
Test status
Simulation time 2678144124 ps
CPU time 12.34 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 237980 kb
Host smart-28555744-d683-4e70-9ef9-a1b9b6a87f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778988812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1778988812
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1083434687
Short name T447
Test name
Test status
Simulation time 1919725802 ps
CPU time 12.63 seconds
Started May 14 01:07:30 PM PDT 24
Finished May 14 01:07:46 PM PDT 24
Peak memory 248716 kb
Host smart-96c26a8c-c7cb-42b9-bbd3-6605bf136c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083434687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1083434687
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3454571708
Short name T147
Test name
Test status
Simulation time 2358457179 ps
CPU time 6.26 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:37 PM PDT 24
Peak memory 223080 kb
Host smart-cba778d7-f753-42fe-97a2-f94a6c373e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3454571708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3454571708
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1844577554
Short name T143
Test name
Test status
Simulation time 24065978537 ps
CPU time 101.28 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:09:12 PM PDT 24
Peak memory 249304 kb
Host smart-7f8573bb-7809-4aba-97d4-3e0de8260e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844577554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1844577554
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.494713882
Short name T767
Test name
Test status
Simulation time 2519637116 ps
CPU time 4.69 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:35 PM PDT 24
Peak memory 216484 kb
Host smart-ce7341d9-23a6-4960-b880-8b9e6d18a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494713882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.494713882
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3989917634
Short name T927
Test name
Test status
Simulation time 12396664 ps
CPU time 0.7 seconds
Started May 14 01:07:26 PM PDT 24
Finished May 14 01:07:30 PM PDT 24
Peak memory 205580 kb
Host smart-82bd1bad-53e9-4a42-9d0c-0beee51ee0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989917634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3989917634
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.402623073
Short name T3
Test name
Test status
Simulation time 28732462 ps
CPU time 0.69 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 205388 kb
Host smart-64e38344-28fe-47b9-b6b2-dd65841ede7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402623073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.402623073
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1799089570
Short name T68
Test name
Test status
Simulation time 164442897 ps
CPU time 0.77 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:32 PM PDT 24
Peak memory 205784 kb
Host smart-0005c92c-955c-44e9-809e-ff7b1c6432bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799089570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1799089570
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3028223238
Short name T939
Test name
Test status
Simulation time 9432279764 ps
CPU time 11.28 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 234104 kb
Host smart-e7efe278-5fc8-4678-9426-69e283bc9150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028223238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3028223238
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2375672618
Short name T580
Test name
Test status
Simulation time 19083369 ps
CPU time 0.72 seconds
Started May 14 01:07:33 PM PDT 24
Finished May 14 01:07:36 PM PDT 24
Peak memory 205296 kb
Host smart-64fafcbf-516c-4094-879d-c0eff1d8bbc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375672618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2375672618
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3170540371
Short name T32
Test name
Test status
Simulation time 935272518 ps
CPU time 6.65 seconds
Started May 14 01:07:33 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 234288 kb
Host smart-3e285299-a0a0-4afc-9ffe-e3e7f317bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170540371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3170540371
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1219495897
Short name T812
Test name
Test status
Simulation time 13792980 ps
CPU time 0.79 seconds
Started May 14 01:07:29 PM PDT 24
Finished May 14 01:07:34 PM PDT 24
Peak memory 205336 kb
Host smart-92a579bd-4319-4265-8a00-127e4a4b668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219495897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1219495897
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3351766763
Short name T221
Test name
Test status
Simulation time 9835924375 ps
CPU time 88 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:09:11 PM PDT 24
Peak memory 262788 kb
Host smart-7ca85248-4cc7-4aa9-a1aa-eea092998616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351766763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3351766763
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4036902251
Short name T224
Test name
Test status
Simulation time 328410008891 ps
CPU time 542.74 seconds
Started May 14 01:07:34 PM PDT 24
Finished May 14 01:16:38 PM PDT 24
Peak memory 273276 kb
Host smart-28449e3c-a0c3-4bb2-b8a2-1e7dd5161403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036902251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4036902251
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.180263948
Short name T129
Test name
Test status
Simulation time 21419339564 ps
CPU time 39.36 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 240080 kb
Host smart-22a8157e-8feb-4791-966f-23c1da8c7c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180263948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.180263948
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_intercept.470697039
Short name T630
Test name
Test status
Simulation time 1679700768 ps
CPU time 8.37 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 233176 kb
Host smart-5e7e4fe4-e663-43c8-bc87-94ec6a6ea662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470697039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.470697039
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4217583253
Short name T849
Test name
Test status
Simulation time 1262880414 ps
CPU time 10.71 seconds
Started May 14 01:07:35 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 218552 kb
Host smart-cd742925-e848-46a7-bdc9-d1050f8e3a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217583253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4217583253
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2807676636
Short name T686
Test name
Test status
Simulation time 25464329231 ps
CPU time 15.26 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:58 PM PDT 24
Peak memory 234840 kb
Host smart-f0f22989-ed6f-40b8-ae5c-a1505b669926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807676636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2807676636
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1646408551
Short name T194
Test name
Test status
Simulation time 1377509633 ps
CPU time 5.23 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 218540 kb
Host smart-946fe62a-f6a4-4245-8b5b-b9489afb2460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646408551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1646408551
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.901563565
Short name T556
Test name
Test status
Simulation time 1192466603 ps
CPU time 9.13 seconds
Started May 14 01:07:41 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 218724 kb
Host smart-50d02f01-eecd-4d55-8e7e-819766c30255
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=901563565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.901563565
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2041899637
Short name T778
Test name
Test status
Simulation time 119528484 ps
CPU time 1.07 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 207092 kb
Host smart-99542d15-6746-4935-b7ca-cccd97e72e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041899637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2041899637
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.222130096
Short name T463
Test name
Test status
Simulation time 430268756 ps
CPU time 7.5 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:46 PM PDT 24
Peak memory 216472 kb
Host smart-916e28f2-ec40-404b-85d8-c327dfd42da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222130096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.222130096
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1934820593
Short name T886
Test name
Test status
Simulation time 24005674007 ps
CPU time 13.79 seconds
Started May 14 01:07:27 PM PDT 24
Finished May 14 01:07:45 PM PDT 24
Peak memory 216508 kb
Host smart-d63638bc-4dcb-4b58-8778-0d5dfececbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934820593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1934820593
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.735289654
Short name T421
Test name
Test status
Simulation time 58084780 ps
CPU time 1.06 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:40 PM PDT 24
Peak memory 207432 kb
Host smart-9bf7880c-7705-421d-9681-47611e14a55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735289654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.735289654
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3093928520
Short name T873
Test name
Test status
Simulation time 41715870 ps
CPU time 0.7 seconds
Started May 14 01:07:35 PM PDT 24
Finished May 14 01:07:37 PM PDT 24
Peak memory 205496 kb
Host smart-61720b6c-05b3-4049-9e93-3c8aa965a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093928520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3093928520
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.652220883
Short name T772
Test name
Test status
Simulation time 5941685993 ps
CPU time 7.86 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:47 PM PDT 24
Peak memory 224612 kb
Host smart-e943b72e-d6f8-4f62-9303-05726c3d02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652220883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.652220883
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2338588081
Short name T536
Test name
Test status
Simulation time 14992849 ps
CPU time 0.71 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 205652 kb
Host smart-11ea0ccb-ce30-4a06-89c4-e9e31675fed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338588081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2338588081
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2207895150
Short name T757
Test name
Test status
Simulation time 605170799 ps
CPU time 4.28 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:47 PM PDT 24
Peak memory 218580 kb
Host smart-d0f8d7b9-270b-433b-9a08-bf29d36b0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207895150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2207895150
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.84396434
Short name T69
Test name
Test status
Simulation time 22680890 ps
CPU time 0.81 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:39 PM PDT 24
Peak memory 206468 kb
Host smart-ed143467-6b5b-4a2e-88c7-00f3a477ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84396434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.84396434
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1950666166
Short name T828
Test name
Test status
Simulation time 97570975715 ps
CPU time 174.66 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:10:33 PM PDT 24
Peak memory 249256 kb
Host smart-fdb222b3-975b-400b-bf40-15d020bfaa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950666166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1950666166
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2068224959
Short name T590
Test name
Test status
Simulation time 4457634300 ps
CPU time 3.64 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 217584 kb
Host smart-51abb9c4-bfd7-4c51-9dc3-a37e81d3373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068224959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2068224959
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3615400518
Short name T696
Test name
Test status
Simulation time 1307581269 ps
CPU time 22.52 seconds
Started May 14 01:07:41 PM PDT 24
Finished May 14 01:08:07 PM PDT 24
Peak memory 238520 kb
Host smart-89e381cd-720c-491a-9c86-5d2a68a1a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615400518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3615400518
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1148796008
Short name T936
Test name
Test status
Simulation time 1672863557 ps
CPU time 16.98 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:54 PM PDT 24
Peak memory 232760 kb
Host smart-6e09af88-7820-47d6-8120-90755a4e9496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148796008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1148796008
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3034603649
Short name T173
Test name
Test status
Simulation time 4865551330 ps
CPU time 18.91 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:57 PM PDT 24
Peak memory 218968 kb
Host smart-b2960792-7ee2-420a-b1ac-3e073f9ff681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034603649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3034603649
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.182907926
Short name T451
Test name
Test status
Simulation time 4582496857 ps
CPU time 39.63 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:08:23 PM PDT 24
Peak memory 218616 kb
Host smart-1370d909-1a93-422d-8833-82b214f4290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182907926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.182907926
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1982321490
Short name T92
Test name
Test status
Simulation time 237090843 ps
CPU time 2.98 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 233716 kb
Host smart-f0eeaad3-ab8c-464b-949d-cc834057f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982321490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1982321490
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4121084257
Short name T286
Test name
Test status
Simulation time 2423991077 ps
CPU time 6.71 seconds
Started May 14 01:07:35 PM PDT 24
Finished May 14 01:07:44 PM PDT 24
Peak memory 233776 kb
Host smart-aaf2339e-3c6d-4148-8393-4dc1d6a0bb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121084257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4121084257
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3567029246
Short name T384
Test name
Test status
Simulation time 199392199 ps
CPU time 4.23 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 222996 kb
Host smart-15a5f757-cfbb-4bfb-83d5-334750f68f8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567029246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3567029246
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3817089200
Short name T895
Test name
Test status
Simulation time 1175156533 ps
CPU time 9.85 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 216408 kb
Host smart-917f46eb-05c6-40a3-a1a2-36a73b01689d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817089200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3817089200
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2179186486
Short name T869
Test name
Test status
Simulation time 31698504082 ps
CPU time 11.15 seconds
Started May 14 01:07:41 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 217588 kb
Host smart-0ed0e26b-0f87-4984-9ced-85153d19962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179186486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2179186486
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3992857019
Short name T414
Test name
Test status
Simulation time 50347416 ps
CPU time 0.88 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:40 PM PDT 24
Peak memory 206960 kb
Host smart-d2d80bcb-a5db-4126-9406-5515fa89c5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992857019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3992857019
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4160132914
Short name T732
Test name
Test status
Simulation time 301865141 ps
CPU time 1.01 seconds
Started May 14 01:07:34 PM PDT 24
Finished May 14 01:07:36 PM PDT 24
Peak memory 206052 kb
Host smart-7d336c0d-4150-487d-8e9b-71dbfc3ceb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160132914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4160132914
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3956238998
Short name T635
Test name
Test status
Simulation time 533576251 ps
CPU time 7.92 seconds
Started May 14 01:07:35 PM PDT 24
Finished May 14 01:07:45 PM PDT 24
Peak memory 219472 kb
Host smart-3c0fded1-2927-4cdc-bd2c-cde7c3af3eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956238998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3956238998
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2597454352
Short name T566
Test name
Test status
Simulation time 46134335 ps
CPU time 0.71 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 204720 kb
Host smart-bb92ca0e-7e5c-4999-8aaf-d21725cc1e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597454352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2597454352
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.795587791
Short name T503
Test name
Test status
Simulation time 917179922 ps
CPU time 5.26 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 218500 kb
Host smart-092e198d-769b-4eeb-8b1b-0958e1df6898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795587791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.795587791
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.67180753
Short name T753
Test name
Test status
Simulation time 18474670 ps
CPU time 0.74 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 205400 kb
Host smart-52779156-8593-4238-90b9-72bdda643ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67180753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.67180753
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1080023178
Short name T834
Test name
Test status
Simulation time 5797486204 ps
CPU time 33.26 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 241164 kb
Host smart-7e4eb1dd-b8f7-4653-8e0a-1416b3f4b7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080023178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1080023178
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1343406300
Short name T716
Test name
Test status
Simulation time 79469641202 ps
CPU time 190.3 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:10:52 PM PDT 24
Peak memory 249328 kb
Host smart-f2b21f29-64bc-474d-8835-04aacc33b1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343406300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1343406300
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2675886947
Short name T12
Test name
Test status
Simulation time 70552186 ps
CPU time 3.25 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 224484 kb
Host smart-25c8eee3-aeea-447c-ab4b-281479dab526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675886947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2675886947
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2821248893
Short name T846
Test name
Test status
Simulation time 124248934 ps
CPU time 2.55 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:07:46 PM PDT 24
Peak memory 224428 kb
Host smart-3d0b7f3f-f560-4f33-899e-9d87fc42361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821248893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2821248893
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.906183942
Short name T857
Test name
Test status
Simulation time 7239402987 ps
CPU time 27.44 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 224596 kb
Host smart-99c2d879-61f0-4f8d-869e-3af0fd60eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906183942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.906183942
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1032475029
Short name T206
Test name
Test status
Simulation time 45702003 ps
CPU time 2.61 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 232740 kb
Host smart-65a14324-6993-4330-b167-69002e42917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032475029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1032475029
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3301777610
Short name T178
Test name
Test status
Simulation time 740408269 ps
CPU time 3.82 seconds
Started May 14 01:07:36 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 218440 kb
Host smart-c006b2a2-06d3-4b30-b1ac-6ff6134e5d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301777610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3301777610
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1883688528
Short name T405
Test name
Test status
Simulation time 247386502 ps
CPU time 4.15 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:46 PM PDT 24
Peak memory 219260 kb
Host smart-7b9e8cd2-0684-4804-b660-32a5881b0f56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1883688528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1883688528
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3308625412
Short name T862
Test name
Test status
Simulation time 11402255232 ps
CPU time 37.37 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 249452 kb
Host smart-91a093f9-e6c2-4be1-a72a-45ca6be5e095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308625412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3308625412
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3186945518
Short name T931
Test name
Test status
Simulation time 14777035647 ps
CPU time 28.76 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 216460 kb
Host smart-cc9286f9-1e0a-4439-831c-f4c7ca4387cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186945518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3186945518
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1297044143
Short name T73
Test name
Test status
Simulation time 3580080296 ps
CPU time 4.94 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:47 PM PDT 24
Peak memory 216512 kb
Host smart-40389d70-7ee3-4b94-9421-bfb0eb12dd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297044143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1297044143
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3087181943
Short name T545
Test name
Test status
Simulation time 306633495 ps
CPU time 8.19 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:50 PM PDT 24
Peak memory 216448 kb
Host smart-594c5856-80b1-4e4d-870e-2e37c88bb4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087181943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3087181943
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1975673702
Short name T6
Test name
Test status
Simulation time 145648206 ps
CPU time 0.83 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:41 PM PDT 24
Peak memory 205768 kb
Host smart-bc1fbd0f-3a26-4605-b281-97d24062bcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975673702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1975673702
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1017100626
Short name T189
Test name
Test status
Simulation time 2554836807 ps
CPU time 5.07 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:45 PM PDT 24
Peak memory 224540 kb
Host smart-e913f7ef-a28a-47af-9e8a-97d1db5f792f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017100626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1017100626
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1726542434
Short name T928
Test name
Test status
Simulation time 43053361 ps
CPU time 0.75 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:07:44 PM PDT 24
Peak memory 205328 kb
Host smart-b77c244e-44d6-460a-ac8c-4f5d29eb9f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726542434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1726542434
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3350216917
Short name T749
Test name
Test status
Simulation time 521928147 ps
CPU time 4.12 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 219728 kb
Host smart-5587ee88-fd4f-4354-9b10-d670b55d8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350216917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3350216917
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.389918666
Short name T343
Test name
Test status
Simulation time 51369544 ps
CPU time 0.79 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:07:44 PM PDT 24
Peak memory 206684 kb
Host smart-18ce5893-7d29-4367-bba5-6961e0f563bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389918666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.389918666
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2767534036
Short name T299
Test name
Test status
Simulation time 167486683 ps
CPU time 4.89 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 233784 kb
Host smart-3b6fe699-eec2-4a5a-849e-f1a669b2313a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767534036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2767534036
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3848292185
Short name T290
Test name
Test status
Simulation time 49215553505 ps
CPU time 78.95 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 232864 kb
Host smart-f6d12154-eb4b-48c6-bfc0-b85adb183cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848292185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3848292185
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.532165358
Short name T212
Test name
Test status
Simulation time 35755312544 ps
CPU time 130.82 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:09:53 PM PDT 24
Peak memory 255408 kb
Host smart-416214ed-942c-4ea9-9f4e-436d70c6edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532165358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.532165358
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3531404822
Short name T567
Test name
Test status
Simulation time 317530774 ps
CPU time 10.4 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:51 PM PDT 24
Peak memory 249216 kb
Host smart-745fd28c-c81c-4835-b9fe-77c4cbefc53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531404822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3531404822
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.676485235
Short name T91
Test name
Test status
Simulation time 4621897835 ps
CPU time 38.67 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 234172 kb
Host smart-1bcea07c-cf17-4011-9e08-a62f5646867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676485235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.676485235
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1324754181
Short name T202
Test name
Test status
Simulation time 13473103996 ps
CPU time 105.11 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:09:26 PM PDT 24
Peak memory 228232 kb
Host smart-598d41ed-121c-43cf-b6bb-4c109905fe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324754181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1324754181
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2475952372
Short name T975
Test name
Test status
Simulation time 24564069181 ps
CPU time 15.23 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 228544 kb
Host smart-bf3cda20-624d-4cad-8836-bfe06aa184b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475952372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2475952372
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1194704077
Short name T164
Test name
Test status
Simulation time 5988900212 ps
CPU time 16.07 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 218588 kb
Host smart-acc8b4ee-cf46-4a9c-bc1c-4687470c7e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194704077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1194704077
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4079476078
Short name T775
Test name
Test status
Simulation time 1822277664 ps
CPU time 16.53 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:58 PM PDT 24
Peak memory 220696 kb
Host smart-30e63d0f-7954-41d6-8567-d4b60e662a91
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4079476078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4079476078
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1425770807
Short name T579
Test name
Test status
Simulation time 5713118968 ps
CPU time 107.4 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:09:33 PM PDT 24
Peak memory 250388 kb
Host smart-4c89e88d-0d1c-4179-8c81-bb06524e668b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425770807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1425770807
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3711841418
Short name T312
Test name
Test status
Simulation time 1445738454 ps
CPU time 21.57 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:08:03 PM PDT 24
Peak memory 216688 kb
Host smart-05ca10ca-74a6-44f4-92c8-05d90f0f3261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711841418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3711841418
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2242474906
Short name T382
Test name
Test status
Simulation time 3652830598 ps
CPU time 10.7 seconds
Started May 14 01:07:41 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 216516 kb
Host smart-1bd3758e-1414-4f2f-8620-148f91924963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242474906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2242474906
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2530244848
Short name T704
Test name
Test status
Simulation time 272728931 ps
CPU time 1.11 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 206916 kb
Host smart-a3836736-36fe-471e-bda5-4e67a84615bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530244848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2530244848
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1551761398
Short name T330
Test name
Test status
Simulation time 152513665 ps
CPU time 0.85 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 205816 kb
Host smart-d347b5fd-7508-4d18-8496-4f3c68516e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551761398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1551761398
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3352859148
Short name T760
Test name
Test status
Simulation time 6237126577 ps
CPU time 6.98 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 233628 kb
Host smart-17fba4ec-c94e-41b6-9b2e-88e5a8527d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352859148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3352859148
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.264407407
Short name T763
Test name
Test status
Simulation time 15276649 ps
CPU time 0.76 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:23 PM PDT 24
Peak memory 205352 kb
Host smart-b17674a3-689f-4954-bee6-03c1129cb395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264407407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.264407407
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3805339700
Short name T344
Test name
Test status
Simulation time 378661894 ps
CPU time 5.17 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:24 PM PDT 24
Peak memory 218816 kb
Host smart-29c4c5e4-7de4-45d6-8de1-0f73f442de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805339700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3805339700
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1674503859
Short name T739
Test name
Test status
Simulation time 298453419 ps
CPU time 0.79 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 206456 kb
Host smart-663e7593-b2e9-4656-b9a4-f16a2b451c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674503859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1674503859
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3360702426
Short name T949
Test name
Test status
Simulation time 4901014460 ps
CPU time 61.33 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:06:28 PM PDT 24
Peak memory 253620 kb
Host smart-15001502-ecf4-49b5-9b2e-58362277835e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360702426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3360702426
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3256725903
Short name T391
Test name
Test status
Simulation time 9973245877 ps
CPU time 84.57 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:06:50 PM PDT 24
Peak memory 232836 kb
Host smart-684a2760-725c-4d69-97ad-181bfcc280cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256725903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3256725903
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.841386539
Short name T669
Test name
Test status
Simulation time 4731806809 ps
CPU time 39.99 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 248576 kb
Host smart-773750d4-653e-4d7d-8f7e-0b2e6130b3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841386539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
841386539
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2741264795
Short name T443
Test name
Test status
Simulation time 225911224 ps
CPU time 4.95 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:30 PM PDT 24
Peak memory 224528 kb
Host smart-6f8aaa29-d683-4565-b1c6-3a4ad55e43fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741264795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2741264795
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3803137504
Short name T282
Test name
Test status
Simulation time 318301970 ps
CPU time 3.33 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 236052 kb
Host smart-8666f1b4-e6d9-44b6-8164-cf292b11f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803137504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3803137504
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3111985571
Short name T273
Test name
Test status
Simulation time 2538408594 ps
CPU time 15.18 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 240984 kb
Host smart-4b7ccfca-b3dd-43d8-8e22-21216db19974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111985571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3111985571
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2614728576
Short name T839
Test name
Test status
Simulation time 130132128 ps
CPU time 1.08 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:05:19 PM PDT 24
Peak memory 216704 kb
Host smart-aa1f043a-e475-454e-8c13-85e308c1d35c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614728576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2614728576
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.540893566
Short name T240
Test name
Test status
Simulation time 8557174607 ps
CPU time 29.39 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:05:56 PM PDT 24
Peak memory 230968 kb
Host smart-40916647-2262-4801-8da1-20c46f491c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540893566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
540893566
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.584415043
Short name T467
Test name
Test status
Simulation time 4310528699 ps
CPU time 13.82 seconds
Started May 14 01:05:20 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 224560 kb
Host smart-3bbe192d-9e31-483e-b58b-df17f218da9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584415043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.584415043
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.811456179
Short name T860
Test name
Test status
Simulation time 14074736291 ps
CPU time 11.69 seconds
Started May 14 01:05:20 PM PDT 24
Finished May 14 01:05:41 PM PDT 24
Peak memory 223004 kb
Host smart-3d637615-69d8-40fa-b420-295b522e0155
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811456179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.811456179
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1791716524
Short name T65
Test name
Test status
Simulation time 62017519 ps
CPU time 1.12 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:05:19 PM PDT 24
Peak memory 235088 kb
Host smart-dda2e7cb-f309-4f21-9239-b9417589b5a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791716524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1791716524
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1237449710
Short name T511
Test name
Test status
Simulation time 3946569120 ps
CPU time 22.42 seconds
Started May 14 01:05:20 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 220748 kb
Host smart-a75f724b-3a1d-43bc-b3a9-19990395412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237449710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1237449710
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.951218187
Short name T607
Test name
Test status
Simulation time 480651915 ps
CPU time 3.91 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:22 PM PDT 24
Peak memory 216316 kb
Host smart-a6a686e9-824e-4f2f-af76-e297260c72d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951218187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.951218187
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.141907375
Short name T663
Test name
Test status
Simulation time 37046762 ps
CPU time 1.07 seconds
Started May 14 01:05:20 PM PDT 24
Finished May 14 01:05:30 PM PDT 24
Peak memory 207828 kb
Host smart-caa537a8-4060-40b6-9929-f02605a8390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141907375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.141907375
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1899384394
Short name T486
Test name
Test status
Simulation time 273766184 ps
CPU time 0.81 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:26 PM PDT 24
Peak memory 205812 kb
Host smart-d56f5841-1774-4b28-a899-90c19d9ec9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899384394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1899384394
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3731996392
Short name T856
Test name
Test status
Simulation time 4853714212 ps
CPU time 17.49 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:36 PM PDT 24
Peak memory 228224 kb
Host smart-1bf0fba4-aed0-467e-83ad-cad23b5655f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731996392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3731996392
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1930024423
Short name T445
Test name
Test status
Simulation time 41684387 ps
CPU time 0.72 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:07:46 PM PDT 24
Peak memory 204764 kb
Host smart-d1615559-3e7b-4896-96b4-d50eb19c7c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930024423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1930024423
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2738387467
Short name T691
Test name
Test status
Simulation time 956546091 ps
CPU time 3.59 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 234320 kb
Host smart-1375a301-9b15-4301-a4cd-52b80cde466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738387467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2738387467
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2372858731
Short name T943
Test name
Test status
Simulation time 33730781 ps
CPU time 0.78 seconds
Started May 14 01:07:38 PM PDT 24
Finished May 14 01:07:42 PM PDT 24
Peak memory 206764 kb
Host smart-94c4b053-9d87-42d4-8544-77854d86c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372858731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2372858731
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1587037536
Short name T386
Test name
Test status
Simulation time 5399548054 ps
CPU time 25.1 seconds
Started May 14 01:07:40 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 249924 kb
Host smart-e975b9d8-13e8-4ff2-9226-50e35606b91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587037536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1587037536
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4205498438
Short name T959
Test name
Test status
Simulation time 3331559989 ps
CPU time 77.75 seconds
Started May 14 01:07:37 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 254956 kb
Host smart-3e82dec9-05b3-46a9-bb7e-92aae8d67dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205498438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4205498438
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2497144591
Short name T187
Test name
Test status
Simulation time 111994785657 ps
CPU time 290.74 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:12:41 PM PDT 24
Peak memory 253472 kb
Host smart-fd95af3f-ec99-419e-9809-8bdd8dca4432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497144591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2497144591
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1329827056
Short name T877
Test name
Test status
Simulation time 3697887250 ps
CPU time 12.01 seconds
Started May 14 01:07:42 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 225000 kb
Host smart-7ffa8469-b701-49f6-88fc-b4fdc5a8feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329827056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1329827056
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3662797644
Short name T875
Test name
Test status
Simulation time 746513895 ps
CPU time 4.92 seconds
Started May 14 01:07:42 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 219628 kb
Host smart-c5ea84a8-7caf-4d99-bebe-684a72d294c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662797644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3662797644
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3032291185
Short name T196
Test name
Test status
Simulation time 34981932112 ps
CPU time 28.25 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:08:11 PM PDT 24
Peak memory 227600 kb
Host smart-1c133613-54d0-4c50-b78d-561d4d270ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032291185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3032291185
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2092109067
Short name T841
Test name
Test status
Simulation time 31415987529 ps
CPU time 27.03 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 248552 kb
Host smart-78405593-8598-45cc-a5a2-30314b0c745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092109067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2092109067
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3883439232
Short name T565
Test name
Test status
Simulation time 57808385451 ps
CPU time 15.1 seconds
Started May 14 01:07:41 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 233724 kb
Host smart-6b2b9bcf-946e-48f8-9865-78f24131acfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883439232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3883439232
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.250252487
Short name T861
Test name
Test status
Simulation time 139216870 ps
CPU time 4.5 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 222916 kb
Host smart-046af09d-e7b5-4124-b77c-83c9c8835326
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=250252487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.250252487
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.998087956
Short name T608
Test name
Test status
Simulation time 414234058 ps
CPU time 2.09 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:52 PM PDT 24
Peak memory 216420 kb
Host smart-319bce9c-e42a-4a9e-8392-7a26c650ccd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998087956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.998087956
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1100160620
Short name T826
Test name
Test status
Simulation time 21917922616 ps
CPU time 15.9 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:08:06 PM PDT 24
Peak memory 216488 kb
Host smart-d1a3addf-504f-405f-a117-9054396daf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100160620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1100160620
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3270820643
Short name T508
Test name
Test status
Simulation time 30422067 ps
CPU time 1.15 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:51 PM PDT 24
Peak memory 216448 kb
Host smart-4c940bc0-7bc8-4585-a488-e20bc087d1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270820643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3270820643
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.836619011
Short name T366
Test name
Test status
Simulation time 50708115 ps
CPU time 0.88 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:07:43 PM PDT 24
Peak memory 206272 kb
Host smart-e98b37e6-0597-49e7-b95b-2d3fdcd35520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836619011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.836619011
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2293748658
Short name T912
Test name
Test status
Simulation time 34271063617 ps
CPU time 28.46 seconds
Started May 14 01:07:39 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 237888 kb
Host smart-e43d40fb-1161-4ab2-9201-a6ad8e7ca284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293748658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2293748658
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2744992360
Short name T737
Test name
Test status
Simulation time 45323445 ps
CPU time 0.73 seconds
Started May 14 01:07:50 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 205308 kb
Host smart-565bd196-b85a-400a-8d88-26aefba6f6c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744992360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2744992360
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3626409832
Short name T622
Test name
Test status
Simulation time 137929052 ps
CPU time 3.25 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 235836 kb
Host smart-cb09f74a-cd7a-4d84-8700-69a8029a4e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626409832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3626409832
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2100846013
Short name T742
Test name
Test status
Simulation time 25990615 ps
CPU time 0.76 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:07:50 PM PDT 24
Peak memory 205444 kb
Host smart-9228de46-b99a-41ac-bc26-6ae7216807ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100846013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2100846013
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2467605505
Short name T279
Test name
Test status
Simulation time 2980001416 ps
CPU time 15.06 seconds
Started May 14 01:07:43 PM PDT 24
Finished May 14 01:08:00 PM PDT 24
Peak memory 241080 kb
Host smart-43743a2e-458e-45d0-8500-ce7ca18d68bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467605505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2467605505
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4051123191
Short name T338
Test name
Test status
Simulation time 5990900979 ps
CPU time 29.53 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:08:21 PM PDT 24
Peak memory 217432 kb
Host smart-b742e90e-c9d3-4a06-ad05-0450cfabfffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051123191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4051123191
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2539630782
Short name T609
Test name
Test status
Simulation time 140580895497 ps
CPU time 352.15 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:13:41 PM PDT 24
Peak memory 257544 kb
Host smart-ec72b654-1c17-4103-9383-8843338a535d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539630782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2539630782
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.306854523
Short name T311
Test name
Test status
Simulation time 4501093204 ps
CPU time 19.41 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:08:11 PM PDT 24
Peak memory 224672 kb
Host smart-b4afcacd-c0a2-4aae-a285-678154bbbb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306854523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.306854523
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.770736164
Short name T661
Test name
Test status
Simulation time 2184838787 ps
CPU time 26.69 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 218500 kb
Host smart-1ccc5cbe-90dc-4d6c-a735-310b80ba38cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770736164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.770736164
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.352496167
Short name T266
Test name
Test status
Simulation time 2116862788 ps
CPU time 13.09 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 240824 kb
Host smart-347fd7ae-11f1-4006-aa39-4d1217fb8323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352496167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.352496167
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3570174105
Short name T816
Test name
Test status
Simulation time 411267364 ps
CPU time 4.75 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 224480 kb
Host smart-a732429f-b08e-4275-8527-75ec5927d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570174105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3570174105
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1086231923
Short name T747
Test name
Test status
Simulation time 4863079001 ps
CPU time 15.75 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 233312 kb
Host smart-406e525d-0516-4281-88cb-296d3e207771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086231923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1086231923
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2240517669
Short name T822
Test name
Test status
Simulation time 839569981 ps
CPU time 9.6 seconds
Started May 14 01:07:45 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 222204 kb
Host smart-dc67e0d3-067e-4cb4-9e43-bdf794da86fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2240517669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2240517669
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1350672078
Short name T55
Test name
Test status
Simulation time 11815748370 ps
CPU time 32.17 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:08:18 PM PDT 24
Peak memory 224780 kb
Host smart-22fd7d24-4799-47a5-b7c3-94d0f14d2bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350672078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1350672078
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.221779881
Short name T412
Test name
Test status
Simulation time 21421750369 ps
CPU time 28.33 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:08:21 PM PDT 24
Peak memory 216452 kb
Host smart-c93b82b2-f7bc-42c7-b6a9-52fb8743dbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221779881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.221779881
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4088688677
Short name T427
Test name
Test status
Simulation time 1475425256 ps
CPU time 2.88 seconds
Started May 14 01:07:45 PM PDT 24
Finished May 14 01:07:50 PM PDT 24
Peak memory 216408 kb
Host smart-4187ab58-d8b0-48e7-a912-d57d48bdbd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088688677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4088688677
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3726198743
Short name T688
Test name
Test status
Simulation time 954056750 ps
CPU time 2.26 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:07:51 PM PDT 24
Peak memory 216348 kb
Host smart-754a0d8f-9d9a-4264-9a1f-eb6ed3e27155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726198743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3726198743
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3191421090
Short name T738
Test name
Test status
Simulation time 215558164 ps
CPU time 0.88 seconds
Started May 14 01:07:45 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 205868 kb
Host smart-60139f53-8956-4de0-95c1-efc5b0c5f2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191421090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3191421090
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1504916394
Short name T104
Test name
Test status
Simulation time 42993280991 ps
CPU time 19.05 seconds
Started May 14 01:07:45 PM PDT 24
Finished May 14 01:08:06 PM PDT 24
Peak memory 234336 kb
Host smart-45d0ff2f-316d-4617-a127-830c048a9ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504916394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1504916394
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1749447539
Short name T597
Test name
Test status
Simulation time 29861732 ps
CPU time 0.7 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 204648 kb
Host smart-1bc3282f-37c9-418d-ab7d-64d0fb08783f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749447539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1749447539
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1957388775
Short name T699
Test name
Test status
Simulation time 2320948725 ps
CPU time 6.81 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 220132 kb
Host smart-8deb7a34-ed0b-4bab-b27a-a93f4d54e87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957388775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1957388775
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3535710843
Short name T628
Test name
Test status
Simulation time 46359323 ps
CPU time 0.77 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 206440 kb
Host smart-98ca9846-705c-4305-9294-6f936b31d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535710843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3535710843
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1556668714
Short name T620
Test name
Test status
Simulation time 1333135099 ps
CPU time 23.32 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 249068 kb
Host smart-015aff82-4158-4d2f-960d-a316a5dbec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556668714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1556668714
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.76015914
Short name T560
Test name
Test status
Simulation time 18851621820 ps
CPU time 82.97 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:09:15 PM PDT 24
Peak memory 241168 kb
Host smart-4967c145-9999-4d54-b4c9-6a1ccf1b68e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76015914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.76015914
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2270340135
Short name T232
Test name
Test status
Simulation time 4416126371 ps
CPU time 60.51 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:08:50 PM PDT 24
Peak memory 239848 kb
Host smart-d54e0912-cfe4-4904-9f55-b0dd75ba0ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270340135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2270340135
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3571593004
Short name T675
Test name
Test status
Simulation time 223320315 ps
CPU time 3.84 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 224540 kb
Host smart-0b4f812e-6dc0-4c4b-9ed3-72a9cfee4468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571593004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3571593004
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.762683840
Short name T729
Test name
Test status
Simulation time 50432963 ps
CPU time 2.13 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 221560 kb
Host smart-8fc87440-d655-44f3-9b58-a3050c861d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762683840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.762683840
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.225976863
Short name T515
Test name
Test status
Simulation time 43293379455 ps
CPU time 72.62 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:08:58 PM PDT 24
Peak memory 230300 kb
Host smart-fc5206b9-d8ed-4a8a-98b2-a2d41615f177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225976863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.225976863
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2519340597
Short name T267
Test name
Test status
Simulation time 879995791 ps
CPU time 9.81 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:08:00 PM PDT 24
Peak memory 245792 kb
Host smart-4403f231-e41e-40d8-8782-bd2176ba0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519340597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2519340597
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3387273210
Short name T645
Test name
Test status
Simulation time 600529026 ps
CPU time 4.39 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 233428 kb
Host smart-fce2bf62-d076-42ea-b0b6-5943ca1c3b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387273210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3387273210
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.233336432
Short name T906
Test name
Test status
Simulation time 231408973 ps
CPU time 5.38 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 218776 kb
Host smart-7e8d7ee7-5547-484f-b2d1-59e2a51308f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233336432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.233336432
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2977612745
Short name T731
Test name
Test status
Simulation time 87739730487 ps
CPU time 426.47 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 254984 kb
Host smart-260d9309-a8c8-46a9-ae7d-44cbffb485b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977612745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2977612745
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4255792885
Short name T652
Test name
Test status
Simulation time 6050754091 ps
CPU time 25.05 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:08:15 PM PDT 24
Peak memory 216504 kb
Host smart-ddc05c4c-b889-48dc-8ffa-bf50beb24a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255792885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4255792885
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.181719222
Short name T448
Test name
Test status
Simulation time 9647912007 ps
CPU time 8.37 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:07:54 PM PDT 24
Peak memory 216504 kb
Host smart-89ab2def-b1e7-415c-915b-1cfc550d8e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181719222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.181719222
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4050175638
Short name T18
Test name
Test status
Simulation time 218333545 ps
CPU time 1.37 seconds
Started May 14 01:07:44 PM PDT 24
Finished May 14 01:07:47 PM PDT 24
Peak memory 216380 kb
Host smart-4bd5dd5d-6770-4ec3-b211-da99d7eb45c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050175638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4050175638
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2302829656
Short name T967
Test name
Test status
Simulation time 48335432 ps
CPU time 0.83 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:07:50 PM PDT 24
Peak memory 205876 kb
Host smart-bb975708-aedf-445a-8a2b-1051cc53c9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302829656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2302829656
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3284997380
Short name T272
Test name
Test status
Simulation time 1480886608 ps
CPU time 7.62 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:08:00 PM PDT 24
Peak memory 233472 kb
Host smart-b8d03799-2073-4a25-b0ec-b8c53e07553e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284997380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3284997380
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1229931485
Short name T712
Test name
Test status
Simulation time 46498557 ps
CPU time 0.69 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:01 PM PDT 24
Peak memory 205296 kb
Host smart-9ee09847-a65c-44f0-a045-1155be5c7a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229931485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1229931485
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3920826647
Short name T549
Test name
Test status
Simulation time 60816809 ps
CPU time 2.36 seconds
Started May 14 01:07:50 PM PDT 24
Finished May 14 01:07:57 PM PDT 24
Peak memory 221008 kb
Host smart-8e10951a-de78-41a0-835c-3888a733bdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920826647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3920826647
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3047592569
Short name T466
Test name
Test status
Simulation time 39662981 ps
CPU time 0.77 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:52 PM PDT 24
Peak memory 206688 kb
Host smart-111ae22d-e6aa-4922-8c58-83b33f711e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047592569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3047592569
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2345535967
Short name T244
Test name
Test status
Simulation time 2457168801 ps
CPU time 47.34 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:08:43 PM PDT 24
Peak memory 249256 kb
Host smart-9c4e9eb6-2bd8-4c04-a7da-644cbfecaa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345535967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2345535967
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3494533958
Short name T270
Test name
Test status
Simulation time 19802480112 ps
CPU time 104.38 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:09:35 PM PDT 24
Peak memory 253692 kb
Host smart-399d76a9-a000-4f74-b965-3a4c5fca0b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494533958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3494533958
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4095861717
Short name T83
Test name
Test status
Simulation time 140203523183 ps
CPU time 279.54 seconds
Started May 14 01:07:50 PM PDT 24
Finished May 14 01:12:34 PM PDT 24
Peak memory 251348 kb
Host smart-4e06c3fa-1f36-4c32-9992-df66b101a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095861717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4095861717
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.47190007
Short name T872
Test name
Test status
Simulation time 5466911470 ps
CPU time 14.5 seconds
Started May 14 01:07:51 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 241068 kb
Host smart-960df7ee-732a-4186-91dd-ed54c98d8d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47190007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.47190007
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3258160005
Short name T654
Test name
Test status
Simulation time 65080031 ps
CPU time 2.9 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 232336 kb
Host smart-cb47126c-820b-430c-a88c-9df9bc987918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258160005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3258160005
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.804237168
Short name T487
Test name
Test status
Simulation time 39560577019 ps
CPU time 110.8 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:09:52 PM PDT 24
Peak memory 238832 kb
Host smart-c9963ae8-b613-4bf6-9211-8a8b7a9c62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804237168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.804237168
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.332513003
Short name T568
Test name
Test status
Simulation time 4060155728 ps
CPU time 7.64 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 224648 kb
Host smart-2a978b6b-190a-486f-887d-2e374a6c1aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332513003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.332513003
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2445505391
Short name T569
Test name
Test status
Simulation time 203790334 ps
CPU time 2.53 seconds
Started May 14 01:07:45 PM PDT 24
Finished May 14 01:07:49 PM PDT 24
Peak memory 221452 kb
Host smart-1be49736-41cb-4ea3-8a33-34118785a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445505391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2445505391
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3635816009
Short name T926
Test name
Test status
Simulation time 3634738412 ps
CPU time 8.22 seconds
Started May 14 01:07:46 PM PDT 24
Finished May 14 01:07:58 PM PDT 24
Peak memory 219284 kb
Host smart-d29328d4-f072-4f2c-8c15-982f8ab6d7e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3635816009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3635816009
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1863506245
Short name T472
Test name
Test status
Simulation time 1642898187 ps
CPU time 7.05 seconds
Started May 14 01:07:50 PM PDT 24
Finished May 14 01:08:02 PM PDT 24
Peak memory 216420 kb
Host smart-28c35254-dc40-4060-857f-f3b627d58e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863506245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1863506245
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1408557178
Short name T606
Test name
Test status
Simulation time 4498770016 ps
CPU time 16.29 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 216400 kb
Host smart-a79694da-9f36-464c-8caa-3a7eb540f68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408557178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1408557178
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3471020246
Short name T411
Test name
Test status
Simulation time 280576158 ps
CPU time 5.69 seconds
Started May 14 01:07:55 PM PDT 24
Finished May 14 01:08:06 PM PDT 24
Peak memory 216368 kb
Host smart-4b36ac25-1ee6-4726-9211-1b89b014359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471020246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3471020246
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4071887829
Short name T909
Test name
Test status
Simulation time 131497306 ps
CPU time 0.73 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:07:52 PM PDT 24
Peak memory 205764 kb
Host smart-5c2b077a-b570-4b2c-8128-f52d599f4c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071887829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4071887829
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3785826197
Short name T843
Test name
Test status
Simulation time 8724862897 ps
CPU time 29.65 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:08:23 PM PDT 24
Peak memory 239796 kb
Host smart-b3adc698-487d-422b-8612-3e3f5337cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785826197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3785826197
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.123459706
Short name T623
Test name
Test status
Simulation time 18535545 ps
CPU time 0.73 seconds
Started May 14 01:07:59 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 205372 kb
Host smart-82f3d21e-7b5a-476c-9c94-a04c06a78a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123459706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.123459706
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.96484771
Short name T166
Test name
Test status
Simulation time 361627745 ps
CPU time 3.65 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 218564 kb
Host smart-7023cca0-d84f-468c-a41f-a3737c7f2fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96484771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.96484771
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1187122202
Short name T132
Test name
Test status
Simulation time 115871073 ps
CPU time 0.77 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:07:54 PM PDT 24
Peak memory 206676 kb
Host smart-423e1a94-24d3-4d4d-894d-cf3b8147f38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187122202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1187122202
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.348633170
Short name T131
Test name
Test status
Simulation time 32436435199 ps
CPU time 72.36 seconds
Started May 14 01:07:50 PM PDT 24
Finished May 14 01:09:07 PM PDT 24
Peak memory 257428 kb
Host smart-0fa6989e-fa18-47f4-bcf1-dbf710bec67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348633170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.348633170
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1713205855
Short name T105
Test name
Test status
Simulation time 20784993818 ps
CPU time 61.19 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:08:57 PM PDT 24
Peak memory 239352 kb
Host smart-3e6c8292-f6d1-4f13-9b42-b2b8e679aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713205855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1713205855
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3803085547
Short name T576
Test name
Test status
Simulation time 124172726 ps
CPU time 3.57 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 233368 kb
Host smart-2d7458ef-b88b-477d-a0ca-c17c70b282c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803085547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3803085547
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1077451109
Short name T31
Test name
Test status
Simulation time 20349947732 ps
CPU time 59.42 seconds
Started May 14 01:07:59 PM PDT 24
Finished May 14 01:09:03 PM PDT 24
Peak memory 232812 kb
Host smart-ca81a9a9-b15c-4706-aa25-5efd255d28be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077451109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1077451109
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3385089831
Short name T859
Test name
Test status
Simulation time 92213043 ps
CPU time 3.01 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 224192 kb
Host smart-ed17fdae-fe7c-4e3f-896b-9e8a264d80e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385089831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3385089831
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1445850222
Short name T33
Test name
Test status
Simulation time 4660889600 ps
CPU time 14.91 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:16 PM PDT 24
Peak memory 224660 kb
Host smart-709cbca4-d6ac-43ff-81ae-3f9112fcf40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445850222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1445850222
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2679531435
Short name T423
Test name
Test status
Simulation time 2945433611 ps
CPU time 5.45 seconds
Started May 14 01:07:51 PM PDT 24
Finished May 14 01:08:01 PM PDT 24
Peak memory 222556 kb
Host smart-6f5a0aad-cee1-4c13-b2d5-39933e4ffc00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2679531435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2679531435
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2719577533
Short name T128
Test name
Test status
Simulation time 8876591368 ps
CPU time 92.41 seconds
Started May 14 01:07:59 PM PDT 24
Finished May 14 01:09:36 PM PDT 24
Peak memory 241180 kb
Host smart-e5e795fb-c952-4b4e-9605-66b0b4de4c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719577533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2719577533
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.845090104
Short name T86
Test name
Test status
Simulation time 1388320951 ps
CPU time 8.94 seconds
Started May 14 01:07:47 PM PDT 24
Finished May 14 01:08:00 PM PDT 24
Peak memory 216380 kb
Host smart-66d63a96-44aa-4362-ba04-95306f32fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845090104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.845090104
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3503384151
Short name T806
Test name
Test status
Simulation time 7360858782 ps
CPU time 21.69 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:22 PM PDT 24
Peak memory 216484 kb
Host smart-ec96861a-4d5a-4b3d-8865-c8ef88dff0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503384151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3503384151
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3343231576
Short name T327
Test name
Test status
Simulation time 103296135 ps
CPU time 0.73 seconds
Started May 14 01:07:51 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 206060 kb
Host smart-ad57a7a4-3116-4b67-8253-b1b963d46734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343231576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3343231576
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1225751517
Short name T352
Test name
Test status
Simulation time 81584433 ps
CPU time 0.91 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:02 PM PDT 24
Peak memory 205844 kb
Host smart-dbd23551-04d1-470f-94a3-71ed482d8a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225751517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1225751517
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2247130699
Short name T269
Test name
Test status
Simulation time 89166530334 ps
CPU time 18.27 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 235424 kb
Host smart-769f4434-957c-44e5-b9c4-7d5621c45558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247130699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2247130699
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1681432110
Short name T718
Test name
Test status
Simulation time 33630778 ps
CPU time 0.74 seconds
Started May 14 01:07:53 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 205328 kb
Host smart-0b2ac154-db23-4738-b564-69ec09e53e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681432110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1681432110
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1726017075
Short name T657
Test name
Test status
Simulation time 2857947394 ps
CPU time 19.75 seconds
Started May 14 01:07:54 PM PDT 24
Finished May 14 01:08:19 PM PDT 24
Peak memory 220928 kb
Host smart-d355f431-ff58-4b91-8561-3025f9443cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726017075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1726017075
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.273919612
Short name T784
Test name
Test status
Simulation time 49404594 ps
CPU time 0.76 seconds
Started May 14 01:07:49 PM PDT 24
Finished May 14 01:07:54 PM PDT 24
Peak memory 205368 kb
Host smart-a48ec949-503e-4aa9-af22-5b768878776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273919612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.273919612
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1336906834
Short name T162
Test name
Test status
Simulation time 110176420802 ps
CPU time 356.7 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:13:54 PM PDT 24
Peak memory 265456 kb
Host smart-4dda82de-072c-49c0-aa3e-5c379fb0153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336906834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1336906834
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1075024817
Short name T197
Test name
Test status
Simulation time 51940736215 ps
CPU time 63.91 seconds
Started May 14 01:08:06 PM PDT 24
Finished May 14 01:09:16 PM PDT 24
Peak memory 249316 kb
Host smart-5ca03322-bc49-4032-905b-97304bc6d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075024817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1075024817
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.125178285
Short name T388
Test name
Test status
Simulation time 38276547546 ps
CPU time 50.74 seconds
Started May 14 01:07:53 PM PDT 24
Finished May 14 01:08:48 PM PDT 24
Peak memory 237380 kb
Host smart-286d6d29-5c6d-4666-8082-d1bdbfedcef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125178285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.125178285
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3155417587
Short name T770
Test name
Test status
Simulation time 403008715 ps
CPU time 15.16 seconds
Started May 14 01:07:54 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 234832 kb
Host smart-7817b63c-4baa-49c4-88dd-71ba2b376546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155417587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3155417587
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.429723656
Short name T446
Test name
Test status
Simulation time 1079601911 ps
CPU time 2.3 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 216104 kb
Host smart-9d723e0f-197c-4eaf-b44d-604b75c5b203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429723656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.429723656
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2450455520
Short name T555
Test name
Test status
Simulation time 798660256 ps
CPU time 10.79 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:13 PM PDT 24
Peak memory 219412 kb
Host smart-eecd8816-4a77-4373-afca-4db00d404019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450455520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2450455520
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1738802312
Short name T528
Test name
Test status
Simulation time 1293963820 ps
CPU time 3.61 seconds
Started May 14 01:07:53 PM PDT 24
Finished May 14 01:08:01 PM PDT 24
Peak memory 233624 kb
Host smart-c498553b-96d3-40d3-8d45-ba32eab696ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738802312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1738802312
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.16930828
Short name T963
Test name
Test status
Simulation time 794047117 ps
CPU time 8.19 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 227644 kb
Host smart-2e90d7ba-2d4f-43e4-b89a-a3c027210f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16930828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.16930828
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.518218593
Short name T532
Test name
Test status
Simulation time 1192469592 ps
CPU time 4.97 seconds
Started May 14 01:07:55 PM PDT 24
Finished May 14 01:08:05 PM PDT 24
Peak memory 222516 kb
Host smart-23109a79-c146-43bf-a8c5-458a6da7fa13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=518218593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.518218593
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2426650471
Short name T370
Test name
Test status
Simulation time 467513711 ps
CPU time 1.2 seconds
Started May 14 01:07:53 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 207020 kb
Host smart-376d6d51-12b5-4965-a1dc-4fa6e4e386ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426650471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2426650471
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1440458662
Short name T5
Test name
Test status
Simulation time 3536658780 ps
CPU time 10.41 seconds
Started May 14 01:08:00 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 216544 kb
Host smart-7964705f-2a15-485a-a32b-de679e2d343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440458662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1440458662
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.115562598
Short name T722
Test name
Test status
Simulation time 4990576252 ps
CPU time 4.99 seconds
Started May 14 01:07:59 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 216504 kb
Host smart-156fe73b-24cf-4a9d-aa08-177058b283e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115562598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.115562598
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1306474222
Short name T326
Test name
Test status
Simulation time 354136425 ps
CPU time 1.62 seconds
Started May 14 01:07:50 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 216320 kb
Host smart-2dd27811-8444-4780-8cc7-a8cb7e78bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306474222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1306474222
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3089504620
Short name T924
Test name
Test status
Simulation time 23974727 ps
CPU time 0.68 seconds
Started May 14 01:07:48 PM PDT 24
Finished May 14 01:07:53 PM PDT 24
Peak memory 205408 kb
Host smart-f7732217-8aa7-4b41-8dec-4a962c75d529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089504620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3089504620
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2009681469
Short name T161
Test name
Test status
Simulation time 380332140 ps
CPU time 3.01 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 218824 kb
Host smart-34ac4979-7a9f-4559-8549-be72cc3961ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009681469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2009681469
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2547954271
Short name T334
Test name
Test status
Simulation time 23118289 ps
CPU time 0.73 seconds
Started May 14 01:07:54 PM PDT 24
Finished May 14 01:07:59 PM PDT 24
Peak memory 204676 kb
Host smart-e4c87d82-0873-44d9-a874-6af95b6eca45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547954271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2547954271
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2318908284
Short name T70
Test name
Test status
Simulation time 126438945 ps
CPU time 2.4 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:16 PM PDT 24
Peak memory 220964 kb
Host smart-294810fe-c18b-447c-93ab-00c83bb365b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318908284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2318908284
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1523860015
Short name T919
Test name
Test status
Simulation time 18260372 ps
CPU time 0.8 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 206724 kb
Host smart-46e231e5-8216-4d18-94f5-9f7e4296e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523860015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1523860015
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3644615267
Short name T810
Test name
Test status
Simulation time 34545035 ps
CPU time 0.74 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:02 PM PDT 24
Peak memory 215872 kb
Host smart-75789b0d-67d5-427e-a9f6-0ef22ccda732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644615267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3644615267
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1663262309
Short name T551
Test name
Test status
Simulation time 6248080512 ps
CPU time 56.47 seconds
Started May 14 01:08:01 PM PDT 24
Finished May 14 01:09:02 PM PDT 24
Peak memory 234004 kb
Host smart-4c3809d7-5cd7-415d-8050-ef1cfdc2f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663262309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1663262309
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4268658129
Short name T614
Test name
Test status
Simulation time 11301699850 ps
CPU time 111.34 seconds
Started May 14 01:08:06 PM PDT 24
Finished May 14 01:10:03 PM PDT 24
Peak memory 249572 kb
Host smart-b719b5c9-2fed-4a99-8a83-2f0f209c680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268658129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4268658129
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1125967888
Short name T703
Test name
Test status
Simulation time 417252506 ps
CPU time 8.1 seconds
Started May 14 01:07:59 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 224532 kb
Host smart-5256ec99-b5ba-4777-86b6-92222117920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125967888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1125967888
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1305369745
Short name T697
Test name
Test status
Simulation time 1090803757 ps
CPU time 4.3 seconds
Started May 14 01:07:55 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 224464 kb
Host smart-2188a005-5a52-4182-b41e-c85776e28efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305369745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1305369745
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.876667265
Short name T855
Test name
Test status
Simulation time 6173611286 ps
CPU time 6.66 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 224568 kb
Host smart-e0fa4005-fc2d-4f3c-bf02-91c2896d8483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876667265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.876667265
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2502961918
Short name T918
Test name
Test status
Simulation time 7321453486 ps
CPU time 9.88 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 219016 kb
Host smart-0381855f-8da6-4627-b08a-d71f6c743b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502961918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2502961918
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.456681988
Short name T583
Test name
Test status
Simulation time 6214514159 ps
CPU time 21.02 seconds
Started May 14 01:07:55 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 233756 kb
Host smart-bd7a25f6-1dcb-4989-bb20-e3d1db235a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456681988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.456681988
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2987271071
Short name T149
Test name
Test status
Simulation time 281731458 ps
CPU time 3.64 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:16 PM PDT 24
Peak memory 218712 kb
Host smart-51e01b39-6e80-478b-a749-35bfcbc44042
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2987271071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2987271071
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3108434500
Short name T910
Test name
Test status
Simulation time 64903397 ps
CPU time 1.06 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 206904 kb
Host smart-bf7faf1b-b562-4779-9b73-33a92a1d1c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108434500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3108434500
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4283496918
Short name T815
Test name
Test status
Simulation time 14672440716 ps
CPU time 25.57 seconds
Started May 14 01:08:06 PM PDT 24
Finished May 14 01:08:38 PM PDT 24
Peak memory 216472 kb
Host smart-9c41dcbf-91fe-4b41-9e33-8f2a64ef864c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283496918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4283496918
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1391441155
Short name T505
Test name
Test status
Simulation time 13946910356 ps
CPU time 12.98 seconds
Started May 14 01:07:53 PM PDT 24
Finished May 14 01:08:11 PM PDT 24
Peak memory 216512 kb
Host smart-7b932578-fa0f-4dd2-bf3a-6f6dc02e7c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391441155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1391441155
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2186350471
Short name T764
Test name
Test status
Simulation time 193518284 ps
CPU time 3.69 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:05 PM PDT 24
Peak memory 216436 kb
Host smart-8aeef102-3d35-47e9-89c3-746e021ef33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186350471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2186350471
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3884053263
Short name T811
Test name
Test status
Simulation time 13012666 ps
CPU time 0.7 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:07:56 PM PDT 24
Peak memory 205460 kb
Host smart-fc32ef51-ccac-420e-8689-393fddbc12a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884053263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3884053263
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.34501419
Short name T876
Test name
Test status
Simulation time 17820893842 ps
CPU time 18.66 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:26 PM PDT 24
Peak memory 228708 kb
Host smart-720e1f06-23ce-461d-b2c5-9923fc45a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34501419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.34501419
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1053110815
Short name T631
Test name
Test status
Simulation time 10624919 ps
CPU time 0.73 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 204628 kb
Host smart-5f1b71e7-9ed4-4af3-807a-ed0e9c83772d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053110815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1053110815
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2749906307
Short name T291
Test name
Test status
Simulation time 131844883 ps
CPU time 1.93 seconds
Started May 14 01:08:05 PM PDT 24
Finished May 14 01:08:13 PM PDT 24
Peak memory 219008 kb
Host smart-34d9d516-d57b-49e4-abb2-92ae2402705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749906307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2749906307
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3225286115
Short name T842
Test name
Test status
Simulation time 64670951 ps
CPU time 0.83 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:03 PM PDT 24
Peak memory 206456 kb
Host smart-8694d690-5ca1-4389-9ead-f782f9fe81e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225286115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3225286115
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4071899416
Short name T236
Test name
Test status
Simulation time 73624677920 ps
CPU time 110.86 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:09:59 PM PDT 24
Peak memory 241084 kb
Host smart-68dcbfaa-7d72-46c6-86ce-91f32f85ec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071899416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4071899416
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1135638698
Short name T821
Test name
Test status
Simulation time 21218533874 ps
CPU time 84.81 seconds
Started May 14 01:08:05 PM PDT 24
Finished May 14 01:09:36 PM PDT 24
Peak memory 255856 kb
Host smart-84d3d807-66f8-4c44-b20f-bd6ac05af720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135638698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1135638698
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.513780416
Short name T319
Test name
Test status
Simulation time 4868056773 ps
CPU time 23.31 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:30 PM PDT 24
Peak memory 224088 kb
Host smart-5769749b-d978-4352-a487-a03f1d03c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513780416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.513780416
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1093231609
Short name T911
Test name
Test status
Simulation time 648728916 ps
CPU time 6.32 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 234592 kb
Host smart-ad309c38-edd9-4882-a6ed-a76b368bd1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093231609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1093231609
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1060427026
Short name T776
Test name
Test status
Simulation time 9582405144 ps
CPU time 25.29 seconds
Started May 14 01:07:51 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 218564 kb
Host smart-38bf2f94-ff3c-4f03-9952-25c058bc1d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060427026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1060427026
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.82453476
Short name T976
Test name
Test status
Simulation time 16291692902 ps
CPU time 37.98 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 246724 kb
Host smart-72005c03-068c-4d3f-9d71-c2a97c21f78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82453476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.82453476
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3385632671
Short name T298
Test name
Test status
Simulation time 507862632 ps
CPU time 4.32 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 235228 kb
Host smart-5cc8976a-9038-44f7-90a0-3d3af75b25d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385632671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3385632671
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1888598755
Short name T937
Test name
Test status
Simulation time 1482869366 ps
CPU time 9.06 seconds
Started May 14 01:08:06 PM PDT 24
Finished May 14 01:08:21 PM PDT 24
Peak memory 216704 kb
Host smart-f25c935d-9755-421c-97c6-75d1231698b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888598755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1888598755
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3524668540
Short name T546
Test name
Test status
Simulation time 3071504099 ps
CPU time 9.38 seconds
Started May 14 01:08:01 PM PDT 24
Finished May 14 01:08:15 PM PDT 24
Peak memory 220636 kb
Host smart-55e9c4dc-b509-4fd0-95dd-4b115bb6ae68
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3524668540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3524668540
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.123885904
Short name T768
Test name
Test status
Simulation time 1045529405 ps
CPU time 11.4 seconds
Started May 14 01:08:08 PM PDT 24
Finished May 14 01:08:25 PM PDT 24
Peak memory 240976 kb
Host smart-ff230d1a-0116-4cf9-b4fa-8278871abe54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123885904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.123885904
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3822431547
Short name T563
Test name
Test status
Simulation time 22343824317 ps
CPU time 27.41 seconds
Started May 14 01:07:56 PM PDT 24
Finished May 14 01:08:28 PM PDT 24
Peak memory 216424 kb
Host smart-82a471e6-2367-40fc-842a-b20c37f793c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822431547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3822431547
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1447826718
Short name T892
Test name
Test status
Simulation time 30536807575 ps
CPU time 22.11 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:08:18 PM PDT 24
Peak memory 216472 kb
Host smart-2d788be0-70d4-4c81-b861-027b1b97c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447826718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1447826718
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.545738835
Short name T20
Test name
Test status
Simulation time 37404955 ps
CPU time 0.88 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 206560 kb
Host smart-10eaffac-9b8f-4b7c-82e0-e8bf173c9f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545738835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.545738835
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1598146708
Short name T497
Test name
Test status
Simulation time 19795608 ps
CPU time 0.73 seconds
Started May 14 01:08:06 PM PDT 24
Finished May 14 01:08:13 PM PDT 24
Peak memory 205792 kb
Host smart-29d84053-9fe8-4ddc-a7e0-a63516405a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598146708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1598146708
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1698848247
Short name T709
Test name
Test status
Simulation time 17061637470 ps
CPU time 13.3 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:20 PM PDT 24
Peak memory 228924 kb
Host smart-ba1a8301-f353-4475-acca-882692388cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698848247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1698848247
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.698443725
Short name T809
Test name
Test status
Simulation time 40602725 ps
CPU time 0.77 seconds
Started May 14 01:08:01 PM PDT 24
Finished May 14 01:08:06 PM PDT 24
Peak memory 204768 kb
Host smart-1b72f4bd-a182-49a6-86ee-9547afb62284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698443725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.698443725
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.999280075
Short name T685
Test name
Test status
Simulation time 2643288173 ps
CPU time 7.74 seconds
Started May 14 01:08:05 PM PDT 24
Finished May 14 01:08:19 PM PDT 24
Peak memory 234024 kb
Host smart-bcb24335-aff5-4fe7-b226-aea8f31460fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999280075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.999280075
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2643315447
Short name T874
Test name
Test status
Simulation time 18207296 ps
CPU time 0.8 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 206316 kb
Host smart-e2840987-1d30-4ffa-aa80-598d668dbd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643315447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2643315447
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3088292572
Short name T416
Test name
Test status
Simulation time 3543160906 ps
CPU time 36.22 seconds
Started May 14 01:08:11 PM PDT 24
Finished May 14 01:08:53 PM PDT 24
Peak memory 236332 kb
Host smart-7cef4dd8-803a-43e8-a2b4-b6ca8cee783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088292572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3088292572
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.798211634
Short name T948
Test name
Test status
Simulation time 79932095883 ps
CPU time 165.64 seconds
Started May 14 01:08:05 PM PDT 24
Finished May 14 01:10:57 PM PDT 24
Peak memory 249336 kb
Host smart-b3cd4e8a-c7a0-4d3a-bbbb-e71799e090cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798211634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.798211634
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.411772058
Short name T476
Test name
Test status
Simulation time 26430427120 ps
CPU time 236.57 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:12:05 PM PDT 24
Peak memory 256596 kb
Host smart-a93cd006-b46d-484e-ac9c-95c28e097bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411772058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.411772058
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2747836058
Short name T646
Test name
Test status
Simulation time 200263880 ps
CPU time 6.43 seconds
Started May 14 01:07:57 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 240684 kb
Host smart-15449edf-eff8-48b9-9546-199353c63c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747836058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2747836058
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2858469877
Short name T260
Test name
Test status
Simulation time 1280478010 ps
CPU time 13.14 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:15 PM PDT 24
Peak memory 233372 kb
Host smart-fbd16b23-31b8-4724-a6df-1e1480d4c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858469877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2858469877
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.959617057
Short name T288
Test name
Test status
Simulation time 26412062265 ps
CPU time 55.4 seconds
Started May 14 01:07:52 PM PDT 24
Finished May 14 01:08:51 PM PDT 24
Peak memory 227800 kb
Host smart-40429085-b8aa-4ee7-89d7-a3e89c72e5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959617057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.959617057
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2215742998
Short name T297
Test name
Test status
Simulation time 739573215 ps
CPU time 4.12 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 216604 kb
Host smart-b11e0784-32bf-44dd-a359-7e8071cfdeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215742998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2215742998
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3049062562
Short name T170
Test name
Test status
Simulation time 1356539576 ps
CPU time 5.03 seconds
Started May 14 01:07:55 PM PDT 24
Finished May 14 01:08:04 PM PDT 24
Peak memory 233388 kb
Host smart-eed3ebce-91f3-48d2-88f5-1bfb0599f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049062562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3049062562
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2157791986
Short name T418
Test name
Test status
Simulation time 682812753 ps
CPU time 5.04 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:07 PM PDT 24
Peak memory 219220 kb
Host smart-7bfe013f-4f95-42a3-bab3-ab1d1bb7ff2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2157791986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2157791986
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.601609825
Short name T37
Test name
Test status
Simulation time 22827919624 ps
CPU time 288.72 seconds
Started May 14 01:08:11 PM PDT 24
Finished May 14 01:13:06 PM PDT 24
Peak memory 286564 kb
Host smart-74425a21-db78-468a-b3ae-fa451c8ff069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601609825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.601609825
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1589749771
Short name T882
Test name
Test status
Simulation time 1018332515 ps
CPU time 10.01 seconds
Started May 14 01:07:55 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 216332 kb
Host smart-7ae16c3a-fee8-442d-b95a-507e7f59ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589749771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1589749771
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2643647977
Short name T81
Test name
Test status
Simulation time 2172288819 ps
CPU time 5.98 seconds
Started May 14 01:07:58 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 216380 kb
Host smart-ee8513cf-14b6-427a-84af-eef91ec72633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643647977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2643647977
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1925567138
Short name T407
Test name
Test status
Simulation time 1063220846 ps
CPU time 4.27 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 216512 kb
Host smart-741ea2cb-982c-4c65-9882-bd65f7ae250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925567138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1925567138
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2350356674
Short name T507
Test name
Test status
Simulation time 21908927 ps
CPU time 0.74 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 205776 kb
Host smart-b03e31c6-261b-4069-97b2-025af7c248b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350356674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2350356674
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2114427455
Short name T761
Test name
Test status
Simulation time 208841162 ps
CPU time 2.8 seconds
Started May 14 01:08:07 PM PDT 24
Finished May 14 01:08:16 PM PDT 24
Peak memory 232720 kb
Host smart-25181169-827a-46aa-9fdf-698bf0da1321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114427455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2114427455
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4189018806
Short name T649
Test name
Test status
Simulation time 38712487 ps
CPU time 0.71 seconds
Started May 14 01:08:01 PM PDT 24
Finished May 14 01:08:08 PM PDT 24
Peak memory 205372 kb
Host smart-c4a5c390-9113-4438-926b-091c3996f3ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189018806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4189018806
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2502581567
Short name T14
Test name
Test status
Simulation time 39544000 ps
CPU time 2.52 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 233544 kb
Host smart-a8199b94-02a3-43c2-b4eb-48a1d0814ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502581567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2502581567
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1118859807
Short name T514
Test name
Test status
Simulation time 64746105 ps
CPU time 0.73 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 205984 kb
Host smart-2ab3403d-cd59-438a-95d2-0d76c1c9e056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118859807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1118859807
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4145445634
Short name T836
Test name
Test status
Simulation time 419758086 ps
CPU time 6.26 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:08:15 PM PDT 24
Peak memory 232864 kb
Host smart-f6169798-f435-4d7f-8de4-a117c55165a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145445634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4145445634
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2740839561
Short name T844
Test name
Test status
Simulation time 48041671068 ps
CPU time 155.24 seconds
Started May 14 01:08:05 PM PDT 24
Finished May 14 01:10:46 PM PDT 24
Peak memory 249352 kb
Host smart-405ca27e-afb8-43c7-be8a-810e6ac38979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740839561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2740839561
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.931733754
Short name T139
Test name
Test status
Simulation time 103008972927 ps
CPU time 189.22 seconds
Started May 14 01:08:01 PM PDT 24
Finished May 14 01:11:16 PM PDT 24
Peak memory 249416 kb
Host smart-137ebc91-316c-46f2-b65f-6cb607195da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931733754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.931733754
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2774100593
Short name T951
Test name
Test status
Simulation time 213466999 ps
CPU time 3.02 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:10 PM PDT 24
Peak memory 232740 kb
Host smart-f3003a9c-c4b3-4236-9ff2-9d960c490766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774100593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2774100593
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.758583617
Short name T274
Test name
Test status
Simulation time 4070250399 ps
CPU time 4.61 seconds
Started May 14 01:08:01 PM PDT 24
Finished May 14 01:08:11 PM PDT 24
Peak memory 233352 kb
Host smart-9b1589cf-84fa-4c74-8e7b-eb71c94321c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758583617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.758583617
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3654549269
Short name T802
Test name
Test status
Simulation time 106325457196 ps
CPU time 77.71 seconds
Started May 14 01:08:04 PM PDT 24
Finished May 14 01:09:27 PM PDT 24
Peak memory 240484 kb
Host smart-68025946-875e-4a01-a9ec-43aabc80eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654549269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3654549269
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2661495718
Short name T460
Test name
Test status
Simulation time 551029435 ps
CPU time 5.2 seconds
Started May 14 01:08:06 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 238384 kb
Host smart-8ffc70ff-4401-4701-8341-a61c8c13e1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661495718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2661495718
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1236862673
Short name T275
Test name
Test status
Simulation time 1221986735 ps
CPU time 8.94 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 235740 kb
Host smart-a55cc7a8-f2e7-46f6-af91-0b759e478fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236862673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1236862673
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4204955281
Short name T484
Test name
Test status
Simulation time 1023394053 ps
CPU time 4.68 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:12 PM PDT 24
Peak memory 222980 kb
Host smart-0c05caf8-9641-434b-ace0-88d8f3e4bb57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4204955281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4204955281
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2539195397
Short name T524
Test name
Test status
Simulation time 3378077551 ps
CPU time 4.6 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 217764 kb
Host smart-05a174a8-fa59-47bd-a791-c240fd003582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539195397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2539195397
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.543693042
Short name T88
Test name
Test status
Simulation time 189446950 ps
CPU time 1.38 seconds
Started May 14 01:08:03 PM PDT 24
Finished May 14 01:08:11 PM PDT 24
Peak memory 206876 kb
Host smart-fa68665e-7128-4332-a726-78c8b126eb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543693042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.543693042
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1489663073
Short name T538
Test name
Test status
Simulation time 191742506 ps
CPU time 1.18 seconds
Started May 14 01:08:02 PM PDT 24
Finished May 14 01:08:09 PM PDT 24
Peak memory 207992 kb
Host smart-d0bb8bef-a87e-42f5-bd2b-51496b297f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489663073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1489663073
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2933518073
Short name T840
Test name
Test status
Simulation time 74920254 ps
CPU time 0.84 seconds
Started May 14 01:08:04 PM PDT 24
Finished May 14 01:08:11 PM PDT 24
Peak memory 206140 kb
Host smart-3e2be99a-c38b-4a9d-abf7-a610fef9a7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933518073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2933518073
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3218601958
Short name T788
Test name
Test status
Simulation time 5817116144 ps
CPU time 17.94 seconds
Started May 14 01:08:11 PM PDT 24
Finished May 14 01:08:35 PM PDT 24
Peak memory 226696 kb
Host smart-0fcd8804-4221-461d-b274-29b6cc022c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218601958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3218601958
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2805132409
Short name T396
Test name
Test status
Simulation time 21313888 ps
CPU time 0.71 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:22 PM PDT 24
Peak memory 204772 kb
Host smart-38fe8b4c-9403-4d43-bff2-42fbd8adfd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805132409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
805132409
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1844667407
Short name T783
Test name
Test status
Simulation time 1966670764 ps
CPU time 4.23 seconds
Started May 14 01:05:20 PM PDT 24
Finished May 14 01:05:32 PM PDT 24
Peak memory 234312 kb
Host smart-d294b380-400d-46f5-ae9e-cdf5776cb218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844667407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1844667407
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1448199499
Short name T72
Test name
Test status
Simulation time 118289810 ps
CPU time 0.78 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:20 PM PDT 24
Peak memory 206440 kb
Host smart-8a81d604-3c00-4836-953a-a6a7949e4495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448199499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1448199499
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4169142311
Short name T135
Test name
Test status
Simulation time 3826252802 ps
CPU time 43.66 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:06:03 PM PDT 24
Peak memory 253452 kb
Host smart-220e4629-54f7-486a-ba92-d2ed799bc2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169142311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4169142311
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.337381627
Short name T138
Test name
Test status
Simulation time 3845190303 ps
CPU time 40.41 seconds
Started May 14 01:05:23 PM PDT 24
Finished May 14 01:06:12 PM PDT 24
Peak memory 249396 kb
Host smart-c57d1993-a8a0-476f-9ab1-b53f39cccef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337381627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
337381627
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.31010092
Short name T363
Test name
Test status
Simulation time 227764096 ps
CPU time 4.82 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 224548 kb
Host smart-8603755a-61fb-45b8-8a5c-a7648ec9f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31010092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.31010092
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3505245474
Short name T50
Test name
Test status
Simulation time 276737833 ps
CPU time 2.79 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:05:20 PM PDT 24
Peak memory 218592 kb
Host smart-f759fac5-31bc-45aa-9b88-5a1065738cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505245474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3505245474
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1435575814
Short name T558
Test name
Test status
Simulation time 425096773 ps
CPU time 7.01 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:31 PM PDT 24
Peak memory 228340 kb
Host smart-4d7b0207-7871-41c0-877c-8b519b4077f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435575814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1435575814
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3536937232
Short name T26
Test name
Test status
Simulation time 242869198 ps
CPU time 1.03 seconds
Started May 14 01:05:19 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 216724 kb
Host smart-bcac32cd-9c25-44d5-9dca-01253f1db4e3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536937232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3536937232
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2517723155
Short name T410
Test name
Test status
Simulation time 12870908921 ps
CPU time 14.22 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 233532 kb
Host smart-8092191f-4e96-4229-8150-d967e11796f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517723155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2517723155
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4173138328
Short name T183
Test name
Test status
Simulation time 474693698 ps
CPU time 5.65 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:25 PM PDT 24
Peak memory 237736 kb
Host smart-61400718-71da-408a-a00f-e19b13a089e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173138328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4173138328
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2843563512
Short name T373
Test name
Test status
Simulation time 179771699 ps
CPU time 4.11 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 222908 kb
Host smart-06200d39-8199-4f10-b0dd-7a6f362478c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2843563512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2843563512
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.480580027
Short name T315
Test name
Test status
Simulation time 4636087104 ps
CPU time 15.98 seconds
Started May 14 01:05:16 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 218904 kb
Host smart-b0f58922-a422-49ac-b0fc-9c49ed4c6fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480580027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.480580027
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.412302097
Short name T825
Test name
Test status
Simulation time 1236884211 ps
CPU time 2.44 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:26 PM PDT 24
Peak memory 216316 kb
Host smart-b191c55d-456b-415f-864c-2fe5af5099e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412302097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.412302097
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2336131026
Short name T790
Test name
Test status
Simulation time 46731021 ps
CPU time 0.73 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:05:18 PM PDT 24
Peak memory 205796 kb
Host smart-099779bc-7ef7-479d-94e1-c8f8f88db9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336131026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2336131026
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3340041244
Short name T871
Test name
Test status
Simulation time 25284298 ps
CPU time 0.71 seconds
Started May 14 01:05:15 PM PDT 24
Finished May 14 01:05:18 PM PDT 24
Peak memory 205824 kb
Host smart-087e1410-7281-4081-a20c-49e2cd65b433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340041244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3340041244
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3112755142
Short name T181
Test name
Test status
Simulation time 1022392141 ps
CPU time 6.22 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:31 PM PDT 24
Peak memory 218904 kb
Host smart-c56fd9ef-d487-412e-8cfe-31a93e9ef901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112755142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3112755142
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2233663347
Short name T346
Test name
Test status
Simulation time 29547206 ps
CPU time 0.69 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:39 PM PDT 24
Peak memory 205372 kb
Host smart-ea913129-1568-404e-a4e1-101552ba2e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233663347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
233663347
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2723466570
Short name T482
Test name
Test status
Simulation time 155385673 ps
CPU time 3.62 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:05:37 PM PDT 24
Peak memory 218516 kb
Host smart-0c196ab7-17fd-4e2f-a4fa-d1c98fb4c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723466570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2723466570
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3047632562
Short name T361
Test name
Test status
Simulation time 94482087 ps
CPU time 0.78 seconds
Started May 14 01:05:23 PM PDT 24
Finished May 14 01:05:33 PM PDT 24
Peak memory 206464 kb
Host smart-7a5272ef-90a7-42ce-93a1-022e3b402a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047632562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3047632562
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3143487456
Short name T710
Test name
Test status
Simulation time 8588698353 ps
CPU time 57.64 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:06:33 PM PDT 24
Peak memory 249204 kb
Host smart-ef422a33-619a-498e-abb9-bd2777076903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143487456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3143487456
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2874239181
Short name T23
Test name
Test status
Simulation time 84986491058 ps
CPU time 204.23 seconds
Started May 14 01:05:28 PM PDT 24
Finished May 14 01:09:00 PM PDT 24
Peak memory 241216 kb
Host smart-5f746bb4-8910-48eb-a5c0-2396a63c78f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874239181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2874239181
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1466359035
Short name T531
Test name
Test status
Simulation time 195676212 ps
CPU time 3.04 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:42 PM PDT 24
Peak memory 232732 kb
Host smart-fa81a4d5-edfc-48fd-8280-cdf701aa52fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466359035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1466359035
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4078539623
Short name T564
Test name
Test status
Simulation time 1809985613 ps
CPU time 12.15 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:46 PM PDT 24
Peak memory 234152 kb
Host smart-64c7614f-b1f2-476e-b2c0-48475977cb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078539623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4078539623
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3998912924
Short name T10
Test name
Test status
Simulation time 207646384 ps
CPU time 3.68 seconds
Started May 14 01:05:31 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 218668 kb
Host smart-a0431977-4aa4-4790-9ba7-df53549b9872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998912924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3998912924
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1992600505
Short name T838
Test name
Test status
Simulation time 64344531 ps
CPU time 1.09 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:26 PM PDT 24
Peak memory 216756 kb
Host smart-530ab593-7744-4985-a1ed-07203ca31ce0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992600505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1992600505
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2142022349
Short name T942
Test name
Test status
Simulation time 3550162324 ps
CPU time 5.17 seconds
Started May 14 01:05:31 PM PDT 24
Finished May 14 01:05:44 PM PDT 24
Peak memory 218916 kb
Host smart-72874d04-5ec7-4d92-ad72-e167e0896945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142022349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2142022349
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2342959708
Short name T76
Test name
Test status
Simulation time 127727361 ps
CPU time 2.3 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:25 PM PDT 24
Peak memory 220816 kb
Host smart-72eeecc9-c620-4948-997f-b20abc4d39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342959708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2342959708
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1670222599
Short name T42
Test name
Test status
Simulation time 149853320 ps
CPU time 4.5 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 222912 kb
Host smart-e0024d26-8add-47c5-adcb-bae87980ffec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1670222599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1670222599
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1601572977
Short name T142
Test name
Test status
Simulation time 13525748831 ps
CPU time 156.66 seconds
Started May 14 01:05:29 PM PDT 24
Finished May 14 01:08:14 PM PDT 24
Peak memory 256580 kb
Host smart-5b378aa0-8215-4599-9867-3be4fe1cd483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601572977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1601572977
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3799708553
Short name T395
Test name
Test status
Simulation time 11651097 ps
CPU time 0.78 seconds
Started May 14 01:05:17 PM PDT 24
Finished May 14 01:05:22 PM PDT 24
Peak memory 205628 kb
Host smart-b7861f13-9cc5-408f-b690-90490b74f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799708553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3799708553
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3303453061
Short name T901
Test name
Test status
Simulation time 299554565 ps
CPU time 2.04 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 216344 kb
Host smart-af2e52dd-ad67-4b75-b502-06f5c26db8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303453061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3303453061
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.764648327
Short name T972
Test name
Test status
Simulation time 171070116 ps
CPU time 1.71 seconds
Started May 14 01:05:18 PM PDT 24
Finished May 14 01:05:27 PM PDT 24
Peak memory 216260 kb
Host smart-426daaff-5408-40c8-94d2-9890c9eadad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764648327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.764648327
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.285735299
Short name T328
Test name
Test status
Simulation time 18751661 ps
CPU time 0.76 seconds
Started May 14 01:05:21 PM PDT 24
Finished May 14 01:05:30 PM PDT 24
Peak memory 205828 kb
Host smart-d8c56183-ba31-4934-af20-027ff598cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285735299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.285735299
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3056776227
Short name T342
Test name
Test status
Simulation time 1177783326 ps
CPU time 2.61 seconds
Started May 14 01:05:29 PM PDT 24
Finished May 14 01:05:40 PM PDT 24
Peak memory 233564 kb
Host smart-2ed76d71-57c3-4165-aff6-008481971e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056776227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3056776227
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3488320110
Short name T517
Test name
Test status
Simulation time 12809330 ps
CPU time 0.71 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:05:36 PM PDT 24
Peak memory 205424 kb
Host smart-2bd7b5fc-a3ce-4e24-b935-3d45a2bb9811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488320110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
488320110
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.940658255
Short name T957
Test name
Test status
Simulation time 438138364 ps
CPU time 1.99 seconds
Started May 14 01:05:27 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 216080 kb
Host smart-40f82ab5-c8be-4617-8347-eda94686c674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940658255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.940658255
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.678923576
Short name T518
Test name
Test status
Simulation time 144751066 ps
CPU time 0.74 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 206364 kb
Host smart-b4ce944b-7bcf-4245-a90a-e788e4abd52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678923576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.678923576
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.204895220
Short name T521
Test name
Test status
Simulation time 45239578618 ps
CPU time 160.52 seconds
Started May 14 01:05:28 PM PDT 24
Finished May 14 01:08:17 PM PDT 24
Peak memory 252808 kb
Host smart-3bdb238f-5c95-4f84-8dc8-f6c6bab84410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204895220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.204895220
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.530796428
Short name T280
Test name
Test status
Simulation time 4508673169 ps
CPU time 47.32 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:06:21 PM PDT 24
Peak memory 253112 kb
Host smart-a091dc9e-2e76-4b33-a259-f8de6ae09140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530796428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.530796428
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1143467775
Short name T591
Test name
Test status
Simulation time 49251904649 ps
CPU time 184.76 seconds
Started May 14 01:05:31 PM PDT 24
Finished May 14 01:08:44 PM PDT 24
Peak memory 257528 kb
Host smart-6470f1ff-5491-45dd-9ced-929490c9d60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143467775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1143467775
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3156005395
Short name T409
Test name
Test status
Simulation time 135708864 ps
CPU time 5.93 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:45 PM PDT 24
Peak memory 232732 kb
Host smart-852c4423-3c1d-487c-a54a-1c8ca5272a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156005395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3156005395
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1748787486
Short name T207
Test name
Test status
Simulation time 976971736 ps
CPU time 4.9 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:39 PM PDT 24
Peak memory 219552 kb
Host smart-2ef21a78-5b70-4646-a7b8-762867e03aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748787486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1748787486
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2253560011
Short name T452
Test name
Test status
Simulation time 1802999239 ps
CPU time 23.43 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:57 PM PDT 24
Peak memory 216512 kb
Host smart-d8b63b4a-9106-4b86-964e-e7d6796d569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253560011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2253560011
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3383254658
Short name T769
Test name
Test status
Simulation time 126460481 ps
CPU time 1.05 seconds
Started May 14 01:05:29 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 216736 kb
Host smart-5bf670bf-cd2e-4fab-bf54-610d60f3e204
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383254658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3383254658
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3974933488
Short name T734
Test name
Test status
Simulation time 5968690555 ps
CPU time 6.36 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:05:50 PM PDT 24
Peak memory 235508 kb
Host smart-258cb0e3-7e61-4e75-a173-d4b98262279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974933488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3974933488
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2914683895
Short name T824
Test name
Test status
Simulation time 210930400 ps
CPU time 3.09 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:48 PM PDT 24
Peak memory 233876 kb
Host smart-9daa4fa1-d91a-43e7-8b09-9f64f59ab116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914683895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2914683895
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3523355560
Short name T43
Test name
Test status
Simulation time 356703287 ps
CPU time 5.32 seconds
Started May 14 01:05:23 PM PDT 24
Finished May 14 01:05:37 PM PDT 24
Peak memory 220052 kb
Host smart-b64a1397-39c9-4ebc-9f83-9362c6ae9a9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3523355560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3523355560
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4073668071
Short name T781
Test name
Test status
Simulation time 8668104868 ps
CPU time 133.46 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:07:48 PM PDT 24
Peak memory 255304 kb
Host smart-a10de0d6-6437-4d5e-b432-6026542e4157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073668071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4073668071
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2479082493
Short name T87
Test name
Test status
Simulation time 4782779295 ps
CPU time 25.55 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:06:00 PM PDT 24
Peak memory 216460 kb
Host smart-4592a74b-dc82-4520-8a88-953a229d4d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479082493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2479082493
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1209948019
Short name T357
Test name
Test status
Simulation time 25260247 ps
CPU time 0.75 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 205512 kb
Host smart-8b5482ce-7068-421f-8477-be41ba6a710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209948019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1209948019
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3599987036
Short name T735
Test name
Test status
Simulation time 263820301 ps
CPU time 1.63 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:36 PM PDT 24
Peak memory 216440 kb
Host smart-7f64913a-156b-4acb-a035-8ff481b5b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599987036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3599987036
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3638741479
Short name T570
Test name
Test status
Simulation time 46420085 ps
CPU time 0.87 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:05:36 PM PDT 24
Peak memory 205812 kb
Host smart-dd8518ba-1fa0-4f0e-8bca-8b73a4de60cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638741479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3638741479
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.228843436
Short name T362
Test name
Test status
Simulation time 3407971316 ps
CPU time 15.65 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:05:49 PM PDT 24
Peak memory 234940 kb
Host smart-d4841607-b4d4-4911-b5d0-703b24f5fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228843436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.228843436
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.952657477
Short name T444
Test name
Test status
Simulation time 40944609 ps
CPU time 0.7 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:40 PM PDT 24
Peak memory 205700 kb
Host smart-20b77c5d-f9fd-4470-a8cb-af427f3db144
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952657477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.952657477
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1470463233
Short name T553
Test name
Test status
Simulation time 1064979929 ps
CPU time 8.2 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 234760 kb
Host smart-af7a5469-12c1-46ff-a955-8b2deb89f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470463233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1470463233
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4247893231
Short name T500
Test name
Test status
Simulation time 112658666 ps
CPU time 0.83 seconds
Started May 14 01:05:24 PM PDT 24
Finished May 14 01:05:34 PM PDT 24
Peak memory 205680 kb
Host smart-e7b9c428-fc3a-4730-a49f-6ab96a8ad04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247893231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4247893231
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1514574606
Short name T235
Test name
Test status
Simulation time 1379808430 ps
CPU time 30.08 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:06:04 PM PDT 24
Peak memory 240976 kb
Host smart-6d73a981-2541-4bd2-b63f-0b4a6e430fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514574606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1514574606
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2120967008
Short name T19
Test name
Test status
Simulation time 8922421806 ps
CPU time 63.08 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:06:42 PM PDT 24
Peak memory 255004 kb
Host smart-d5eac4a9-40b5-4838-be15-12cc473f7e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120967008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2120967008
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3748457365
Short name T780
Test name
Test status
Simulation time 297793039 ps
CPU time 3.02 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:37 PM PDT 24
Peak memory 224564 kb
Host smart-d1246ccc-89d1-4c81-be3e-6020d241233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748457365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3748457365
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.889073448
Short name T674
Test name
Test status
Simulation time 452453162 ps
CPU time 2.98 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:47 PM PDT 24
Peak memory 224544 kb
Host smart-be4d92ad-3399-462a-80a5-bf238adcee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889073448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.889073448
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1691794336
Short name T182
Test name
Test status
Simulation time 85863427 ps
CPU time 3.77 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 233732 kb
Host smart-64f87a6f-d5fb-46fb-987d-5eb9aad7aabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691794336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1691794336
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1815066056
Short name T950
Test name
Test status
Simulation time 24852284 ps
CPU time 1.04 seconds
Started May 14 01:05:27 PM PDT 24
Finished May 14 01:05:37 PM PDT 24
Peak memory 217936 kb
Host smart-30ff3854-7637-4e8f-b206-1204cc16b9d7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815066056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1815066056
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.19702583
Short name T296
Test name
Test status
Simulation time 14055544395 ps
CPU time 12.72 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:51 PM PDT 24
Peak memory 233592 kb
Host smart-2d7cccf9-8334-4d30-84b1-f9ee1547ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19702583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.19702583
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.69067856
Short name T157
Test name
Test status
Simulation time 555359713 ps
CPU time 3.58 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 216884 kb
Host smart-90ef54df-0bd8-4643-8909-b3961838424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69067856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.69067856
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1713263694
Short name T819
Test name
Test status
Simulation time 1417878827 ps
CPU time 15.97 seconds
Started May 14 01:05:23 PM PDT 24
Finished May 14 01:05:48 PM PDT 24
Peak memory 222856 kb
Host smart-f1297caf-ea46-476c-8f49-1fb69873b94c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1713263694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1713263694
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.905097384
Short name T154
Test name
Test status
Simulation time 221648944 ps
CPU time 0.98 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 206568 kb
Host smart-6a6d48db-b44f-4b34-99ac-4783767cd587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905097384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.905097384
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3232240864
Short name T880
Test name
Test status
Simulation time 13256363126 ps
CPU time 31.41 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:06:07 PM PDT 24
Peak memory 216604 kb
Host smart-ae892bcb-4a52-4850-82a0-0b7a08e1888f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232240864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3232240864
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1589178138
Short name T795
Test name
Test status
Simulation time 159837600 ps
CPU time 1.18 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:35 PM PDT 24
Peak memory 207816 kb
Host smart-0a2959d0-d71b-4f0c-913a-d02ffddecbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589178138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1589178138
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3040323134
Short name T695
Test name
Test status
Simulation time 92191072 ps
CPU time 0.95 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:05:36 PM PDT 24
Peak memory 206828 kb
Host smart-ff2e0d1b-8eea-4621-9620-028ebdaa8781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040323134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3040323134
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1582106980
Short name T347
Test name
Test status
Simulation time 90490503 ps
CPU time 0.91 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 205816 kb
Host smart-3572e978-26cc-49b4-b275-84bed721b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582106980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1582106980
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3626484679
Short name T380
Test name
Test status
Simulation time 283518202 ps
CPU time 2.65 seconds
Started May 14 01:05:25 PM PDT 24
Finished May 14 01:05:37 PM PDT 24
Peak memory 234256 kb
Host smart-6ea1a16f-602a-4bd5-99ec-d401a304b709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626484679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3626484679
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1057300334
Short name T588
Test name
Test status
Simulation time 13802954 ps
CPU time 0.75 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:43 PM PDT 24
Peak memory 205400 kb
Host smart-7c89fcf4-6adb-4c6c-b5c2-a72f582495f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057300334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
057300334
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2313655822
Short name T176
Test name
Test status
Simulation time 989573657 ps
CPU time 5.49 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:05:55 PM PDT 24
Peak memory 224428 kb
Host smart-2db880e4-a031-41fe-a700-671fc6c92ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313655822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2313655822
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2429587659
Short name T46
Test name
Test status
Simulation time 68646337 ps
CPU time 0.74 seconds
Started May 14 01:05:31 PM PDT 24
Finished May 14 01:05:39 PM PDT 24
Peak memory 206764 kb
Host smart-07299c01-1871-4e37-9e07-ab9175ade2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429587659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2429587659
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2790571179
Short name T468
Test name
Test status
Simulation time 29180036217 ps
CPU time 125.34 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:07:55 PM PDT 24
Peak memory 249216 kb
Host smart-421a9817-9082-4ab2-b4f9-a472d8b10ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790571179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2790571179
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3684026680
Short name T424
Test name
Test status
Simulation time 3994038044 ps
CPU time 94.03 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:07:26 PM PDT 24
Peak memory 257548 kb
Host smart-cba61e8a-00e9-438a-ac7f-294c4187f873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684026680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3684026680
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4140912037
Short name T314
Test name
Test status
Simulation time 16452549290 ps
CPU time 46.8 seconds
Started May 14 01:05:38 PM PDT 24
Finished May 14 01:06:39 PM PDT 24
Peak memory 254024 kb
Host smart-4f05b337-dee3-426b-acb9-d91a0e9ab916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140912037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4140912037
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1311337671
Short name T945
Test name
Test status
Simulation time 2526886495 ps
CPU time 14.52 seconds
Started May 14 01:05:33 PM PDT 24
Finished May 14 01:05:56 PM PDT 24
Peak memory 234388 kb
Host smart-8fabd8e2-bf4b-40e9-98ea-92b843842ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311337671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1311337671
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2305386340
Short name T209
Test name
Test status
Simulation time 1439134850 ps
CPU time 4.29 seconds
Started May 14 01:05:27 PM PDT 24
Finished May 14 01:05:40 PM PDT 24
Peak memory 234376 kb
Host smart-c9dd2980-77fb-440d-9fc3-cda9399f9f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305386340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2305386340
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1880764422
Short name T537
Test name
Test status
Simulation time 6066531191 ps
CPU time 18.43 seconds
Started May 14 01:05:22 PM PDT 24
Finished May 14 01:05:50 PM PDT 24
Peak memory 236368 kb
Host smart-082c43b1-a1db-41c2-99cd-049536151c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880764422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1880764422
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2029141588
Short name T25
Test name
Test status
Simulation time 51563550 ps
CPU time 1.03 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:05:36 PM PDT 24
Peak memory 217904 kb
Host smart-237fffde-29c6-4bad-8e96-a7ac627b0a5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029141588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2029141588
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3779810103
Short name T199
Test name
Test status
Simulation time 45887800 ps
CPU time 2.59 seconds
Started May 14 01:05:28 PM PDT 24
Finished May 14 01:05:39 PM PDT 24
Peak memory 233528 kb
Host smart-8c906f2d-59f9-4059-bf00-973e2f574f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779810103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3779810103
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.154042060
Short name T915
Test name
Test status
Simulation time 639866359 ps
CPU time 7.26 seconds
Started May 14 01:05:35 PM PDT 24
Finished May 14 01:05:52 PM PDT 24
Peak memory 222984 kb
Host smart-1667cc54-8526-46f4-a23e-6dd703aeab2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=154042060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.154042060
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3957665241
Short name T935
Test name
Test status
Simulation time 37743854216 ps
CPU time 404.52 seconds
Started May 14 01:05:34 PM PDT 24
Finished May 14 01:12:27 PM PDT 24
Peak memory 273896 kb
Host smart-151a061b-5119-4ef3-b581-9a1b4b3bcbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957665241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3957665241
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3843077443
Short name T725
Test name
Test status
Simulation time 9653619772 ps
CPU time 20.99 seconds
Started May 14 01:05:26 PM PDT 24
Finished May 14 01:05:56 PM PDT 24
Peak memory 216552 kb
Host smart-87566f78-fad1-426e-9dfd-93edf2684782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843077443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3843077443
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1831690930
Short name T75
Test name
Test status
Simulation time 3017008679 ps
CPU time 6.17 seconds
Started May 14 01:05:27 PM PDT 24
Finished May 14 01:05:42 PM PDT 24
Peak memory 216496 kb
Host smart-878a3c56-5f72-4f4d-bc96-fd7b4bdfff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831690930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1831690930
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3156694534
Short name T526
Test name
Test status
Simulation time 234057460 ps
CPU time 1.49 seconds
Started May 14 01:05:28 PM PDT 24
Finished May 14 01:05:38 PM PDT 24
Peak memory 216428 kb
Host smart-9b63167e-a266-440e-9215-c4cd77327a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156694534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3156694534
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2188852748
Short name T647
Test name
Test status
Simulation time 388985583 ps
CPU time 0.79 seconds
Started May 14 01:05:30 PM PDT 24
Finished May 14 01:05:40 PM PDT 24
Peak memory 205792 kb
Host smart-590ee157-3ec3-4e56-a495-72df2678635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188852748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2188852748
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1467685907
Short name T960
Test name
Test status
Simulation time 1856507153 ps
CPU time 13.19 seconds
Started May 14 01:05:37 PM PDT 24
Finished May 14 01:06:04 PM PDT 24
Peak memory 238768 kb
Host smart-9d49fe34-7359-478d-afc5-382887f36b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467685907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1467685907
Directory /workspace/9.spi_device_upload/latest
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