Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2779006	1			T1	1		T3	73		T4	4
all_values[1]	2779006	1			T1	1		T3	73		T4	4
all_values[2]	2779006	1			T1	1		T3	73		T4	4
all_values[3]	2779006	1			T1	1		T3	73		T4	4
all_values[4]	2779006	1			T1	1		T3	73		T4	4
all_values[5]	2779006	1			T1	1		T3	73		T4	4
all_values[6]	2779006	1			T1	1		T3	73		T4	4
all_values[7]	2779006	1			T1	1		T3	73		T4	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21975556

1

T1

8

T3

584

T4

32

auto[1]

256492

1

T62

67

T34

22

T63

31338

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22207573

1

T1

8

T3

584

T4

32

auto[1]

24475

1

T8

109

T16

248

T18

124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2754601	1			T1	1		T3	73		T4	4
all_values[0]	auto[0]	auto[1]	12656	1			T8	73		T16	134		T18	77
all_values[0]	auto[1]	auto[0]	11210	1			T62	3		T34	4		T63	6171
all_values[0]	auto[1]	auto[1]	539	1			T62	1		T63	93		T64	1
all_values[1]	auto[0]	auto[0]	2732349	1			T1	1		T3	73		T4	4
all_values[1]	auto[0]	auto[1]	6643	1			T8	18		T16	107		T18	46
all_values[1]	auto[1]	auto[0]	39719	1			T62	3		T34	2		T63	6188
all_values[1]	auto[1]	auto[1]	295	1			T62	2		T63	78		T64	1
all_values[2]	auto[0]	auto[0]	2742823	1			T1	1		T3	73		T4	4
all_values[2]	auto[0]	auto[1]	2277	1			T8	18		T16	7		T18	1
all_values[2]	auto[1]	auto[0]	33654	1			T62	5		T64	2		T153	11
all_values[2]	auto[1]	auto[1]	252	1			T62	6		T63	3		T64	2
all_values[3]	auto[0]	auto[0]	2772109	1			T1	1		T3	73		T4	4
all_values[3]	auto[0]	auto[1]	164	1			T62	2		T63	1		T153	4
all_values[3]	auto[1]	auto[0]	6551	1			T62	6		T34	3		T63	6261
all_values[3]	auto[1]	auto[1]	182	1			T62	4		T34	2		T63	6
all_values[4]	auto[0]	auto[0]	2760586	1			T1	1		T3	73		T4	4
all_values[4]	auto[0]	auto[1]	161	1			T62	3		T34	1		T63	3
all_values[4]	auto[1]	auto[0]	18075	1			T62	4		T34	3		T63	2
all_values[4]	auto[1]	auto[1]	184	1			T62	2		T34	2		T63	2
all_values[5]	auto[0]	auto[0]	2721470	1			T1	1		T3	73		T4	4
all_values[5]	auto[0]	auto[1]	291	1			T62	4		T251	4		T142	6
all_values[5]	auto[1]	auto[0]	57100	1			T62	11		T34	5		T63	6264
all_values[5]	auto[1]	auto[1]	145	1			T62	1		T63	2		T64	1
all_values[6]	auto[0]	auto[0]	2726423	1			T1	1		T3	73		T4	4
all_values[6]	auto[0]	auto[1]	147	1			T62	5		T34	1		T63	1
all_values[6]	auto[1]	auto[0]	52261	1			T62	4		T34	1		T63	6263
all_values[6]	auto[1]	auto[1]	175	1			T62	7		T63	2		T64	3
all_values[7]	auto[0]	auto[0]	2742671	1			T1	1		T3	73		T4	4
all_values[7]	auto[0]	auto[1]	185	1			T62	6		T63	3		T153	7
all_values[7]	auto[1]	auto[0]	35971	1			T62	7		T64	3		T153	5
all_values[7]	auto[1]	auto[1]	179	1			T62	1		T63	3		T64	2