Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32437	1			T3	8		T6	12		T8	146
auto[SpiFlashAddrCfg]	6931	1			T3	2		T8	59		T9	2
auto[SpiFlashAddr3b]	8502	1			T3	2		T8	60		T11	2
auto[SpiFlashAddr4b]	6990	1			T3	8		T8	57		T9	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31215

1

T3

20

T6

12

T8

160

auto[1]

23645

1

T8

162

T16

298

T18

117

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28446

1

T3

12

T6

10

T8

161

auto[1]

26414

1

T3

8

T6

2

T8

161

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36759	1			T3	12		T6	12		T8	173
values[1]	1091	1			T8	4		T15	4		T16	19
values[2]	1426	1			T8	16		T16	14		T18	10
values[3]	1317	1			T8	15		T16	19		T18	4
values[4]	1344	1			T3	2		T8	12		T15	2
values[5]	1331	1			T8	6		T16	12		T18	11
values[6]	1349	1			T8	11		T15	2		T16	14
values[7]	1321	1			T8	7		T11	2		T16	12
values[8]	8922	1			T3	6		T8	78		T9	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26490

1

T3

20

T6

12

T8

322

auto[1]

28370

1

T16

212

T21

47

T27

268

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52849

1

T3

20

T6

12

T8

309

write

2011

1

T8

13

T16

24

T18

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18103

1

T3

10

T8

148

T9

6

valids[0x1]

36757

1

T3

10

T6

12

T8

174

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1464	1			T8	10		T16	16		T18	8
internal_process_ops[0x5a]	1440	1			T8	10		T16	21		T18	11
internal_process_ops[0x05]	19587	1			T3	2		T6	2		T8	50
internal_process_ops[0x35]	1434	1			T3	4		T8	12		T9	4
internal_process_ops[0x15]	1473	1			T3	2		T6	10		T8	10
internal_process_ops[0x03]	959	1			T8	13		T9	2		T15	2
internal_process_ops[0x0b]	974	1			T8	6		T16	17		T18	10
internal_process_ops[0x3b]	937	1			T3	4		T8	11		T15	2
internal_process_ops[0x6b]	970	1			T8	9		T9	6		T16	6
internal_process_ops[0xbb]	977	1			T8	11		T11	2		T16	10
internal_process_ops[0xeb]	968	1			T8	10		T14	2		T15	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53927

1

T3

20

T6

12

T8

312

auto[1]

933

1

T8

10

T16

8

T18

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52911

1

T3

20

T6

12

T8

310

auto[1]

1949

1

T8

12

T16

24

T18

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9266

1

T3

8

T6

12

T8

80

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5241

1

T8

64

T16

152

T18

42

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1819

1

T3

2

T8

23

T9

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1554

1

T8

33

T16

19

T18

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2306

1

T3

2

T8

26

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1885

1

T8

28

T16

28

T18

26

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1937

1

T3

8

T8

25

T9

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1587

1

T8

30

T16

21

T18

29

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

62

1

T8

1

T16

1

T28

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

37

1

T8

1

T32

2

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T29

2

T30

2

T177

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

37

1

T18

2

T28

1

T29

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

71

1

T16

1

T43

2

T30

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

40

1

T8

1

T16

1

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

63

1

T177

3

T32

1

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T8

2

T29

1

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

53

1

T43

2

T29

1

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

55

1

T8

2

T18

1

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

54

1

T16

1

T29

1

T30

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

55

1

T8

4

T16

1

T18

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

80

1

T8

1

T16

5

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

43

1

T28

2

T30

2

T31

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

41

1

T8

1

T31

2

T33

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

70

1

T16

3

T28

1

T30

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9936

1

T16

98

T21

17

T27

69

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7515

1

T16

16

T21

8

T27

62

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1485

1

T16

10

T21

3

T27

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1576

1

T16

21

T21

5

T27

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1982

1

T16

17

T21

1

T27

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1826

1

T16

22

T21

2

T27

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1485

1

T16

6

T21

4

T27

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1449

1

T16

11

T21

5

T27

23

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

74

1

T39

1

T178

1

T179

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

64

1

T39

1

T41

1

T178

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

73

1

T27

2

T41

1

T34

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

61

1

T27

2

T34

1

T178

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

70

1

T16

1

T27

1

T41

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T16

1

T39

2

T178

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

84

1

T21

2

T27

1

T39

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

56

1

T41

2

T34

2

T180

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

55

1

T16

2

T39

2

T178

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

74

1

T27

3

T41

2

T178

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T27

1

T39

1

T137

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

78

1

T27

1

T178

1

T179

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

79

1

T16

4

T27

1

T34

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T41

3

T34

2

T136

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

69

1

T16

1

T39

1

T34

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

58

1

T16

2

T27

2

T39

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3537	1			T3	2		T8	58		T16	48
auto[0]	values[0]	valids[0x1]	13342	1			T3	10		T6	12		T8	115
auto[0]	values[1]	valids[0x1]	526	1			T8	4		T15	4		T16	11
auto[0]	values[2]	valids[0x0]	487	1			T8	11		T16	2		T18	7
auto[0]	values[2]	valids[0x1]	258	1			T8	5		T16	5		T18	3
auto[0]	values[3]	valids[0x0]	437	1			T8	9		T16	11		T18	2
auto[0]	values[3]	valids[0x1]	285	1			T8	6		T16	3		T18	2
auto[0]	values[4]	valids[0x0]	458	1			T3	2		T8	5		T15	2
auto[0]	values[4]	valids[0x1]	250	1			T8	7		T16	5		T18	4
auto[0]	values[5]	valids[0x0]	441	1			T8	4		T16	3		T18	7
auto[0]	values[5]	valids[0x1]	263	1			T8	2		T16	1		T18	4
auto[0]	values[6]	valids[0x0]	478	1			T8	9		T16	6		T18	5
auto[0]	values[6]	valids[0x1]	260	1			T8	2		T15	2		T16	4
auto[0]	values[7]	valids[0x0]	454	1			T8	5		T11	2		T16	9
auto[0]	values[7]	valids[0x1]	245	1			T8	2		T16	2		T18	3
auto[0]	values[8]	valids[0x0]	3003	1			T3	6		T8	47		T9	6
auto[0]	values[8]	valids[0x1]	1766	1			T8	31		T16	18		T18	21
auto[1]	values[0]	valids[0x0]	4095	1			T16	42		T21	15		T27	41
auto[1]	values[0]	valids[0x1]	15785	1			T16	86		T21	17		T27	122
auto[1]	values[1]	valids[0x1]	565	1			T16	8		T21	1		T27	5
auto[1]	values[2]	valids[0x0]	396	1			T16	4		T27	3		T39	4
auto[1]	values[2]	valids[0x1]	285	1			T16	3		T21	1		T27	2
auto[1]	values[3]	valids[0x0]	375	1			T16	4		T21	1		T27	5
auto[1]	values[3]	valids[0x1]	220	1			T16	1		T27	1		T39	3
auto[1]	values[4]	valids[0x0]	387	1			T16	4		T27	2		T39	3
auto[1]	values[4]	valids[0x1]	249	1			T16	1		T27	7		T39	2
auto[1]	values[5]	valids[0x0]	401	1			T16	4		T21	1		T27	3
auto[1]	values[5]	valids[0x1]	226	1			T16	4		T39	1		T41	7
auto[1]	values[6]	valids[0x0]	374	1			T16	3		T21	1		T27	4
auto[1]	values[6]	valids[0x1]	237	1			T16	1		T21	1		T27	3
auto[1]	values[7]	valids[0x0]	398	1			T27	4		T39	5		T154	2
auto[1]	values[7]	valids[0x1]	224	1			T16	1		T41	1		T178	3
auto[1]	values[8]	valids[0x0]	2382	1			T16	25		T21	8		T27	39
auto[1]	values[8]	valids[0x1]	1771	1			T16	21		T21	1		T27	27