Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2987858

1

T3

17703

T6

1080

T8

22150

auto[1]

18065

1

T8

42

T16

231

T18

24

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

827955

1

T3

1

T6

1080

T8

81

auto[1]

2177968

1

T3

17702

T8

22111

T16

23469

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	559651	1			T3	17703		T8	7027		T9	51
auto[524288:1048575]	375774	1			T6	96		T8	3664		T9	903
auto[1048576:1572863]	350736	1			T6	114		T8	2105		T9	558
auto[1572864:2097151]	330812	1			T6	80		T8	304		T9	209
auto[2097152:2621439]	345177	1			T6	154		T8	529		T9	39
auto[2621440:3145727]	391553	1			T8	135		T14	146		T16	3062
auto[3145728:3670015]	299794	1			T6	44		T8	1		T9	395
auto[3670016:4194303]	352426	1			T6	592		T8	8427		T9	45

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2198056

1

T3

17703

T6

53

T8

22191

auto[1]

807867

1

T6

1027

T8

1

T9

2172

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2571059

1

T3

17703

T6

1080

T8

18980

auto[1]

434864

1

T8

3212

T16

6842

T18

8416

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	193396	1			T3	1		T8	15		T9	51
auto[0]	auto[0]	auto[0:524287]	auto[1]	314751	1			T3	17702		T8	7002		T16	2487
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	94021	1			T6	96		T8	12		T9	903
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	221045	1			T8	3377		T16	1063		T18	519
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	85714	1			T6	114		T8	5		T9	558
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	217186	1			T8	2095		T16	3345		T18	2256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	78856	1			T6	80		T8	6		T9	209
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	185450	1			T8	295		T16	1686		T18	513
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	94784	1			T6	154		T9	39		T14	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	189201	1			T16	902		T18	1		T27	1404
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	124420	1			T8	2		T14	146		T16	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	229172	1			T8	129		T16	3053		T18	527
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	74599	1			T6	44		T9	395		T14	78
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	168180	1			T16	775		T27	768		T37	2808
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	74842	1			T6	592		T8	11		T9	45
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	210861	1			T8	6002		T16	3154		T27	1929
auto[0]	auto[1]	auto[0:524287]	auto[0]	1768	1			T8	3		T16	2		T27	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	46715	1			T16	1		T27	512		T28	6
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	516	1			T8	5		T16	2		T18	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	58164	1			T8	256		T16	2976		T18	2485
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	595	1			T8	1		T16	4		T18	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	44893	1			T8	3		T16	512		T27	922
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	704	1			T16	7		T27	2		T37	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	63518	1			T16	3044		T29	2091		T30	129
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	406	1			T8	3		T16	6		T27	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	58603	1			T8	513		T16	256		T39	3580
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	280	1			T8	1		T16	3		T18	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	35773	1			T18	129		T29	3360		T30	513
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	789	1			T8	1		T18	1		T27	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54104	1			T16	8		T39	3		T41	238
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	314	1			T8	4		T27	10		T39	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	64238	1			T8	2409		T18	5784		T27	277
auto[1]	auto[0]	auto[0:524287]	auto[0]	268	1			T8	4		T16	3		T21	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2347	1			T8	3		T16	47		T21	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	210	1			T8	3		T16	1		T18	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1474	1			T8	11		T16	7		T18	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	177	1			T8	1		T16	2		T41	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1616	1			T16	39		T29	7		T31	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	192	1			T8	1		T16	4		T18	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1665	1			T8	2		T16	9		T18	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	193	1			T16	6		T18	1		T27	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1478	1			T16	71		T18	4		T27	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	179	1			T8	1		T18	3		T21	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1409	1			T8	2		T18	2		T21	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	168	1			T16	2		T41	2		T29	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1345	1			T16	16		T41	1		T30	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	173	1			T8	1		T16	2		T27	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1687	1			T16	1		T27	8		T39	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	49	1			T16	1		T28	1		T41	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	357	1			T16	5		T41	1		T33	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	41	1			T16	1		T177	1		T268	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	303	1			T16	7		T177	1		T268	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	56	1			T39	2		T177	1		T32	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	499	1			T39	25		T177	5		T32	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	55	1			T16	2		T30	1		T32	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	372	1			T16	5		T32	5		T33	30
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	49	1			T8	1		T41	1		T29	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	463	1			T8	12		T29	1		T34	20
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	34	1			T18	1		T30	1		T31	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	286	1			T18	4		T31	1		T85	14
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	49	1			T39	3		T29	1		T177	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	560	1			T39	82		T177	17		T33	21
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	58	1			T27	3		T29	5		T30	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	253	1			T27	14		T29	5		T34	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1751502	1			T3	17703		T6	53		T8	18951
auto[0]	auto[0]	auto[1]	804976	1			T6	1027		T9	2172		T12	6705
auto[0]	auto[1]	auto[0]	428868	1			T8	3198		T16	6820		T18	8411
auto[0]	auto[1]	auto[1]	2512	1			T8	1		T16	1		T39	1
auto[1]	auto[0]	auto[0]	14271	1			T8	29		T16	203		T18	18
auto[1]	auto[0]	auto[1]	310	1			T16	7		T18	1		T43	1
auto[1]	auto[1]	auto[0]	3415	1			T8	13		T16	20		T18	5
auto[1]	auto[1]	auto[1]	69	1			T16	1		T29	3		T177	1