Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15769

1

T3

20

T6

12

T8

160

auto[1]

10721

1

T8

162

T16

225

T18

117

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3044	1			T8	55		T16	71		T18	60
values[1]	3290	1			T8	92		T14	2		T15	8
values[2]	3243	1			T107	6		T198	26		T29	43
values[3]	4126	1			T8	70		T16	148		T18	67
values[4]	2858	1			T8	20		T18	25		T37	40
values[5]	3562	1			T3	20		T6	12		T8	20
values[6]	3279	1			T9	14		T11	20		T16	20
values[7]	3088	1			T8	65		T16	99		T18	25

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2982	1			T3	20		T11	20		T18	20
values[1]	3337	1			T8	74		T16	71		T123	6
values[2]	3473	1			T8	70		T15	8		T16	40
values[3]	3049	1			T6	12		T8	20		T16	63
values[4]	3204	1			T8	25		T16	102		T18	20
values[5]	2931	1			T8	67		T14	2		T16	20
values[6]	3838	1			T8	42		T9	14		T16	77
values[7]	3676	1			T8	24		T16	46		T18	107

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	201	1			T81	16		T168	18		T226	10
auto[0]	values[0]	values[1]	226	1			T8	13		T16	6		T187	16
auto[0]	values[0]	values[2]	126	1			T28	14		T96	12		T176	34
auto[0]	values[0]	values[3]	222	1			T28	10		T30	8		T193	11
auto[0]	values[0]	values[4]	313	1			T32	21		T270	10		T278	8
auto[0]	values[0]	values[5]	125	1			T191	14		T183	13		T221	15
auto[0]	values[0]	values[6]	378	1			T8	15		T29	6		T32	46
auto[0]	values[0]	values[7]	273	1			T18	29		T177	11		T34	26
auto[0]	values[1]	values[0]	144	1			T29	5		T31	26		T33	8
auto[0]	values[1]	values[1]	257	1			T200	24		T33	22		T81	11
auto[0]	values[1]	values[2]	512	1			T15	8		T16	14		T18	10
auto[0]	values[1]	values[3]	160	1			T36	4		T32	12		T33	10
auto[0]	values[1]	values[4]	172	1			T8	8		T31	14		T32	13
auto[0]	values[1]	values[5]	163	1			T8	25		T14	2		T29	12
auto[0]	values[1]	values[6]	266	1			T8	11		T31	13		T185	72
auto[0]	values[1]	values[7]	185	1			T168	12		T199	23		T279	13
auto[0]	values[2]	values[0]	262	1			T32	9		T234	11		T280	6
auto[0]	values[2]	values[1]	214	1			T33	80		T167	17		T261	9
auto[0]	values[2]	values[2]	280	1			T107	6		T63	13		T183	14
auto[0]	values[2]	values[3]	170	1			T30	9		T197	19		T281	16
auto[0]	values[2]	values[4]	147	1			T29	4		T81	14		T167	21
auto[0]	values[2]	values[5]	236	1			T198	26		T177	10		T63	8
auto[0]	values[2]	values[6]	310	1			T29	11		T63	16		T185	18
auto[0]	values[2]	values[7]	285	1			T33	15		T63	12		T221	12
auto[0]	values[3]	values[0]	236	1			T18	16		T31	5		T85	30
auto[0]	values[3]	values[1]	338	1			T123	6		T28	12		T177	14
auto[0]	values[3]	values[2]	238	1			T8	25		T32	11		T33	10
auto[0]	values[3]	values[3]	433	1			T8	9		T50	2		T166	18
auto[0]	values[3]	values[4]	453	1			T16	50		T18	7		T181	22
auto[0]	values[3]	values[5]	70	1			T8	16		T63	9		T282	28
auto[0]	values[3]	values[6]	355	1			T18	13		T106	6		T81	18
auto[0]	values[3]	values[7]	402	1			T16	11		T28	20		T188	16
auto[0]	values[4]	values[0]	227	1			T31	24		T197	10		T176	13
auto[0]	values[4]	values[1]	139	1			T95	12		T185	17		T176	6
auto[0]	values[4]	values[2]	243	1			T8	9		T30	8		T283	16
auto[0]	values[4]	values[3]	254	1			T18	13		T30	10		T81	12
auto[0]	values[4]	values[4]	229	1			T37	10		T204	12		T284	2
auto[0]	values[4]	values[5]	163	1			T29	22		T177	18		T201	10
auto[0]	values[4]	values[6]	271	1			T29	9		T177	12		T32	10
auto[0]	values[4]	values[7]	203	1			T37	16		T30	11		T184	2
auto[0]	values[5]	values[0]	241	1			T3	20		T30	26		T166	13
auto[0]	values[5]	values[1]	361	1			T30	8		T34	11		T63	26
auto[0]	values[5]	values[2]	172	1			T8	7		T16	16		T183	21
auto[0]	values[5]	values[3]	189	1			T6	12		T16	12		T34	9
auto[0]	values[5]	values[4]	259	1			T28	8		T207	14		T274	12
auto[0]	values[5]	values[5]	395	1			T33	38		T185	9		T241	10
auto[0]	values[5]	values[6]	364	1			T183	19		T193	10		T285	125
auto[0]	values[5]	values[7]	242	1			T18	22		T31	14		T32	25
auto[0]	values[6]	values[0]	255	1			T11	20		T28	14		T177	40
auto[0]	values[6]	values[1]	218	1			T272	12		T176	13		T226	20
auto[0]	values[6]	values[2]	252	1			T183	9		T167	9		T168	13
auto[0]	values[6]	values[3]	159	1			T37	8		T29	9		T189	12
auto[0]	values[6]	values[4]	246	1			T31	14		T177	31		T205	6
auto[0]	values[6]	values[5]	282	1			T16	9		T177	14		T85	147
auto[0]	values[6]	values[6]	293	1			T9	14		T33	12		T195	6
auto[0]	values[6]	values[7]	340	1			T18	9		T29	25		T32	75
auto[0]	values[7]	values[0]	235	1			T177	13		T34	9		T63	11
auto[0]	values[7]	values[1]	172	1			T8	14		T29	12		T32	12
auto[0]	values[7]	values[2]	248	1			T30	14		T85	21		T183	14
auto[0]	values[7]	values[3]	265	1			T16	16		T18	8		T32	15
auto[0]	values[7]	values[4]	148	1			T108	16		T85	28		T193	8
auto[0]	values[7]	values[5]	140	1			T258	12		T261	13		T242	13
auto[0]	values[7]	values[6]	170	1			T16	60		T34	12		T63	31
auto[0]	values[7]	values[7]	242	1			T8	8		T28	14		T29	20
auto[1]	values[0]	values[0]	113	1			T81	8		T286	10		T168	11
auto[1]	values[0]	values[1]	170	1			T8	20		T16	65		T81	7
auto[1]	values[0]	values[2]	101	1			T28	7		T176	26		T216	6
auto[1]	values[0]	values[3]	125	1			T28	10		T30	12		T193	10
auto[1]	values[0]	values[4]	174	1			T32	6		T203	12		T183	4
auto[1]	values[0]	values[5]	169	1			T183	7		T221	5		T190	12
auto[1]	values[0]	values[6]	123	1			T8	7		T29	14		T32	8
auto[1]	values[0]	values[7]	205	1			T18	31		T177	9		T34	8
auto[1]	values[1]	values[0]	158	1			T29	15		T31	14		T33	15
auto[1]	values[1]	values[1]	172	1			T33	80		T81	10		T183	12
auto[1]	values[1]	values[2]	146	1			T16	6		T18	10		T30	6
auto[1]	values[1]	values[3]	254	1			T32	14		T33	10		T81	8
auto[1]	values[1]	values[4]	177	1			T8	17		T31	10		T32	7
auto[1]	values[1]	values[5]	148	1			T8	22		T29	9		T32	18
auto[1]	values[1]	values[6]	212	1			T8	9		T31	7		T185	6
auto[1]	values[1]	values[7]	164	1			T168	8		T199	5		T279	7
auto[1]	values[2]	values[0]	171	1			T32	11		T54	8		T234	9
auto[1]	values[2]	values[1]	120	1			T33	5		T167	10		T261	11
auto[1]	values[2]	values[2]	384	1			T63	7		T183	49		T167	5
auto[1]	values[2]	values[3]	83	1			T30	11		T197	9		T226	13
auto[1]	values[2]	values[4]	120	1			T29	17		T81	6		T167	19
auto[1]	values[2]	values[5]	116	1			T177	10		T63	13		T208	31
auto[1]	values[2]	values[6]	206	1			T29	11		T63	6		T185	8
auto[1]	values[2]	values[7]	139	1			T33	10		T63	8		T221	26
auto[1]	values[3]	values[0]	154	1			T18	4		T31	18		T85	24
auto[1]	values[3]	values[1]	238	1			T28	8		T177	6		T34	13
auto[1]	values[3]	values[2]	274	1			T8	5		T32	9		T33	10
auto[1]	values[3]	values[3]	124	1			T8	11		T166	8		T167	2
auto[1]	values[3]	values[4]	331	1			T16	52		T18	13		T183	7
auto[1]	values[3]	values[5]	32	1			T8	4		T63	11		T282	6
auto[1]	values[3]	values[6]	265	1			T18	14		T81	3		T221	5
auto[1]	values[3]	values[7]	183	1			T16	35		T28	22		T110	6
auto[1]	values[4]	values[0]	163	1			T31	23		T197	12		T260	20
auto[1]	values[4]	values[1]	111	1			T185	3		T176	18		T168	28
auto[1]	values[4]	values[2]	156	1			T8	11		T30	13		T192	13
auto[1]	values[4]	values[3]	138	1			T18	12		T30	19		T81	10
auto[1]	values[4]	values[4]	184	1			T37	10		T259	16		T197	13
auto[1]	values[4]	values[5]	73	1			T29	8		T177	2		T287	8
auto[1]	values[4]	values[6]	156	1			T29	11		T177	8		T32	17
auto[1]	values[4]	values[7]	148	1			T37	4		T30	11		T247	11
auto[1]	values[5]	values[0]	141	1			T30	3		T166	7		T226	14
auto[1]	values[5]	values[1]	247	1			T30	12		T34	14		T63	7
auto[1]	values[5]	values[2]	133	1			T8	13		T16	4		T183	6
auto[1]	values[5]	values[3]	149	1			T16	29		T34	11		T167	5
auto[1]	values[5]	values[4]	90	1			T28	24		T237	6		T246	7
auto[1]	values[5]	values[5]	294	1			T33	26		T185	41		T241	39
auto[1]	values[5]	values[6]	125	1			T183	28		T193	10		T226	9
auto[1]	values[5]	values[7]	160	1			T18	5		T31	10		T32	9
auto[1]	values[6]	values[0]	154	1			T28	6		T177	37		T34	10
auto[1]	values[6]	values[1]	142	1			T176	10		T226	37		T288	7
auto[1]	values[6]	values[2]	97	1			T183	11		T167	11		T168	7
auto[1]	values[6]	values[3]	124	1			T37	12		T29	12		T221	14
auto[1]	values[6]	values[4]	96	1			T31	6		T177	7		T176	10
auto[1]	values[6]	values[5]	153	1			T16	11		T177	6		T85	11
auto[1]	values[6]	values[6]	251	1			T33	8		T63	8		T85	21
auto[1]	values[6]	values[7]	217	1			T18	11		T29	16		T32	16
auto[1]	values[7]	values[0]	127	1			T177	13		T34	11		T63	13
auto[1]	values[7]	values[1]	212	1			T8	27		T29	8		T32	8
auto[1]	values[7]	values[2]	111	1			T30	7		T85	19		T183	6
auto[1]	values[7]	values[3]	200	1			T16	6		T18	17		T32	10
auto[1]	values[7]	values[4]	65	1			T85	10		T193	13		T279	15
auto[1]	values[7]	values[5]	372	1			T261	9		T242	133		T192	4
auto[1]	values[7]	values[6]	93	1			T16	17		T34	8		T63	10
auto[1]	values[7]	values[7]	288	1			T8	16		T28	6		T29	30