Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	360	1			T8	3		T9	6		T16	3
auto[ReadAddrCrossIntoMailbox]	285	1			T8	7		T16	1		T18	2
auto[ReadAddrCrossOutOfMailbox]	281	1			T8	3		T16	1		T18	3
auto[ReadAddrCrossAllMailbox]	185	1			T8	2		T16	2		T18	4
auto[ReadAddrOutsideMailbox]	3096	1			T3	4		T8	45		T9	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2121

1

T3

2

T8

28

T9

4

auto[1]

2086

1

T3

2

T8

32

T9

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	712	1			T8	13		T9	2		T15	2
read_ops[0x0b]	697	1			T8	6		T16	13		T18	10
read_ops[0x3b]	664	1			T3	4		T8	11		T15	2
read_ops[0x6b]	695	1			T8	9		T9	6		T16	4
read_ops[0xbb]	711	1			T8	11		T11	2		T16	6
read_ops[0xeb]	728	1			T8	10		T14	2		T16	8

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T9	1		T205	1		T185	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T9	1		T16	1		T29	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T108	1		T29	1		T32	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T8	3		T18	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T8	1		T32	1		T270	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T8	1		T37	1		T63	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T32	1		T81	1		T270	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T63	1		T85	1		T270	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	241	1			T8	6		T15	1		T16	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T8	2		T15	1		T16	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T18	1		T177	1		T187	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T187	1		T81	2		T185	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T8	1		T177	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T29	1		T31	2		T34	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T8	1		T31	1		T33	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T29	1		T189	1		T85	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T8	1		T16	1		T18	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T189	1		T176	1		T247	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T8	1		T16	8		T18	6
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T8	2		T16	4		T28	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T28	1		T30	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T187	1		T85	1		T270	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T34	1		T270	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T28	1		T270	1		T221	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T18	1		T28	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T16	1		T33	1		T85	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T8	1		T31	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T272	1		T241	1		T176	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	231	1			T3	2		T8	2		T15	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T3	2		T8	8		T15	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T9	2		T30	1		T31	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T8	1		T9	2		T18	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T8	2		T18	1		T34	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T37	1		T31	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T29	1		T189	1		T185	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T31	1		T189	1		T63	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T32	1		T81	1		T185	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T16	1		T29	1		T85	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T8	4		T9	1		T16	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T8	2		T9	1		T16	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T8	1		T106	2		T28	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T16	1		T106	2		T29	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T108	1		T33	1		T190	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T16	1		T108	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T28	2		T32	1		T63	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T18	1		T29	1		T85	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T241	1		T289	2		T226	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T18	1		T32	1		T183	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T8	5		T11	1		T16	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T8	5		T11	1		T16	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T18	1		T34	1		T63	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T8	1		T16	1		T81	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	39	1			T29	1		T31	1		T63	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T8	1		T81	1		T272	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T18	1		T28	2		T31	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T28	1		T30	2		T32	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T177	1		T63	1		T183	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T30	1		T32	1		T81	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T8	2		T14	1		T16	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T8	6		T14	1		T16	4