Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2779006	1			T1	1		T3	73		T4	4
all_pins[1]	2779006	1			T1	1		T3	73		T4	4
all_pins[2]	2779006	1			T1	1		T3	73		T4	4
all_pins[3]	2779006	1			T1	1		T3	73		T4	4
all_pins[4]	2779006	1			T1	1		T3	73		T4	4
all_pins[5]	2779006	1			T1	1		T3	73		T4	4
all_pins[6]	2779006	1			T1	1		T3	73		T4	4
all_pins[7]	2779006	1			T1	1		T3	73		T4	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22176426	1			T1	8		T3	584		T4	32
values[0x1]	55622	1			T62	24		T34	4		T63	5926
transitions[0x0=>0x1]	54211	1			T62	22		T34	2		T63	5669
transitions[0x1=>0x0]	54222	1			T62	22		T34	2		T63	5669

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2778426	1			T1	1		T3	73		T4	4
all_pins[0]	values[0x1]	580	1			T62	1		T63	97		T64	1
all_pins[0]	transitions[0x0=>0x1]	457	1			T62	1		T63	17		T64	1
all_pins[0]	transitions[0x1=>0x0]	177	1			T62	2		T63	1		T64	1
all_pins[1]	values[0x0]	2778706	1			T1	1		T3	73		T4	4
all_pins[1]	values[0x1]	300	1			T62	2		T63	81		T64	1
all_pins[1]	transitions[0x0=>0x1]	269	1			T62	1		T63	81		T64	1
all_pins[1]	transitions[0x1=>0x0]	234	1			T62	5		T63	3		T64	2
all_pins[2]	values[0x0]	2778741	1			T1	1		T3	73		T4	4
all_pins[2]	values[0x1]	265	1			T62	6		T63	3		T64	2
all_pins[2]	transitions[0x0=>0x1]	213	1			T62	6		T44	96		T166	2
all_pins[2]	transitions[0x1=>0x0]	130	1			T62	4		T34	2		T63	3
all_pins[3]	values[0x0]	2778824	1			T1	1		T3	73		T4	4
all_pins[3]	values[0x1]	182	1			T62	4		T34	2		T63	6
all_pins[3]	transitions[0x0=>0x1]	129	1			T62	4		T63	5		T64	2
all_pins[3]	transitions[0x1=>0x0]	131	1			T62	2		T63	1		T153	4
all_pins[4]	values[0x0]	2778822	1			T1	1		T3	73		T4	4
all_pins[4]	values[0x1]	184	1			T62	2		T34	2		T63	2
all_pins[4]	transitions[0x0=>0x1]	151	1			T62	1		T34	2		T63	2
all_pins[4]	transitions[0x1=>0x0]	2564	1			T63	177		T64	1		T153	4
all_pins[5]	values[0x0]	2776409	1			T1	1		T3	73		T4	4
all_pins[5]	values[0x1]	2597	1			T62	1		T63	177		T64	1
all_pins[5]	transitions[0x0=>0x1]	1569	1			T62	1		T63	4		T64	1
all_pins[5]	transitions[0x1=>0x0]	50307	1			T62	7		T63	5384		T64	3
all_pins[6]	values[0x0]	2727671	1			T1	1		T3	73		T4	4
all_pins[6]	values[0x1]	51335	1			T62	7		T63	5557		T64	3
all_pins[6]	transitions[0x0=>0x1]	51293	1			T62	7		T63	5557		T64	1
all_pins[6]	transitions[0x1=>0x0]	137	1			T62	1		T63	3		T153	7
all_pins[7]	values[0x0]	2778827	1			T1	1		T3	73		T4	4
all_pins[7]	values[0x1]	179	1			T62	1		T63	3		T64	2
all_pins[7]	transitions[0x0=>0x1]	130	1			T62	1		T63	3		T64	1
all_pins[7]	transitions[0x1=>0x0]	542	1			T62	1		T63	97		T153	7