Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3295	1			T8	22		T18	20		T28	21
values[1]	3348	1			T6	12		T8	25		T9	14
values[2]	3162	1			T8	51		T14	2		T16	111
values[3]	3698	1			T8	33		T18	65		T28	40
values[4]	3356	1			T8	40		T11	20		T16	60
values[5]	3415	1			T8	51		T36	4		T18	40
values[6]	2922	1			T8	20		T15	8		T16	48
values[7]	3294	1			T3	20		T8	80		T16	137

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3695	1			T8	69		T9	14		T18	40
values[1]	2843	1			T16	128		T28	22		T29	91
values[2]	3321	1			T3	20		T8	20		T14	2
values[3]	4010	1			T16	61		T18	47		T28	40
values[4]	3323	1			T8	25		T15	8		T18	45
values[5]	2838	1			T8	20		T16	48		T18	45
values[6]	3361	1			T8	20		T11	20		T16	76
values[7]	3099	1			T6	12		T8	168		T16	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26090

1

T3

20

T6

12

T8

312

auto[1]

400

1

T8

10

T16

5

T18

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	[values[3]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	409	1			T8	22		T28	21		T29	41
auto[0]	values[0]	values[1]	397	1			T29	20		T32	20		T34	33
auto[0]	values[0]	values[2]	453	1			T29	20		T63	20		T176	20
auto[0]	values[0]	values[3]	637	1			T18	20		T30	20		T81	20
auto[0]	values[0]	values[4]	393	1			T181	22		T33	20		T34	20
auto[0]	values[0]	values[5]	259	1			T63	20		T182	20		T183	20
auto[0]	values[0]	values[6]	454	1			T184	2		T185	19		T186	14
auto[0]	values[0]	values[7]	243	1			T30	20		T32	25		T187	16
auto[0]	values[1]	values[0]	374	1			T9	14		T177	20		T185	78
auto[0]	values[1]	values[1]	397	1			T30	22		T188	16		T189	12
auto[0]	values[1]	values[2]	466	1			T29	20		T167	27		T190	42
auto[0]	values[1]	values[3]	482	1			T16	41		T18	27		T28	20
auto[0]	values[1]	values[4]	332	1			T8	25		T63	20		T191	14
auto[0]	values[1]	values[5]	433	1			T81	43		T185	50		T192	24
auto[0]	values[1]	values[6]	332	1			T16	22		T31	18		T33	23
auto[0]	values[1]	values[7]	485	1			T6	12		T43	81		T33	23
auto[0]	values[2]	values[0]	468	1			T8	26		T18	20		T177	20
auto[0]	values[2]	values[1]	416	1			T16	56		T30	19		T81	23
auto[0]	values[2]	values[2]	191	1			T14	2		T177	20		T32	20
auto[0]	values[2]	values[3]	383	1			T37	20		T177	26		T33	20
auto[0]	values[2]	values[4]	340	1			T31	23		T167	19		T193	40
auto[0]	values[2]	values[5]	277	1			T18	25		T110	6		T31	21
auto[0]	values[2]	values[6]	511	1			T16	54		T29	20		T185	26
auto[0]	values[2]	values[7]	536	1			T8	24		T107	6		T167	87
auto[0]	values[3]	values[0]	500	1			T33	83		T194	20		T193	48
auto[0]	values[3]	values[1]	433	1			T81	19		T167	23		T193	22
auto[0]	values[3]	values[2]	596	1			T18	20		T28	18		T177	20
auto[0]	values[3]	values[3]	547	1			T34	20		T195	6		T167	29
auto[0]	values[3]	values[4]	526	1			T18	44		T177	20		T190	68
auto[0]	values[3]	values[5]	389	1			T32	26		T35	14		T63	20
auto[0]	values[3]	values[6]	328	1			T32	60		T63	20		T183	27
auto[0]	values[3]	values[7]	317	1			T8	32		T28	20		T81	20
auto[0]	values[4]	values[0]	462	1			T177	38		T79	6		T185	20
auto[0]	values[4]	values[1]	141	1			T28	21		T29	21		T33	33
auto[0]	values[4]	values[2]	499	1			T8	20		T16	40		T183	62
auto[0]	values[4]	values[3]	439	1			T30	21		T32	51		T96	12
auto[0]	values[4]	values[4]	538	1			T28	20		T95	12		T183	19
auto[0]	values[4]	values[5]	248	1			T18	20		T28	31		T193	19
auto[0]	values[4]	values[6]	524	1			T11	20		T18	24		T63	33
auto[0]	values[4]	values[7]	474	1			T8	19		T16	20		T31	23
auto[0]	values[5]	values[0]	341	1			T18	20		T32	20		T196	4
auto[0]	values[5]	values[1]	285	1			T29	29		T32	43		T197	72
auto[0]	values[5]	values[2]	402	1			T36	4		T18	20		T29	30
auto[0]	values[5]	values[3]	630	1			T198	26		T108	16		T63	21
auto[0]	values[5]	values[4]	604	1			T30	28		T31	22		T34	25
auto[0]	values[5]	values[5]	140	1			T123	6		T37	40		T199	20
auto[0]	values[5]	values[6]	474	1			T30	16		T31	20		T32	26
auto[0]	values[5]	values[7]	475	1			T8	49		T34	25		T183	20
auto[0]	values[6]	values[0]	596	1			T8	20		T200	24		T32	19
auto[0]	values[6]	values[1]	370	1			T31	24		T177	20		T32	18
auto[0]	values[6]	values[2]	237	1			T177	35		T201	10		T202	14
auto[0]	values[6]	values[3]	487	1			T28	19		T85	19		T167	31
auto[0]	values[6]	values[4]	222	1			T15	8		T31	40		T203	12
auto[0]	values[6]	values[5]	433	1			T16	48		T106	6		T29	41
auto[0]	values[6]	values[6]	342	1			T33	31		T204	12		T54	4
auto[0]	values[6]	values[7]	180	1			T32	34		T63	20		T205	6
auto[0]	values[7]	values[0]	486	1			T31	24		T63	21		T206	16
auto[0]	values[7]	values[1]	354	1			T16	69		T29	20		T177	20
auto[0]	values[7]	values[2]	430	1			T3	20		T16	44		T29	20
auto[0]	values[7]	values[3]	366	1			T16	20		T207	14		T167	20
auto[0]	values[7]	values[4]	320	1			T30	20		T208	20		T209	16
auto[0]	values[7]	values[5]	617	1			T8	20		T30	20		T34	20
auto[0]	values[7]	values[6]	324	1			T8	18		T33	20		T81	19
auto[0]	values[7]	values[7]	346	1			T8	37		T210	2		T193	20
auto[1]	values[0]	values[0]	14	1			T29	1		T30	2		T32	1
auto[1]	values[0]	values[1]	3	1			T34	1		T211	2		-	-
auto[1]	values[0]	values[2]	4	1			T212	1		T213	2		T214	1
auto[1]	values[0]	values[3]	9	1			T30	1		T167	1		T208	2
auto[1]	values[0]	values[4]	5	1			T208	1		T215	4		-	-
auto[1]	values[0]	values[5]	4	1			T176	2		T216	2		-	-
auto[1]	values[0]	values[6]	9	1			T185	1		T217	1		T218	4
auto[1]	values[0]	values[7]	2	1			T32	1		T219	1		-	-
auto[1]	values[1]	values[0]	3	1			T208	1		T220	1		T211	1
auto[1]	values[1]	values[1]	8	1			T221	2		T192	1		T222	2
auto[1]	values[1]	values[2]	7	1			T29	1		T190	1		T223	2
auto[1]	values[1]	values[3]	3	1			T176	1		T222	1		T150	1
auto[1]	values[1]	values[4]	5	1			T185	2		T176	1		T168	1
auto[1]	values[1]	values[5]	7	1			T81	2		T217	2		T212	2
auto[1]	values[1]	values[6]	9	1			T31	2		T33	2		T192	4
auto[1]	values[1]	values[7]	5	1			T85	2		T223	1		T224	2
auto[1]	values[2]	values[0]	7	1			T8	1		T222	4		T217	1
auto[1]	values[2]	values[1]	6	1			T16	1		T30	1		T225	2
auto[1]	values[2]	values[2]	6	1			T177	2		T63	1		T222	3
auto[1]	values[2]	values[4]	5	1			T167	1		T193	3		T226	1
auto[1]	values[2]	values[5]	4	1			T31	1		T226	1		T150	1
auto[1]	values[2]	values[6]	8	1			T197	1		T176	1		T149	4
auto[1]	values[2]	values[7]	4	1			T176	2		T168	1		T212	1
auto[1]	values[3]	values[0]	7	1			T33	2		T227	1		T228	1
auto[1]	values[3]	values[1]	11	1			T81	1		T193	1		T226	4
auto[1]	values[3]	values[2]	11	1			T28	2		T167	2		T229	1
auto[1]	values[3]	values[3]	4	1			T167	1		T230	2		T231	1
auto[1]	values[3]	values[4]	10	1			T18	1		T199	2		T170	2
auto[1]	values[3]	values[5]	7	1			T32	1		T35	4		T183	1
auto[1]	values[3]	values[6]	4	1			T226	2		T232	2		-	-
auto[1]	values[3]	values[7]	8	1			T8	1		T233	1		T170	1
auto[1]	values[4]	values[0]	2	1			T234	1		T233	1		-	-
auto[1]	values[4]	values[1]	2	1			T28	1		T235	1		-	-
auto[1]	values[4]	values[2]	3	1			T183	1		T170	2		-	-
auto[1]	values[4]	values[3]	3	1			T32	3		-	-		-	-
auto[1]	values[4]	values[4]	6	1			T183	1		T236	1		T231	4
auto[1]	values[4]	values[5]	3	1			T28	1		T193	1		T235	1
auto[1]	values[4]	values[6]	8	1			T18	3		T237	2		T219	2
auto[1]	values[4]	values[7]	4	1			T8	1		T85	2		T238	1
auto[1]	values[5]	values[0]	5	1			T196	2		T226	1		T239	2
auto[1]	values[5]	values[1]	9	1			T29	1		T32	2		T197	3
auto[1]	values[5]	values[2]	4	1			T190	1		T231	2		T240	1
auto[1]	values[5]	values[3]	8	1			T241	4		T217	1		T220	1
auto[1]	values[5]	values[4]	11	1			T30	1		T31	2		T34	3
auto[1]	values[5]	values[5]	3	1			T199	1		T240	2		-	-
auto[1]	values[5]	values[6]	11	1			T30	4		T32	1		T226	3
auto[1]	values[5]	values[7]	13	1			T8	2		T226	3		T222	1
auto[1]	values[6]	values[0]	9	1			T32	1		T242	2		T243	4
auto[1]	values[6]	values[1]	5	1			T32	2		T167	1		T47	1
auto[1]	values[6]	values[2]	2	1			T244	2		-	-		-	-
auto[1]	values[6]	values[3]	10	1			T28	1		T85	1		T167	1
auto[1]	values[6]	values[4]	4	1			T245	2		T244	2		-	-
auto[1]	values[6]	values[5]	5	1			T29	1		T241	2		T47	2
auto[1]	values[6]	values[6]	17	1			T54	4		T167	1		T246	1
auto[1]	values[6]	values[7]	3	1			T247	2		T226	1		-	-
auto[1]	values[7]	values[0]	12	1			T185	3		T167	2		T228	5
auto[1]	values[7]	values[1]	6	1			T16	2		T85	1		T248	1
auto[1]	values[7]	values[2]	10	1			T16	2		T249	2		T247	2
auto[1]	values[7]	values[3]	2	1			T216	2		-	-		-	-
auto[1]	values[7]	values[4]	2	1			T250	2		-	-		-	-
auto[1]	values[7]	values[5]	9	1			T30	1		T176	3		T170	1
auto[1]	values[7]	values[6]	6	1			T8	2		T81	1		T170	1
auto[1]	values[7]	values[7]	4	1			T8	3		T231	1		-	-