Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1807

1

T1

3

T8

8

T10

6

auto[1]

1858

1

T1

7

T8

6

T10

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1989

1

T8

11

T10

10

T16

20

auto[1]

1676

1

T1

10

T8

3

T10

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2906

1

T1

10

T8

8

T10

8

auto[1]

759

1

T8

6

T10

3

T16

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	751	1			T1	1		T8	4		T10	3
valid[1]	730	1			T1	3		T8	4		T10	3
valid[2]	743	1			T1	3		T10	2		T16	6
valid[3]	724	1			T8	2		T10	2		T16	1
valid[4]	717	1			T1	3		T8	4		T10	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T8	1		T10	1		T16	2
auto[0]	auto[0]	valid[0]	auto[1]	152	1			T8	1		T42	2		T93	3
auto[0]	auto[0]	valid[1]	auto[0]	108	1			T16	1		T21	1		T27	2
auto[0]	auto[0]	valid[1]	auto[1]	158	1			T1	1		T19	2		T93	1
auto[0]	auto[0]	valid[2]	auto[0]	134	1			T16	4		T18	2		T27	1
auto[0]	auto[0]	valid[2]	auto[1]	152	1			T1	1		T19	3		T93	1
auto[0]	auto[0]	valid[3]	auto[0]	123	1			T21	2		T27	1		T28	2
auto[0]	auto[0]	valid[3]	auto[1]	166	1			T10	1		T18	1		T19	1
auto[0]	auto[0]	valid[4]	auto[0]	131	1			T8	1		T10	1		T16	2
auto[0]	auto[0]	valid[4]	auto[1]	159	1			T1	1		T93	3		T29	1
auto[0]	auto[1]	valid[0]	auto[0]	138	1			T8	1		T10	2		T16	2
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T1	1		T8	1		T19	2
auto[0]	auto[1]	valid[1]	auto[0]	106	1			T8	1		T10	1		T37	1
auto[0]	auto[1]	valid[1]	auto[1]	199	1			T1	2		T93	3		T29	2
auto[0]	auto[1]	valid[2]	auto[0]	116	1			T10	1		T16	1		T27	1
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T1	2		T19	1		T93	1
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T10	1		T18	3		T21	1
auto[0]	auto[1]	valid[3]	auto[1]	165	1			T8	1		T19	1		T93	2
auto[0]	auto[1]	valid[4]	auto[0]	127	1			T8	1		T16	1		T18	2
auto[0]	auto[1]	valid[4]	auto[1]	172	1			T1	2		T19	1		T93	2
auto[1]	auto[0]	valid[0]	auto[0]	73	1			T16	1		T18	1		T27	1
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T8	2		T10	2		T16	3
auto[1]	auto[0]	valid[2]	auto[0]	94	1			T10	1		T16	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	78	1			T8	1		T37	1		T41	1
auto[1]	auto[0]	valid[4]	auto[0]	72	1			T8	2		T28	1		T37	1
auto[1]	auto[1]	valid[0]	auto[0]	86	1			T37	1		T298	1		T34	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T8	1		T28	1		T303	2
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T27	2		T34	2		T303	3
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T16	1		T18	1		T41	1
auto[1]	auto[1]	valid[4]	auto[0]	56	1			T16	1		T27	1		T34	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal