Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51161

1

T8

219

T10

311

T16

472

auto[1]

17250

1

T1

10

T8

23

T10

56

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49998

1

T1

10

T8

168

T10

242

auto[1]

18413

1

T8

74

T10

125

T16

149

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35190	1			T1	10		T8	129		T10	197
others[1]	5808	1			T8	14		T10	23		T16	41
others[2]	5824	1			T8	26		T10	33		T16	40
others[3]	6670	1			T8	22		T10	32		T16	45
interest[1]	3753	1			T8	17		T10	19		T16	23
interest[4]	23195	1			T1	10		T8	95		T10	125
interest[64]	11166	1			T8	34		T10	63		T16	82

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16582	1			T8	79		T10	111		T16	169
auto[0]	auto[0]	others[1]	2812	1			T8	5		T10	7		T16	26
auto[0]	auto[0]	others[2]	2818	1			T8	16		T10	13		T16	22
auto[0]	auto[0]	others[3]	3235	1			T8	14		T10	13		T16	37
auto[0]	auto[0]	interest[1]	1822	1			T8	9		T10	10		T16	18
auto[0]	auto[0]	interest[4]	10887	1			T8	58		T10	74		T16	112
auto[0]	auto[0]	interest[64]	5479	1			T8	22		T10	32		T16	51
auto[0]	auto[1]	others[0]	9055	1			T1	10		T8	9		T10	27
auto[0]	auto[1]	others[1]	1410	1			T8	1		T10	3		T16	2
auto[0]	auto[1]	others[2]	1433	1			T8	4		T10	2		T16	2
auto[0]	auto[1]	others[3]	1645	1			T8	5		T10	6		T18	2
auto[0]	auto[1]	interest[1]	955	1			T10	4		T18	2		T19	13
auto[0]	auto[1]	interest[4]	6091	1			T1	10		T8	8		T10	16
auto[0]	auto[1]	interest[64]	2752	1			T8	4		T10	14		T16	3
auto[1]	auto[0]	others[0]	9553	1			T8	41		T10	59		T16	79
auto[1]	auto[0]	others[1]	1586	1			T8	8		T10	13		T16	13
auto[1]	auto[0]	others[2]	1573	1			T8	6		T10	18		T16	16
auto[1]	auto[0]	others[3]	1790	1			T8	3		T10	13		T16	8
auto[1]	auto[0]	interest[1]	976	1			T8	8		T10	5		T16	5
auto[1]	auto[0]	interest[4]	6217	1			T8	29		T10	35		T16	50
auto[1]	auto[0]	interest[64]	2935	1			T8	8		T10	17		T16	28

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal