Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	742	1			T62	15		T34	4		T63	7
all_values[1]	742	1			T62	15		T34	4		T63	7
all_values[2]	742	1			T62	15		T34	4		T63	7
all_values[3]	742	1			T62	15		T34	4		T63	7
all_values[4]	742	1			T62	15		T34	4		T63	7
all_values[5]	742	1			T62	15		T34	4		T63	7
all_values[6]	742	1			T62	15		T34	4		T63	7
all_values[7]	742	1			T62	15		T34	4		T63	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3208

1

T62

71

T34

19

T63

21

auto[1]

2728

1

T62

49

T34

13

T63

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410

1

T62

50

T34

23

T63

16

auto[1]

3526

1

T62

70

T34

9

T63

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3408

1

T62

72

T34

26

T63

31

auto[1]

2528

1

T62

48

T34

6

T63

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	140	1			T62	4		T34	3		T63	1
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T62	2		T64	1		T153	1
all_values[0]	auto[0]	auto[1]	auto[0]	109	1			T62	3		T34	1		T153	2
all_values[0]	auto[0]	auto[1]	auto[1]	70	1			T62	1		T63	1		T153	5
all_values[0]	auto[1]	auto[0]	auto[1]	188	1			T62	5		T63	3		T64	3
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T63	2		T153	6		T167	1
all_values[1]	auto[0]	auto[0]	auto[0]	141	1			T62	1		T34	1		T63	2
all_values[1]	auto[0]	auto[0]	auto[1]	67	1			T62	5		T63	1		T153	3
all_values[1]	auto[0]	auto[1]	auto[0]	151	1			T62	2		T34	2		T63	3
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T64	1		T153	5		T44	2
all_values[1]	auto[1]	auto[0]	auto[1]	165	1			T62	4		T64	1		T153	5
all_values[1]	auto[1]	auto[1]	auto[1]	144	1			T62	3		T34	1		T63	1
all_values[2]	auto[0]	auto[0]	auto[0]	176	1			T62	4		T34	3		T64	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T62	1		T63	1		T153	2
all_values[2]	auto[0]	auto[1]	auto[0]	104	1			T153	8		T175	2		T176	1
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T62	2		T63	2		T64	1
all_values[2]	auto[1]	auto[0]	auto[1]	190	1			T62	3		T34	1		T63	2
all_values[2]	auto[1]	auto[1]	auto[1]	136	1			T62	5		T63	2		T64	2
all_values[3]	auto[0]	auto[0]	auto[0]	149	1			T62	7		T34	1		T64	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T153	2		T166	1		T167	1
all_values[3]	auto[0]	auto[1]	auto[0]	132	1			T62	1		T34	1		T64	1
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T62	2		T34	1		T63	5
all_values[3]	auto[1]	auto[0]	auto[1]	164	1			T62	2		T34	1		T153	3
all_values[3]	auto[1]	auto[1]	auto[1]	160	1			T62	3		T63	2		T64	1
all_values[4]	auto[0]	auto[0]	auto[0]	172	1			T62	5		T64	1		T153	4
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T62	1		T34	1		T63	1
all_values[4]	auto[0]	auto[1]	auto[0]	116	1			T62	4		T63	1		T153	7
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T34	1		T166	2		T175	2
all_values[4]	auto[1]	auto[0]	auto[1]	171	1			T62	2		T34	1		T63	3
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T62	3		T34	1		T63	2
all_values[5]	auto[0]	auto[0]	auto[0]	234	1			T62	5		T34	1		T63	1
all_values[5]	auto[0]	auto[1]	auto[0]	211	1			T62	5		T34	3		T63	4
all_values[5]	auto[1]	auto[0]	auto[1]	163	1			T62	3		T64	1		T153	4
all_values[5]	auto[1]	auto[1]	auto[1]	134	1			T62	2		T63	2		T64	1
all_values[6]	auto[0]	auto[0]	auto[0]	161	1			T62	1		T34	1		T63	2
all_values[6]	auto[0]	auto[0]	auto[1]	57	1			T62	1		T153	2		T44	1
all_values[6]	auto[0]	auto[1]	auto[0]	137	1			T62	1		T34	2		T63	2
all_values[6]	auto[0]	auto[1]	auto[1]	76	1			T62	4		T63	1		T64	2
all_values[6]	auto[1]	auto[0]	auto[1]	170	1			T62	5		T34	1		T63	1
all_values[6]	auto[1]	auto[1]	auto[1]	141	1			T62	3		T63	1		T64	1
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T62	4		T34	4		T64	1
all_values[7]	auto[0]	auto[0]	auto[1]	83	1			T62	2		T63	2		T153	3
all_values[7]	auto[0]	auto[1]	auto[0]	111	1			T62	3		T64	1		T153	2
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T62	1		T63	1		T64	1
all_values[7]	auto[1]	auto[0]	auto[1]	157	1			T62	4		T63	1		T153	5
all_values[7]	auto[1]	auto[1]	auto[1]	153	1			T62	1		T63	3		T64	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal