Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3728306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3951200

1

T1

13

T2

876

T3

643

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4455404	1			T1	1		T2	3		T3	1
values[0x0]	1610255	1			T1	9		T2	418		T3	397
values[0x1]	1613847	1			T1	7		T2	457		T3	391

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2647193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5032313

1

T1

14

T2

877

T3

681

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30724	1			T1	3		T2	5		T4	40
valid_sources[0x01]	32860	1			T2	3		T4	58		T6	4
valid_sources[0x02]	29989	1			T2	1		T4	44		T7	3
valid_sources[0x03]	29542	1			T2	11		T4	37		T5	2
valid_sources[0x04]	27204	1			T2	4		T4	44		T8	4
valid_sources[0x05]	31261	1			T2	5		T4	47		T7	8
valid_sources[0x06]	33127	1			T2	5		T4	30		T6	1
valid_sources[0x07]	28038	1			T2	3		T4	46		T7	7
valid_sources[0x08]	31269	1			T2	3		T4	52		T7	2
valid_sources[0x09]	28082	1			T1	1		T2	7		T4	53
valid_sources[0x0a]	29160	1			T2	3		T4	53		T7	2
valid_sources[0x0b]	29354	1			T2	2		T4	52		T7	7
valid_sources[0x0c]	30255	1			T2	3		T4	62		T6	1
valid_sources[0x0d]	27711	1			T2	3		T4	32		T7	1
valid_sources[0x0e]	28526	1			T2	3		T4	35		T7	11
valid_sources[0x0f]	29357	1			T2	1		T4	62		T6	4
valid_sources[0x10]	28437	1			T2	5		T4	52		T7	1
valid_sources[0x11]	27656	1			T2	6		T4	55		T7	2
valid_sources[0x12]	27270	1			T2	6		T4	42		T6	5
valid_sources[0x13]	31497	1			T2	2		T4	36		T7	9
valid_sources[0x14]	31695	1			T2	3		T4	52		T7	4
valid_sources[0x15]	27642	1			T4	44		T6	1		T7	2
valid_sources[0x16]	30226	1			T2	2		T4	48		T6	6
valid_sources[0x17]	31161	1			T2	2		T4	40		T6	9
valid_sources[0x18]	28457	1			T2	5		T4	39		T7	7
valid_sources[0x19]	28669	1			T2	5		T4	49		T6	1
valid_sources[0x1a]	27430	1			T2	2		T4	45		T6	13
valid_sources[0x1b]	28420	1			T2	5		T4	43		T6	1
valid_sources[0x1c]	29580	1			T2	2		T4	50		T7	1
valid_sources[0x1d]	27447	1			T2	5		T4	44		T7	1
valid_sources[0x1e]	28847	1			T2	1		T4	36		T8	2
valid_sources[0x1f]	29273	1			T1	1		T2	3		T4	41
valid_sources[0x20]	31202	1			T2	3		T4	38		T5	7
valid_sources[0x21]	27039	1			T2	2		T4	50		T6	1
valid_sources[0x22]	32008	1			T2	3		T4	44		T5	6
valid_sources[0x23]	28320	1			T2	1		T4	38		T6	11
valid_sources[0x24]	30084	1			T2	1		T4	47		T7	5
valid_sources[0x25]	30903	1			T1	1		T2	5		T4	56
valid_sources[0x26]	29266	1			T2	5		T4	47		T7	6
valid_sources[0x27]	31721	1			T2	4		T4	49		T7	2
valid_sources[0x28]	29519	1			T2	2		T4	61		T7	1
valid_sources[0x29]	26666	1			T4	61		T7	2		T8	4
valid_sources[0x2a]	28773	1			T2	4		T4	45		T7	3
valid_sources[0x2b]	30310	1			T2	4		T4	51		T7	2
valid_sources[0x2c]	30798	1			T2	4		T4	45		T6	17
valid_sources[0x2d]	28713	1			T2	5		T4	47		T6	2
valid_sources[0x2e]	27872	1			T2	2		T4	45		T7	4
valid_sources[0x2f]	29569	1			T2	2		T4	42		T6	2
valid_sources[0x30]	30727	1			T4	34		T6	3		T7	3
valid_sources[0x31]	27182	1			T2	4		T4	33		T5	19
valid_sources[0x32]	32444	1			T2	2		T4	44		T6	4
valid_sources[0x33]	31767	1			T2	3		T4	58		T5	9
valid_sources[0x34]	28147	1			T2	4		T4	35		T6	7
valid_sources[0x35]	28980	1			T2	2		T4	49		T7	2
valid_sources[0x36]	28814	1			T2	4		T4	41		T8	2
valid_sources[0x37]	28743	1			T2	1		T4	44		T6	2
valid_sources[0x38]	29555	1			T2	5		T4	57		T6	10
valid_sources[0x39]	29119	1			T2	3		T4	48		T7	1
valid_sources[0x3a]	28345	1			T2	2		T4	57		T8	8
valid_sources[0x3b]	28953	1			T1	2		T2	4		T4	47
valid_sources[0x3c]	28431	1			T2	3		T4	55		T8	2
valid_sources[0x3d]	29448	1			T2	1		T4	29		T7	5
valid_sources[0x3e]	28377	1			T2	6		T4	50		T6	3
valid_sources[0x3f]	29841	1			T2	3		T4	40		T7	1
valid_sources[0x40]	27995	1			T2	6		T4	37		T5	22
valid_sources[0x41]	29784	1			T2	4		T4	41		T7	1
valid_sources[0x42]	28727	1			T2	4		T4	50		T6	15
valid_sources[0x43]	27687	1			T2	4		T4	43		T5	13
valid_sources[0x44]	32059	1			T2	3		T4	50		T7	4
valid_sources[0x45]	28967	1			T2	7		T4	42		T7	9
valid_sources[0x46]	27566	1			T2	3		T4	49		T6	1
valid_sources[0x47]	30358	1			T2	2		T4	35		T6	3
valid_sources[0x48]	28846	1			T2	5		T4	41		T6	9
valid_sources[0x49]	29183	1			T2	4		T4	44		T6	4
valid_sources[0x4a]	27364	1			T2	3		T4	43		T6	15
valid_sources[0x4b]	30841	1			T2	1		T4	54		T6	4
valid_sources[0x4c]	31841	1			T2	6		T4	52		T6	3
valid_sources[0x4d]	28959	1			T2	5		T4	58		T7	7
valid_sources[0x4e]	28472	1			T2	4		T4	43		T5	1
valid_sources[0x4f]	30507	1			T2	1		T4	56		T7	9
valid_sources[0x50]	28718	1			T2	8		T4	36		T7	3
valid_sources[0x51]	37328	1			T2	4		T4	48		T7	11
valid_sources[0x52]	29667	1			T2	6		T4	49		T6	5
valid_sources[0x53]	28591	1			T2	2		T4	46		T6	8
valid_sources[0x54]	27158	1			T2	3		T4	51		T7	5
valid_sources[0x55]	28525	1			T2	7		T4	46		T6	6
valid_sources[0x56]	30769	1			T2	3		T4	50		T6	3
valid_sources[0x57]	33777	1			T2	2		T4	45		T6	8
valid_sources[0x58]	30624	1			T2	1		T4	51		T6	4
valid_sources[0x59]	27852	1			T2	2		T4	48		T7	8
valid_sources[0x5a]	27416	1			T2	1		T4	39		T6	2
valid_sources[0x5b]	29972	1			T2	3		T4	39		T5	24
valid_sources[0x5c]	29308	1			T2	2		T4	51		T7	6
valid_sources[0x5d]	75340	1			T2	2		T4	46		T7	8
valid_sources[0x5e]	27839	1			T2	4		T4	47		T6	7
valid_sources[0x5f]	28078	1			T2	5		T4	34		T6	1
valid_sources[0x60]	31194	1			T2	5		T4	49		T8	4
valid_sources[0x61]	27677	1			T2	4		T4	44		T6	1
valid_sources[0x62]	30951	1			T2	1		T4	47		T7	6
valid_sources[0x63]	28553	1			T2	6		T4	46		T7	1
valid_sources[0x64]	30846	1			T2	4		T4	52		T6	1
valid_sources[0x65]	29003	1			T2	4		T4	50		T7	4
valid_sources[0x66]	30871	1			T2	6		T4	47		T7	3
valid_sources[0x67]	32590	1			T2	2		T4	48		T6	1
valid_sources[0x68]	33182	1			T2	4		T4	36		T8	3
valid_sources[0x69]	29649	1			T2	6		T4	50		T6	7
valid_sources[0x6a]	33879	1			T2	2		T4	43		T6	2
valid_sources[0x6b]	30083	1			T2	4		T4	46		T5	24
valid_sources[0x6c]	28148	1			T2	2		T4	50		T7	2
valid_sources[0x6d]	29714	1			T2	5		T4	42		T6	1
valid_sources[0x6e]	30382	1			T2	9		T4	56		T7	7
valid_sources[0x6f]	29335	1			T4	50		T7	4		T8	4
valid_sources[0x70]	29845	1			T2	3		T4	56		T7	2
valid_sources[0x71]	30295	1			T2	5		T4	72		T7	5
valid_sources[0x72]	29358	1			T2	5		T4	48		T7	3
valid_sources[0x73]	27915	1			T4	52		T7	2		T8	3
valid_sources[0x74]	31808	1			T2	2		T4	39		T6	4
valid_sources[0x75]	29410	1			T2	8		T4	42		T7	6
valid_sources[0x76]	33816	1			T2	3		T4	46		T6	2
valid_sources[0x77]	31102	1			T2	5		T4	51		T9	79
valid_sources[0x78]	29495	1			T2	6		T4	42		T5	9
valid_sources[0x79]	28650	1			T2	5		T4	53		T6	9
valid_sources[0x7a]	29005	1			T2	2		T4	44		T6	2
valid_sources[0x7b]	26996	1			T2	2		T4	40		T7	2
valid_sources[0x7c]	35098	1			T2	7		T4	60		T7	4
valid_sources[0x7d]	29291	1			T2	4		T4	47		T6	7
valid_sources[0x7e]	28069	1			T2	7		T4	37		T6	3
valid_sources[0x7f]	28242	1			T2	3		T4	51		T7	1
valid_sources[0x80]	31058	1			T2	2		T4	52		T6	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063487

1

T1

1

T2

2

T3

1

values[0x0]

all_enables

biggest_size

1454606

1

T1

7

T2

417

T3

321

values[0x1]

all_enables

biggest_size

1433107

1

T1

5

T2

457

T3

321