Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3745360

1

T1

4

T2

2

T3

146

full_word

3950191

1

T1

13

T2

876

T3

643

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7695131	1			T1	17		T2	878		T3	789
auto[TlIntgErrCmd]	124	1			T113	9		T116	9		T117	1
auto[TlIntgErrData]	164	1			T113	7		T116	7		T117	3
auto[TlIntgErrBoth]	132	1			T113	4		T116	4		T117	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4456438

1

T1

1

T2

3

T3

1

auto[1]

3239113

1

T1

16

T2

875

T3

788

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3392704	1			T2	1		T4	407		T5	250
auto[TlIntgErrNone]	partial	auto[1]	352274	1			T1	4		T2	1		T3	146
auto[TlIntgErrNone]	full_word	auto[0]	1063547	1			T1	1		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	2886606	1			T1	12		T2	874		T3	642
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T113	3		T116	3		T117	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T113	5		T116	5		T134	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T113	1		T292	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T116	1		T293	2		T292	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T113	2		T116	2		T117	1
auto[TlIntgErrData]	partial	auto[1]	78	1			T113	2		T116	3		T117	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T113	1		T116	1		T294	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T113	2		T116	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T113	3		T116	1		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T113	1		T116	2		T117	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T135	1		T291	1		T290	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T116	1		T134	1		T178	1