Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12
1	1	Covered	T4,T11,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T4,T11,T12
1	1	Covered	T4,T11,T12

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1150305864	2289	0	0
SrcPulseCheck_M	376732047	2289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150305864	2289	0	0
T4	327352	17	0	0
T5	3450	0	0	0
T6	6431	0	0	0
T7	5169	0	0	0
T8	8056	0	0	0
T9	441969	0	0	0
T10	103611	0	0	0
T11	143694	7	0	0
T12	45594	7	0	0
T13	46629	0	0	0
T14	17355	0	0	0
T15	210822	0	0	0
T16	5510	0	0	0
T17	19642	0	0	0
T18	0	9	0	0
T21	0	4	0	0
T28	0	13	0	0
T31	0	8	0	0
T32	0	25	0	0
T36	1460044	0	0	0
T37	258442	0	0	0
T47	0	6	0	0
T52	0	7	0	0
T53	0	7	0	0
T54	0	7	0	0
T55	0	2	0	0
T67	0	10	0	0
T70	2046	0	0	0
T74	22184	0	0	0
T136	0	6	0	0
T169	6046	0	0	0
T170	0	4	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	7	0	0
T174	0	7	0	0
T175	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	376732047	2289	0	0
T4	840123	17	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	64359	7	0	0
T12	26960	7	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T15	204656	0	0	0
T16	720	0	0	0
T17	48998	0	0	0
T18	1093432	9	0	0
T19	176572	0	0	0
T21	0	4	0	0
T28	0	13	0	0
T31	0	8	0	0
T32	0	25	0	0
T36	291136	0	0	0
T37	252292	0	0	0
T47	0	6	0	0
T52	0	7	0	0
T53	0	7	0	0
T54	0	7	0	0
T55	0	2	0	0
T67	0	10	0	0
T74	35710	0	0	0
T136	0	6	0	0
T170	0	4	0	0
T171	0	1	0	0
T172	0	2	0	0
T173	0	7	0	0
T174	0	7	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T54
1	0	Covered	T11,T12,T54
1	1	Covered	T11,T12,T54

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T54
1	0	Covered	T11,T12,T54
1	1	Covered	T11,T12,T54

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	383435288	201	0	0
SrcPulseCheck_M	125577349	201	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	201	0	0
T11	47898	2	0	0
T12	22797	2	0	0
T15	105411	0	0	0
T16	2755	0	0	0
T17	9821	0	0	0
T36	730022	0	0	0
T37	129221	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T70	1023	0	0	0
T74	11092	0	0	0
T136	0	3	0	0
T169	3023	0	0	0
T170	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	201	0	0
T11	21453	2	0	0
T12	13480	2	0	0
T15	102328	0	0	0
T16	360	0	0	0
T17	24499	0	0	0
T18	546716	0	0	0
T19	88286	0	0	0
T36	145568	0	0	0
T37	126146	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T74	17855	0	0	0
T136	0	3	0	0
T170	0	2	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T54
1	0	Covered	T11,T12,T54
1	1	Covered	T11,T12,T54

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T54
1	0	Covered	T11,T12,T54
1	1	Covered	T11,T12,T54

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	383435288	348	0	0
SrcPulseCheck_M	125577349	348	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	348	0	0
T11	47898	5	0	0
T12	22797	5	0	0
T15	105411	0	0	0
T16	2755	0	0	0
T17	9821	0	0	0
T36	730022	0	0	0
T37	129221	0	0	0
T52	0	5	0	0
T54	0	5	0	0
T70	1023	0	0	0
T74	11092	0	0	0
T136	0	3	0	0
T169	3023	0	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	5	0	0
T174	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	348	0	0
T11	21453	5	0	0
T12	13480	5	0	0
T15	102328	0	0	0
T16	360	0	0	0
T17	24499	0	0	0
T18	546716	0	0	0
T19	88286	0	0	0
T36	145568	0	0	0
T37	126146	0	0	0
T52	0	5	0	0
T54	0	5	0	0
T74	17855	0	0	0
T136	0	3	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	5	0	0
T174	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T28
1	0	Covered	T4,T18,T28
1	1	Covered	T4,T18,T28

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T28
1	0	Covered	T4,T18,T28
1	1	Covered	T4,T18,T28

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	383435288	1740	0	0
SrcPulseCheck_M	125577349	1740	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1740	0	0
T4	327352	17	0	0
T5	3450	0	0	0
T6	6431	0	0	0
T7	5169	0	0	0
T8	8056	0	0	0
T9	441969	0	0	0
T10	103611	0	0	0
T11	47898	0	0	0
T13	46629	0	0	0
T14	17355	0	0	0
T18	0	9	0	0
T21	0	4	0	0
T28	0	13	0	0
T31	0	8	0	0
T32	0	25	0	0
T47	0	6	0	0
T53	0	7	0	0
T55	0	2	0	0
T67	0	10	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	1740	0	0
T4	840123	17	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	9	0	0
T21	0	4	0	0
T28	0	13	0	0
T31	0	8	0	0
T32	0	25	0	0
T47	0	6	0	0
T53	0	7	0	0
T55	0	2	0	0
T67	0	10	0	0