Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385468596	2402919	0	0
DepthKnown_A	385468596	385335796	0	0
RvalidKnown_A	385468596	385335796	0	0
WreadyKnown_A	385468596	385335796	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	2402919	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	16632	0	0
T5	3450	0	0	0
T6	6431	0	0	0
T7	5169	1663	0	0
T8	8056	0	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	46629	1663	0	0
T14	0	832	0	0
T15	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385468596	2695318	0	0
DepthKnown_A	385468596	385335796	0	0
RvalidKnown_A	385468596	385335796	0	0
WreadyKnown_A	385468596	385335796	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	2695318	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	9984	0	0
T5	3450	0	0	0
T6	6431	0	0	0
T7	5169	832	0	0
T8	8056	0	0	0
T9	441969	832	0	0
T10	103611	3776	0	0
T11	0	832	0	0
T12	0	2537	0	0
T13	46629	832	0	0
T14	0	832	0	0
T15	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385468596	161304	0	0
DepthKnown_A	385468596	385335796	0	0
RvalidKnown_A	385468596	385335796	0	0
WreadyKnown_A	385468596	385335796	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	161304	0	0
T4	327352	513	0	0
T5	3450	18	0	0
T6	6431	33	0	0
T7	5169	0	0	0
T8	8056	3	0	0
T9	441969	0	0	0
T10	103611	0	0	0
T11	47898	0	0	0
T13	46629	0	0	0
T14	17355	0	0	0
T18	0	649	0	0
T20	0	382	0	0
T21	0	278	0	0
T25	0	100	0	0
T28	0	420	0	0
T30	0	641	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385468596	389825	0	0
DepthKnown_A	385468596	385335796	0	0
RvalidKnown_A	385468596	385335796	0	0
WreadyKnown_A	385468596	385335796	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	389825	0	0
T4	327352	513	0	0
T5	3450	18	0	0
T6	6431	124	0	0
T7	5169	0	0	0
T8	8056	3	0	0
T9	441969	0	0	0
T10	103611	0	0	0
T11	47898	0	0	0
T13	46629	0	0	0
T14	17355	0	0	0
T18	0	1779	0	0
T20	0	382	0	0
T21	0	278	0	0
T25	0	100	0	0
T28	0	420	0	0
T30	0	641	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385468596	6371230	0	0
DepthKnown_A	385468596	385335796	0	0
RvalidKnown_A	385468596	385335796	0	0
WreadyKnown_A	385468596	385335796	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	6371230	0	0
T1	4062	17	0	0
T2	2704	46	0	0
T3	784791	789	0	0
T4	327352	1333	0	0
T5	3450	289	0	0
T6	6431	496	0	0
T7	5169	75	0	0
T8	8056	842	0	0
T9	441969	19096	0	0
T10	103611	3362	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	385468596	13806295	0	0
DepthKnown_A	385468596	385335796	0	0
RvalidKnown_A	385468596	385335796	0	0
WreadyKnown_A	385468596	385335796	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	13806295	0	0
T1	4062	78	0	0
T2	2704	46	0	0
T3	784791	789	0	0
T4	327352	1331	0	0
T5	3450	289	0	0
T6	6431	1491	0	0
T7	5169	212	0	0
T8	8056	842	0	0
T9	441969	19096	0	0
T10	103611	14337	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385468596	385335796	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0