Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T28

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T28
1	0	Covered	T4,T18,T28

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T4,T18,T28

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	634589986	507668996	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	634589986	3044588	0	0
GntImpliesValid_A	634589986	3044588	0	0
GrantKnown_A	634589986	507668996	0	0
IdxKnown_A	634589986	507668996	0	0
IndexIsCorrect_A	634589986	3044588	0	0
LockArbDecision_A	634589986	0	0	0
NoReadyValidNoGrant_A	634589986	0	0	0
ReadyAndValidImplyGrant_A	634589986	3044588	0	0
ReqAndReadyImplyGrant_A	634589986	3044588	0	0
ReqImpliesValid_A	634589986	3044588	0	0
ReqStaysHighUntilGranted0_M	634589986	0	0	0
RoundRobin_A	634589986	4	0	926
ValidKnown_A	634589986	507668996	0	0
gen_data_port_assertion.DataFlow_A	634589986	3044588	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	507668996	0	0
T1	4422	4355	0	0
T2	2822	2675	0	0
T3	983581	880423	0	0
T4	2007598	1162305	0	0
T5	5610	4445	0	0
T6	9747	7830	0	0
T7	6441	5755	0	0
T8	11000	9456	0	0
T9	587637	513954	0	0
T10	165597	134231	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	507668996	0	0
T1	4422	4355	0	0
T2	2822	2675	0	0
T3	983581	880423	0	0
T4	2007598	1162305	0	0
T5	5610	4445	0	0
T6	9747	7830	0	0
T7	6441	5755	0	0
T8	11000	9456	0	0
T9	587637	513954	0	0
T10	165597	134231	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	507668996	0	0
T1	4422	4355	0	0
T2	2822	2675	0	0
T3	983581	880423	0	0
T4	2007598	1162305	0	0
T5	5610	4445	0	0
T6	9747	7830	0	0
T7	6441	5755	0	0
T8	11000	9456	0	0
T9	587637	513954	0	0
T10	165597	134231	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	4	0	926
T23	296870	2	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	1546	0	0	1
T59	20519	0	0	1
T60	1457	0	0	1
T61	1720	0	0	1
T62	459784	0	0	1
T63	8048	0	0	1
T64	576479	0	0	1
T65	1816	0	0	1
T66	637807	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	507668996	0	0
T1	4422	4355	0	0
T2	2822	2675	0	0
T3	983581	880423	0	0
T4	2007598	1162305	0	0
T5	5610	4445	0	0
T6	9747	7830	0	0
T7	6441	5755	0	0
T8	11000	9456	0	0
T9	587637	513954	0	0
T10	165597	134231	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	634589986	3044588	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	1167475	17435	0	0
T5	5610	102	0	0
T6	9747	175	0	0
T7	6441	832	0	0
T8	11000	82	0	0
T9	587637	832	0	0
T10	165597	832	0	0
T11	42906	0	0	0
T12	13480	0	0	0
T13	68549	832	0	0
T14	10464	832	0	0
T18	0	4508	0	0
T20	0	2391	0	0
T21	0	1735	0	0
T22	0	2	0	0
T28	0	1714	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T55	0	1823	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T8
1	0	Covered	T5,T6,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Unreachable
1	1	Covered	T5,T6,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T6,T8
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125577349	28299724	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	125577349	650497	0	0
GntImpliesValid_A	125577349	650497	0	0
GrantKnown_A	125577349	28299724	0	0
IdxKnown_A	125577349	28299724	0	0
IndexIsCorrect_A	125577349	650497	0	0
LockArbDecision_A	125577349	0	0	0
NoReadyValidNoGrant_A	125577349	0	0	0
ReadyAndValidImplyGrant_A	125577349	650497	0	0
ReqAndReadyImplyGrant_A	125577349	650497	0	0
ReqImpliesValid_A	125577349	650497	0	0
ReqStaysHighUntilGranted0_M	125577349	0	0	0
RoundRobin_A	125577349	0	0	0
ValidKnown_A	125577349	28299724	0	0
gen_data_port_assertion.DataFlow_A	125577349	650497	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	28299724	0	0
T1	360	360	0	0
T2	59	0	0	0
T3	99395	95728	0	0
T4	840123	0	0	0
T5	1080	1080	0	0
T6	1658	1488	0	0
T7	636	0	0	0
T8	1472	1472	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	28299724	0	0
T1	360	360	0	0
T2	59	0	0	0
T3	99395	95728	0	0
T4	840123	0	0	0
T5	1080	1080	0	0
T6	1658	1488	0	0
T7	636	0	0	0
T8	1472	1472	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	28299724	0	0
T1	360	360	0	0
T2	59	0	0	0
T3	99395	95728	0	0
T4	840123	0	0	0
T5	1080	1080	0	0
T6	1658	1488	0	0
T7	636	0	0	0
T8	1472	1472	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	28299724	0	0
T1	360	360	0	0
T2	59	0	0	0
T3	99395	95728	0	0
T4	840123	0	0	0
T5	1080	1080	0	0
T6	1658	1488	0	0
T7	636	0	0	0
T8	1472	1472	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T16	0	360	0	0
T18	0	303344	0	0
T19	0	82152	0	0
T20	0	55328	0	0
T22	0	88	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	650497	0	0
T5	1080	79	0	0
T6	1658	138	0	0
T7	636	0	0	0
T8	1472	45	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T12	13480	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	3462	0	0
T20	0	2391	0	0
T21	0	699	0	0
T22	0	2	0	0
T29	0	3627	0	0
T30	0	3786	0	0
T55	0	1691	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T18,T28

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T18,T28
1	0	Covered	T4,T18,T28

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Unreachable
1	1	Covered	T4,T18,T28

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T18,T28
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T18,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	125577349	96020159	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	125577349	459790	0	0
GntImpliesValid_A	125577349	459790	0	0
GrantKnown_A	125577349	96020159	0	0
IdxKnown_A	125577349	96020159	0	0
IndexIsCorrect_A	125577349	459790	0	0
LockArbDecision_A	125577349	0	0	0
NoReadyValidNoGrant_A	125577349	0	0	0
ReadyAndValidImplyGrant_A	125577349	459790	0	0
ReqAndReadyImplyGrant_A	125577349	459790	0	0
ReqImpliesValid_A	125577349	459790	0	0
ReqStaysHighUntilGranted0_M	125577349	0	0	0
RoundRobin_A	125577349	0	0	0
ValidKnown_A	125577349	96020159	0	0
gen_data_port_assertion.DataFlow_A	125577349	459790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	96020159	0	0
T2	59	59	0	0
T3	99395	0	0	0
T4	840123	835048	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	636	0	0
T8	1472	0	0	0
T9	72834	72064	0	0
T10	30993	30704	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	96020159	0	0
T2	59	59	0	0
T3	99395	0	0	0
T4	840123	835048	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	636	0	0
T8	1472	0	0	0
T9	72834	72064	0	0
T10	30993	30704	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	96020159	0	0
T2	59	59	0	0
T3	99395	0	0	0
T4	840123	835048	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	636	0	0
T8	1472	0	0	0
T9	72834	72064	0	0
T10	30993	30704	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	96020159	0	0
T2	59	59	0	0
T3	99395	0	0	0
T4	840123	835048	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	636	0	0
T8	1472	0	0	0
T9	72834	72064	0	0
T10	30993	30704	0	0
T11	0	21236	0	0
T12	0	13480	0	0
T13	10960	10960	0	0
T14	0	5232	0	0
T15	0	102328	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125577349	459790	0	0
T4	840123	6908	0	0
T5	1080	0	0	0
T6	1658	0	0	0
T7	636	0	0	0
T8	1472	0	0	0
T9	72834	0	0	0
T10	30993	0	0	0
T11	21453	0	0	0
T13	10960	0	0	0
T14	5232	0	0	0
T18	0	1046	0	0
T21	0	1036	0	0
T28	0	1714	0	0
T31	0	4958	0	0
T32	0	7393	0	0
T47	0	650	0	0
T53	0	2280	0	0
T55	0	132	0	0
T67	0	789	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	383435288	383349113	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	383435288	1934301	0	0
GntImpliesValid_A	383435288	1934301	0	0
GrantKnown_A	383435288	383349113	0	0
IdxKnown_A	383435288	383349113	0	0
IndexIsCorrect_A	383435288	1934301	0	0
LockArbDecision_A	383435288	0	0	0
NoReadyValidNoGrant_A	383435288	0	0	0
ReadyAndValidImplyGrant_A	383435288	1934301	0	0
ReqAndReadyImplyGrant_A	383435288	1934301	0	0
ReqImpliesValid_A	383435288	1934301	0	0
ReqStaysHighUntilGranted0_M	383435288	0	0	0
RoundRobin_A	383435288	4	0	926
ValidKnown_A	383435288	383349113	0	0
gen_data_port_assertion.DataFlow_A	383435288	1934301	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	383349113	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	383349113	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	383349113	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	4	0	926
T23	296870	2	0	1
T56	0	1	0	0
T57	0	1	0	0
T58	1546	0	0	1
T59	20519	0	0	1
T60	1457	0	0	1
T61	1720	0	0	1
T62	459784	0	0	1
T63	8048	0	0	1
T64	576479	0	0	1
T65	1816	0	0	1
T66	637807	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	383349113	0	0
T1	4062	3995	0	0
T2	2704	2616	0	0
T3	784791	784695	0	0
T4	327352	327257	0	0
T5	3450	3365	0	0
T6	6431	6342	0	0
T7	5169	5119	0	0
T8	8056	7984	0	0
T9	441969	441890	0	0
T10	103611	103527	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383435288	1934301	0	0
T2	2704	832	0	0
T3	784791	0	0	0
T4	327352	10527	0	0
T5	3450	23	0	0
T6	6431	37	0	0
T7	5169	832	0	0
T8	8056	37	0	0
T9	441969	832	0	0
T10	103611	832	0	0
T13	46629	832	0	0
T14	0	832	0	0