Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3321 |
0 |
0 |
T111 |
4952 |
153 |
0 |
0 |
T112 |
2395 |
4 |
0 |
0 |
T113 |
19599 |
1 |
0 |
0 |
T114 |
14812 |
200 |
0 |
0 |
T115 |
12304 |
4 |
0 |
0 |
T116 |
71843 |
2 |
0 |
0 |
T117 |
27196 |
2 |
0 |
0 |
T118 |
13856 |
150 |
0 |
0 |
T127 |
3872 |
5 |
0 |
0 |
T133 |
13900 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1583 |
0 |
0 |
T93 |
3229 |
1 |
0 |
0 |
T115 |
12304 |
20 |
0 |
0 |
T116 |
71843 |
92 |
0 |
0 |
T132 |
35614 |
38 |
0 |
0 |
T133 |
13900 |
20 |
0 |
0 |
T137 |
9795 |
9 |
0 |
0 |
T138 |
3560 |
5 |
0 |
0 |
T167 |
13230 |
54 |
0 |
0 |
T176 |
12304 |
12 |
0 |
0 |
T177 |
12387 |
17 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1863 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
16 |
0 |
0 |
T116 |
71843 |
80 |
0 |
0 |
T132 |
35614 |
44 |
0 |
0 |
T133 |
13900 |
17 |
0 |
0 |
T137 |
9795 |
15 |
0 |
0 |
T138 |
3560 |
9 |
0 |
0 |
T167 |
13230 |
33 |
0 |
0 |
T176 |
12304 |
16 |
0 |
0 |
T177 |
12387 |
50 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1754 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
21 |
0 |
0 |
T116 |
71843 |
151 |
0 |
0 |
T132 |
35614 |
65 |
0 |
0 |
T133 |
13900 |
22 |
0 |
0 |
T137 |
9795 |
18 |
0 |
0 |
T138 |
3560 |
17 |
0 |
0 |
T167 |
13230 |
40 |
0 |
0 |
T176 |
12304 |
4 |
0 |
0 |
T177 |
12387 |
17 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
6634 |
0 |
0 |
T93 |
3229 |
3 |
0 |
0 |
T115 |
12304 |
126 |
0 |
0 |
T116 |
71843 |
1017 |
0 |
0 |
T132 |
35614 |
952 |
0 |
0 |
T133 |
13900 |
72 |
0 |
0 |
T137 |
9795 |
91 |
0 |
0 |
T138 |
3560 |
69 |
0 |
0 |
T167 |
13230 |
66 |
0 |
0 |
T176 |
12304 |
18 |
0 |
0 |
T177 |
12387 |
19 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
7560 |
0 |
0 |
T93 |
3229 |
9 |
0 |
0 |
T115 |
12304 |
141 |
0 |
0 |
T116 |
71843 |
1656 |
0 |
0 |
T132 |
35614 |
632 |
0 |
0 |
T133 |
13900 |
213 |
0 |
0 |
T137 |
9795 |
210 |
0 |
0 |
T138 |
3560 |
2 |
0 |
0 |
T167 |
13230 |
39 |
0 |
0 |
T176 |
12304 |
29 |
0 |
0 |
T177 |
12387 |
4 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
6017 |
0 |
0 |
T93 |
3229 |
13 |
0 |
0 |
T115 |
12304 |
30 |
0 |
0 |
T116 |
71843 |
992 |
0 |
0 |
T132 |
35614 |
429 |
0 |
0 |
T133 |
13900 |
68 |
0 |
0 |
T137 |
9795 |
167 |
0 |
0 |
T138 |
3560 |
4 |
0 |
0 |
T167 |
13230 |
42 |
0 |
0 |
T176 |
12304 |
5 |
0 |
0 |
T177 |
12387 |
23 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
7475 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T115 |
12304 |
20 |
0 |
0 |
T116 |
71843 |
1854 |
0 |
0 |
T132 |
35614 |
905 |
0 |
0 |
T133 |
13900 |
77 |
0 |
0 |
T137 |
9795 |
118 |
0 |
0 |
T167 |
13230 |
40 |
0 |
0 |
T176 |
12304 |
32 |
0 |
0 |
T177 |
12387 |
29 |
0 |
0 |
T178 |
68966 |
1499 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
6289 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T115 |
12304 |
23 |
0 |
0 |
T116 |
71843 |
730 |
0 |
0 |
T132 |
35614 |
688 |
0 |
0 |
T133 |
13900 |
112 |
0 |
0 |
T137 |
9795 |
92 |
0 |
0 |
T167 |
13230 |
10 |
0 |
0 |
T176 |
12304 |
40 |
0 |
0 |
T177 |
12387 |
60 |
0 |
0 |
T178 |
68966 |
1680 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
5792 |
0 |
0 |
T93 |
3229 |
7 |
0 |
0 |
T115 |
12304 |
166 |
0 |
0 |
T116 |
71843 |
960 |
0 |
0 |
T132 |
35614 |
736 |
0 |
0 |
T133 |
13900 |
23 |
0 |
0 |
T137 |
9795 |
2 |
0 |
0 |
T138 |
3560 |
84 |
0 |
0 |
T167 |
13230 |
77 |
0 |
0 |
T176 |
12304 |
18 |
0 |
0 |
T177 |
12387 |
15 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
6369 |
0 |
0 |
T93 |
3229 |
8 |
0 |
0 |
T115 |
12304 |
203 |
0 |
0 |
T116 |
71843 |
1168 |
0 |
0 |
T132 |
35614 |
852 |
0 |
0 |
T133 |
13900 |
123 |
0 |
0 |
T137 |
9795 |
89 |
0 |
0 |
T138 |
3560 |
63 |
0 |
0 |
T167 |
13230 |
20 |
0 |
0 |
T176 |
12304 |
25 |
0 |
0 |
T177 |
12387 |
20 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
6410 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
34 |
0 |
0 |
T116 |
71843 |
1267 |
0 |
0 |
T132 |
35614 |
771 |
0 |
0 |
T133 |
13900 |
111 |
0 |
0 |
T137 |
9795 |
46 |
0 |
0 |
T138 |
3560 |
2 |
0 |
0 |
T167 |
13230 |
33 |
0 |
0 |
T176 |
12304 |
19 |
0 |
0 |
T177 |
12387 |
71 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3887 |
0 |
0 |
T93 |
3229 |
13 |
0 |
0 |
T115 |
12304 |
152 |
0 |
0 |
T116 |
71843 |
690 |
0 |
0 |
T132 |
35614 |
200 |
0 |
0 |
T133 |
13900 |
87 |
0 |
0 |
T137 |
9795 |
84 |
0 |
0 |
T138 |
3560 |
38 |
0 |
0 |
T167 |
13230 |
37 |
0 |
0 |
T176 |
12304 |
50 |
0 |
0 |
T177 |
12387 |
19 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3538 |
0 |
0 |
T93 |
3229 |
8 |
0 |
0 |
T114 |
14812 |
2 |
0 |
0 |
T115 |
12304 |
89 |
0 |
0 |
T116 |
71843 |
407 |
0 |
0 |
T132 |
35614 |
373 |
0 |
0 |
T133 |
13900 |
56 |
0 |
0 |
T137 |
9795 |
12 |
0 |
0 |
T167 |
13230 |
37 |
0 |
0 |
T176 |
12304 |
11 |
0 |
0 |
T177 |
12387 |
30 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3080 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
23 |
0 |
0 |
T116 |
71843 |
341 |
0 |
0 |
T132 |
35614 |
322 |
0 |
0 |
T133 |
13900 |
64 |
0 |
0 |
T137 |
9795 |
61 |
0 |
0 |
T138 |
3560 |
4 |
0 |
0 |
T167 |
13230 |
13 |
0 |
0 |
T176 |
12304 |
17 |
0 |
0 |
T177 |
12387 |
39 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3619 |
0 |
0 |
T93 |
3229 |
8 |
0 |
0 |
T115 |
12304 |
92 |
0 |
0 |
T116 |
71843 |
599 |
0 |
0 |
T132 |
35614 |
340 |
0 |
0 |
T133 |
13900 |
9 |
0 |
0 |
T137 |
9795 |
37 |
0 |
0 |
T167 |
13230 |
24 |
0 |
0 |
T176 |
12304 |
32 |
0 |
0 |
T177 |
12387 |
30 |
0 |
0 |
T178 |
68966 |
557 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3917 |
0 |
0 |
T93 |
3229 |
6 |
0 |
0 |
T115 |
12304 |
140 |
0 |
0 |
T116 |
71843 |
728 |
0 |
0 |
T132 |
35614 |
197 |
0 |
0 |
T133 |
13900 |
18 |
0 |
0 |
T137 |
9795 |
49 |
0 |
0 |
T138 |
3560 |
33 |
0 |
0 |
T167 |
13230 |
58 |
0 |
0 |
T176 |
12304 |
22 |
0 |
0 |
T177 |
12387 |
19 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3619 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T114 |
14812 |
1 |
0 |
0 |
T115 |
12304 |
12 |
0 |
0 |
T116 |
71843 |
803 |
0 |
0 |
T132 |
35614 |
189 |
0 |
0 |
T133 |
13900 |
17 |
0 |
0 |
T137 |
9795 |
31 |
0 |
0 |
T167 |
13230 |
41 |
0 |
0 |
T176 |
12304 |
14 |
0 |
0 |
T177 |
12387 |
44 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3681 |
0 |
0 |
T93 |
3229 |
8 |
0 |
0 |
T115 |
12304 |
20 |
0 |
0 |
T116 |
71843 |
642 |
0 |
0 |
T132 |
35614 |
161 |
0 |
0 |
T133 |
13900 |
36 |
0 |
0 |
T137 |
9795 |
72 |
0 |
0 |
T138 |
3560 |
4 |
0 |
0 |
T167 |
13230 |
58 |
0 |
0 |
T176 |
12304 |
10 |
0 |
0 |
T177 |
12387 |
48 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3725 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
113 |
0 |
0 |
T116 |
71843 |
464 |
0 |
0 |
T132 |
35614 |
360 |
0 |
0 |
T133 |
13900 |
42 |
0 |
0 |
T137 |
9795 |
16 |
0 |
0 |
T167 |
13230 |
47 |
0 |
0 |
T176 |
12304 |
10 |
0 |
0 |
T177 |
12387 |
34 |
0 |
0 |
T178 |
68966 |
583 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3424 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
137 |
0 |
0 |
T116 |
71843 |
438 |
0 |
0 |
T132 |
35614 |
218 |
0 |
0 |
T133 |
13900 |
47 |
0 |
0 |
T137 |
9795 |
50 |
0 |
0 |
T167 |
13230 |
45 |
0 |
0 |
T176 |
12304 |
13 |
0 |
0 |
T177 |
12387 |
49 |
0 |
0 |
T178 |
68966 |
534 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3666 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T115 |
12304 |
117 |
0 |
0 |
T116 |
71843 |
573 |
0 |
0 |
T132 |
35614 |
283 |
0 |
0 |
T133 |
13900 |
39 |
0 |
0 |
T137 |
9795 |
63 |
0 |
0 |
T167 |
13230 |
24 |
0 |
0 |
T176 |
12304 |
18 |
0 |
0 |
T177 |
12387 |
26 |
0 |
0 |
T178 |
68966 |
525 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3338 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
91 |
0 |
0 |
T116 |
71843 |
550 |
0 |
0 |
T132 |
35614 |
192 |
0 |
0 |
T133 |
13900 |
56 |
0 |
0 |
T137 |
9795 |
5 |
0 |
0 |
T138 |
3560 |
2 |
0 |
0 |
T167 |
13230 |
54 |
0 |
0 |
T176 |
12304 |
43 |
0 |
0 |
T177 |
12387 |
29 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3646 |
0 |
0 |
T93 |
3229 |
9 |
0 |
0 |
T115 |
12304 |
24 |
0 |
0 |
T116 |
71843 |
585 |
0 |
0 |
T132 |
35614 |
360 |
0 |
0 |
T133 |
13900 |
5 |
0 |
0 |
T137 |
9795 |
68 |
0 |
0 |
T138 |
3560 |
39 |
0 |
0 |
T167 |
13230 |
82 |
0 |
0 |
T176 |
12304 |
27 |
0 |
0 |
T177 |
12387 |
34 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3790 |
0 |
0 |
T93 |
3229 |
8 |
0 |
0 |
T115 |
12304 |
29 |
0 |
0 |
T116 |
71843 |
521 |
0 |
0 |
T132 |
35614 |
201 |
0 |
0 |
T133 |
13900 |
50 |
0 |
0 |
T137 |
9795 |
34 |
0 |
0 |
T138 |
3560 |
28 |
0 |
0 |
T167 |
13230 |
60 |
0 |
0 |
T176 |
12304 |
32 |
0 |
0 |
T177 |
12387 |
26 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3880 |
0 |
0 |
T93 |
3229 |
2 |
0 |
0 |
T115 |
12304 |
130 |
0 |
0 |
T116 |
71843 |
639 |
0 |
0 |
T132 |
35614 |
245 |
0 |
0 |
T133 |
13900 |
80 |
0 |
0 |
T137 |
9795 |
66 |
0 |
0 |
T138 |
3560 |
17 |
0 |
0 |
T167 |
13230 |
28 |
0 |
0 |
T176 |
12304 |
26 |
0 |
0 |
T177 |
12387 |
30 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3283 |
0 |
0 |
T93 |
3229 |
8 |
0 |
0 |
T115 |
12304 |
51 |
0 |
0 |
T116 |
71843 |
323 |
0 |
0 |
T132 |
35614 |
94 |
0 |
0 |
T133 |
13900 |
89 |
0 |
0 |
T137 |
9795 |
47 |
0 |
0 |
T138 |
3560 |
26 |
0 |
0 |
T167 |
13230 |
87 |
0 |
0 |
T176 |
12304 |
16 |
0 |
0 |
T177 |
12387 |
11 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3170 |
0 |
0 |
T93 |
3229 |
9 |
0 |
0 |
T115 |
12304 |
25 |
0 |
0 |
T116 |
71843 |
516 |
0 |
0 |
T132 |
35614 |
269 |
0 |
0 |
T133 |
13900 |
18 |
0 |
0 |
T137 |
9795 |
55 |
0 |
0 |
T167 |
13230 |
25 |
0 |
0 |
T176 |
12304 |
42 |
0 |
0 |
T177 |
12387 |
11 |
0 |
0 |
T178 |
68966 |
443 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3076 |
0 |
0 |
T93 |
3229 |
9 |
0 |
0 |
T115 |
12304 |
73 |
0 |
0 |
T116 |
71843 |
487 |
0 |
0 |
T132 |
35614 |
185 |
0 |
0 |
T133 |
13900 |
12 |
0 |
0 |
T137 |
9795 |
57 |
0 |
0 |
T138 |
3560 |
29 |
0 |
0 |
T167 |
13230 |
23 |
0 |
0 |
T176 |
12304 |
36 |
0 |
0 |
T177 |
12387 |
43 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3729 |
0 |
0 |
T93 |
3229 |
9 |
0 |
0 |
T115 |
12304 |
108 |
0 |
0 |
T116 |
71843 |
528 |
0 |
0 |
T132 |
35614 |
496 |
0 |
0 |
T133 |
13900 |
25 |
0 |
0 |
T137 |
9795 |
76 |
0 |
0 |
T138 |
3560 |
49 |
0 |
0 |
T167 |
13230 |
37 |
0 |
0 |
T176 |
12304 |
67 |
0 |
0 |
T177 |
12387 |
11 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3747 |
0 |
0 |
T93 |
3229 |
6 |
0 |
0 |
T115 |
12304 |
78 |
0 |
0 |
T116 |
71843 |
703 |
0 |
0 |
T132 |
35614 |
237 |
0 |
0 |
T133 |
13900 |
35 |
0 |
0 |
T137 |
9795 |
37 |
0 |
0 |
T138 |
3560 |
26 |
0 |
0 |
T167 |
13230 |
20 |
0 |
0 |
T176 |
12304 |
21 |
0 |
0 |
T177 |
12387 |
30 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3986 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T115 |
12304 |
115 |
0 |
0 |
T116 |
71843 |
707 |
0 |
0 |
T132 |
35614 |
368 |
0 |
0 |
T133 |
13900 |
3 |
0 |
0 |
T137 |
9795 |
91 |
0 |
0 |
T167 |
13230 |
54 |
0 |
0 |
T176 |
12304 |
23 |
0 |
0 |
T177 |
12387 |
25 |
0 |
0 |
T178 |
68966 |
781 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3708 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T115 |
12304 |
20 |
0 |
0 |
T116 |
71843 |
564 |
0 |
0 |
T132 |
35614 |
308 |
0 |
0 |
T133 |
13900 |
74 |
0 |
0 |
T137 |
9795 |
2 |
0 |
0 |
T138 |
3560 |
25 |
0 |
0 |
T167 |
13230 |
22 |
0 |
0 |
T176 |
12304 |
25 |
0 |
0 |
T177 |
12387 |
31 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3187 |
0 |
0 |
T93 |
3229 |
1 |
0 |
0 |
T115 |
12304 |
109 |
0 |
0 |
T116 |
71843 |
406 |
0 |
0 |
T118 |
13856 |
9 |
0 |
0 |
T132 |
35614 |
183 |
0 |
0 |
T133 |
13900 |
63 |
0 |
0 |
T137 |
9795 |
97 |
0 |
0 |
T167 |
13230 |
25 |
0 |
0 |
T176 |
12304 |
16 |
0 |
0 |
T177 |
12387 |
8 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3762 |
0 |
0 |
T93 |
3229 |
7 |
0 |
0 |
T115 |
12304 |
183 |
0 |
0 |
T116 |
71843 |
676 |
0 |
0 |
T118 |
13856 |
2 |
0 |
0 |
T132 |
35614 |
128 |
0 |
0 |
T133 |
13900 |
18 |
0 |
0 |
T137 |
9795 |
35 |
0 |
0 |
T138 |
3560 |
37 |
0 |
0 |
T167 |
13230 |
63 |
0 |
0 |
T176 |
12304 |
42 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3249 |
0 |
0 |
T93 |
3229 |
2 |
0 |
0 |
T115 |
12304 |
73 |
0 |
0 |
T116 |
71843 |
391 |
0 |
0 |
T132 |
35614 |
120 |
0 |
0 |
T133 |
13900 |
24 |
0 |
0 |
T137 |
9795 |
84 |
0 |
0 |
T138 |
3560 |
30 |
0 |
0 |
T167 |
13230 |
68 |
0 |
0 |
T176 |
12304 |
22 |
0 |
0 |
T177 |
12387 |
57 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1760 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T115 |
12304 |
24 |
0 |
0 |
T116 |
71843 |
79 |
0 |
0 |
T132 |
35614 |
67 |
0 |
0 |
T133 |
13900 |
12 |
0 |
0 |
T137 |
9795 |
14 |
0 |
0 |
T167 |
13230 |
31 |
0 |
0 |
T176 |
12304 |
12 |
0 |
0 |
T177 |
12387 |
58 |
0 |
0 |
T178 |
68966 |
109 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1720 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
36 |
0 |
0 |
T116 |
71843 |
90 |
0 |
0 |
T132 |
35614 |
63 |
0 |
0 |
T133 |
13900 |
33 |
0 |
0 |
T137 |
9795 |
11 |
0 |
0 |
T167 |
13230 |
28 |
0 |
0 |
T176 |
12304 |
18 |
0 |
0 |
T177 |
12387 |
19 |
0 |
0 |
T178 |
68966 |
129 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1800 |
0 |
0 |
T93 |
3229 |
12 |
0 |
0 |
T115 |
12304 |
19 |
0 |
0 |
T116 |
71843 |
128 |
0 |
0 |
T132 |
35614 |
53 |
0 |
0 |
T133 |
13900 |
11 |
0 |
0 |
T137 |
9795 |
13 |
0 |
0 |
T167 |
13230 |
46 |
0 |
0 |
T176 |
12304 |
25 |
0 |
0 |
T177 |
12387 |
31 |
0 |
0 |
T178 |
68966 |
119 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1759 |
0 |
0 |
T93 |
3229 |
6 |
0 |
0 |
T115 |
12304 |
24 |
0 |
0 |
T116 |
71843 |
105 |
0 |
0 |
T132 |
35614 |
59 |
0 |
0 |
T133 |
13900 |
6 |
0 |
0 |
T137 |
9795 |
12 |
0 |
0 |
T138 |
3560 |
12 |
0 |
0 |
T167 |
13230 |
44 |
0 |
0 |
T176 |
12304 |
13 |
0 |
0 |
T177 |
12387 |
15 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
2099 |
0 |
0 |
T93 |
3229 |
4 |
0 |
0 |
T114 |
14812 |
4 |
0 |
0 |
T115 |
12304 |
29 |
0 |
0 |
T116 |
71843 |
195 |
0 |
0 |
T132 |
35614 |
125 |
0 |
0 |
T133 |
13900 |
16 |
0 |
0 |
T137 |
9795 |
3 |
0 |
0 |
T138 |
3560 |
7 |
0 |
0 |
T176 |
12304 |
34 |
0 |
0 |
T177 |
12387 |
7 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
3857 |
0 |
0 |
T18 |
190796 |
3 |
0 |
0 |
T19 |
266308 |
0 |
0 |
0 |
T20 |
421288 |
0 |
0 |
0 |
T21 |
436130 |
0 |
0 |
0 |
T22 |
734 |
0 |
0 |
0 |
T25 |
2217 |
0 |
0 |
0 |
T28 |
184676 |
0 |
0 |
0 |
T34 |
3561 |
0 |
0 |
0 |
T68 |
0 |
52 |
0 |
0 |
T89 |
209316 |
0 |
0 |
0 |
T90 |
283976 |
0 |
0 |
0 |
T91 |
0 |
16 |
0 |
0 |
T98 |
0 |
28 |
0 |
0 |
T101 |
0 |
8 |
0 |
0 |
T161 |
0 |
65 |
0 |
0 |
T162 |
0 |
23 |
0 |
0 |
T179 |
0 |
48 |
0 |
0 |
T180 |
0 |
8 |
0 |
0 |
T181 |
0 |
14 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1679 |
0 |
0 |
T93 |
3229 |
2 |
0 |
0 |
T115 |
12304 |
33 |
0 |
0 |
T116 |
71843 |
96 |
0 |
0 |
T132 |
35614 |
66 |
0 |
0 |
T133 |
13900 |
14 |
0 |
0 |
T137 |
9795 |
7 |
0 |
0 |
T138 |
3560 |
3 |
0 |
0 |
T167 |
13230 |
28 |
0 |
0 |
T176 |
12304 |
16 |
0 |
0 |
T177 |
12387 |
34 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1776 |
0 |
0 |
T93 |
3229 |
7 |
0 |
0 |
T115 |
12304 |
18 |
0 |
0 |
T116 |
71843 |
145 |
0 |
0 |
T132 |
35614 |
51 |
0 |
0 |
T133 |
13900 |
9 |
0 |
0 |
T137 |
9795 |
7 |
0 |
0 |
T167 |
13230 |
26 |
0 |
0 |
T177 |
12387 |
1 |
0 |
0 |
T178 |
68966 |
104 |
0 |
0 |
T182 |
6892 |
35 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1641 |
0 |
0 |
T93 |
3229 |
12 |
0 |
0 |
T115 |
12304 |
24 |
0 |
0 |
T116 |
71843 |
73 |
0 |
0 |
T132 |
35614 |
44 |
0 |
0 |
T133 |
13900 |
20 |
0 |
0 |
T137 |
9795 |
17 |
0 |
0 |
T138 |
3560 |
1 |
0 |
0 |
T167 |
13230 |
48 |
0 |
0 |
T176 |
12304 |
30 |
0 |
0 |
T177 |
12387 |
11 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1710 |
0 |
0 |
T93 |
3229 |
13 |
0 |
0 |
T115 |
12304 |
12 |
0 |
0 |
T116 |
71843 |
67 |
0 |
0 |
T132 |
35614 |
36 |
0 |
0 |
T133 |
13900 |
13 |
0 |
0 |
T137 |
9795 |
11 |
0 |
0 |
T138 |
3560 |
7 |
0 |
0 |
T167 |
13230 |
35 |
0 |
0 |
T176 |
12304 |
40 |
0 |
0 |
T177 |
12387 |
17 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1623 |
0 |
0 |
T93 |
3229 |
13 |
0 |
0 |
T115 |
12304 |
13 |
0 |
0 |
T116 |
71843 |
66 |
0 |
0 |
T132 |
35614 |
45 |
0 |
0 |
T133 |
13900 |
23 |
0 |
0 |
T137 |
9795 |
7 |
0 |
0 |
T138 |
3560 |
3 |
0 |
0 |
T167 |
13230 |
66 |
0 |
0 |
T176 |
12304 |
23 |
0 |
0 |
T177 |
12387 |
21 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1574 |
0 |
0 |
T93 |
3229 |
10 |
0 |
0 |
T115 |
12304 |
14 |
0 |
0 |
T116 |
71843 |
72 |
0 |
0 |
T132 |
35614 |
26 |
0 |
0 |
T133 |
13900 |
4 |
0 |
0 |
T137 |
9795 |
4 |
0 |
0 |
T167 |
13230 |
44 |
0 |
0 |
T176 |
12304 |
22 |
0 |
0 |
T177 |
12387 |
55 |
0 |
0 |
T178 |
68966 |
85 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
2042 |
0 |
0 |
T93 |
3229 |
14 |
0 |
0 |
T115 |
12304 |
30 |
0 |
0 |
T116 |
71843 |
147 |
0 |
0 |
T132 |
35614 |
116 |
0 |
0 |
T133 |
13900 |
32 |
0 |
0 |
T137 |
9795 |
19 |
0 |
0 |
T138 |
3560 |
7 |
0 |
0 |
T167 |
13230 |
57 |
0 |
0 |
T176 |
12304 |
6 |
0 |
0 |
T177 |
12387 |
42 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1708 |
0 |
0 |
T93 |
3229 |
9 |
0 |
0 |
T115 |
12304 |
22 |
0 |
0 |
T116 |
71843 |
106 |
0 |
0 |
T132 |
35614 |
48 |
0 |
0 |
T133 |
13900 |
9 |
0 |
0 |
T137 |
9795 |
2 |
0 |
0 |
T167 |
13230 |
31 |
0 |
0 |
T176 |
12304 |
30 |
0 |
0 |
T177 |
12387 |
28 |
0 |
0 |
T178 |
68966 |
89 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
2404 |
0 |
0 |
T93 |
3229 |
1 |
0 |
0 |
T115 |
12304 |
42 |
0 |
0 |
T116 |
71843 |
254 |
0 |
0 |
T132 |
35614 |
112 |
0 |
0 |
T133 |
13900 |
22 |
0 |
0 |
T137 |
9795 |
21 |
0 |
0 |
T138 |
3560 |
9 |
0 |
0 |
T167 |
13230 |
35 |
0 |
0 |
T176 |
12304 |
24 |
0 |
0 |
T177 |
12387 |
51 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1848 |
0 |
0 |
T93 |
3229 |
5 |
0 |
0 |
T115 |
12304 |
26 |
0 |
0 |
T116 |
71843 |
137 |
0 |
0 |
T118 |
13856 |
7 |
0 |
0 |
T132 |
35614 |
63 |
0 |
0 |
T133 |
13900 |
20 |
0 |
0 |
T137 |
9795 |
11 |
0 |
0 |
T138 |
3560 |
3 |
0 |
0 |
T167 |
13230 |
41 |
0 |
0 |
T176 |
12304 |
49 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1579 |
0 |
0 |
T93 |
3229 |
13 |
0 |
0 |
T115 |
12304 |
28 |
0 |
0 |
T116 |
71843 |
56 |
0 |
0 |
T132 |
35614 |
45 |
0 |
0 |
T137 |
9795 |
14 |
0 |
0 |
T167 |
13230 |
54 |
0 |
0 |
T176 |
12304 |
14 |
0 |
0 |
T177 |
12387 |
9 |
0 |
0 |
T178 |
68966 |
86 |
0 |
0 |
T182 |
6892 |
21 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1590 |
0 |
0 |
T93 |
3229 |
3 |
0 |
0 |
T115 |
12304 |
18 |
0 |
0 |
T116 |
71843 |
57 |
0 |
0 |
T132 |
35614 |
24 |
0 |
0 |
T133 |
13900 |
11 |
0 |
0 |
T137 |
9795 |
8 |
0 |
0 |
T138 |
3560 |
5 |
0 |
0 |
T167 |
13230 |
1 |
0 |
0 |
T176 |
12304 |
21 |
0 |
0 |
T177 |
12387 |
4 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1593 |
0 |
0 |
T93 |
3229 |
6 |
0 |
0 |
T115 |
12304 |
33 |
0 |
0 |
T116 |
71843 |
90 |
0 |
0 |
T132 |
35614 |
42 |
0 |
0 |
T133 |
13900 |
16 |
0 |
0 |
T137 |
9795 |
1 |
0 |
0 |
T167 |
13230 |
65 |
0 |
0 |
T176 |
12304 |
27 |
0 |
0 |
T177 |
12387 |
9 |
0 |
0 |
T178 |
68966 |
78 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1536 |
0 |
0 |
T93 |
3229 |
7 |
0 |
0 |
T115 |
12304 |
10 |
0 |
0 |
T116 |
71843 |
70 |
0 |
0 |
T132 |
35614 |
29 |
0 |
0 |
T133 |
13900 |
11 |
0 |
0 |
T137 |
9795 |
7 |
0 |
0 |
T138 |
3560 |
3 |
0 |
0 |
T167 |
13230 |
37 |
0 |
0 |
T176 |
12304 |
41 |
0 |
0 |
T177 |
12387 |
30 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1587 |
0 |
0 |
T93 |
3229 |
3 |
0 |
0 |
T115 |
12304 |
18 |
0 |
0 |
T116 |
71843 |
79 |
0 |
0 |
T132 |
35614 |
38 |
0 |
0 |
T133 |
13900 |
10 |
0 |
0 |
T137 |
9795 |
3 |
0 |
0 |
T138 |
3560 |
3 |
0 |
0 |
T167 |
13230 |
79 |
0 |
0 |
T176 |
12304 |
12 |
0 |
0 |
T177 |
12387 |
21 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
385468596 |
1652 |
0 |
0 |
T93 |
3229 |
13 |
0 |
0 |
T115 |
12304 |
24 |
0 |
0 |
T116 |
71843 |
86 |
0 |
0 |
T132 |
35614 |
19 |
0 |
0 |
T133 |
13900 |
20 |
0 |
0 |
T137 |
9795 |
10 |
0 |
0 |
T167 |
13230 |
50 |
0 |
0 |
T176 |
12304 |
34 |
0 |
0 |
T177 |
12387 |
21 |
0 |
0 |
T178 |
68966 |
56 |
0 |
0 |