Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3621433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3799711

1

T1

106

T2

49

T3

1232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4276037	1			T1	101		T2	61		T3	637
values[0x0]	1571942	1			T1	57		T2	35		T3	455
values[0x1]	1573165	1			T1	43		T2	25		T3	462

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2564996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4856148

1

T1

160

T2

61

T3

1305

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	34395	1			T3	8		T7	28		T9	5
valid_sources[0x01]	26026	1			T3	2		T4	1		T7	25
valid_sources[0x02]	27978	1			T1	1		T3	5		T7	26
valid_sources[0x03]	29576	1			T1	2		T3	6		T7	20
valid_sources[0x04]	26847	1			T1	2		T3	9		T7	22
valid_sources[0x05]	28099	1			T3	6		T7	25		T9	9
valid_sources[0x06]	26288	1			T3	8		T7	19		T9	3
valid_sources[0x07]	28375	1			T3	1		T7	16		T9	1
valid_sources[0x08]	28997	1			T3	3		T7	26		T9	4
valid_sources[0x09]	29800	1			T3	7		T7	27		T9	1
valid_sources[0x0a]	29233	1			T3	10		T7	15		T8	1
valid_sources[0x0b]	28245	1			T3	3		T7	27		T9	3
valid_sources[0x0c]	29092	1			T7	13		T9	4		T12	2
valid_sources[0x0d]	31259	1			T3	5		T7	20		T9	3
valid_sources[0x0e]	35845	1			T3	15		T7	19		T9	2
valid_sources[0x0f]	31522	1			T3	3		T7	24		T8	4
valid_sources[0x10]	33340	1			T3	12		T7	16		T8	12
valid_sources[0x11]	33043	1			T3	4		T4	1		T7	24
valid_sources[0x12]	29559	1			T3	5		T7	24		T9	2
valid_sources[0x13]	28646	1			T1	1		T3	12		T7	28
valid_sources[0x14]	27707	1			T1	1		T3	8		T7	22
valid_sources[0x15]	30538	1			T1	2		T3	5		T7	21
valid_sources[0x16]	24972	1			T3	8		T7	26		T9	1
valid_sources[0x17]	37191	1			T3	6		T7	22		T9	1
valid_sources[0x18]	26680	1			T1	1		T3	10		T7	14
valid_sources[0x19]	26510	1			T3	9		T5	1		T7	23
valid_sources[0x1a]	25817	1			T3	8		T7	13		T9	2
valid_sources[0x1b]	27750	1			T3	4		T4	2		T7	16
valid_sources[0x1c]	27177	1			T3	5		T7	20		T9	3
valid_sources[0x1d]	29177	1			T3	7		T7	20		T9	5
valid_sources[0x1e]	27110	1			T1	5		T3	7		T7	30
valid_sources[0x1f]	27850	1			T3	7		T7	16		T10	147
valid_sources[0x20]	28369	1			T3	2		T7	30		T8	4
valid_sources[0x21]	28762	1			T3	4		T7	17		T8	1
valid_sources[0x22]	29322	1			T3	6		T7	18		T9	2
valid_sources[0x23]	29387	1			T1	1		T3	4		T7	24
valid_sources[0x24]	28918	1			T3	5		T7	22		T9	3
valid_sources[0x25]	28701	1			T3	2		T6	142		T7	20
valid_sources[0x26]	27353	1			T3	7		T7	20		T9	11
valid_sources[0x27]	29197	1			T3	1		T7	18		T9	3
valid_sources[0x28]	31942	1			T1	2		T3	4		T7	26
valid_sources[0x29]	26144	1			T3	3		T7	26		T9	1
valid_sources[0x2a]	30981	1			T3	2		T7	28		T9	3
valid_sources[0x2b]	30432	1			T3	2		T6	5		T7	22
valid_sources[0x2c]	30746	1			T3	4		T7	13		T8	4
valid_sources[0x2d]	29525	1			T3	10		T7	21		T9	5
valid_sources[0x2e]	29058	1			T3	5		T7	19		T9	3
valid_sources[0x2f]	26918	1			T3	1		T7	10		T9	3
valid_sources[0x30]	26986	1			T3	6		T7	22		T9	4
valid_sources[0x31]	30434	1			T1	3		T3	13		T7	17
valid_sources[0x32]	25902	1			T3	3		T7	15		T9	5
valid_sources[0x33]	27808	1			T1	1		T3	6		T7	20
valid_sources[0x34]	28941	1			T3	5		T7	23		T8	3
valid_sources[0x35]	29900	1			T3	4		T7	28		T8	2
valid_sources[0x36]	29275	1			T1	1		T3	6		T7	17
valid_sources[0x37]	30776	1			T3	1		T4	3		T7	24
valid_sources[0x38]	28869	1			T3	9		T7	26		T8	4
valid_sources[0x39]	26588	1			T3	2		T7	20		T9	5
valid_sources[0x3a]	26697	1			T1	2		T3	3		T7	26
valid_sources[0x3b]	29144	1			T3	5		T7	22		T9	2
valid_sources[0x3c]	27753	1			T3	7		T7	19		T9	3
valid_sources[0x3d]	54325	1			T3	2		T7	30		T9	8
valid_sources[0x3e]	28966	1			T3	7		T7	21		T9	9
valid_sources[0x3f]	29847	1			T1	4		T3	6		T7	27
valid_sources[0x40]	28345	1			T1	6		T3	4		T7	27
valid_sources[0x41]	27345	1			T3	4		T7	20		T12	4
valid_sources[0x42]	27193	1			T3	8		T7	22		T9	8
valid_sources[0x43]	25942	1			T1	4		T3	6		T7	35
valid_sources[0x44]	31025	1			T3	5		T7	22		T9	7
valid_sources[0x45]	27465	1			T1	5		T3	3		T7	22
valid_sources[0x46]	28130	1			T3	5		T7	14		T8	1
valid_sources[0x47]	31447	1			T3	8		T5	258		T7	20
valid_sources[0x48]	25662	1			T1	1		T3	5		T7	16
valid_sources[0x49]	26823	1			T1	5		T3	9		T7	17
valid_sources[0x4a]	31818	1			T3	8		T7	18		T8	15
valid_sources[0x4b]	26671	1			T3	6		T7	21		T8	1
valid_sources[0x4c]	26881	1			T1	4		T3	6		T7	15
valid_sources[0x4d]	26861	1			T3	9		T7	26		T9	6
valid_sources[0x4e]	29260	1			T3	10		T7	20		T9	7
valid_sources[0x4f]	30126	1			T3	5		T7	23		T8	7
valid_sources[0x50]	28413	1			T3	2		T7	15		T9	4
valid_sources[0x51]	27120	1			T1	3		T3	9		T7	27
valid_sources[0x52]	27836	1			T3	9		T7	18		T9	5
valid_sources[0x53]	31318	1			T3	4		T7	20		T9	1
valid_sources[0x54]	28927	1			T3	7		T7	17		T9	1
valid_sources[0x55]	28362	1			T3	7		T7	15		T9	4
valid_sources[0x56]	30433	1			T1	1		T3	14		T7	25
valid_sources[0x57]	28059	1			T1	1		T3	6		T7	21
valid_sources[0x58]	26897	1			T1	3		T3	10		T7	17
valid_sources[0x59]	28821	1			T3	6		T7	22		T9	5
valid_sources[0x5a]	34343	1			T3	7		T7	20		T9	4
valid_sources[0x5b]	27401	1			T1	6		T3	7		T7	27
valid_sources[0x5c]	27999	1			T3	10		T7	18		T9	2
valid_sources[0x5d]	28418	1			T3	4		T7	22		T9	4
valid_sources[0x5e]	28530	1			T1	8		T3	8		T7	17
valid_sources[0x5f]	27937	1			T1	1		T3	6		T7	24
valid_sources[0x60]	31231	1			T3	7		T7	16		T9	7
valid_sources[0x61]	27933	1			T1	3		T3	9		T7	19
valid_sources[0x62]	26158	1			T1	2		T3	6		T7	21
valid_sources[0x63]	29913	1			T2	121		T3	6		T7	14
valid_sources[0x64]	32548	1			T3	8		T4	2		T7	20
valid_sources[0x65]	34724	1			T3	10		T7	14		T8	1
valid_sources[0x66]	30670	1			T3	12		T7	38		T9	3
valid_sources[0x67]	26801	1			T3	3		T7	18		T8	7
valid_sources[0x68]	28760	1			T3	6		T7	21		T9	8
valid_sources[0x69]	28463	1			T3	3		T7	15		T9	2
valid_sources[0x6a]	27206	1			T3	9		T7	27		T8	1
valid_sources[0x6b]	26453	1			T3	10		T7	17		T8	5
valid_sources[0x6c]	28885	1			T3	8		T7	24		T8	8
valid_sources[0x6d]	32260	1			T3	11		T7	19		T8	3
valid_sources[0x6e]	28478	1			T3	3		T5	1		T7	14
valid_sources[0x6f]	26689	1			T3	7		T7	20		T9	2
valid_sources[0x70]	27477	1			T3	8		T7	26		T9	1
valid_sources[0x71]	29396	1			T3	8		T7	17		T8	6
valid_sources[0x72]	30871	1			T1	1		T3	5		T4	2
valid_sources[0x73]	36322	1			T3	1		T5	131		T7	21
valid_sources[0x74]	27160	1			T3	2		T7	16		T8	11
valid_sources[0x75]	28556	1			T1	1		T3	5		T7	16
valid_sources[0x76]	27201	1			T1	1		T3	5		T7	26
valid_sources[0x77]	26612	1			T3	7		T7	26		T9	5
valid_sources[0x78]	29607	1			T1	1		T3	5		T7	25
valid_sources[0x79]	26189	1			T3	6		T7	21		T8	1
valid_sources[0x7a]	27176	1			T3	9		T7	24		T8	1
valid_sources[0x7b]	26508	1			T1	4		T3	4		T7	18
valid_sources[0x7c]	29278	1			T1	3		T3	6		T7	14
valid_sources[0x7d]	29074	1			T3	7		T7	22		T9	6
valid_sources[0x7e]	28989	1			T1	1		T3	9		T7	20
valid_sources[0x7f]	27905	1			T3	9		T7	25		T9	4
valid_sources[0x80]	29483	1			T3	9		T7	21		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

989342

1

T1

6

T2

33

T3

324

values[0x0]

all_enables

biggest_size

1416676

1

T1

57

T2

10

T3

454

values[0x1]

all_enables

biggest_size

1393693

1

T1

43

T2

6

T3

454