Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3639096

1

T2

72

T3

322

T4

12

full_word

3798727

1

T2

49

T3

1232

T4

3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7437403	1			T2	121		T3	1554		T4	15
auto[TlIntgErrCmd]	133	1			T96	7		T100	13		T101	10
auto[TlIntgErrData]	146	1			T96	9		T100	10		T101	12
auto[TlIntgErrBoth]	141	1			T96	14		T100	7		T101	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4277348

1

T2

61

T3

637

T4

1

auto[1]

3160475

1

T2

60

T3

917

T4

14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3287734	1			T2	28		T3	313		T5	108
auto[TlIntgErrNone]	partial	auto[1]	350975	1			T2	44		T3	9		T4	12
auto[TlIntgErrNone]	full_word	auto[0]	989416	1			T2	33		T3	324		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	2809278	1			T2	16		T3	908		T4	2
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T96	1		T100	3		T101	5
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T96	5		T100	9		T101	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T100	1		T153	1		T271	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T96	1		T101	1		T272	1
auto[TlIntgErrData]	partial	auto[0]	75	1			T96	5		T100	7		T101	5
auto[TlIntgErrData]	partial	auto[1]	59	1			T96	4		T100	2		T101	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T101	2		T153	1		T271	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T100	1		T101	1		T273	1
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T96	3		T100	2		T101	3
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T96	10		T100	5		T101	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T274	1		T153	1		T275	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T96	1		T271	1		T276	2