Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T13
1	0	Covered	T8,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T13
1	0	Unreachable
1	1	Covered	T8,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T18
1	0	Covered	T13,T14,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T13,T14,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	591265675	472953250	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	591265675	2847166	0	0
GntImpliesValid_A	591265675	2847166	0	0
GrantKnown_A	591265675	472953250	0	0
IdxKnown_A	591265675	472953250	0	0
IndexIsCorrect_A	591265675	2847166	0	0
LockArbDecision_A	591265675	0	0	0
NoReadyValidNoGrant_A	591265675	0	0	0
ReadyAndValidImplyGrant_A	591265675	2847166	0	0
ReqAndReadyImplyGrant_A	591265675	2847166	0	0
ReqImpliesValid_A	591265675	2847166	0	0
ReqStaysHighUntilGranted0_M	591265675	0	0	0
RoundRobin_A	591265675	4	0	926
ValidKnown_A	591265675	472953250	0	0
gen_data_port_assertion.DataFlow_A	591265675	2847166	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	472953250	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	45736	45256	0	0
T4	1329	1253	0	0
T5	49993	49678	0	0
T6	56222	55524	0	0
T7	126023	125685	0	0
T8	4144	3641	0	0
T9	2923	2742	0	0
T10	141063	95084	0	0
T11	143714	71820	0	0
T12	15136	7254	0	0
T13	199821	377160	0	0
T14	104815	130848	0	0
T15	8224	4112	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	472953250	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	45736	45256	0	0
T4	1329	1253	0	0
T5	49993	49678	0	0
T6	56222	55524	0	0
T7	126023	125685	0	0
T8	4144	3641	0	0
T9	2923	2742	0	0
T10	141063	95084	0	0
T11	143714	71820	0	0
T12	15136	7254	0	0
T13	199821	377160	0	0
T14	104815	130848	0	0
T15	8224	4112	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	472953250	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	45736	45256	0	0
T4	1329	1253	0	0
T5	49993	49678	0	0
T6	56222	55524	0	0
T7	126023	125685	0	0
T8	4144	3641	0	0
T9	2923	2742	0	0
T10	141063	95084	0	0
T11	143714	71820	0	0
T12	15136	7254	0	0
T13	199821	377160	0	0
T14	104815	130848	0	0
T15	8224	4112	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	4	0	926
T47	475704	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	551240	0	0	1
T52	619213	0	0	1
T53	62216	0	0	1
T54	94016	0	0	1
T55	154851	0	0	1
T56	39322	0	0	1
T57	868	0	0	1
T58	16295	0	0	1
T59	9825	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	472953250	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	45736	45256	0	0
T4	1329	1253	0	0
T5	49993	49678	0	0
T6	56222	55524	0	0
T7	126023	125685	0	0
T8	4144	3641	0	0
T9	2923	2742	0	0
T10	141063	95084	0	0
T11	143714	71820	0	0
T12	15136	7254	0	0
T13	199821	377160	0	0
T14	104815	130848	0	0
T15	8224	4112	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591265675	2847166	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3728	40	0	0
T9	2827	832	0	0
T10	96727	1540	0	0
T11	71857	832	0	0
T12	7568	832	0	0
T13	399642	9882	0	0
T14	209630	8517	0	0
T15	4112	0	0	0
T17	73278	0	0	0
T18	560085	2583	0	0
T19	0	13	0	0
T20	0	347	0	0
T21	0	9263	0	0
T25	0	2786	0	0
T26	81267	0	0	0
T35	16674	0	0	0
T36	8324	0	0	0
T37	4056	0	0	0
T43	0	1338	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T10,T13
1	0	Covered	T8,T10,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T13
1	0	Unreachable
1	1	Covered	T8,T10,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T8,T10,T13
0	0	1	Unreachable
0	0	0	Covered	T8,T10,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	117028741	28330615	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	117028741	641416	0	0
GntImpliesValid_A	117028741	641416	0	0
GrantKnown_A	117028741	28330615	0	0
IdxKnown_A	117028741	28330615	0	0
IndexIsCorrect_A	117028741	641416	0	0
LockArbDecision_A	117028741	0	0	0
NoReadyValidNoGrant_A	117028741	0	0	0
ReadyAndValidImplyGrant_A	117028741	641416	0	0
ReqAndReadyImplyGrant_A	117028741	641416	0	0
ReqImpliesValid_A	117028741	641416	0	0
ReqStaysHighUntilGranted0_M	117028741	0	0	0
RoundRobin_A	117028741	0	0	0
ValidKnown_A	117028741	28330615	0	0
gen_data_port_assertion.DataFlow_A	117028741	641416	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	28330615	0	0
T8	416	416	0	0
T9	96	0	0	0
T10	44336	42784	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	198208	0	0
T14	104815	29376	0	0
T15	4112	0	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	28330615	0	0
T8	416	416	0	0
T9	96	0	0	0
T10	44336	42784	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	198208	0	0
T14	104815	29376	0	0
T15	4112	0	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	28330615	0	0
T8	416	416	0	0
T9	96	0	0	0
T10	44336	42784	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	198208	0	0
T14	104815	29376	0	0
T15	4112	0	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	28330615	0	0
T8	416	416	0	0
T9	96	0	0	0
T10	44336	42784	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	198208	0	0
T14	104815	29376	0	0
T15	4112	0	0	0
T17	0	69024	0	0
T18	0	50352	0	0
T19	0	424	0	0
T20	0	18840	0	0
T21	0	227760	0	0
T25	0	45240	0	0
T35	8337	0	0	0
T36	4162	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	641416	0	0
T8	416	31	0	0
T9	96	0	0	0
T10	44336	1038	0	0
T11	71857	0	0	0
T12	7568	0	0	0
T13	199821	4765	0	0
T14	104815	189	0	0
T15	4112	0	0	0
T18	0	2208	0	0
T19	0	13	0	0
T20	0	324	0	0
T21	0	5612	0	0
T25	0	1753	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T43	0	1338	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T18

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T18
1	0	Covered	T13,T14,T18

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T13,T14,T18

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T14,T18
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	117028741	87499500	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	117028741	368877	0	0
GntImpliesValid_A	117028741	368877	0	0
GrantKnown_A	117028741	87499500	0	0
IdxKnown_A	117028741	87499500	0	0
IndexIsCorrect_A	117028741	368877	0	0
LockArbDecision_A	117028741	0	0	0
NoReadyValidNoGrant_A	117028741	0	0	0
ReadyAndValidImplyGrant_A	117028741	368877	0	0
ReqAndReadyImplyGrant_A	117028741	368877	0	0
ReqImpliesValid_A	117028741	368877	0	0
ReqStaysHighUntilGranted0_M	117028741	0	0	0
RoundRobin_A	117028741	0	0	0
ValidKnown_A	117028741	87499500	0	0
gen_data_port_assertion.DataFlow_A	117028741	368877	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	87499500	0	0
T3	28647	28230	0	0
T5	22257	22036	0	0
T6	11875	11248	0	0
T7	24533	24288	0	0
T8	416	0	0	0
T9	96	96	0	0
T10	44336	0	0	0
T11	71857	71820	0	0
T12	7568	7254	0	0
T13	0	178952	0	0
T14	0	101472	0	0
T15	4112	4112	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	87499500	0	0
T3	28647	28230	0	0
T5	22257	22036	0	0
T6	11875	11248	0	0
T7	24533	24288	0	0
T8	416	0	0	0
T9	96	96	0	0
T10	44336	0	0	0
T11	71857	71820	0	0
T12	7568	7254	0	0
T13	0	178952	0	0
T14	0	101472	0	0
T15	4112	4112	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	87499500	0	0
T3	28647	28230	0	0
T5	22257	22036	0	0
T6	11875	11248	0	0
T7	24533	24288	0	0
T8	416	0	0	0
T9	96	96	0	0
T10	44336	0	0	0
T11	71857	71820	0	0
T12	7568	7254	0	0
T13	0	178952	0	0
T14	0	101472	0	0
T15	4112	4112	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	87499500	0	0
T3	28647	28230	0	0
T5	22257	22036	0	0
T6	11875	11248	0	0
T7	24533	24288	0	0
T8	416	0	0	0
T9	96	96	0	0
T10	44336	0	0	0
T11	71857	71820	0	0
T12	7568	7254	0	0
T13	0	178952	0	0
T14	0	101472	0	0
T15	4112	4112	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117028741	368877	0	0
T13	199821	5117	0	0
T14	104815	8328	0	0
T17	73278	0	0	0
T18	560085	375	0	0
T19	424	0	0	0
T20	892298	23	0	0
T21	0	3651	0	0
T25	0	1033	0	0
T26	81267	0	0	0
T28	0	4	0	0
T35	8337	0	0	0
T36	4162	0	0	0
T37	4056	0	0	0
T44	0	1038	0	0
T45	0	3546	0	0
T46	0	488	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T8,T10
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	357208193	357123135	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	357208193	1836873	0	0
GntImpliesValid_A	357208193	1836873	0	0
GrantKnown_A	357208193	357123135	0	0
IdxKnown_A	357208193	357123135	0	0
IndexIsCorrect_A	357208193	1836873	0	0
LockArbDecision_A	357208193	0	0	0
NoReadyValidNoGrant_A	357208193	0	0	0
ReadyAndValidImplyGrant_A	357208193	1836873	0	0
ReqAndReadyImplyGrant_A	357208193	1836873	0	0
ReqImpliesValid_A	357208193	1836873	0	0
ReqStaysHighUntilGranted0_M	357208193	0	0	0
RoundRobin_A	357208193	4	0	926
ValidKnown_A	357208193	357123135	0	0
gen_data_port_assertion.DataFlow_A	357208193	1836873	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	357123135	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	17089	17026	0	0
T4	1329	1253	0	0
T5	27736	27642	0	0
T6	44347	44276	0	0
T7	101490	101397	0	0
T8	3312	3225	0	0
T9	2731	2646	0	0
T10	52391	52300	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	357123135	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	17089	17026	0	0
T4	1329	1253	0	0
T5	27736	27642	0	0
T6	44347	44276	0	0
T7	101490	101397	0	0
T8	3312	3225	0	0
T9	2731	2646	0	0
T10	52391	52300	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	357123135	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	17089	17026	0	0
T4	1329	1253	0	0
T5	27736	27642	0	0
T6	44347	44276	0	0
T7	101490	101397	0	0
T8	3312	3225	0	0
T9	2731	2646	0	0
T10	52391	52300	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	4	0	926
T47	475704	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	551240	0	0	1
T52	619213	0	0	1
T53	62216	0	0	1
T54	94016	0	0	1
T55	154851	0	0	1
T56	39322	0	0	1
T57	868	0	0	1
T58	16295	0	0	1
T59	9825	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	357123135	0	0
T1	1314	1248	0	0
T2	2856	2700	0	0
T3	17089	17026	0	0
T4	1329	1253	0	0
T5	27736	27642	0	0
T6	44347	44276	0	0
T7	101490	101397	0	0
T8	3312	3225	0	0
T9	2731	2646	0	0
T10	52391	52300	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357208193	1836873	0	0
T1	1314	200	0	0
T2	2856	0	0	0
T3	17089	832	0	0
T4	1329	0	0	0
T5	27736	1344	0	0
T6	44347	832	0	0
T7	101490	832	0	0
T8	3312	9	0	0
T9	2731	832	0	0
T10	52391	502	0	0
T11	0	832	0	0
T12	0	832	0	0