Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
3598 |
0 |
0 |
T96 |
29436 |
3 |
0 |
0 |
T97 |
4872 |
87 |
0 |
0 |
T98 |
5486 |
13 |
0 |
0 |
T99 |
12913 |
182 |
0 |
0 |
T100 |
30109 |
2 |
0 |
0 |
T102 |
2962 |
113 |
0 |
0 |
T104 |
6248 |
319 |
0 |
0 |
T105 |
19927 |
254 |
0 |
0 |
T113 |
8736 |
6 |
0 |
0 |
T114 |
5385 |
6 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2412 |
0 |
0 |
T101 |
103057 |
87 |
0 |
0 |
T116 |
4535 |
1 |
0 |
0 |
T117 |
10373 |
10 |
0 |
0 |
T123 |
269908 |
670 |
0 |
0 |
T152 |
10110 |
20 |
0 |
0 |
T153 |
97538 |
111 |
0 |
0 |
T154 |
19002 |
9 |
0 |
0 |
T155 |
7072 |
11 |
0 |
0 |
T156 |
13570 |
17 |
0 |
0 |
T157 |
4091 |
8 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2554 |
0 |
0 |
T101 |
103057 |
106 |
0 |
0 |
T116 |
4535 |
4 |
0 |
0 |
T117 |
10373 |
20 |
0 |
0 |
T123 |
269908 |
663 |
0 |
0 |
T152 |
10110 |
5 |
0 |
0 |
T153 |
97538 |
122 |
0 |
0 |
T154 |
19002 |
23 |
0 |
0 |
T155 |
7072 |
5 |
0 |
0 |
T156 |
13570 |
33 |
0 |
0 |
T157 |
4091 |
2 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
3096 |
0 |
0 |
T101 |
103057 |
210 |
0 |
0 |
T116 |
4535 |
1 |
0 |
0 |
T117 |
10373 |
32 |
0 |
0 |
T123 |
269908 |
647 |
0 |
0 |
T152 |
10110 |
20 |
0 |
0 |
T153 |
97538 |
243 |
0 |
0 |
T154 |
19002 |
28 |
0 |
0 |
T155 |
7072 |
21 |
0 |
0 |
T156 |
13570 |
55 |
0 |
0 |
T157 |
4091 |
11 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
11570 |
0 |
0 |
T101 |
103057 |
1914 |
0 |
0 |
T116 |
4535 |
3 |
0 |
0 |
T117 |
10373 |
346 |
0 |
0 |
T123 |
269908 |
637 |
0 |
0 |
T152 |
10110 |
16 |
0 |
0 |
T153 |
97538 |
2006 |
0 |
0 |
T154 |
19002 |
17 |
0 |
0 |
T155 |
7072 |
156 |
0 |
0 |
T156 |
13570 |
103 |
0 |
0 |
T157 |
4091 |
111 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
12418 |
0 |
0 |
T101 |
103057 |
2212 |
0 |
0 |
T116 |
4535 |
64 |
0 |
0 |
T117 |
10373 |
23 |
0 |
0 |
T123 |
269908 |
735 |
0 |
0 |
T152 |
10110 |
20 |
0 |
0 |
T153 |
97538 |
2096 |
0 |
0 |
T154 |
19002 |
40 |
0 |
0 |
T155 |
7072 |
298 |
0 |
0 |
T156 |
13570 |
64 |
0 |
0 |
T157 |
4091 |
5 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
12385 |
0 |
0 |
T101 |
103057 |
1689 |
0 |
0 |
T116 |
4535 |
102 |
0 |
0 |
T117 |
10373 |
227 |
0 |
0 |
T123 |
269908 |
690 |
0 |
0 |
T152 |
10110 |
147 |
0 |
0 |
T153 |
97538 |
1691 |
0 |
0 |
T154 |
19002 |
22 |
0 |
0 |
T155 |
7072 |
160 |
0 |
0 |
T156 |
13570 |
14 |
0 |
0 |
T157 |
4091 |
2 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
12800 |
0 |
0 |
T101 |
103057 |
2365 |
0 |
0 |
T116 |
4535 |
90 |
0 |
0 |
T117 |
10373 |
123 |
0 |
0 |
T123 |
269908 |
710 |
0 |
0 |
T152 |
10110 |
14 |
0 |
0 |
T153 |
97538 |
1613 |
0 |
0 |
T154 |
19002 |
43 |
0 |
0 |
T155 |
7072 |
117 |
0 |
0 |
T156 |
13570 |
43 |
0 |
0 |
T157 |
4091 |
111 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
11453 |
0 |
0 |
T101 |
103057 |
1932 |
0 |
0 |
T116 |
4535 |
4 |
0 |
0 |
T117 |
10373 |
347 |
0 |
0 |
T123 |
269908 |
740 |
0 |
0 |
T152 |
10110 |
26 |
0 |
0 |
T153 |
97538 |
1464 |
0 |
0 |
T154 |
19002 |
26 |
0 |
0 |
T155 |
7072 |
5 |
0 |
0 |
T156 |
13570 |
36 |
0 |
0 |
T157 |
4091 |
111 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
11323 |
0 |
0 |
T101 |
103057 |
2709 |
0 |
0 |
T116 |
4535 |
81 |
0 |
0 |
T117 |
10373 |
112 |
0 |
0 |
T123 |
269908 |
662 |
0 |
0 |
T152 |
10110 |
131 |
0 |
0 |
T153 |
97538 |
2134 |
0 |
0 |
T154 |
19002 |
58 |
0 |
0 |
T155 |
7072 |
11 |
0 |
0 |
T156 |
13570 |
33 |
0 |
0 |
T157 |
4091 |
122 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
13971 |
0 |
0 |
T101 |
103057 |
2395 |
0 |
0 |
T116 |
4535 |
133 |
0 |
0 |
T117 |
10373 |
124 |
0 |
0 |
T123 |
269908 |
725 |
0 |
0 |
T152 |
10110 |
264 |
0 |
0 |
T153 |
97538 |
2078 |
0 |
0 |
T154 |
19002 |
45 |
0 |
0 |
T155 |
7072 |
128 |
0 |
0 |
T156 |
13570 |
62 |
0 |
0 |
T157 |
4091 |
133 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
11924 |
0 |
0 |
T101 |
103057 |
1649 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
168 |
0 |
0 |
T123 |
269908 |
676 |
0 |
0 |
T152 |
10110 |
120 |
0 |
0 |
T153 |
97538 |
1965 |
0 |
0 |
T154 |
19002 |
46 |
0 |
0 |
T155 |
7072 |
253 |
0 |
0 |
T156 |
13570 |
49 |
0 |
0 |
T157 |
4091 |
10 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
5636 |
0 |
0 |
T101 |
103057 |
815 |
0 |
0 |
T116 |
4535 |
43 |
0 |
0 |
T117 |
10373 |
100 |
0 |
0 |
T123 |
269908 |
668 |
0 |
0 |
T152 |
10110 |
116 |
0 |
0 |
T153 |
97538 |
596 |
0 |
0 |
T154 |
19002 |
26 |
0 |
0 |
T155 |
7072 |
1 |
0 |
0 |
T156 |
13570 |
64 |
0 |
0 |
T157 |
4091 |
9 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6119 |
0 |
0 |
T101 |
103057 |
790 |
0 |
0 |
T116 |
4535 |
4 |
0 |
0 |
T117 |
10373 |
18 |
0 |
0 |
T123 |
269908 |
622 |
0 |
0 |
T152 |
10110 |
135 |
0 |
0 |
T153 |
97538 |
839 |
0 |
0 |
T154 |
19002 |
21 |
0 |
0 |
T155 |
7072 |
2 |
0 |
0 |
T156 |
13570 |
37 |
0 |
0 |
T158 |
72514 |
500 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6227 |
0 |
0 |
T101 |
103057 |
960 |
0 |
0 |
T116 |
4535 |
27 |
0 |
0 |
T117 |
10373 |
97 |
0 |
0 |
T123 |
269908 |
683 |
0 |
0 |
T152 |
10110 |
9 |
0 |
0 |
T153 |
97538 |
898 |
0 |
0 |
T154 |
19002 |
30 |
0 |
0 |
T155 |
7072 |
56 |
0 |
0 |
T156 |
13570 |
52 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6621 |
0 |
0 |
T101 |
103057 |
974 |
0 |
0 |
T116 |
4535 |
27 |
0 |
0 |
T117 |
10373 |
70 |
0 |
0 |
T123 |
269908 |
659 |
0 |
0 |
T152 |
10110 |
8 |
0 |
0 |
T153 |
97538 |
917 |
0 |
0 |
T154 |
19002 |
49 |
0 |
0 |
T155 |
7072 |
123 |
0 |
0 |
T156 |
13570 |
48 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6226 |
0 |
0 |
T101 |
103057 |
577 |
0 |
0 |
T116 |
4535 |
2 |
0 |
0 |
T117 |
10373 |
77 |
0 |
0 |
T123 |
269908 |
708 |
0 |
0 |
T152 |
10110 |
98 |
0 |
0 |
T153 |
97538 |
870 |
0 |
0 |
T154 |
19002 |
32 |
0 |
0 |
T155 |
7072 |
60 |
0 |
0 |
T156 |
13570 |
42 |
0 |
0 |
T158 |
72514 |
527 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6059 |
0 |
0 |
T101 |
103057 |
599 |
0 |
0 |
T116 |
4535 |
1 |
0 |
0 |
T117 |
10373 |
118 |
0 |
0 |
T123 |
269908 |
653 |
0 |
0 |
T152 |
10110 |
119 |
0 |
0 |
T153 |
97538 |
814 |
0 |
0 |
T154 |
19002 |
21 |
0 |
0 |
T155 |
7072 |
45 |
0 |
0 |
T156 |
13570 |
48 |
0 |
0 |
T157 |
4091 |
33 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
5991 |
0 |
0 |
T101 |
103057 |
709 |
0 |
0 |
T116 |
4535 |
4 |
0 |
0 |
T117 |
10373 |
59 |
0 |
0 |
T123 |
269908 |
720 |
0 |
0 |
T152 |
10110 |
108 |
0 |
0 |
T153 |
97538 |
684 |
0 |
0 |
T154 |
19002 |
27 |
0 |
0 |
T155 |
7072 |
44 |
0 |
0 |
T156 |
13570 |
50 |
0 |
0 |
T157 |
4091 |
45 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6309 |
0 |
0 |
T101 |
103057 |
626 |
0 |
0 |
T116 |
4535 |
28 |
0 |
0 |
T117 |
10373 |
83 |
0 |
0 |
T123 |
269908 |
632 |
0 |
0 |
T152 |
10110 |
72 |
0 |
0 |
T153 |
97538 |
957 |
0 |
0 |
T154 |
19002 |
48 |
0 |
0 |
T155 |
7072 |
107 |
0 |
0 |
T156 |
13570 |
50 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6589 |
0 |
0 |
T101 |
103057 |
979 |
0 |
0 |
T116 |
4535 |
8 |
0 |
0 |
T117 |
10373 |
107 |
0 |
0 |
T123 |
269908 |
624 |
0 |
0 |
T152 |
10110 |
107 |
0 |
0 |
T153 |
97538 |
586 |
0 |
0 |
T154 |
19002 |
19 |
0 |
0 |
T155 |
7072 |
46 |
0 |
0 |
T156 |
13570 |
54 |
0 |
0 |
T157 |
4091 |
53 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6248 |
0 |
0 |
T101 |
103057 |
775 |
0 |
0 |
T116 |
4535 |
39 |
0 |
0 |
T117 |
10373 |
124 |
0 |
0 |
T123 |
269908 |
728 |
0 |
0 |
T152 |
10110 |
53 |
0 |
0 |
T153 |
97538 |
425 |
0 |
0 |
T154 |
19002 |
14 |
0 |
0 |
T155 |
7072 |
66 |
0 |
0 |
T156 |
13570 |
27 |
0 |
0 |
T157 |
4091 |
4 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6408 |
0 |
0 |
T101 |
103057 |
649 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
50 |
0 |
0 |
T123 |
269908 |
647 |
0 |
0 |
T152 |
10110 |
137 |
0 |
0 |
T153 |
97538 |
996 |
0 |
0 |
T154 |
19002 |
43 |
0 |
0 |
T155 |
7072 |
52 |
0 |
0 |
T156 |
13570 |
71 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
5815 |
0 |
0 |
T101 |
103057 |
597 |
0 |
0 |
T117 |
10373 |
47 |
0 |
0 |
T123 |
269908 |
644 |
0 |
0 |
T152 |
10110 |
9 |
0 |
0 |
T153 |
97538 |
833 |
0 |
0 |
T154 |
19002 |
31 |
0 |
0 |
T155 |
7072 |
149 |
0 |
0 |
T156 |
13570 |
52 |
0 |
0 |
T157 |
4091 |
5 |
0 |
0 |
T158 |
72514 |
375 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6421 |
0 |
0 |
T101 |
103057 |
1013 |
0 |
0 |
T117 |
10373 |
64 |
0 |
0 |
T123 |
269908 |
742 |
0 |
0 |
T152 |
10110 |
59 |
0 |
0 |
T153 |
97538 |
981 |
0 |
0 |
T154 |
19002 |
25 |
0 |
0 |
T155 |
7072 |
48 |
0 |
0 |
T156 |
13570 |
71 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
T158 |
72514 |
498 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6057 |
0 |
0 |
T101 |
103057 |
789 |
0 |
0 |
T116 |
4535 |
10 |
0 |
0 |
T117 |
10373 |
115 |
0 |
0 |
T123 |
269908 |
597 |
0 |
0 |
T152 |
10110 |
53 |
0 |
0 |
T153 |
97538 |
790 |
0 |
0 |
T154 |
19002 |
26 |
0 |
0 |
T155 |
7072 |
7 |
0 |
0 |
T156 |
13570 |
43 |
0 |
0 |
T157 |
4091 |
6 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6112 |
0 |
0 |
T101 |
103057 |
706 |
0 |
0 |
T116 |
4535 |
46 |
0 |
0 |
T117 |
10373 |
126 |
0 |
0 |
T123 |
269908 |
673 |
0 |
0 |
T152 |
10110 |
124 |
0 |
0 |
T153 |
97538 |
522 |
0 |
0 |
T154 |
19002 |
34 |
0 |
0 |
T155 |
7072 |
5 |
0 |
0 |
T156 |
13570 |
11 |
0 |
0 |
T157 |
4091 |
6 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6371 |
0 |
0 |
T101 |
103057 |
565 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
47 |
0 |
0 |
T123 |
269908 |
682 |
0 |
0 |
T152 |
10110 |
109 |
0 |
0 |
T153 |
97538 |
891 |
0 |
0 |
T154 |
19002 |
27 |
0 |
0 |
T155 |
7072 |
55 |
0 |
0 |
T156 |
13570 |
53 |
0 |
0 |
T157 |
4091 |
51 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6123 |
0 |
0 |
T101 |
103057 |
786 |
0 |
0 |
T116 |
4535 |
59 |
0 |
0 |
T117 |
10373 |
101 |
0 |
0 |
T123 |
269908 |
626 |
0 |
0 |
T152 |
10110 |
64 |
0 |
0 |
T153 |
97538 |
631 |
0 |
0 |
T154 |
19002 |
59 |
0 |
0 |
T155 |
7072 |
8 |
0 |
0 |
T156 |
13570 |
7 |
0 |
0 |
T157 |
4091 |
50 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6260 |
0 |
0 |
T101 |
103057 |
734 |
0 |
0 |
T116 |
4535 |
33 |
0 |
0 |
T117 |
10373 |
144 |
0 |
0 |
T123 |
269908 |
678 |
0 |
0 |
T152 |
10110 |
14 |
0 |
0 |
T153 |
97538 |
762 |
0 |
0 |
T154 |
19002 |
53 |
0 |
0 |
T155 |
7072 |
59 |
0 |
0 |
T156 |
13570 |
53 |
0 |
0 |
T157 |
4091 |
6 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6184 |
0 |
0 |
T101 |
103057 |
973 |
0 |
0 |
T116 |
4535 |
41 |
0 |
0 |
T117 |
10373 |
107 |
0 |
0 |
T123 |
269908 |
591 |
0 |
0 |
T152 |
10110 |
19 |
0 |
0 |
T153 |
97538 |
687 |
0 |
0 |
T154 |
19002 |
41 |
0 |
0 |
T155 |
7072 |
61 |
0 |
0 |
T156 |
13570 |
30 |
0 |
0 |
T157 |
4091 |
37 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6340 |
0 |
0 |
T101 |
103057 |
975 |
0 |
0 |
T116 |
4535 |
40 |
0 |
0 |
T117 |
10373 |
111 |
0 |
0 |
T123 |
269908 |
615 |
0 |
0 |
T152 |
10110 |
75 |
0 |
0 |
T153 |
97538 |
548 |
0 |
0 |
T154 |
19002 |
23 |
0 |
0 |
T155 |
7072 |
48 |
0 |
0 |
T156 |
13570 |
36 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6160 |
0 |
0 |
T101 |
103057 |
848 |
0 |
0 |
T116 |
4535 |
30 |
0 |
0 |
T117 |
10373 |
17 |
0 |
0 |
T123 |
269908 |
703 |
0 |
0 |
T152 |
10110 |
8 |
0 |
0 |
T153 |
97538 |
739 |
0 |
0 |
T154 |
19002 |
55 |
0 |
0 |
T155 |
7072 |
90 |
0 |
0 |
T156 |
13570 |
22 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6366 |
0 |
0 |
T101 |
103057 |
1067 |
0 |
0 |
T116 |
4535 |
42 |
0 |
0 |
T117 |
10373 |
65 |
0 |
0 |
T123 |
269908 |
615 |
0 |
0 |
T152 |
10110 |
119 |
0 |
0 |
T153 |
97538 |
783 |
0 |
0 |
T154 |
19002 |
55 |
0 |
0 |
T155 |
7072 |
38 |
0 |
0 |
T156 |
13570 |
24 |
0 |
0 |
T157 |
4091 |
6 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6728 |
0 |
0 |
T101 |
103057 |
1219 |
0 |
0 |
T116 |
4535 |
57 |
0 |
0 |
T117 |
10373 |
50 |
0 |
0 |
T123 |
269908 |
754 |
0 |
0 |
T152 |
10110 |
69 |
0 |
0 |
T153 |
97538 |
772 |
0 |
0 |
T154 |
19002 |
69 |
0 |
0 |
T155 |
7072 |
74 |
0 |
0 |
T156 |
13570 |
47 |
0 |
0 |
T157 |
4091 |
67 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
6389 |
0 |
0 |
T101 |
103057 |
946 |
0 |
0 |
T116 |
4535 |
2 |
0 |
0 |
T117 |
10373 |
111 |
0 |
0 |
T123 |
269908 |
656 |
0 |
0 |
T152 |
10110 |
87 |
0 |
0 |
T153 |
97538 |
771 |
0 |
0 |
T154 |
19002 |
25 |
0 |
0 |
T155 |
7072 |
6 |
0 |
0 |
T156 |
13570 |
37 |
0 |
0 |
T157 |
4091 |
63 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2772 |
0 |
0 |
T101 |
103057 |
150 |
0 |
0 |
T117 |
10373 |
23 |
0 |
0 |
T123 |
269908 |
726 |
0 |
0 |
T152 |
10110 |
8 |
0 |
0 |
T153 |
97538 |
179 |
0 |
0 |
T154 |
19002 |
14 |
0 |
0 |
T155 |
7072 |
9 |
0 |
0 |
T156 |
13570 |
34 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
T158 |
72514 |
93 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2884 |
0 |
0 |
T101 |
103057 |
194 |
0 |
0 |
T116 |
4535 |
9 |
0 |
0 |
T117 |
10373 |
8 |
0 |
0 |
T123 |
269908 |
655 |
0 |
0 |
T152 |
10110 |
33 |
0 |
0 |
T153 |
97538 |
185 |
0 |
0 |
T154 |
19002 |
41 |
0 |
0 |
T155 |
7072 |
10 |
0 |
0 |
T156 |
13570 |
42 |
0 |
0 |
T157 |
4091 |
2 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2850 |
0 |
0 |
T101 |
103057 |
168 |
0 |
0 |
T116 |
4535 |
4 |
0 |
0 |
T117 |
10373 |
20 |
0 |
0 |
T123 |
269908 |
659 |
0 |
0 |
T152 |
10110 |
29 |
0 |
0 |
T153 |
97538 |
195 |
0 |
0 |
T154 |
19002 |
26 |
0 |
0 |
T155 |
7072 |
8 |
0 |
0 |
T156 |
13570 |
29 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2664 |
0 |
0 |
T101 |
103057 |
135 |
0 |
0 |
T116 |
4535 |
2 |
0 |
0 |
T117 |
10373 |
5 |
0 |
0 |
T123 |
269908 |
630 |
0 |
0 |
T152 |
10110 |
30 |
0 |
0 |
T153 |
97538 |
137 |
0 |
0 |
T154 |
19002 |
35 |
0 |
0 |
T155 |
7072 |
3 |
0 |
0 |
T156 |
13570 |
27 |
0 |
0 |
T157 |
4091 |
2 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
3452 |
0 |
0 |
T101 |
103057 |
359 |
0 |
0 |
T116 |
4535 |
1 |
0 |
0 |
T117 |
10373 |
34 |
0 |
0 |
T123 |
269908 |
661 |
0 |
0 |
T152 |
10110 |
29 |
0 |
0 |
T153 |
97538 |
274 |
0 |
0 |
T154 |
19002 |
36 |
0 |
0 |
T155 |
7072 |
19 |
0 |
0 |
T156 |
13570 |
44 |
0 |
0 |
T157 |
4091 |
12 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
5444 |
0 |
0 |
T29 |
897314 |
0 |
0 |
0 |
T52 |
0 |
18 |
0 |
0 |
T62 |
266750 |
23 |
0 |
0 |
T63 |
0 |
33 |
0 |
0 |
T87 |
387482 |
0 |
0 |
0 |
T94 |
433153 |
0 |
0 |
0 |
T142 |
16056 |
0 |
0 |
0 |
T159 |
0 |
22 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T161 |
0 |
55 |
0 |
0 |
T162 |
0 |
12 |
0 |
0 |
T163 |
0 |
13 |
0 |
0 |
T164 |
0 |
48 |
0 |
0 |
T165 |
0 |
51 |
0 |
0 |
T166 |
174646 |
0 |
0 |
0 |
T167 |
21662 |
0 |
0 |
0 |
T168 |
1292 |
0 |
0 |
0 |
T169 |
35866 |
0 |
0 |
0 |
T170 |
32429 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2832 |
0 |
0 |
T101 |
103057 |
143 |
0 |
0 |
T116 |
4535 |
13 |
0 |
0 |
T117 |
10373 |
6 |
0 |
0 |
T123 |
269908 |
692 |
0 |
0 |
T152 |
10110 |
11 |
0 |
0 |
T153 |
97538 |
131 |
0 |
0 |
T154 |
19002 |
22 |
0 |
0 |
T156 |
13570 |
27 |
0 |
0 |
T157 |
4091 |
5 |
0 |
0 |
T158 |
72514 |
123 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2753 |
0 |
0 |
T101 |
103057 |
165 |
0 |
0 |
T116 |
4535 |
13 |
0 |
0 |
T117 |
10373 |
17 |
0 |
0 |
T123 |
269908 |
651 |
0 |
0 |
T152 |
10110 |
25 |
0 |
0 |
T153 |
97538 |
144 |
0 |
0 |
T154 |
19002 |
19 |
0 |
0 |
T155 |
7072 |
14 |
0 |
0 |
T156 |
13570 |
29 |
0 |
0 |
T157 |
4091 |
9 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2508 |
0 |
0 |
T101 |
103057 |
133 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
19 |
0 |
0 |
T123 |
269908 |
675 |
0 |
0 |
T152 |
10110 |
1 |
0 |
0 |
T153 |
97538 |
127 |
0 |
0 |
T154 |
19002 |
16 |
0 |
0 |
T155 |
7072 |
13 |
0 |
0 |
T156 |
13570 |
31 |
0 |
0 |
T157 |
4091 |
4 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2618 |
0 |
0 |
T101 |
103057 |
94 |
0 |
0 |
T117 |
10373 |
12 |
0 |
0 |
T123 |
269908 |
667 |
0 |
0 |
T152 |
10110 |
7 |
0 |
0 |
T153 |
97538 |
75 |
0 |
0 |
T154 |
19002 |
45 |
0 |
0 |
T155 |
7072 |
11 |
0 |
0 |
T156 |
13570 |
61 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
T158 |
72514 |
83 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2560 |
0 |
0 |
T101 |
103057 |
137 |
0 |
0 |
T116 |
4535 |
2 |
0 |
0 |
T117 |
10373 |
12 |
0 |
0 |
T123 |
269908 |
699 |
0 |
0 |
T152 |
10110 |
12 |
0 |
0 |
T153 |
97538 |
139 |
0 |
0 |
T154 |
19002 |
52 |
0 |
0 |
T155 |
7072 |
11 |
0 |
0 |
T156 |
13570 |
59 |
0 |
0 |
T157 |
4091 |
2 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2602 |
0 |
0 |
T101 |
103057 |
135 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
15 |
0 |
0 |
T123 |
269908 |
597 |
0 |
0 |
T152 |
10110 |
15 |
0 |
0 |
T153 |
97538 |
118 |
0 |
0 |
T154 |
19002 |
18 |
0 |
0 |
T155 |
7072 |
12 |
0 |
0 |
T156 |
13570 |
59 |
0 |
0 |
T157 |
4091 |
1 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
3430 |
0 |
0 |
T101 |
103057 |
283 |
0 |
0 |
T116 |
4535 |
16 |
0 |
0 |
T117 |
10373 |
20 |
0 |
0 |
T123 |
269908 |
674 |
0 |
0 |
T152 |
10110 |
24 |
0 |
0 |
T153 |
97538 |
317 |
0 |
0 |
T154 |
19002 |
30 |
0 |
0 |
T155 |
7072 |
9 |
0 |
0 |
T156 |
13570 |
40 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2656 |
0 |
0 |
T101 |
103057 |
129 |
0 |
0 |
T117 |
10373 |
10 |
0 |
0 |
T123 |
269908 |
652 |
0 |
0 |
T152 |
10110 |
11 |
0 |
0 |
T153 |
97538 |
97 |
0 |
0 |
T154 |
19002 |
18 |
0 |
0 |
T155 |
7072 |
11 |
0 |
0 |
T156 |
13570 |
74 |
0 |
0 |
T157 |
4091 |
1 |
0 |
0 |
T158 |
72514 |
85 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
3732 |
0 |
0 |
T101 |
103057 |
370 |
0 |
0 |
T116 |
4535 |
4 |
0 |
0 |
T117 |
10373 |
32 |
0 |
0 |
T123 |
269908 |
644 |
0 |
0 |
T152 |
10110 |
41 |
0 |
0 |
T153 |
97538 |
390 |
0 |
0 |
T154 |
19002 |
48 |
0 |
0 |
T155 |
7072 |
29 |
0 |
0 |
T156 |
13570 |
33 |
0 |
0 |
T157 |
4091 |
30 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2903 |
0 |
0 |
T101 |
103057 |
161 |
0 |
0 |
T116 |
4535 |
3 |
0 |
0 |
T117 |
10373 |
19 |
0 |
0 |
T123 |
269908 |
685 |
0 |
0 |
T152 |
10110 |
19 |
0 |
0 |
T153 |
97538 |
145 |
0 |
0 |
T154 |
19002 |
60 |
0 |
0 |
T155 |
7072 |
8 |
0 |
0 |
T156 |
13570 |
65 |
0 |
0 |
T157 |
4091 |
3 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2586 |
0 |
0 |
T101 |
103057 |
133 |
0 |
0 |
T116 |
4535 |
3 |
0 |
0 |
T117 |
10373 |
2 |
0 |
0 |
T123 |
269908 |
660 |
0 |
0 |
T152 |
10110 |
13 |
0 |
0 |
T153 |
97538 |
104 |
0 |
0 |
T154 |
19002 |
57 |
0 |
0 |
T155 |
7072 |
1 |
0 |
0 |
T156 |
13570 |
24 |
0 |
0 |
T157 |
4091 |
1 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2664 |
0 |
0 |
T101 |
103057 |
106 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
7 |
0 |
0 |
T123 |
269908 |
681 |
0 |
0 |
T152 |
10110 |
20 |
0 |
0 |
T153 |
97538 |
134 |
0 |
0 |
T154 |
19002 |
29 |
0 |
0 |
T155 |
7072 |
10 |
0 |
0 |
T156 |
13570 |
34 |
0 |
0 |
T158 |
72514 |
52 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2615 |
0 |
0 |
T101 |
103057 |
128 |
0 |
0 |
T116 |
4535 |
5 |
0 |
0 |
T117 |
10373 |
7 |
0 |
0 |
T123 |
269908 |
711 |
0 |
0 |
T152 |
10110 |
19 |
0 |
0 |
T153 |
97538 |
124 |
0 |
0 |
T154 |
19002 |
51 |
0 |
0 |
T155 |
7072 |
13 |
0 |
0 |
T156 |
13570 |
36 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2545 |
0 |
0 |
T101 |
103057 |
134 |
0 |
0 |
T116 |
4535 |
9 |
0 |
0 |
T117 |
10373 |
11 |
0 |
0 |
T123 |
269908 |
622 |
0 |
0 |
T152 |
10110 |
14 |
0 |
0 |
T153 |
97538 |
104 |
0 |
0 |
T154 |
19002 |
39 |
0 |
0 |
T155 |
7072 |
10 |
0 |
0 |
T156 |
13570 |
47 |
0 |
0 |
T157 |
4091 |
7 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2597 |
0 |
0 |
T99 |
12913 |
9 |
0 |
0 |
T101 |
103057 |
104 |
0 |
0 |
T116 |
4535 |
9 |
0 |
0 |
T117 |
10373 |
22 |
0 |
0 |
T123 |
269908 |
654 |
0 |
0 |
T152 |
10110 |
5 |
0 |
0 |
T153 |
97538 |
147 |
0 |
0 |
T154 |
19002 |
69 |
0 |
0 |
T155 |
7072 |
9 |
0 |
0 |
T156 |
13570 |
27 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
359659899 |
2485 |
0 |
0 |
T101 |
103057 |
99 |
0 |
0 |
T117 |
10373 |
17 |
0 |
0 |
T123 |
269908 |
685 |
0 |
0 |
T152 |
10110 |
9 |
0 |
0 |
T153 |
97538 |
97 |
0 |
0 |
T154 |
19002 |
25 |
0 |
0 |
T155 |
7072 |
12 |
0 |
0 |
T156 |
13570 |
59 |
0 |
0 |
T157 |
4091 |
5 |
0 |
0 |
T158 |
72514 |
86 |
0 |
0 |