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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.93 98.35 94.20 98.61 89.36 97.14 95.81 98.07


Total test records in report: 1101
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T818 /workspace/coverage/default/42.spi_device_tpm_all.3797467419 May 21 12:31:27 PM PDT 24 May 21 12:31:54 PM PDT 24 497893367 ps
T819 /workspace/coverage/default/31.spi_device_tpm_sts_read.3635286723 May 21 12:31:10 PM PDT 24 May 21 12:31:35 PM PDT 24 42003202 ps
T262 /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1750070311 May 21 12:31:17 PM PDT 24 May 21 12:31:50 PM PDT 24 2008606244 ps
T820 /workspace/coverage/default/31.spi_device_tpm_rw.2230456737 May 21 12:31:02 PM PDT 24 May 21 12:31:32 PM PDT 24 1366947162 ps
T821 /workspace/coverage/default/34.spi_device_csb_read.2289924807 May 21 12:31:08 PM PDT 24 May 21 12:31:34 PM PDT 24 23011626 ps
T822 /workspace/coverage/default/42.spi_device_tpm_sts_read.1561050535 May 21 12:31:39 PM PDT 24 May 21 12:32:00 PM PDT 24 33068580 ps
T823 /workspace/coverage/default/16.spi_device_csb_read.1220917836 May 21 12:30:17 PM PDT 24 May 21 12:30:47 PM PDT 24 71784857 ps
T824 /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2909180107 May 21 12:30:04 PM PDT 24 May 21 12:30:39 PM PDT 24 621345143 ps
T255 /workspace/coverage/default/11.spi_device_stress_all.2368432310 May 21 12:30:04 PM PDT 24 May 21 12:35:55 PM PDT 24 256914066806 ps
T258 /workspace/coverage/default/41.spi_device_stress_all.3993176452 May 21 12:31:35 PM PDT 24 May 21 12:33:57 PM PDT 24 54892782588 ps
T825 /workspace/coverage/default/11.spi_device_cfg_cmd.1386546113 May 21 12:30:05 PM PDT 24 May 21 12:30:40 PM PDT 24 336620857 ps
T826 /workspace/coverage/default/46.spi_device_upload.1354154512 May 21 12:31:36 PM PDT 24 May 21 12:32:02 PM PDT 24 375368847 ps
T827 /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1635216554 May 21 12:31:02 PM PDT 24 May 21 12:31:36 PM PDT 24 9134646846 ps
T828 /workspace/coverage/default/5.spi_device_tpm_rw.3737801104 May 21 12:29:57 PM PDT 24 May 21 12:30:27 PM PDT 24 137886966 ps
T829 /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1131933063 May 21 12:31:23 PM PDT 24 May 21 12:31:56 PM PDT 24 9633365371 ps
T830 /workspace/coverage/default/34.spi_device_flash_all.277935357 May 21 12:31:11 PM PDT 24 May 21 12:32:52 PM PDT 24 39454247229 ps
T831 /workspace/coverage/default/21.spi_device_read_buffer_direct.20169790 May 21 12:30:34 PM PDT 24 May 21 12:31:08 PM PDT 24 2263880798 ps
T832 /workspace/coverage/default/35.spi_device_csb_read.3336994896 May 21 12:31:06 PM PDT 24 May 21 12:31:32 PM PDT 24 17048824 ps
T833 /workspace/coverage/default/23.spi_device_cfg_cmd.2692304093 May 21 12:30:38 PM PDT 24 May 21 12:31:40 PM PDT 24 36963435542 ps
T834 /workspace/coverage/default/18.spi_device_mem_parity.3039508004 May 21 12:30:28 PM PDT 24 May 21 12:30:57 PM PDT 24 16327249 ps
T835 /workspace/coverage/default/6.spi_device_mailbox.3063604439 May 21 12:29:50 PM PDT 24 May 21 12:30:35 PM PDT 24 1155673447 ps
T836 /workspace/coverage/default/23.spi_device_tpm_rw.452141153 May 21 12:30:42 PM PDT 24 May 21 12:31:15 PM PDT 24 794659782 ps
T837 /workspace/coverage/default/48.spi_device_flash_mode.3652446084 May 21 12:31:44 PM PDT 24 May 21 12:32:12 PM PDT 24 871622844 ps
T838 /workspace/coverage/default/49.spi_device_upload.2410672666 May 21 12:31:53 PM PDT 24 May 21 12:32:13 PM PDT 24 16805774125 ps
T839 /workspace/coverage/default/27.spi_device_flash_mode.198497970 May 21 12:30:52 PM PDT 24 May 21 12:31:44 PM PDT 24 5035345786 ps
T840 /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3558004403 May 21 12:31:18 PM PDT 24 May 21 12:31:44 PM PDT 24 94175195 ps
T841 /workspace/coverage/default/33.spi_device_csb_read.2977380754 May 21 12:31:01 PM PDT 24 May 21 12:31:28 PM PDT 24 23077156 ps
T842 /workspace/coverage/default/10.spi_device_tpm_rw.992205841 May 21 12:30:04 PM PDT 24 May 21 12:30:39 PM PDT 24 336313203 ps
T843 /workspace/coverage/default/41.spi_device_flash_mode.1151791265 May 21 12:31:41 PM PDT 24 May 21 12:32:28 PM PDT 24 8430335906 ps
T844 /workspace/coverage/default/47.spi_device_tpm_rw.2515954204 May 21 12:31:49 PM PDT 24 May 21 12:32:06 PM PDT 24 72819538 ps
T845 /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1639190133 May 21 12:29:45 PM PDT 24 May 21 12:30:25 PM PDT 24 2697059087 ps
T846 /workspace/coverage/default/48.spi_device_pass_cmd_filtering.472986334 May 21 12:31:47 PM PDT 24 May 21 12:32:10 PM PDT 24 2462816585 ps
T847 /workspace/coverage/default/1.spi_device_alert_test.4050193442 May 21 12:29:37 PM PDT 24 May 21 12:30:04 PM PDT 24 48075396 ps
T848 /workspace/coverage/default/26.spi_device_flash_and_tpm.519652888 May 21 12:30:51 PM PDT 24 May 21 12:31:47 PM PDT 24 1036283274 ps
T849 /workspace/coverage/default/37.spi_device_stress_all.976331057 May 21 12:31:28 PM PDT 24 May 21 12:31:52 PM PDT 24 219949211 ps
T850 /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.173597935 May 21 12:30:39 PM PDT 24 May 21 12:31:13 PM PDT 24 2344900800 ps
T237 /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.934373609 May 21 12:32:33 PM PDT 24 May 21 12:33:11 PM PDT 24 22852650044 ps
T851 /workspace/coverage/default/29.spi_device_flash_and_tpm.4031047037 May 21 12:30:51 PM PDT 24 May 21 12:31:41 PM PDT 24 3049980092 ps
T852 /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3600292407 May 21 12:30:48 PM PDT 24 May 21 12:31:17 PM PDT 24 212799412 ps
T853 /workspace/coverage/default/11.spi_device_alert_test.3508618057 May 21 12:30:09 PM PDT 24 May 21 12:30:39 PM PDT 24 11297641 ps
T854 /workspace/coverage/default/48.spi_device_flash_and_tpm.1265835516 May 21 12:31:46 PM PDT 24 May 21 12:32:39 PM PDT 24 5868936113 ps
T855 /workspace/coverage/default/14.spi_device_cfg_cmd.1616210741 May 21 12:30:19 PM PDT 24 May 21 12:30:52 PM PDT 24 84708612 ps
T856 /workspace/coverage/default/0.spi_device_flash_and_tpm.3322807561 May 21 12:29:40 PM PDT 24 May 21 12:30:50 PM PDT 24 8056695426 ps
T857 /workspace/coverage/default/14.spi_device_csb_read.1914924149 May 21 12:30:08 PM PDT 24 May 21 12:30:39 PM PDT 24 74151596 ps
T858 /workspace/coverage/default/21.spi_device_tpm_all.382419758 May 21 12:30:33 PM PDT 24 May 21 12:31:09 PM PDT 24 3871903127 ps
T859 /workspace/coverage/default/43.spi_device_flash_mode.362201115 May 21 12:31:38 PM PDT 24 May 21 12:32:10 PM PDT 24 967576910 ps
T860 /workspace/coverage/default/21.spi_device_tpm_sts_read.4253456021 May 21 12:30:32 PM PDT 24 May 21 12:31:03 PM PDT 24 307981125 ps
T252 /workspace/coverage/default/10.spi_device_flash_all.966282595 May 21 12:30:03 PM PDT 24 May 21 12:31:47 PM PDT 24 61738483937 ps
T861 /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3264252233 May 21 12:29:53 PM PDT 24 May 21 12:30:34 PM PDT 24 28026783421 ps
T862 /workspace/coverage/default/6.spi_device_tpm_rw.2895852270 May 21 12:29:50 PM PDT 24 May 21 12:30:28 PM PDT 24 785354103 ps
T863 /workspace/coverage/default/45.spi_device_read_buffer_direct.2372367553 May 21 12:31:40 PM PDT 24 May 21 12:32:19 PM PDT 24 8045929812 ps
T864 /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3420203282 May 21 12:30:20 PM PDT 24 May 21 12:31:51 PM PDT 24 19792626386 ps
T246 /workspace/coverage/default/1.spi_device_flash_all.3327829273 May 21 12:29:36 PM PDT 24 May 21 12:32:53 PM PDT 24 24377854389 ps
T865 /workspace/coverage/default/30.spi_device_tpm_sts_read.3172349847 May 21 12:30:50 PM PDT 24 May 21 12:31:17 PM PDT 24 18220825 ps
T866 /workspace/coverage/default/13.spi_device_tpm_rw.2860951308 May 21 12:30:09 PM PDT 24 May 21 12:30:40 PM PDT 24 43232858 ps
T867 /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1387035259 May 21 12:30:52 PM PDT 24 May 21 12:31:22 PM PDT 24 2665611663 ps
T868 /workspace/coverage/default/12.spi_device_mem_parity.3537523130 May 21 12:30:09 PM PDT 24 May 21 12:30:41 PM PDT 24 16763823 ps
T869 /workspace/coverage/default/11.spi_device_mailbox.1825325108 May 21 12:30:07 PM PDT 24 May 21 12:31:17 PM PDT 24 3511969257 ps
T248 /workspace/coverage/default/45.spi_device_flash_all.3483459295 May 21 12:32:53 PM PDT 24 May 21 12:35:22 PM PDT 24 11951159355 ps
T870 /workspace/coverage/default/17.spi_device_intercept.2661294131 May 21 12:30:25 PM PDT 24 May 21 12:30:58 PM PDT 24 446306828 ps
T871 /workspace/coverage/default/27.spi_device_tpm_all.3744838644 May 21 12:30:58 PM PDT 24 May 21 12:31:46 PM PDT 24 2141077887 ps
T872 /workspace/coverage/default/12.spi_device_tpm_all.1209299697 May 21 12:30:06 PM PDT 24 May 21 12:30:48 PM PDT 24 3485104338 ps
T873 /workspace/coverage/default/32.spi_device_read_buffer_direct.294744178 May 21 12:31:01 PM PDT 24 May 21 12:31:32 PM PDT 24 147213655 ps
T874 /workspace/coverage/default/14.spi_device_tpm_all.3337929958 May 21 12:30:09 PM PDT 24 May 21 12:30:45 PM PDT 24 1971462794 ps
T875 /workspace/coverage/default/12.spi_device_csb_read.1978582496 May 21 12:30:10 PM PDT 24 May 21 12:30:40 PM PDT 24 150382176 ps
T876 /workspace/coverage/default/28.spi_device_intercept.62913672 May 21 12:30:56 PM PDT 24 May 21 12:31:28 PM PDT 24 110994072 ps
T877 /workspace/coverage/default/30.spi_device_stress_all.384485108 May 21 12:31:00 PM PDT 24 May 21 12:32:51 PM PDT 24 4165999985 ps
T878 /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2658613735 May 21 12:30:31 PM PDT 24 May 21 12:31:03 PM PDT 24 31432036 ps
T253 /workspace/coverage/default/6.spi_device_stress_all.3537940048 May 21 12:29:50 PM PDT 24 May 21 12:34:15 PM PDT 24 39035425621 ps
T879 /workspace/coverage/default/29.spi_device_stress_all.632382884 May 21 12:31:07 PM PDT 24 May 21 12:34:07 PM PDT 24 54250050817 ps
T244 /workspace/coverage/default/27.spi_device_flash_and_tpm.3206294828 May 21 12:30:54 PM PDT 24 May 21 12:32:18 PM PDT 24 2738273119 ps
T880 /workspace/coverage/default/41.spi_device_flash_and_tpm.379241287 May 21 12:31:20 PM PDT 24 May 21 12:32:06 PM PDT 24 4164243149 ps
T881 /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.616794683 May 21 12:31:43 PM PDT 24 May 21 12:32:04 PM PDT 24 107741895 ps
T882 /workspace/coverage/default/12.spi_device_upload.656718467 May 21 12:30:13 PM PDT 24 May 21 12:30:51 PM PDT 24 1557113822 ps
T883 /workspace/coverage/default/35.spi_device_tpm_all.3609191354 May 21 12:31:12 PM PDT 24 May 21 12:31:56 PM PDT 24 11009901366 ps
T884 /workspace/coverage/default/40.spi_device_mailbox.398569643 May 21 12:31:18 PM PDT 24 May 21 12:31:49 PM PDT 24 459961417 ps
T885 /workspace/coverage/default/18.spi_device_tpm_all.3361014774 May 21 12:30:24 PM PDT 24 May 21 12:30:58 PM PDT 24 1397182509 ps
T886 /workspace/coverage/default/17.spi_device_mem_parity.2748479881 May 21 12:30:23 PM PDT 24 May 21 12:30:54 PM PDT 24 60845694 ps
T887 /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3713562640 May 21 12:32:47 PM PDT 24 May 21 12:34:12 PM PDT 24 9440511917 ps
T888 /workspace/coverage/default/47.spi_device_alert_test.1351874455 May 21 12:31:43 PM PDT 24 May 21 12:32:03 PM PDT 24 29849555 ps
T889 /workspace/coverage/default/36.spi_device_upload.3217670665 May 21 12:31:06 PM PDT 24 May 21 12:32:08 PM PDT 24 9483516818 ps
T139 /workspace/coverage/default/2.spi_device_stress_all.716126247 May 21 12:29:46 PM PDT 24 May 21 12:31:22 PM PDT 24 13756525474 ps
T890 /workspace/coverage/default/36.spi_device_tpm_rw.1337500703 May 21 12:31:30 PM PDT 24 May 21 12:31:53 PM PDT 24 11931826 ps
T891 /workspace/coverage/default/25.spi_device_mailbox.2324654366 May 21 12:30:47 PM PDT 24 May 21 12:31:19 PM PDT 24 287809935 ps
T892 /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2993669589 May 21 12:30:30 PM PDT 24 May 21 12:33:07 PM PDT 24 11535840907 ps
T893 /workspace/coverage/default/36.spi_device_mailbox.242918031 May 21 12:31:22 PM PDT 24 May 21 12:32:07 PM PDT 24 3926948294 ps
T894 /workspace/coverage/default/47.spi_device_tpm_all.1663937666 May 21 12:31:45 PM PDT 24 May 21 12:32:11 PM PDT 24 1008610792 ps
T895 /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1248518031 May 21 12:29:31 PM PDT 24 May 21 12:30:04 PM PDT 24 6216544208 ps
T896 /workspace/coverage/default/27.spi_device_mailbox.996886989 May 21 12:31:01 PM PDT 24 May 21 12:31:33 PM PDT 24 5306151613 ps
T897 /workspace/coverage/default/28.spi_device_alert_test.3597539337 May 21 12:30:57 PM PDT 24 May 21 12:31:25 PM PDT 24 30451049 ps
T898 /workspace/coverage/default/8.spi_device_tpm_sts_read.3067024317 May 21 12:29:57 PM PDT 24 May 21 12:30:27 PM PDT 24 30709371 ps
T899 /workspace/coverage/default/21.spi_device_flash_mode.2869026926 May 21 12:30:33 PM PDT 24 May 21 12:31:16 PM PDT 24 1287594079 ps
T900 /workspace/coverage/default/43.spi_device_csb_read.703682943 May 21 12:31:28 PM PDT 24 May 21 12:31:52 PM PDT 24 36664307 ps
T901 /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3536018599 May 21 12:29:59 PM PDT 24 May 21 12:30:35 PM PDT 24 8342454829 ps
T902 /workspace/coverage/default/48.spi_device_read_buffer_direct.112939511 May 21 12:31:46 PM PDT 24 May 21 12:32:18 PM PDT 24 1103905222 ps
T903 /workspace/coverage/default/25.spi_device_flash_and_tpm.964624144 May 21 12:30:47 PM PDT 24 May 21 12:31:32 PM PDT 24 1387816501 ps
T904 /workspace/coverage/default/11.spi_device_csb_read.3853743254 May 21 12:30:04 PM PDT 24 May 21 12:30:36 PM PDT 24 90488923 ps
T905 /workspace/coverage/default/4.spi_device_flash_all.3662886059 May 21 12:29:48 PM PDT 24 May 21 12:31:39 PM PDT 24 6692395332 ps
T906 /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2838023091 May 21 12:31:28 PM PDT 24 May 21 12:31:53 PM PDT 24 190687543 ps
T64 /workspace/coverage/default/0.spi_device_ram_cfg.3183249832 May 21 12:29:35 PM PDT 24 May 21 12:29:59 PM PDT 24 72700332 ps
T232 /workspace/coverage/default/12.spi_device_stress_all.3833236264 May 21 12:30:03 PM PDT 24 May 21 12:42:11 PM PDT 24 148174707297 ps
T907 /workspace/coverage/default/38.spi_device_csb_read.4231206552 May 21 12:31:51 PM PDT 24 May 21 12:32:06 PM PDT 24 21536124 ps
T908 /workspace/coverage/default/37.spi_device_read_buffer_direct.4269847474 May 21 12:31:12 PM PDT 24 May 21 12:31:42 PM PDT 24 218485075 ps
T909 /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3956457142 May 21 12:32:29 PM PDT 24 May 21 12:32:51 PM PDT 24 83608030454 ps
T910 /workspace/coverage/default/23.spi_device_alert_test.224233092 May 21 12:30:39 PM PDT 24 May 21 12:31:09 PM PDT 24 17287179 ps
T911 /workspace/coverage/default/2.spi_device_mem_parity.979069984 May 21 12:29:43 PM PDT 24 May 21 12:30:11 PM PDT 24 26569153 ps
T912 /workspace/coverage/default/20.spi_device_flash_all.1041120597 May 21 12:30:30 PM PDT 24 May 21 12:32:19 PM PDT 24 47069597783 ps
T254 /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1525522001 May 21 12:29:58 PM PDT 24 May 21 12:31:53 PM PDT 24 9128175945 ps
T913 /workspace/coverage/default/18.spi_device_intercept.2959602640 May 21 12:30:27 PM PDT 24 May 21 12:31:00 PM PDT 24 1159497694 ps
T914 /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.228558282 May 21 12:30:59 PM PDT 24 May 21 12:31:38 PM PDT 24 3790537107 ps
T915 /workspace/coverage/default/0.spi_device_tpm_sts_read.2645112271 May 21 12:29:28 PM PDT 24 May 21 12:29:46 PM PDT 24 15743687 ps
T916 /workspace/coverage/default/24.spi_device_mailbox.4173408828 May 21 12:30:59 PM PDT 24 May 21 12:31:29 PM PDT 24 90124431 ps
T242 /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2534943404 May 21 12:29:45 PM PDT 24 May 21 12:30:22 PM PDT 24 9149900466 ps
T917 /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1929679653 May 21 12:31:33 PM PDT 24 May 21 12:32:09 PM PDT 24 4627382116 ps
T918 /workspace/coverage/default/41.spi_device_read_buffer_direct.1779655923 May 21 12:31:33 PM PDT 24 May 21 12:32:00 PM PDT 24 976079729 ps
T919 /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3409057662 May 21 12:30:22 PM PDT 24 May 21 12:30:53 PM PDT 24 564367580 ps
T920 /workspace/coverage/default/19.spi_device_flash_mode.1984374306 May 21 12:30:30 PM PDT 24 May 21 12:31:12 PM PDT 24 912724993 ps
T921 /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4052775660 May 21 12:30:30 PM PDT 24 May 21 12:31:01 PM PDT 24 1750601953 ps
T922 /workspace/coverage/default/27.spi_device_upload.39385329 May 21 12:30:52 PM PDT 24 May 21 12:31:21 PM PDT 24 142919831 ps
T923 /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1658808130 May 21 12:29:45 PM PDT 24 May 21 12:30:19 PM PDT 24 4705276750 ps
T924 /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1697039751 May 21 12:29:47 PM PDT 24 May 21 12:32:49 PM PDT 24 16687053018 ps
T925 /workspace/coverage/default/22.spi_device_flash_all.2919774597 May 21 12:30:36 PM PDT 24 May 21 12:32:30 PM PDT 24 23632639828 ps
T926 /workspace/coverage/default/49.spi_device_flash_and_tpm.2077032298 May 21 12:31:49 PM PDT 24 May 21 12:33:22 PM PDT 24 12229535130 ps
T927 /workspace/coverage/default/20.spi_device_upload.388377771 May 21 12:30:30 PM PDT 24 May 21 12:31:04 PM PDT 24 377396661 ps
T928 /workspace/coverage/default/10.spi_device_intercept.2304703810 May 21 12:30:04 PM PDT 24 May 21 12:30:42 PM PDT 24 2744981624 ps
T929 /workspace/coverage/default/29.spi_device_read_buffer_direct.3048505989 May 21 12:30:59 PM PDT 24 May 21 12:31:37 PM PDT 24 4906948630 ps
T930 /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1527309408 May 21 12:30:29 PM PDT 24 May 21 12:30:58 PM PDT 24 12617103 ps
T931 /workspace/coverage/default/17.spi_device_tpm_all.2839787348 May 21 12:30:22 PM PDT 24 May 21 12:31:27 PM PDT 24 5278944016 ps
T932 /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2607503901 May 21 12:31:02 PM PDT 24 May 21 12:31:34 PM PDT 24 420997457 ps
T933 /workspace/coverage/default/25.spi_device_alert_test.2058434547 May 21 12:30:46 PM PDT 24 May 21 12:31:14 PM PDT 24 16822982 ps
T934 /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3243420351 May 21 12:31:24 PM PDT 24 May 21 12:31:49 PM PDT 24 343293636 ps
T225 /workspace/coverage/default/36.spi_device_flash_and_tpm.3552573541 May 21 12:31:05 PM PDT 24 May 21 12:41:56 PM PDT 24 262651712562 ps
T935 /workspace/coverage/default/29.spi_device_flash_all.612372775 May 21 12:30:58 PM PDT 24 May 21 12:35:54 PM PDT 24 183370481686 ps
T936 /workspace/coverage/default/44.spi_device_intercept.1142315874 May 21 12:31:25 PM PDT 24 May 21 12:31:52 PM PDT 24 457546340 ps
T937 /workspace/coverage/default/26.spi_device_alert_test.1440473703 May 21 12:30:51 PM PDT 24 May 21 12:31:18 PM PDT 24 15597650 ps
T938 /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3393152189 May 21 12:31:40 PM PDT 24 May 21 12:32:02 PM PDT 24 11520456540 ps
T939 /workspace/coverage/default/8.spi_device_tpm_rw.1504491451 May 21 12:29:57 PM PDT 24 May 21 12:30:27 PM PDT 24 259818974 ps
T940 /workspace/coverage/default/10.spi_device_cfg_cmd.2593366945 May 21 12:29:58 PM PDT 24 May 21 12:30:40 PM PDT 24 5121549671 ps
T226 /workspace/coverage/default/2.spi_device_flash_and_tpm.1153214369 May 21 12:29:48 PM PDT 24 May 21 12:35:24 PM PDT 24 34296631870 ps
T941 /workspace/coverage/default/21.spi_device_flash_and_tpm.2114808783 May 21 12:30:33 PM PDT 24 May 21 12:33:58 PM PDT 24 76452015631 ps
T942 /workspace/coverage/default/1.spi_device_intercept.2602331530 May 21 12:29:32 PM PDT 24 May 21 12:29:56 PM PDT 24 37316517 ps
T943 /workspace/coverage/default/29.spi_device_tpm_all.1630407832 May 21 12:30:57 PM PDT 24 May 21 12:31:30 PM PDT 24 3687738946 ps
T944 /workspace/coverage/default/43.spi_device_cfg_cmd.4043287399 May 21 12:31:28 PM PDT 24 May 21 12:31:53 PM PDT 24 597705185 ps
T945 /workspace/coverage/default/40.spi_device_intercept.2163447932 May 21 12:31:30 PM PDT 24 May 21 12:32:14 PM PDT 24 4235291254 ps
T946 /workspace/coverage/default/42.spi_device_flash_and_tpm.2095401052 May 21 12:31:25 PM PDT 24 May 21 12:32:12 PM PDT 24 2233383022 ps
T947 /workspace/coverage/default/42.spi_device_flash_mode.652536591 May 21 12:31:27 PM PDT 24 May 21 12:31:55 PM PDT 24 432059485 ps
T948 /workspace/coverage/default/1.spi_device_flash_and_tpm.2699268404 May 21 12:29:35 PM PDT 24 May 21 12:30:36 PM PDT 24 2258848322 ps
T949 /workspace/coverage/default/25.spi_device_upload.1580215761 May 21 12:30:52 PM PDT 24 May 21 12:31:24 PM PDT 24 1256883546 ps
T950 /workspace/coverage/default/18.spi_device_flash_mode.3057546699 May 21 12:30:25 PM PDT 24 May 21 12:31:01 PM PDT 24 468337134 ps
T951 /workspace/coverage/default/17.spi_device_upload.3671715910 May 21 12:30:22 PM PDT 24 May 21 12:31:03 PM PDT 24 2382378831 ps
T952 /workspace/coverage/default/46.spi_device_tpm_sts_read.2197087079 May 21 12:31:31 PM PDT 24 May 21 12:31:54 PM PDT 24 88918293 ps
T953 /workspace/coverage/default/32.spi_device_alert_test.1480910841 May 21 12:31:02 PM PDT 24 May 21 12:31:29 PM PDT 24 93679601 ps
T954 /workspace/coverage/default/40.spi_device_cfg_cmd.1055415840 May 21 12:31:18 PM PDT 24 May 21 12:31:47 PM PDT 24 418668020 ps
T955 /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.474739899 May 21 12:29:53 PM PDT 24 May 21 12:30:27 PM PDT 24 888508876 ps
T956 /workspace/coverage/default/36.spi_device_tpm_all.2242913935 May 21 12:31:09 PM PDT 24 May 21 12:32:00 PM PDT 24 11902516969 ps
T957 /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.259934513 May 21 12:31:39 PM PDT 24 May 21 12:32:16 PM PDT 24 4342962835 ps
T958 /workspace/coverage/default/18.spi_device_csb_read.3975900678 May 21 12:30:26 PM PDT 24 May 21 12:30:56 PM PDT 24 120627066 ps
T959 /workspace/coverage/default/47.spi_device_read_buffer_direct.3631455852 May 21 12:31:45 PM PDT 24 May 21 12:32:08 PM PDT 24 929323733 ps
T960 /workspace/coverage/default/32.spi_device_flash_mode.2178084889 May 21 12:30:58 PM PDT 24 May 21 12:31:41 PM PDT 24 2128644807 ps
T961 /workspace/coverage/default/21.spi_device_intercept.2391315859 May 21 12:30:29 PM PDT 24 May 21 12:31:11 PM PDT 24 1414019516 ps
T962 /workspace/coverage/default/15.spi_device_tpm_rw.89047808 May 21 12:30:15 PM PDT 24 May 21 12:30:46 PM PDT 24 12589501 ps
T963 /workspace/coverage/default/10.spi_device_tpm_all.704707137 May 21 12:30:03 PM PDT 24 May 21 12:30:55 PM PDT 24 1773107135 ps
T964 /workspace/coverage/default/14.spi_device_upload.2605707237 May 21 12:30:19 PM PDT 24 May 21 12:31:03 PM PDT 24 16549070092 ps
T965 /workspace/coverage/default/4.spi_device_flash_and_tpm.1251216054 May 21 12:29:47 PM PDT 24 May 21 12:31:08 PM PDT 24 22824998861 ps
T966 /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.304592434 May 21 12:30:39 PM PDT 24 May 21 12:31:12 PM PDT 24 419767324 ps
T967 /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2058298137 May 21 12:31:20 PM PDT 24 May 21 12:31:58 PM PDT 24 14652222940 ps
T968 /workspace/coverage/default/1.spi_device_tpm_all.3062619844 May 21 12:29:37 PM PDT 24 May 21 12:30:20 PM PDT 24 3666484515 ps
T969 /workspace/coverage/default/9.spi_device_tpm_all.427253884 May 21 12:30:03 PM PDT 24 May 21 12:30:33 PM PDT 24 16757952 ps
T970 /workspace/coverage/default/21.spi_device_alert_test.3919302661 May 21 12:30:40 PM PDT 24 May 21 12:31:11 PM PDT 24 15742878 ps
T971 /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.562095388 May 21 12:29:50 PM PDT 24 May 21 12:31:40 PM PDT 24 6656093845 ps
T972 /workspace/coverage/default/6.spi_device_read_buffer_direct.3536383958 May 21 12:29:52 PM PDT 24 May 21 12:30:29 PM PDT 24 2173046597 ps
T973 /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2399938940 May 21 12:29:45 PM PDT 24 May 21 12:30:16 PM PDT 24 1245422224 ps
T974 /workspace/coverage/default/14.spi_device_mailbox.1580200173 May 21 12:30:18 PM PDT 24 May 21 12:30:53 PM PDT 24 6510015212 ps
T975 /workspace/coverage/default/24.spi_device_flash_and_tpm.561991908 May 21 12:30:46 PM PDT 24 May 21 12:31:49 PM PDT 24 2161505046 ps
T976 /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2961730822 May 21 12:29:48 PM PDT 24 May 21 12:30:24 PM PDT 24 1487621091 ps
T977 /workspace/coverage/default/42.spi_device_stress_all.2516230573 May 21 12:31:28 PM PDT 24 May 21 12:31:51 PM PDT 24 54627070 ps
T978 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3462780371 May 21 12:25:45 PM PDT 24 May 21 12:26:06 PM PDT 24 11795619 ps
T140 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1537526303 May 21 12:25:34 PM PDT 24 May 21 12:25:55 PM PDT 24 48763896 ps
T116 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.279048956 May 21 12:25:38 PM PDT 24 May 21 12:26:01 PM PDT 24 45384105 ps
T979 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2030859167 May 21 12:25:33 PM PDT 24 May 21 12:25:52 PM PDT 24 16401497 ps
T82 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3162516466 May 21 12:25:24 PM PDT 24 May 21 12:25:32 PM PDT 24 23725430 ps
T96 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.389531134 May 21 12:25:28 PM PDT 24 May 21 12:26:09 PM PDT 24 306668060 ps
T97 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2722260753 May 21 12:25:51 PM PDT 24 May 21 12:26:13 PM PDT 24 49729690 ps
T98 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4003816221 May 21 12:26:12 PM PDT 24 May 21 12:26:49 PM PDT 24 57182881 ps
T117 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2767497522 May 21 12:25:31 PM PDT 24 May 21 12:25:48 PM PDT 24 207494544 ps
T83 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.514550816 May 21 12:25:38 PM PDT 24 May 21 12:26:01 PM PDT 24 45696793 ps
T99 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.391585809 May 21 12:25:39 PM PDT 24 May 21 12:26:03 PM PDT 24 269030952 ps
T118 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.896092332 May 21 12:25:33 PM PDT 24 May 21 12:25:52 PM PDT 24 100375185 ps
T102 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.148261437 May 21 12:25:53 PM PDT 24 May 21 12:26:16 PM PDT 24 40604455 ps
T105 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2071073438 May 21 12:25:36 PM PDT 24 May 21 12:26:01 PM PDT 24 797151868 ps
T980 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2197298898 May 21 12:25:28 PM PDT 24 May 21 12:25:39 PM PDT 24 28089333 ps
T113 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3918916588 May 21 12:25:36 PM PDT 24 May 21 12:25:59 PM PDT 24 379905708 ps
T119 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1179794281 May 21 12:25:40 PM PDT 24 May 21 12:26:03 PM PDT 24 38781252 ps
T981 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.854410078 May 21 12:25:45 PM PDT 24 May 21 12:26:06 PM PDT 24 14467853 ps
T114 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2763760170 May 21 12:25:37 PM PDT 24 May 21 12:26:01 PM PDT 24 56121054 ps
T100 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2139108065 May 21 12:25:25 PM PDT 24 May 21 12:25:49 PM PDT 24 307251257 ps
T982 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1393476483 May 21 12:25:32 PM PDT 24 May 21 12:25:49 PM PDT 24 11598668 ps
T983 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.514894751 May 21 12:25:49 PM PDT 24 May 21 12:26:10 PM PDT 24 16011005 ps
T984 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.54449294 May 21 12:25:46 PM PDT 24 May 21 12:26:08 PM PDT 24 23599396 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3526061877 May 21 12:25:34 PM PDT 24 May 21 12:26:32 PM PDT 24 17994026413 ps
T141 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2522545943 May 21 12:25:40 PM PDT 24 May 21 12:26:03 PM PDT 24 32192975 ps
T985 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3100853135 May 21 12:25:35 PM PDT 24 May 21 12:25:57 PM PDT 24 58543050 ps
T104 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1585483097 May 21 12:26:01 PM PDT 24 May 21 12:26:26 PM PDT 24 297573914 ps
T986 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2620021646 May 21 12:25:34 PM PDT 24 May 21 12:25:53 PM PDT 24 29766682 ps
T115 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2639298010 May 21 12:25:36 PM PDT 24 May 21 12:25:59 PM PDT 24 41184063 ps
T120 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1161704391 May 21 12:25:36 PM PDT 24 May 21 12:25:59 PM PDT 24 81064414 ps
T987 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.552973364 May 21 12:26:02 PM PDT 24 May 21 12:26:24 PM PDT 24 73845809 ps
T101 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3885128846 May 21 12:25:36 PM PDT 24 May 21 12:26:18 PM PDT 24 1030599134 ps
T988 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2829968528 May 21 12:26:11 PM PDT 24 May 21 12:26:44 PM PDT 24 81923145 ps
T152 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.909614527 May 21 12:25:33 PM PDT 24 May 21 12:25:54 PM PDT 24 109922105 ps
T989 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2995902128 May 21 12:25:37 PM PDT 24 May 21 12:26:03 PM PDT 24 13142630 ps
T990 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.263244881 May 21 12:25:37 PM PDT 24 May 21 12:26:02 PM PDT 24 149900417 ps
T991 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2876927476 May 21 12:25:46 PM PDT 24 May 21 12:26:08 PM PDT 24 18691061 ps
T121 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3940031540 May 21 12:25:23 PM PDT 24 May 21 12:25:48 PM PDT 24 302307152 ps
T274 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4093739220 May 21 12:25:26 PM PDT 24 May 21 12:25:41 PM PDT 24 287791412 ps
T992 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2432532637 May 21 12:25:38 PM PDT 24 May 21 12:25:59 PM PDT 24 105089515 ps
T122 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1245912207 May 21 12:25:44 PM PDT 24 May 21 12:26:06 PM PDT 24 22793941 ps
T993 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1075928361 May 21 12:25:36 PM PDT 24 May 21 12:26:01 PM PDT 24 234299789 ps
T994 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1640849364 May 21 12:25:28 PM PDT 24 May 21 12:25:40 PM PDT 24 14156711 ps
T153 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4029541092 May 21 12:25:36 PM PDT 24 May 21 12:26:17 PM PDT 24 975413673 ps
T995 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3429585220 May 21 12:26:03 PM PDT 24 May 21 12:26:29 PM PDT 24 206985277 ps
T154 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2026717886 May 21 12:25:57 PM PDT 24 May 21 12:26:21 PM PDT 24 301644871 ps
T996 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.567324535 May 21 12:25:41 PM PDT 24 May 21 12:26:03 PM PDT 24 11506293 ps
T997 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1445725179 May 21 12:26:02 PM PDT 24 May 21 12:26:28 PM PDT 24 120323266 ps
T272 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3408158672 May 21 12:25:28 PM PDT 24 May 21 12:25:57 PM PDT 24 320589136 ps
T998 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.440714355 May 21 12:25:43 PM PDT 24 May 21 12:26:04 PM PDT 24 37318941 ps
T999 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3459922393 May 21 12:25:35 PM PDT 24 May 21 12:25:57 PM PDT 24 56183051 ps
T1000 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1834788421 May 21 12:25:36 PM PDT 24 May 21 12:25:59 PM PDT 24 87196882 ps
T84 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2168134417 May 21 12:25:33 PM PDT 24 May 21 12:25:52 PM PDT 24 121020014 ps
T155 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2762069959 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 282956827 ps
T124 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.961198717 May 21 12:25:37 PM PDT 24 May 21 12:26:00 PM PDT 24 350367338 ps
T110 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3821882523 May 21 12:25:39 PM PDT 24 May 21 12:26:03 PM PDT 24 159035664 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3720554098 May 21 12:25:35 PM PDT 24 May 21 12:25:58 PM PDT 24 134100808 ps
T112 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3908834754 May 21 12:25:37 PM PDT 24 May 21 12:26:00 PM PDT 24 76433988 ps
T1001 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1666517314 May 21 12:25:24 PM PDT 24 May 21 12:25:33 PM PDT 24 149223855 ps
T156 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2396723168 May 21 12:26:14 PM PDT 24 May 21 12:26:55 PM PDT 24 467989444 ps
T125 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3313124045 May 21 12:25:26 PM PDT 24 May 21 12:25:37 PM PDT 24 367373363 ps
T1002 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2152402732 May 21 12:25:55 PM PDT 24 May 21 12:26:17 PM PDT 24 15131883 ps
T1003 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1564506945 May 21 12:25:34 PM PDT 24 May 21 12:25:55 PM PDT 24 164392544 ps
T1004 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.774725872 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 39669878 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3323841060 May 21 12:25:36 PM PDT 24 May 21 12:25:59 PM PDT 24 131585728 ps
T271 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1284980698 May 21 12:25:43 PM PDT 24 May 21 12:26:15 PM PDT 24 771923136 ps
T157 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2287861123 May 21 12:25:33 PM PDT 24 May 21 12:25:51 PM PDT 24 170563606 ps
T1005 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2765832074 May 21 12:26:04 PM PDT 24 May 21 12:26:30 PM PDT 24 85077005 ps
T106 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3794567140 May 21 12:25:28 PM PDT 24 May 21 12:25:43 PM PDT 24 193403273 ps
T1006 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2704367360 May 21 12:25:24 PM PDT 24 May 21 12:25:31 PM PDT 24 96405641 ps
T1007 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3223942377 May 21 12:26:17 PM PDT 24 May 21 12:27:01 PM PDT 24 46304479 ps
T1008 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.164397842 May 21 12:25:31 PM PDT 24 May 21 12:26:25 PM PDT 24 525867808 ps
T107 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2245713083 May 21 12:25:29 PM PDT 24 May 21 12:25:46 PM PDT 24 603897861 ps
T158 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3545091926 May 21 12:25:27 PM PDT 24 May 21 12:25:52 PM PDT 24 725168598 ps
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