Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.93 98.35 94.20 98.61 89.36 97.14 95.81 98.07


Total test records in report: 1101
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T1009 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2705885620 May 21 12:25:35 PM PDT 24 May 21 12:25:56 PM PDT 24 137472742 ps
T1010 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4006937275 May 21 12:25:24 PM PDT 24 May 21 12:25:32 PM PDT 24 199102826 ps
T1011 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3493378965 May 21 12:25:37 PM PDT 24 May 21 12:26:00 PM PDT 24 71748429 ps
T1012 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1885061833 May 21 12:26:14 PM PDT 24 May 21 12:26:55 PM PDT 24 504279024 ps
T1013 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2079182432 May 21 12:25:36 PM PDT 24 May 21 12:25:57 PM PDT 24 76185017 ps
T1014 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2475449894 May 21 12:25:36 PM PDT 24 May 21 12:25:57 PM PDT 24 20461024 ps
T1015 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1925813890 May 21 12:26:10 PM PDT 24 May 21 12:26:39 PM PDT 24 13843897 ps
T276 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1677817883 May 21 12:25:41 PM PDT 24 May 21 12:26:24 PM PDT 24 3367079622 ps
T1016 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3459808122 May 21 12:25:28 PM PDT 24 May 21 12:25:39 PM PDT 24 10344680 ps
T126 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2206475981 May 21 12:25:55 PM PDT 24 May 21 12:26:18 PM PDT 24 137603841 ps
T109 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2016874593 May 21 12:25:39 PM PDT 24 May 21 12:26:05 PM PDT 24 1474444443 ps
T1017 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1004412850 May 21 12:25:31 PM PDT 24 May 21 12:25:46 PM PDT 24 17626020 ps
T1018 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3002060358 May 21 12:26:16 PM PDT 24 May 21 12:26:58 PM PDT 24 118067051 ps
T1019 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1528068901 May 21 12:25:26 PM PDT 24 May 21 12:25:52 PM PDT 24 557323884 ps
T273 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2106236365 May 21 12:25:33 PM PDT 24 May 21 12:26:20 PM PDT 24 1101253974 ps
T1020 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3428465081 May 21 12:25:24 PM PDT 24 May 21 12:25:33 PM PDT 24 127750343 ps
T1021 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4260474971 May 21 12:25:51 PM PDT 24 May 21 12:26:12 PM PDT 24 47092898 ps
T1022 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1703467864 May 21 12:25:34 PM PDT 24 May 21 12:26:18 PM PDT 24 1807485144 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3223149208 May 21 12:25:26 PM PDT 24 May 21 12:25:35 PM PDT 24 59506088 ps
T1023 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.568414136 May 21 12:26:06 PM PDT 24 May 21 12:26:33 PM PDT 24 121720666 ps
T1024 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.276882516 May 21 12:26:08 PM PDT 24 May 21 12:26:35 PM PDT 24 24131345 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.496257541 May 21 12:25:39 PM PDT 24 May 21 12:26:08 PM PDT 24 282007475 ps
T1026 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4166992437 May 21 12:25:25 PM PDT 24 May 21 12:25:34 PM PDT 24 596814556 ps
T270 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1096838893 May 21 12:25:29 PM PDT 24 May 21 12:25:43 PM PDT 24 43130527 ps
T275 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2221889085 May 21 12:25:25 PM PDT 24 May 21 12:25:54 PM PDT 24 4151977307 ps
T1027 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2949947778 May 21 12:25:57 PM PDT 24 May 21 12:26:18 PM PDT 24 30741311 ps
T1028 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.870230412 May 21 12:25:37 PM PDT 24 May 21 12:26:31 PM PDT 24 538817852 ps
T1029 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1082754909 May 21 12:25:37 PM PDT 24 May 21 12:26:09 PM PDT 24 3269100887 ps
T1030 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1323164154 May 21 12:25:37 PM PDT 24 May 21 12:25:58 PM PDT 24 51863915 ps
T1031 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2586031789 May 21 12:25:46 PM PDT 24 May 21 12:26:08 PM PDT 24 44536940 ps
T1032 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.80375615 May 21 12:25:37 PM PDT 24 May 21 12:26:01 PM PDT 24 932023601 ps
T1033 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1923783711 May 21 12:25:27 PM PDT 24 May 21 12:25:38 PM PDT 24 101491413 ps
T1034 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3940815710 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 33235633 ps
T1035 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.923624197 May 21 12:25:36 PM PDT 24 May 21 12:25:59 PM PDT 24 41180984 ps
T1036 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2169179011 May 21 12:25:58 PM PDT 24 May 21 12:26:25 PM PDT 24 25166538 ps
T1037 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1029380579 May 21 12:25:30 PM PDT 24 May 21 12:25:46 PM PDT 24 56375648 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2233262013 May 21 12:25:29 PM PDT 24 May 21 12:25:42 PM PDT 24 47143278 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.502250803 May 21 12:25:33 PM PDT 24 May 21 12:25:51 PM PDT 24 11870326 ps
T1040 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.356299581 May 21 12:25:33 PM PDT 24 May 21 12:25:51 PM PDT 24 62786997 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3068717924 May 21 12:25:27 PM PDT 24 May 21 12:25:36 PM PDT 24 13807220 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.544566656 May 21 12:25:33 PM PDT 24 May 21 12:25:53 PM PDT 24 13416410 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3649525233 May 21 12:25:28 PM PDT 24 May 21 12:25:40 PM PDT 24 133493311 ps
T1044 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1121244594 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 64898808 ps
T85 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.838173405 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 266274453 ps
T1045 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1464783171 May 21 12:26:17 PM PDT 24 May 21 12:27:05 PM PDT 24 425210933 ps
T1046 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2041616422 May 21 12:25:31 PM PDT 24 May 21 12:25:47 PM PDT 24 1614714540 ps
T1047 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3998133618 May 21 12:25:49 PM PDT 24 May 21 12:26:11 PM PDT 24 24944090 ps
T1048 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1135208743 May 21 12:25:35 PM PDT 24 May 21 12:25:54 PM PDT 24 56690550 ps
T1049 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2755217316 May 21 12:26:13 PM PDT 24 May 21 12:26:50 PM PDT 24 39102858 ps
T1050 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3266323937 May 21 12:25:37 PM PDT 24 May 21 12:25:59 PM PDT 24 42533709 ps
T1051 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1224227409 May 21 12:26:27 PM PDT 24 May 21 12:27:20 PM PDT 24 17547445 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4258220405 May 21 12:26:01 PM PDT 24 May 21 12:26:25 PM PDT 24 200464208 ps
T1053 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3915390254 May 21 12:25:53 PM PDT 24 May 21 12:26:14 PM PDT 24 52893477 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1553929144 May 21 12:25:27 PM PDT 24 May 21 12:25:37 PM PDT 24 13729938 ps
T1055 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.550513280 May 21 12:25:35 PM PDT 24 May 21 12:25:56 PM PDT 24 116342881 ps
T1056 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2330106855 May 21 12:25:40 PM PDT 24 May 21 12:26:07 PM PDT 24 233439330 ps
T1057 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1909486432 May 21 12:25:36 PM PDT 24 May 21 12:26:00 PM PDT 24 658657557 ps
T1058 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2337055299 May 21 12:25:34 PM PDT 24 May 21 12:25:54 PM PDT 24 101813411 ps
T1059 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3641274958 May 21 12:25:40 PM PDT 24 May 21 12:26:04 PM PDT 24 93485672 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3384964822 May 21 12:25:29 PM PDT 24 May 21 12:25:50 PM PDT 24 1406242722 ps
T1061 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1189023457 May 21 12:25:53 PM PDT 24 May 21 12:26:14 PM PDT 24 14435509 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1373924276 May 21 12:25:37 PM PDT 24 May 21 12:26:14 PM PDT 24 3336963883 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2083301422 May 21 12:25:39 PM PDT 24 May 21 12:26:01 PM PDT 24 15033855 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2419640103 May 21 12:25:35 PM PDT 24 May 21 12:25:59 PM PDT 24 83296296 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.646718919 May 21 12:25:25 PM PDT 24 May 21 12:25:33 PM PDT 24 41763062 ps
T1066 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4176307511 May 21 12:25:27 PM PDT 24 May 21 12:25:49 PM PDT 24 218486710 ps
T1067 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1343871294 May 21 12:25:34 PM PDT 24 May 21 12:25:54 PM PDT 24 30512849 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4060421322 May 21 12:25:35 PM PDT 24 May 21 12:25:59 PM PDT 24 56333734 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.529861280 May 21 12:25:40 PM PDT 24 May 21 12:26:03 PM PDT 24 209578438 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.726079860 May 21 12:25:26 PM PDT 24 May 21 12:25:36 PM PDT 24 32376131 ps
T1071 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.948371808 May 21 12:25:42 PM PDT 24 May 21 12:26:04 PM PDT 24 14374405 ps
T1072 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.475940496 May 21 12:25:51 PM PDT 24 May 21 12:26:12 PM PDT 24 396018152 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1299176737 May 21 12:25:39 PM PDT 24 May 21 12:26:01 PM PDT 24 77430656 ps
T1074 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1933886535 May 21 12:26:18 PM PDT 24 May 21 12:27:09 PM PDT 24 986874082 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.84362248 May 21 12:25:34 PM PDT 24 May 21 12:26:00 PM PDT 24 104549309 ps
T1076 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1016232206 May 21 12:26:08 PM PDT 24 May 21 12:26:36 PM PDT 24 15956827 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2828590525 May 21 12:25:53 PM PDT 24 May 21 12:26:16 PM PDT 24 64138820 ps
T1078 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1287726146 May 21 12:25:40 PM PDT 24 May 21 12:26:02 PM PDT 24 109037735 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1576803792 May 21 12:25:30 PM PDT 24 May 21 12:25:45 PM PDT 24 55789029 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2071524674 May 21 12:25:37 PM PDT 24 May 21 12:26:03 PM PDT 24 439622488 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2177728782 May 21 12:25:26 PM PDT 24 May 21 12:25:35 PM PDT 24 11120529 ps
T1082 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2328488535 May 21 12:25:28 PM PDT 24 May 21 12:25:43 PM PDT 24 242106055 ps
T1083 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2980995114 May 21 12:25:35 PM PDT 24 May 21 12:25:57 PM PDT 24 195519554 ps
T1084 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.306179413 May 21 12:26:21 PM PDT 24 May 21 12:27:16 PM PDT 24 35080101 ps
T1085 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.845586545 May 21 12:25:39 PM PDT 24 May 21 12:26:01 PM PDT 24 18929840 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1389093255 May 21 12:25:38 PM PDT 24 May 21 12:26:04 PM PDT 24 873427152 ps
T1087 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3316856279 May 21 12:26:02 PM PDT 24 May 21 12:26:30 PM PDT 24 289302935 ps
T1088 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3282598970 May 21 12:25:28 PM PDT 24 May 21 12:25:43 PM PDT 24 490765711 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.939194965 May 21 12:25:28 PM PDT 24 May 21 12:25:53 PM PDT 24 225772113 ps
T1090 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2794624403 May 21 12:25:33 PM PDT 24 May 21 12:25:58 PM PDT 24 60192934 ps
T1091 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3568346249 May 21 12:25:50 PM PDT 24 May 21 12:26:11 PM PDT 24 42851848 ps
T1092 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4003801024 May 21 12:25:37 PM PDT 24 May 21 12:26:02 PM PDT 24 136852779 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3315901810 May 21 12:25:32 PM PDT 24 May 21 12:25:52 PM PDT 24 105130299 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2919757225 May 21 12:25:36 PM PDT 24 May 21 12:26:11 PM PDT 24 2272494369 ps
T1095 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4221199314 May 21 12:25:37 PM PDT 24 May 21 12:25:58 PM PDT 24 11862992 ps
T1096 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1890851708 May 21 12:25:38 PM PDT 24 May 21 12:26:05 PM PDT 24 121316817 ps
T1097 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2851877586 May 21 12:25:27 PM PDT 24 May 21 12:25:49 PM PDT 24 272839739 ps
T1098 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2668810687 May 21 12:26:12 PM PDT 24 May 21 12:26:47 PM PDT 24 98686566 ps
T1099 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3424975831 May 21 12:25:38 PM PDT 24 May 21 12:26:00 PM PDT 24 45274870 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2545745871 May 21 12:25:38 PM PDT 24 May 21 12:25:59 PM PDT 24 19893831 ps
T1101 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1874985382 May 21 12:25:57 PM PDT 24 May 21 12:26:19 PM PDT 24 88422708 ps

Test location /workspace/coverage/default/32.spi_device_intercept.2517515447
Short name T3
Test name
Test status
Simulation time 176195205 ps
CPU time 5.04 seconds
Started May 21 12:31:04 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 233548 kb
Host smart-8b46dffd-89dd-4056-b32b-40225dee15ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517515447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2517515447
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1388102905
Short name T13
Test name
Test status
Simulation time 35972754502 ps
CPU time 276.27 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:35:06 PM PDT 24
Peak memory 289076 kb
Host smart-9a564bb7-e739-43fd-8094-d01300b4e844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388102905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1388102905
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1664830848
Short name T62
Test name
Test status
Simulation time 54438436798 ps
CPU time 276.37 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:35:39 PM PDT 24
Peak memory 264588 kb
Host smart-34d58ef0-f217-4372-a80d-9af6d6f1baa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664830848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1664830848
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3414106499
Short name T51
Test name
Test status
Simulation time 56248624205 ps
CPU time 572.58 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:40:41 PM PDT 24
Peak memory 266136 kb
Host smart-3e69430a-8f22-4b00-bc28-2824d3e313ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414106499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3414106499
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3885128846
Short name T101
Test name
Test status
Simulation time 1030599134 ps
CPU time 22.25 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:26:18 PM PDT 24
Peak memory 215608 kb
Host smart-927f77fa-8eae-4f79-aa2e-ab218b26ae1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885128846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3885128846
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3936274590
Short name T21
Test name
Test status
Simulation time 12235391842 ps
CPU time 94.93 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 251340 kb
Host smart-f4fa25b8-c69c-4dcc-ab80-9642c23c8243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936274590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3936274590
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3183249832
Short name T64
Test name
Test status
Simulation time 72700332 ps
CPU time 0.76 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:29:59 PM PDT 24
Peak memory 216140 kb
Host smart-dc5e5147-6173-464f-89b8-f9f8870f9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183249832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3183249832
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1585483097
Short name T104
Test name
Test status
Simulation time 297573914 ps
CPU time 4.25 seconds
Started May 21 12:26:01 PM PDT 24
Finished May 21 12:26:26 PM PDT 24
Peak memory 215724 kb
Host smart-f97567a0-fd25-4ddb-8dd1-61759ac790bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585483097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1585483097
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4246604485
Short name T32
Test name
Test status
Simulation time 268554925289 ps
CPU time 584.79 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:40:33 PM PDT 24
Peak memory 254700 kb
Host smart-ef516148-e343-4d60-a72d-2053e40bf168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246604485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4246604485
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3737353040
Short name T184
Test name
Test status
Simulation time 136940990402 ps
CPU time 367.91 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:37:36 PM PDT 24
Peak memory 265700 kb
Host smart-ababf466-0fd2-4a7e-948f-e7949c7376cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737353040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3737353040
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3921819505
Short name T31
Test name
Test status
Simulation time 247445018591 ps
CPU time 623.89 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:41:44 PM PDT 24
Peak memory 257116 kb
Host smart-0967be46-e5a5-4b5e-bf1a-62aa53d1074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921819505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3921819505
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3907686013
Short name T4
Test name
Test status
Simulation time 13585983 ps
CPU time 0.71 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 204560 kb
Host smart-1d03c4c8-dca0-4893-8a8b-838f0ce3510a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907686013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3907686013
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4129842947
Short name T81
Test name
Test status
Simulation time 71780544444 ps
CPU time 659.6 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:43:01 PM PDT 24
Peak memory 254444 kb
Host smart-986bb2a1-6a89-494c-b7de-b385fac9a83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129842947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4129842947
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2672909209
Short name T128
Test name
Test status
Simulation time 23052459974 ps
CPU time 125.89 seconds
Started May 21 12:31:05 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 262888 kb
Host smart-a7ba4b0a-7ad8-4e41-9d5a-ded9dc949637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672909209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2672909209
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.271986182
Short name T142
Test name
Test status
Simulation time 669110282 ps
CPU time 5.06 seconds
Started May 21 12:30:16 PM PDT 24
Finished May 21 12:30:50 PM PDT 24
Peak memory 222872 kb
Host smart-31fefb48-30e6-4037-ab79-dfb0f68b35d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=271986182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.271986182
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.935113313
Short name T14
Test name
Test status
Simulation time 20456354503 ps
CPU time 98.65 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:32:52 PM PDT 24
Peak memory 265668 kb
Host smart-f77133f0-ee28-4dbd-ab4a-a566959d4935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935113313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.935113313
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3162516466
Short name T82
Test name
Test status
Simulation time 23725430 ps
CPU time 1.32 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:32 PM PDT 24
Peak memory 216516 kb
Host smart-5bdb40e1-182a-4971-9b93-cd5461b5b223
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162516466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3162516466
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1117361991
Short name T47
Test name
Test status
Simulation time 97081704886 ps
CPU time 411.74 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:37:40 PM PDT 24
Peak memory 250100 kb
Host smart-a18c2b92-42d5-4716-96ed-df35188c12da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117361991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1117361991
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.720231109
Short name T1
Test name
Test status
Simulation time 54817646 ps
CPU time 0.96 seconds
Started May 21 12:29:28 PM PDT 24
Finished May 21 12:29:46 PM PDT 24
Peak memory 216664 kb
Host smart-2bb40627-8b81-47a7-a148-f4113881b137
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720231109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.720231109
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3400251743
Short name T267
Test name
Test status
Simulation time 17741105508 ps
CPU time 116.48 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:32:34 PM PDT 24
Peak memory 249276 kb
Host smart-400deb9e-6c87-4a32-9b51-bf711b3c9afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400251743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3400251743
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1514183293
Short name T186
Test name
Test status
Simulation time 142925869847 ps
CPU time 226.73 seconds
Started May 21 12:30:35 PM PDT 24
Finished May 21 12:34:50 PM PDT 24
Peak memory 249156 kb
Host smart-141daba2-fe81-45c6-8ba2-8837faeda13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514183293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1514183293
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1360175386
Short name T66
Test name
Test status
Simulation time 116224597 ps
CPU time 1.1 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:01 PM PDT 24
Peak memory 235000 kb
Host smart-1923da2c-8d12-4c78-b7bf-eb09624c732b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360175386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1360175386
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3658803759
Short name T234
Test name
Test status
Simulation time 32348195155 ps
CPU time 345.63 seconds
Started May 21 12:31:52 PM PDT 24
Finished May 21 12:37:51 PM PDT 24
Peak memory 257512 kb
Host smart-f7c9c8c5-435c-416d-897a-1096f077c6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658803759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3658803759
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.425136613
Short name T34
Test name
Test status
Simulation time 12440666677 ps
CPU time 122.47 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:33:11 PM PDT 24
Peak memory 251648 kb
Host smart-69ab3acb-ff38-4e1a-8c08-e7d283cb6eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425136613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.425136613
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4107418801
Short name T227
Test name
Test status
Simulation time 51237649827 ps
CPU time 158.9 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:34:25 PM PDT 24
Peak memory 270576 kb
Host smart-a0b0955c-360b-4e32-8745-4c8eb300a648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107418801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4107418801
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.789167741
Short name T233
Test name
Test status
Simulation time 72873261468 ps
CPU time 337.82 seconds
Started May 21 12:30:14 PM PDT 24
Finished May 21 12:36:22 PM PDT 24
Peak memory 250924 kb
Host smart-9739fafe-0567-4508-a9d7-5c5e72bb59f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789167741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.789167741
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3614525386
Short name T137
Test name
Test status
Simulation time 83395029698 ps
CPU time 255 seconds
Started May 21 12:30:22 PM PDT 24
Finished May 21 12:35:07 PM PDT 24
Peak memory 262512 kb
Host smart-df7c2905-0540-4dbe-9393-a646361315d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614525386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3614525386
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2409123900
Short name T294
Test name
Test status
Simulation time 1174192323 ps
CPU time 8.32 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:41 PM PDT 24
Peak memory 232592 kb
Host smart-0d5f5a74-1ed0-4565-ac65-aa5f03ea30ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409123900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2409123900
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.221468966
Short name T50
Test name
Test status
Simulation time 396988884764 ps
CPU time 732.27 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:42:48 PM PDT 24
Peak memory 267460 kb
Host smart-534401b3-1e53-4f1e-8f7d-9457e9b9aa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221468966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.221468966
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.273668035
Short name T231
Test name
Test status
Simulation time 26633661117 ps
CPU time 195.26 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:33:36 PM PDT 24
Peak memory 252896 kb
Host smart-f3663129-c3f9-45d5-b67d-c03e816f164d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273668035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.273668035
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1096838893
Short name T270
Test name
Test status
Simulation time 43130527 ps
CPU time 2.42 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:43 PM PDT 24
Peak memory 215720 kb
Host smart-fccf663c-492f-4ef3-9fd4-30cbfc4f7787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096838893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
096838893
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2174569150
Short name T268
Test name
Test status
Simulation time 16869639948 ps
CPU time 140.81 seconds
Started May 21 12:30:14 PM PDT 24
Finished May 21 12:33:04 PM PDT 24
Peak memory 249416 kb
Host smart-0d35e271-cc77-4f5d-acba-137390a5ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174569150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2174569150
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.480416260
Short name T45
Test name
Test status
Simulation time 53034998735 ps
CPU time 102.55 seconds
Started May 21 12:30:49 PM PDT 24
Finished May 21 12:32:58 PM PDT 24
Peak memory 249356 kb
Host smart-94ff4db5-84b3-4f95-b693-6f356ba5df48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480416260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.480416260
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4029541092
Short name T153
Test name
Test status
Simulation time 975413673 ps
CPU time 20.21 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:26:17 PM PDT 24
Peak memory 215868 kb
Host smart-1ddd8289-4022-4774-bcd4-52906ce29cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029541092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4029541092
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.867130364
Short name T317
Test name
Test status
Simulation time 1927885801 ps
CPU time 26.02 seconds
Started May 21 12:29:33 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 232640 kb
Host smart-8fe70356-4d34-4de8-a8b8-abaaeb187a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867130364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.867130364
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2368432310
Short name T255
Test name
Test status
Simulation time 256914066806 ps
CPU time 319.92 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:35:55 PM PDT 24
Peak memory 273840 kb
Host smart-743bdf44-7132-4779-9593-cbc48048e6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368432310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2368432310
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3173578017
Short name T241
Test name
Test status
Simulation time 47284099355 ps
CPU time 233.17 seconds
Started May 21 12:30:13 PM PDT 24
Finished May 21 12:34:36 PM PDT 24
Peak memory 253072 kb
Host smart-f52dea96-e5a6-4159-b46e-9f50afdee395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173578017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3173578017
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.856464576
Short name T250
Test name
Test status
Simulation time 133950802857 ps
CPU time 459.84 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:38:26 PM PDT 24
Peak memory 254376 kb
Host smart-d552dd08-a6d5-4c28-9340-ba0cf5498025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856464576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.856464576
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.590715829
Short name T218
Test name
Test status
Simulation time 3374811571 ps
CPU time 93.4 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:32:33 PM PDT 24
Peak memory 270996 kb
Host smart-ee56af59-1acd-42a5-8295-012ce1eccb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590715829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.590715829
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4267793279
Short name T52
Test name
Test status
Simulation time 126369109357 ps
CPU time 605.7 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:41:22 PM PDT 24
Peak memory 257468 kb
Host smart-961a9bde-ae94-4f16-897d-dffe63a1df3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267793279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4267793279
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.22784692
Short name T256
Test name
Test status
Simulation time 25683204621 ps
CPU time 219.82 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:35:13 PM PDT 24
Peak memory 240664 kb
Host smart-5030e338-623b-485b-b105-f9c7ccf77219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22784692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.22784692
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1936698324
Short name T660
Test name
Test status
Simulation time 100433075 ps
CPU time 2.74 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 233988 kb
Host smart-a3349fa8-d136-448d-a3f6-8bba1875748c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936698324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1936698324
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3720554098
Short name T108
Test name
Test status
Simulation time 134100808 ps
CPU time 3.56 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:58 PM PDT 24
Peak memory 215824 kb
Host smart-9aaf79e0-723e-4c32-8809-323f19c55bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720554098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3720554098
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.389531134
Short name T96
Test name
Test status
Simulation time 306668060 ps
CPU time 17.89 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:26:09 PM PDT 24
Peak memory 215632 kb
Host smart-22b825bd-78cf-4353-bb03-8c13d7669be0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389531134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.389531134
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4066048451
Short name T261
Test name
Test status
Simulation time 2008401775 ps
CPU time 8.91 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:12 PM PDT 24
Peak memory 240616 kb
Host smart-d5717ffb-92bd-4c95-8b7b-3ea66b0f2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066048451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4066048451
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1440585251
Short name T322
Test name
Test status
Simulation time 4891444244 ps
CPU time 15.82 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:51 PM PDT 24
Peak memory 232772 kb
Host smart-4badaffc-3c29-49c9-8468-32d4848bbd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440585251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1440585251
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1153214369
Short name T226
Test name
Test status
Simulation time 34296631870 ps
CPU time 307.46 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:35:24 PM PDT 24
Peak memory 241112 kb
Host smart-38d98648-fc94-461b-b0bf-e1b73128c51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153214369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1153214369
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3319340191
Short name T207
Test name
Test status
Simulation time 11087220774 ps
CPU time 11.8 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 219776 kb
Host smart-45419298-7f69-45e1-b2a1-0711b5a024e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319340191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3319340191
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2659455710
Short name T171
Test name
Test status
Simulation time 128503396 ps
CPU time 2.47 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 232552 kb
Host smart-dbe560a2-618d-4e34-8e09-4ee4822c1347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659455710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2659455710
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1336350899
Short name T721
Test name
Test status
Simulation time 5912697925 ps
CPU time 65.28 seconds
Started May 21 12:31:03 PM PDT 24
Finished May 21 12:32:33 PM PDT 24
Peak memory 252356 kb
Host smart-eca658db-9775-464a-84a5-a45b362e8612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336350899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1336350899
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4000285823
Short name T306
Test name
Test status
Simulation time 1808180506 ps
CPU time 9.94 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:09 PM PDT 24
Peak memory 224712 kb
Host smart-d3279974-c6b0-4122-883c-622e29487b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000285823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4000285823
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3794567140
Short name T106
Test name
Test status
Simulation time 193403273 ps
CPU time 4.07 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:43 PM PDT 24
Peak memory 216772 kb
Host smart-05047670-5702-4de3-8c38-d5dd9c3ec8b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794567140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3794567140
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.838173405
Short name T85
Test name
Test status
Simulation time 266274453 ps
CPU time 1.31 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 216524 kb
Host smart-d66b50fb-dce7-476c-9b2f-ce36b08d4c91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838173405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.838173405
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4207757976
Short name T22
Test name
Test status
Simulation time 44402304308 ps
CPU time 130.3 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:32:59 PM PDT 24
Peak memory 255396 kb
Host smart-c859c396-fef2-4027-a5ae-4016b1eaa564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207757976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4207757976
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.84362248
Short name T1075
Test name
Test status
Simulation time 104549309 ps
CPU time 7.65 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:26:00 PM PDT 24
Peak memory 207260 kb
Host smart-105bde58-1800-4b73-8834-c45341e68a83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84362248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
aliasing.84362248
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.164397842
Short name T1008
Test name
Test status
Simulation time 525867808 ps
CPU time 33.4 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:26:25 PM PDT 24
Peak memory 207164 kb
Host smart-187316d7-6198-400b-96a3-6c30bd43ea93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164397842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.164397842
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.646718919
Short name T1065
Test name
Test status
Simulation time 41763062 ps
CPU time 0.94 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 207080 kb
Host smart-0c1cd233-35be-4666-8a94-605ac3e25363
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646718919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.646718919
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4060421322
Short name T1068
Test name
Test status
Simulation time 56333734 ps
CPU time 3.82 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 218600 kb
Host smart-dcb5393d-208d-4e80-8f9a-f51220300ab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060421322 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4060421322
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2762069959
Short name T155
Test name
Test status
Simulation time 282956827 ps
CPU time 1.85 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 206848 kb
Host smart-aa538f85-b5b8-4074-b9eb-9d6c5db3ee9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762069959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
762069959
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.544566656
Short name T1042
Test name
Test status
Simulation time 13416410 ps
CPU time 0.7 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 203632 kb
Host smart-cd5b94c2-51b9-4468-b967-e7be580175c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544566656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.544566656
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2705885620
Short name T1009
Test name
Test status
Simulation time 137472742 ps
CPU time 2.1 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:56 PM PDT 24
Peak memory 215576 kb
Host smart-64057be2-a0b4-48d9-b242-9132d5d8a9e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705885620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2705885620
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2177728782
Short name T1081
Test name
Test status
Simulation time 11120529 ps
CPU time 0.69 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:35 PM PDT 24
Peak memory 202936 kb
Host smart-c37ffddf-76d8-4828-8ad2-2d03788b580d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177728782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2177728782
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3315901810
Short name T1093
Test name
Test status
Simulation time 105130299 ps
CPU time 2.8 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 215604 kb
Host smart-9bd436c5-9cc1-4fca-a7d1-98dd10481c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315901810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3315901810
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2041616422
Short name T1046
Test name
Test status
Simulation time 1614714540 ps
CPU time 2.3 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 215728 kb
Host smart-6750017a-27a7-406b-a852-84d5ed54eed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041616422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
041616422
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2106236365
Short name T273
Test name
Test status
Simulation time 1101253974 ps
CPU time 24.92 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:26:20 PM PDT 24
Peak memory 216256 kb
Host smart-77819597-2572-4098-96e0-ea853121bf70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106236365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2106236365
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1373924276
Short name T1062
Test name
Test status
Simulation time 3336963883 ps
CPU time 16.46 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:14 PM PDT 24
Peak memory 215436 kb
Host smart-e985e363-7269-47dd-a355-f42b1f2f44dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373924276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1373924276
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.870230412
Short name T1028
Test name
Test status
Simulation time 538817852 ps
CPU time 33.96 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:31 PM PDT 24
Peak memory 207360 kb
Host smart-52338b67-e431-4c8e-9d22-f17ae11e0f38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870230412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.870230412
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3641274958
Short name T1059
Test name
Test status
Simulation time 93485672 ps
CPU time 2.66 seconds
Started May 21 12:25:40 PM PDT 24
Finished May 21 12:26:04 PM PDT 24
Peak memory 217028 kb
Host smart-ff608b07-55f1-42ef-b150-9b5ea2636bc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641274958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3641274958
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3223149208
Short name T127
Test name
Test status
Simulation time 59506088 ps
CPU time 1.95 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:35 PM PDT 24
Peak memory 215624 kb
Host smart-2d7996b4-599d-460d-ad59-afa8115022f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223149208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
223149208
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1393476483
Short name T982
Test name
Test status
Simulation time 11598668 ps
CPU time 0.71 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 204120 kb
Host smart-25454141-c5ab-4b48-babb-1f617b8be0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393476483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
393476483
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.896092332
Short name T118
Test name
Test status
Simulation time 100375185 ps
CPU time 1.75 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 215508 kb
Host smart-cd5bba66-f9d7-42a6-9da5-e2be7e3e2a5e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896092332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.896092332
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.502250803
Short name T1039
Test name
Test status
Simulation time 11870326 ps
CPU time 0.64 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 203612 kb
Host smart-ebc74f36-5b25-45c5-955d-2009872532f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502250803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.502250803
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2794624403
Short name T1090
Test name
Test status
Simulation time 60192934 ps
CPU time 3.53 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:58 PM PDT 24
Peak memory 215620 kb
Host smart-e610efe9-11c0-475e-8774-fb432c472aae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794624403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2794624403
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2245713083
Short name T107
Test name
Test status
Simulation time 603897861 ps
CPU time 4.65 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:46 PM PDT 24
Peak memory 216068 kb
Host smart-6121e031-7444-437f-ac00-eda75ccecd83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245713083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
245713083
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2919757225
Short name T1094
Test name
Test status
Simulation time 2272494369 ps
CPU time 14.45 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:26:11 PM PDT 24
Peak memory 216136 kb
Host smart-56743ae8-95b1-4c6c-aba3-e618de13cbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919757225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2919757225
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1564506945
Short name T1003
Test name
Test status
Simulation time 164392544 ps
CPU time 2.34 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:55 PM PDT 24
Peak memory 215972 kb
Host smart-1cfc2380-6d57-4a7a-ae1f-7da58bf942bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564506945 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1564506945
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3940815710
Short name T1034
Test name
Test status
Simulation time 33235633 ps
CPU time 1.94 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 215500 kb
Host smart-c33cadac-6de0-4827-ac6c-5dbbc15744e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940815710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3940815710
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2545745871
Short name T1100
Test name
Test status
Simulation time 19893831 ps
CPU time 0.69 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 203556 kb
Host smart-fa40b523-5bbb-40e4-b026-3a480794e04e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545745871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2545745871
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1666517314
Short name T1001
Test name
Test status
Simulation time 149223855 ps
CPU time 2.49 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 215556 kb
Host smart-1b9c091a-0188-44b0-b41a-6d271f1c120e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666517314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1666517314
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4003816221
Short name T98
Test name
Test status
Simulation time 57182881 ps
CPU time 3.65 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:49 PM PDT 24
Peak memory 217964 kb
Host smart-08d54f95-2a13-4528-ab08-146111b901be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003816221 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4003816221
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2287861123
Short name T157
Test name
Test status
Simulation time 170563606 ps
CPU time 1.38 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 207336 kb
Host smart-8b4fbc6a-48fc-4de3-a92f-22f68e226151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287861123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2287861123
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1553929144
Short name T1054
Test name
Test status
Simulation time 13729938 ps
CPU time 0.69 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:37 PM PDT 24
Peak memory 204132 kb
Host smart-fec6736f-b187-412d-8548-f289c0ec4895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553929144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1553929144
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3282598970
Short name T1088
Test name
Test status
Simulation time 490765711 ps
CPU time 3.9 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:43 PM PDT 24
Peak memory 215624 kb
Host smart-95ec1279-c988-49f7-b45c-315326eb3825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282598970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3282598970
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3998133618
Short name T1047
Test name
Test status
Simulation time 24944090 ps
CPU time 1.47 seconds
Started May 21 12:25:49 PM PDT 24
Finished May 21 12:26:11 PM PDT 24
Peak memory 215784 kb
Host smart-3ce3f941-11c3-4ea6-af1c-7ca1c1116237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998133618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3998133618
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2221889085
Short name T275
Test name
Test status
Simulation time 4151977307 ps
CPU time 21.14 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 216344 kb
Host smart-f6138733-7ae7-44bd-a99e-c2c24c377c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221889085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2221889085
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4258220405
Short name T1052
Test name
Test status
Simulation time 200464208 ps
CPU time 2.48 seconds
Started May 21 12:26:01 PM PDT 24
Finished May 21 12:26:25 PM PDT 24
Peak memory 216752 kb
Host smart-328fbe83-7e3a-4cd1-8b35-995d6cd0ad0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258220405 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4258220405
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.550513280
Short name T1055
Test name
Test status
Simulation time 116342881 ps
CPU time 1.15 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:56 PM PDT 24
Peak memory 215428 kb
Host smart-47ccaa05-a9ab-4847-967f-e873748427d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550513280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.550513280
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2995902128
Short name T989
Test name
Test status
Simulation time 13142630 ps
CPU time 0.77 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 203456 kb
Host smart-87e59ab6-1bc4-442e-973d-0dae7ede7caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995902128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2995902128
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4006937275
Short name T1010
Test name
Test status
Simulation time 199102826 ps
CPU time 1.64 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:32 PM PDT 24
Peak memory 207384 kb
Host smart-16ea14d4-fb2e-4cac-bfeb-adbfc0fad5f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006937275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4006937275
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2071073438
Short name T105
Test name
Test status
Simulation time 797151868 ps
CPU time 4.38 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 215956 kb
Host smart-5848eb3c-04b7-460f-92cf-f466eda8a647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071073438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2071073438
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4003801024
Short name T1092
Test name
Test status
Simulation time 136852779 ps
CPU time 3.69 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:02 PM PDT 24
Peak memory 218340 kb
Host smart-0286ab69-6e5f-4827-979b-84ed56a01499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003801024 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4003801024
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1161704391
Short name T120
Test name
Test status
Simulation time 81064414 ps
CPU time 1.75 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 215564 kb
Host smart-42961b9f-c30f-48dc-b6fa-e5bdae5599c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161704391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1161704391
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2475449894
Short name T1014
Test name
Test status
Simulation time 20461024 ps
CPU time 0.72 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:57 PM PDT 24
Peak memory 203856 kb
Host smart-97f561f4-ca58-4311-a116-5ce81d9e026f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475449894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2475449894
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3429585220
Short name T995
Test name
Test status
Simulation time 206985277 ps
CPU time 3.97 seconds
Started May 21 12:26:03 PM PDT 24
Finished May 21 12:26:29 PM PDT 24
Peak memory 215692 kb
Host smart-68a3793d-c4e4-485e-966f-087556fa766f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429585220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3429585220
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1909486432
Short name T1057
Test name
Test status
Simulation time 658657557 ps
CPU time 3.73 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:26:00 PM PDT 24
Peak memory 215696 kb
Host smart-50ef5d2c-6d1a-4956-bbd7-b638eba19e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909486432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1909486432
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3408158672
Short name T272
Test name
Test status
Simulation time 320589136 ps
CPU time 16.75 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:57 PM PDT 24
Peak memory 215636 kb
Host smart-cbe4f03b-496c-477c-b1f2-4500ff71d05b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408158672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3408158672
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.923624197
Short name T1035
Test name
Test status
Simulation time 41180984 ps
CPU time 2.72 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 218512 kb
Host smart-dd3042ec-b46d-4928-a707-18760969bf9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923624197 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.923624197
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2337055299
Short name T1058
Test name
Test status
Simulation time 101813411 ps
CPU time 1.89 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 215600 kb
Host smart-6a4eebf7-17ee-4490-8694-9768e93a000d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337055299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2337055299
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2079182432
Short name T1013
Test name
Test status
Simulation time 76185017 ps
CPU time 0.71 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:57 PM PDT 24
Peak memory 203804 kb
Host smart-c1ce843c-84b7-42a7-9829-60b433c702a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079182432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2079182432
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2828590525
Short name T1077
Test name
Test status
Simulation time 64138820 ps
CPU time 3.57 seconds
Started May 21 12:25:53 PM PDT 24
Finished May 21 12:26:16 PM PDT 24
Peak memory 216072 kb
Host smart-04142521-9082-42be-b737-351cf9dd3b2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828590525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2828590525
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1677817883
Short name T276
Test name
Test status
Simulation time 3367079622 ps
CPU time 21.28 seconds
Started May 21 12:25:41 PM PDT 24
Finished May 21 12:26:24 PM PDT 24
Peak memory 216520 kb
Host smart-29a8b3ae-32f7-4ff0-9b11-414593c056e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677817883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1677817883
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.80375615
Short name T1032
Test name
Test status
Simulation time 932023601 ps
CPU time 2.85 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 216592 kb
Host smart-5fcbeda7-449b-4a67-9f8c-31c85683b592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80375615 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.80375615
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.568414136
Short name T1023
Test name
Test status
Simulation time 121720666 ps
CPU time 1.91 seconds
Started May 21 12:26:06 PM PDT 24
Finished May 21 12:26:33 PM PDT 24
Peak memory 207392 kb
Host smart-07a11196-46ff-4bb0-b552-fa055eebaa86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568414136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.568414136
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3568346249
Short name T1091
Test name
Test status
Simulation time 42851848 ps
CPU time 0.68 seconds
Started May 21 12:25:50 PM PDT 24
Finished May 21 12:26:11 PM PDT 24
Peak memory 204136 kb
Host smart-6b08d175-d373-41c3-a9e6-1e742e2e15ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568346249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3568346249
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3100853135
Short name T985
Test name
Test status
Simulation time 58543050 ps
CPU time 3.53 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:57 PM PDT 24
Peak memory 215712 kb
Host smart-7869a9fc-2fde-49a2-b358-3cd0b6d5ddc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100853135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3100853135
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.391585809
Short name T99
Test name
Test status
Simulation time 269030952 ps
CPU time 3.14 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 215548 kb
Host smart-3b6e2e10-4f92-4494-982e-9572ae68a83a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391585809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.391585809
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1284980698
Short name T271
Test name
Test status
Simulation time 771923136 ps
CPU time 11.25 seconds
Started May 21 12:25:43 PM PDT 24
Finished May 21 12:26:15 PM PDT 24
Peak memory 215452 kb
Host smart-524b38e5-36c3-445a-860f-084a0e82d512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284980698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1284980698
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1885061833
Short name T1012
Test name
Test status
Simulation time 504279024 ps
CPU time 3.38 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:26:55 PM PDT 24
Peak memory 217380 kb
Host smart-5ac4c269-bccb-499a-b2d5-0e97503a943e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885061833 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1885061833
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.961198717
Short name T124
Test name
Test status
Simulation time 350367338 ps
CPU time 2.26 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:00 PM PDT 24
Peak memory 215440 kb
Host smart-4a951cc8-ae94-41bd-af84-49774357870a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961198717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.961198717
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1323164154
Short name T1030
Test name
Test status
Simulation time 51863915 ps
CPU time 0.7 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:58 PM PDT 24
Peak memory 203572 kb
Host smart-f5e689c1-93cc-4535-9de3-830f3bcf2565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323164154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1323164154
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1445725179
Short name T997
Test name
Test status
Simulation time 120323266 ps
CPU time 3.87 seconds
Started May 21 12:26:02 PM PDT 24
Finished May 21 12:26:28 PM PDT 24
Peak memory 215632 kb
Host smart-14f4f5fe-557a-471e-a8cb-a7a3f247aa22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445725179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1445725179
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.475940496
Short name T1072
Test name
Test status
Simulation time 396018152 ps
CPU time 1.38 seconds
Started May 21 12:25:51 PM PDT 24
Finished May 21 12:26:12 PM PDT 24
Peak memory 215728 kb
Host smart-475af7a8-9131-4d86-aefe-7abd3d5492fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475940496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.475940496
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.496257541
Short name T1025
Test name
Test status
Simulation time 282007475 ps
CPU time 7.76 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:08 PM PDT 24
Peak memory 215532 kb
Host smart-e7a7a3ce-b82f-41b0-b0d0-d630d8ae1b76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496257541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.496257541
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1834788421
Short name T1000
Test name
Test status
Simulation time 87196882 ps
CPU time 2.56 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 216688 kb
Host smart-15bd6889-d603-4411-b2ac-721fb1629bfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834788421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1834788421
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2765832074
Short name T1005
Test name
Test status
Simulation time 85077005 ps
CPU time 2.4 seconds
Started May 21 12:26:04 PM PDT 24
Finished May 21 12:26:30 PM PDT 24
Peak memory 207648 kb
Host smart-90aaf5e0-1d46-452e-9127-4cdeb7b86e66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765832074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2765832074
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1189023457
Short name T1061
Test name
Test status
Simulation time 14435509 ps
CPU time 0.7 seconds
Started May 21 12:25:53 PM PDT 24
Finished May 21 12:26:14 PM PDT 24
Peak memory 204140 kb
Host smart-29373177-b2f7-445f-9950-0abe749f09ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189023457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1189023457
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2396723168
Short name T156
Test name
Test status
Simulation time 467989444 ps
CPU time 2.96 seconds
Started May 21 12:26:14 PM PDT 24
Finished May 21 12:26:55 PM PDT 24
Peak memory 215652 kb
Host smart-5ef32a79-728f-4102-9f7d-154576bbc256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396723168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2396723168
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1933886535
Short name T1074
Test name
Test status
Simulation time 986874082 ps
CPU time 6.91 seconds
Started May 21 12:26:18 PM PDT 24
Finished May 21 12:27:09 PM PDT 24
Peak memory 215648 kb
Host smart-6c79c784-385c-4ecc-872a-45c09dca3e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933886535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1933886535
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1923783711
Short name T1033
Test name
Test status
Simulation time 101491413 ps
CPU time 1.71 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 216732 kb
Host smart-8992f041-0dd2-4397-abd3-69ca4fc47c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923783711 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1923783711
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1179794281
Short name T119
Test name
Test status
Simulation time 38781252 ps
CPU time 1.3 seconds
Started May 21 12:25:40 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 215612 kb
Host smart-a3892fbc-721f-455e-9ee6-a362f1ace258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179794281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1179794281
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3462780371
Short name T978
Test name
Test status
Simulation time 11795619 ps
CPU time 0.7 seconds
Started May 21 12:25:45 PM PDT 24
Finished May 21 12:26:06 PM PDT 24
Peak memory 203812 kb
Host smart-7d6fb235-2157-434b-b5c0-5eb7a818e266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462780371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3462780371
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1075928361
Short name T993
Test name
Test status
Simulation time 234299789 ps
CPU time 3.98 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 215640 kb
Host smart-017a7394-67f4-4f55-ba07-d7fd0e4a55cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075928361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1075928361
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.148261437
Short name T102
Test name
Test status
Simulation time 40604455 ps
CPU time 2.04 seconds
Started May 21 12:25:53 PM PDT 24
Finished May 21 12:26:16 PM PDT 24
Peak memory 215656 kb
Host smart-b2b722e0-9660-42bb-82a6-40a51400baf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148261437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.148261437
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1464783171
Short name T1045
Test name
Test status
Simulation time 425210933 ps
CPU time 5.93 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:05 PM PDT 24
Peak memory 216272 kb
Host smart-14560b83-e1c9-4b27-b6b4-b2d7888b867a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464783171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1464783171
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.306179413
Short name T1084
Test name
Test status
Simulation time 35080101 ps
CPU time 1.94 seconds
Started May 21 12:26:21 PM PDT 24
Finished May 21 12:27:16 PM PDT 24
Peak memory 215888 kb
Host smart-5a405e2c-f60e-4c07-93d8-514621fcddf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306179413 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.306179413
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2767497522
Short name T117
Test name
Test status
Simulation time 207494544 ps
CPU time 2.62 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:48 PM PDT 24
Peak memory 215632 kb
Host smart-214be98f-c80a-4a52-9040-4a73feb3ee4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767497522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2767497522
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2829968528
Short name T988
Test name
Test status
Simulation time 81923145 ps
CPU time 0.72 seconds
Started May 21 12:26:11 PM PDT 24
Finished May 21 12:26:44 PM PDT 24
Peak memory 204116 kb
Host smart-a527ad3a-0161-4634-8908-db0c4c5f11eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829968528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2829968528
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1029380579
Short name T1037
Test name
Test status
Simulation time 56375648 ps
CPU time 1.74 seconds
Started May 21 12:25:30 PM PDT 24
Finished May 21 12:25:46 PM PDT 24
Peak memory 215680 kb
Host smart-79828f5f-e7ed-4f54-8868-323f1178458f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029380579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1029380579
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2668810687
Short name T1098
Test name
Test status
Simulation time 98686566 ps
CPU time 1.32 seconds
Started May 21 12:26:12 PM PDT 24
Finished May 21 12:26:47 PM PDT 24
Peak memory 215912 kb
Host smart-7c3dfcf3-e9fa-414f-bf38-90f53d0ecb24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668810687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2668810687
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3316856279
Short name T1087
Test name
Test status
Simulation time 289302935 ps
CPU time 6.57 seconds
Started May 21 12:26:02 PM PDT 24
Finished May 21 12:26:30 PM PDT 24
Peak memory 215708 kb
Host smart-ac039311-cf0d-4e74-93c2-b5ae09ee715e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316856279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3316856279
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3940031540
Short name T121
Test name
Test status
Simulation time 302307152 ps
CPU time 20.74 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:48 PM PDT 24
Peak memory 215592 kb
Host smart-74de7cda-50a0-4dc3-9f0c-28910d495575
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940031540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3940031540
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1703467864
Short name T1022
Test name
Test status
Simulation time 1807485144 ps
CPU time 25.27 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:26:18 PM PDT 24
Peak memory 207240 kb
Host smart-d700cd79-d3ec-4937-92d5-4cab18676b33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703467864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1703467864
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3459922393
Short name T999
Test name
Test status
Simulation time 56183051 ps
CPU time 3.26 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:57 PM PDT 24
Peak memory 216984 kb
Host smart-c7074088-d335-4937-8862-6402d2cf8ee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459922393 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3459922393
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1299176737
Short name T1073
Test name
Test status
Simulation time 77430656 ps
CPU time 1.32 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 207236 kb
Host smart-0e9114b3-3b2d-46af-a18e-7f719d34f074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299176737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
299176737
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1576803792
Short name T1079
Test name
Test status
Simulation time 55789029 ps
CPU time 0.73 seconds
Started May 21 12:25:30 PM PDT 24
Finished May 21 12:25:45 PM PDT 24
Peak memory 203808 kb
Host smart-2a4f9f87-4a47-4f46-8f3e-e6e55c8dacd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576803792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
576803792
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2522545943
Short name T141
Test name
Test status
Simulation time 32192975 ps
CPU time 1.33 seconds
Started May 21 12:25:40 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 215972 kb
Host smart-630fbf2c-3673-43b6-8ddb-164d40d79c05
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522545943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2522545943
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3459808122
Short name T1016
Test name
Test status
Simulation time 10344680 ps
CPU time 0.64 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:39 PM PDT 24
Peak memory 203672 kb
Host smart-1757b90e-c4d8-47f4-a6b4-695128967205
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459808122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3459808122
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3428465081
Short name T1020
Test name
Test status
Simulation time 127750343 ps
CPU time 2.66 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 215928 kb
Host smart-f9d1585f-87c1-4d6f-8882-d27e55b1d25c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428465081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3428465081
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3545091926
Short name T158
Test name
Test status
Simulation time 725168598 ps
CPU time 16.41 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 216424 kb
Host smart-629f41d8-dbc8-493d-809e-8fcd82e0e2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545091926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3545091926
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2169179011
Short name T1036
Test name
Test status
Simulation time 25166538 ps
CPU time 0.72 seconds
Started May 21 12:25:58 PM PDT 24
Finished May 21 12:26:25 PM PDT 24
Peak memory 203912 kb
Host smart-dc6cdcfb-ab07-4499-a1ce-5f3dc65421a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169179011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2169179011
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1016232206
Short name T1076
Test name
Test status
Simulation time 15956827 ps
CPU time 0.74 seconds
Started May 21 12:26:08 PM PDT 24
Finished May 21 12:26:36 PM PDT 24
Peak memory 203856 kb
Host smart-103cbb2f-289f-4921-b413-e9497773bdd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016232206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1016232206
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.567324535
Short name T996
Test name
Test status
Simulation time 11506293 ps
CPU time 0.75 seconds
Started May 21 12:25:41 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 204140 kb
Host smart-9015d184-cf7f-41c1-9612-df100cb46e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567324535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.567324535
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1287726146
Short name T1078
Test name
Test status
Simulation time 109037735 ps
CPU time 0.72 seconds
Started May 21 12:25:40 PM PDT 24
Finished May 21 12:26:02 PM PDT 24
Peak memory 204084 kb
Host smart-7b89df8e-068c-40a1-ac45-70eb35192634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287726146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1287726146
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1224227409
Short name T1051
Test name
Test status
Simulation time 17547445 ps
CPU time 0.76 seconds
Started May 21 12:26:27 PM PDT 24
Finished May 21 12:27:20 PM PDT 24
Peak memory 203872 kb
Host smart-ee309a79-cff6-4bd6-9d0c-1718703c3b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224227409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1224227409
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1925813890
Short name T1015
Test name
Test status
Simulation time 13843897 ps
CPU time 0.72 seconds
Started May 21 12:26:10 PM PDT 24
Finished May 21 12:26:39 PM PDT 24
Peak memory 204088 kb
Host smart-19a592b2-73a6-4769-902e-fc0b37426e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925813890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1925813890
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2030859167
Short name T979
Test name
Test status
Simulation time 16401497 ps
CPU time 0.72 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 204116 kb
Host smart-9213afae-f298-43c8-9656-8dc37cbf752c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030859167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2030859167
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2949947778
Short name T1027
Test name
Test status
Simulation time 30741311 ps
CPU time 0.75 seconds
Started May 21 12:25:57 PM PDT 24
Finished May 21 12:26:18 PM PDT 24
Peak memory 204080 kb
Host smart-f47b1cdb-3e47-43c1-b82c-b629b5ece66d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949947778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2949947778
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3915390254
Short name T1053
Test name
Test status
Simulation time 52893477 ps
CPU time 0.67 seconds
Started May 21 12:25:53 PM PDT 24
Finished May 21 12:26:14 PM PDT 24
Peak memory 203800 kb
Host smart-20cc539f-441d-4bfd-96bc-9391b8963d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915390254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3915390254
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2876927476
Short name T991
Test name
Test status
Simulation time 18691061 ps
CPU time 0.74 seconds
Started May 21 12:25:46 PM PDT 24
Finished May 21 12:26:08 PM PDT 24
Peak memory 203856 kb
Host smart-2ee2397e-0800-46b3-b209-44a42ee4c553
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876927476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2876927476
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3384964822
Short name T1060
Test name
Test status
Simulation time 1406242722 ps
CPU time 8.5 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:50 PM PDT 24
Peak memory 207672 kb
Host smart-ae78c2a5-7b9e-40ea-8f71-e36cdcd2d17c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384964822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3384964822
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1082754909
Short name T1029
Test name
Test status
Simulation time 3269100887 ps
CPU time 11.8 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:09 PM PDT 24
Peak memory 207440 kb
Host smart-4de11c17-08d5-492d-9e1c-a00b63344124
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082754909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1082754909
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2168134417
Short name T84
Test name
Test status
Simulation time 121020014 ps
CPU time 1.33 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 216476 kb
Host smart-0fdd2095-4980-4230-829c-cef910fd59f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168134417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2168134417
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3821882523
Short name T110
Test name
Test status
Simulation time 159035664 ps
CPU time 2.8 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 216700 kb
Host smart-1d064738-7201-4a40-8011-7ad2b3a9b5ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821882523 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3821882523
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3649525233
Short name T1043
Test name
Test status
Simulation time 133493311 ps
CPU time 1.16 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:40 PM PDT 24
Peak memory 207188 kb
Host smart-6636f273-c9fa-43b7-b2a6-216566d331bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649525233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
649525233
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.774725872
Short name T1004
Test name
Test status
Simulation time 39669878 ps
CPU time 0.68 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 204052 kb
Host smart-6643c90b-2160-4d7a-9c85-808f64de6de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774725872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.774725872
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4166992437
Short name T1026
Test name
Test status
Simulation time 596814556 ps
CPU time 2.15 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:34 PM PDT 24
Peak memory 215608 kb
Host smart-74dab033-3980-4b3a-9c53-f00e2b024b8b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166992437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4166992437
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2620021646
Short name T986
Test name
Test status
Simulation time 29766682 ps
CPU time 0.64 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 203648 kb
Host smart-c323d9b4-6cdd-4a35-9f4e-b8c4d66d4970
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620021646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2620021646
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2704367360
Short name T1006
Test name
Test status
Simulation time 96405641 ps
CPU time 1.62 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:31 PM PDT 24
Peak memory 207344 kb
Host smart-b4592245-03f4-4710-a919-03168f858e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704367360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2704367360
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2419640103
Short name T1064
Test name
Test status
Simulation time 83296296 ps
CPU time 2.69 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 214940 kb
Host smart-2fb41370-f64a-4719-bc5a-128a29f4a0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419640103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
419640103
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1528068901
Short name T1019
Test name
Test status
Simulation time 557323884 ps
CPU time 18.68 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 215688 kb
Host smart-4e8b7b8b-71dd-464d-8410-051910755f58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528068901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1528068901
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1135208743
Short name T1048
Test name
Test status
Simulation time 56690550 ps
CPU time 0.75 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 203788 kb
Host smart-89c532eb-e591-4a9e-b585-5023a94ad8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135208743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1135208743
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3266323937
Short name T1050
Test name
Test status
Simulation time 42533709 ps
CPU time 0.7 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 203740 kb
Host smart-b5164cb4-79fd-4aeb-a434-e52ecb2f1dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266323937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3266323937
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3223942377
Short name T1007
Test name
Test status
Simulation time 46304479 ps
CPU time 0.73 seconds
Started May 21 12:26:17 PM PDT 24
Finished May 21 12:27:01 PM PDT 24
Peak memory 203876 kb
Host smart-34fe8c2c-c699-412e-93d4-fdb6764ef4cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223942377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3223942377
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1640849364
Short name T994
Test name
Test status
Simulation time 14156711 ps
CPU time 0.71 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:40 PM PDT 24
Peak memory 203844 kb
Host smart-71883032-aae3-4413-99cd-6fc57d8e200d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640849364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1640849364
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2586031789
Short name T1031
Test name
Test status
Simulation time 44536940 ps
CPU time 0.73 seconds
Started May 21 12:25:46 PM PDT 24
Finished May 21 12:26:08 PM PDT 24
Peak memory 204092 kb
Host smart-c7d66e36-eee3-4dfd-9625-1ac1b23006b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586031789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2586031789
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1004412850
Short name T1017
Test name
Test status
Simulation time 17626020 ps
CPU time 0.72 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:46 PM PDT 24
Peak memory 203828 kb
Host smart-6f0f48c2-98d6-40b2-ae37-470c7e1d58ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004412850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1004412850
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3002060358
Short name T1018
Test name
Test status
Simulation time 118067051 ps
CPU time 0.75 seconds
Started May 21 12:26:16 PM PDT 24
Finished May 21 12:26:58 PM PDT 24
Peak memory 203928 kb
Host smart-f9abb3f4-f045-421c-bacc-12705c730e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002060358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3002060358
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.845586545
Short name T1085
Test name
Test status
Simulation time 18929840 ps
CPU time 0.74 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 203804 kb
Host smart-01d6752c-e03f-4b52-8fb3-99f628fd3862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845586545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.845586545
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.440714355
Short name T998
Test name
Test status
Simulation time 37318941 ps
CPU time 0.67 seconds
Started May 21 12:25:43 PM PDT 24
Finished May 21 12:26:04 PM PDT 24
Peak memory 204144 kb
Host smart-fdcfd9db-991a-4174-878f-5fbe0cb804df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440714355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.440714355
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4221199314
Short name T1095
Test name
Test status
Simulation time 11862992 ps
CPU time 0.68 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:58 PM PDT 24
Peak memory 204048 kb
Host smart-ccf24c8f-6012-4657-8855-615d7d81626c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221199314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4221199314
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4176307511
Short name T1066
Test name
Test status
Simulation time 218486710 ps
CPU time 13.54 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 207268 kb
Host smart-df73126f-4e51-444d-bf87-decd63ebfc67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176307511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4176307511
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3526061877
Short name T123
Test name
Test status
Simulation time 17994026413 ps
CPU time 39.58 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:26:32 PM PDT 24
Peak memory 207480 kb
Host smart-10fcf2fa-3f95-4927-81fc-24a025b2130c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526061877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3526061877
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.514550816
Short name T83
Test name
Test status
Simulation time 45696793 ps
CPU time 1.28 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 207352 kb
Host smart-6b18d981-6b98-4f84-9bad-311f3a67ff6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514550816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.514550816
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2763760170
Short name T114
Test name
Test status
Simulation time 56121054 ps
CPU time 3.58 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 218200 kb
Host smart-d8f481c4-1f1c-486d-a50f-5f01bb96ccb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763760170 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2763760170
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2233262013
Short name T1038
Test name
Test status
Simulation time 47143278 ps
CPU time 1.4 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:42 PM PDT 24
Peak memory 207336 kb
Host smart-c9dda349-03fc-44e6-8e95-74cad98d4171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233262013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
233262013
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2083301422
Short name T1063
Test name
Test status
Simulation time 15033855 ps
CPU time 0.69 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 203688 kb
Host smart-14d8285e-35f1-4b74-9846-769f75588eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083301422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
083301422
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.529861280
Short name T1069
Test name
Test status
Simulation time 209578438 ps
CPU time 1.27 seconds
Started May 21 12:25:40 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 215584 kb
Host smart-eec1acff-f995-40ad-8585-22aeb033780a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529861280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.529861280
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3068717924
Short name T1041
Test name
Test status
Simulation time 13807220 ps
CPU time 0.64 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:36 PM PDT 24
Peak memory 203652 kb
Host smart-c93ce30e-9fd9-4f9e-a919-6978b20c14b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068717924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3068717924
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1389093255
Short name T1086
Test name
Test status
Simulation time 873427152 ps
CPU time 4.02 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:26:04 PM PDT 24
Peak memory 215612 kb
Host smart-947bc66e-74c1-43a1-8860-04e8ce2a7d62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389093255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1389093255
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3323841060
Short name T111
Test name
Test status
Simulation time 131585728 ps
CPU time 1.7 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 215668 kb
Host smart-28d46860-7366-4383-8b8c-b27140c1109b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323841060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
323841060
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4093739220
Short name T274
Test name
Test status
Simulation time 287791412 ps
CPU time 7.52 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:41 PM PDT 24
Peak memory 215920 kb
Host smart-63c49ac2-9e11-4c83-aff8-46bb237ec4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093739220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4093739220
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.854410078
Short name T981
Test name
Test status
Simulation time 14467853 ps
CPU time 0.74 seconds
Started May 21 12:25:45 PM PDT 24
Finished May 21 12:26:06 PM PDT 24
Peak memory 203828 kb
Host smart-cb0fc1dc-f0d8-4e53-84fb-5c5885107abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854410078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.854410078
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1343871294
Short name T1067
Test name
Test status
Simulation time 30512849 ps
CPU time 0.66 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 203748 kb
Host smart-6cf81e35-c0cd-41f5-93d9-72fbb20c8f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343871294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1343871294
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.948371808
Short name T1071
Test name
Test status
Simulation time 14374405 ps
CPU time 0.69 seconds
Started May 21 12:25:42 PM PDT 24
Finished May 21 12:26:04 PM PDT 24
Peak memory 204048 kb
Host smart-a18679f8-6817-4ab6-99f5-05bc7023a668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948371808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.948371808
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.356299581
Short name T1040
Test name
Test status
Simulation time 62786997 ps
CPU time 0.74 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 204060 kb
Host smart-ddc4575a-34c0-47f2-85e8-10bfa85f920e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356299581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.356299581
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.552973364
Short name T987
Test name
Test status
Simulation time 73845809 ps
CPU time 0.72 seconds
Started May 21 12:26:02 PM PDT 24
Finished May 21 12:26:24 PM PDT 24
Peak memory 203888 kb
Host smart-b4d3ef95-3821-49ee-bb7b-becc88bf8a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552973364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.552973364
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2755217316
Short name T1049
Test name
Test status
Simulation time 39102858 ps
CPU time 0.69 seconds
Started May 21 12:26:13 PM PDT 24
Finished May 21 12:26:50 PM PDT 24
Peak memory 204116 kb
Host smart-257b4636-fde1-41ce-b36f-2389cb86a34e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755217316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2755217316
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.54449294
Short name T984
Test name
Test status
Simulation time 23599396 ps
CPU time 0.72 seconds
Started May 21 12:25:46 PM PDT 24
Finished May 21 12:26:08 PM PDT 24
Peak memory 203880 kb
Host smart-c7a0da47-37e8-4652-9813-2c0ec5c4c8e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54449294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.54449294
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.276882516
Short name T1024
Test name
Test status
Simulation time 24131345 ps
CPU time 0.72 seconds
Started May 21 12:26:08 PM PDT 24
Finished May 21 12:26:35 PM PDT 24
Peak memory 204140 kb
Host smart-bfd7d02d-c61a-4219-b79d-5b66814c3b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276882516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.276882516
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1121244594
Short name T1044
Test name
Test status
Simulation time 64898808 ps
CPU time 0.73 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 204080 kb
Host smart-13a851af-29c7-4003-8526-ebb1d9de9045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121244594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1121244594
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.514894751
Short name T983
Test name
Test status
Simulation time 16011005 ps
CPU time 0.73 seconds
Started May 21 12:25:49 PM PDT 24
Finished May 21 12:26:10 PM PDT 24
Peak memory 203776 kb
Host smart-6aeaba08-094e-4404-88dd-a23cf820de35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514894751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.514894751
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.909614527
Short name T152
Test name
Test status
Simulation time 109922105 ps
CPU time 2.45 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 217036 kb
Host smart-2d18250c-9ccf-46cf-99d1-103e5077146c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909614527 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.909614527
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.279048956
Short name T116
Test name
Test status
Simulation time 45384105 ps
CPU time 1.39 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:26:01 PM PDT 24
Peak memory 207140 kb
Host smart-b502d0f8-8593-40e2-bcda-3815d3518c43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279048956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.279048956
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2432532637
Short name T992
Test name
Test status
Simulation time 105089515 ps
CPU time 0.74 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 203816 kb
Host smart-01ce01f0-7bbc-4451-ab04-20afcab6dd31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432532637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
432532637
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2980995114
Short name T1083
Test name
Test status
Simulation time 195519554 ps
CPU time 3.71 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:57 PM PDT 24
Peak memory 215648 kb
Host smart-ae331539-47a7-453d-9a3a-48d6b3967a64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980995114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2980995114
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2016874593
Short name T109
Test name
Test status
Simulation time 1474444443 ps
CPU time 4.54 seconds
Started May 21 12:25:39 PM PDT 24
Finished May 21 12:26:05 PM PDT 24
Peak memory 215728 kb
Host smart-35c60ff9-f513-4863-b9db-cd271fb52d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016874593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
016874593
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3918916588
Short name T113
Test name
Test status
Simulation time 379905708 ps
CPU time 2.59 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 217588 kb
Host smart-c12b9da6-7174-415d-bd39-39e17d385ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918916588 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3918916588
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.726079860
Short name T1070
Test name
Test status
Simulation time 32376131 ps
CPU time 1.84 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:36 PM PDT 24
Peak memory 207368 kb
Host smart-5b9d3c0c-6371-4b9a-b312-da8d78eb4183
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726079860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.726079860
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2197298898
Short name T980
Test name
Test status
Simulation time 28089333 ps
CPU time 0.73 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:39 PM PDT 24
Peak memory 203824 kb
Host smart-a42513f8-e5d4-4eea-bcf1-30e17707cca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197298898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
197298898
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1537526303
Short name T140
Test name
Test status
Simulation time 48763896 ps
CPU time 2.91 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:55 PM PDT 24
Peak memory 215636 kb
Host smart-60094101-85aa-4540-8469-b152207c9a77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537526303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1537526303
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2330106855
Short name T1056
Test name
Test status
Simulation time 233439330 ps
CPU time 5.08 seconds
Started May 21 12:25:40 PM PDT 24
Finished May 21 12:26:07 PM PDT 24
Peak memory 215632 kb
Host smart-dfdc89b1-854a-4c60-83da-be1c4030e48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330106855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
330106855
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2139108065
Short name T100
Test name
Test status
Simulation time 307251257 ps
CPU time 17.01 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 215664 kb
Host smart-ba8bc8b3-83fc-4d8d-9559-640b32881d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139108065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2139108065
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2639298010
Short name T115
Test name
Test status
Simulation time 41184063 ps
CPU time 2.47 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:59 PM PDT 24
Peak memory 216612 kb
Host smart-52835485-01a0-42df-a921-db4f0f11aca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639298010 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2639298010
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1245912207
Short name T122
Test name
Test status
Simulation time 22793941 ps
CPU time 1.25 seconds
Started May 21 12:25:44 PM PDT 24
Finished May 21 12:26:06 PM PDT 24
Peak memory 207328 kb
Host smart-757e2726-9510-4406-9f85-b94faeb46478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245912207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
245912207
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3424975831
Short name T1099
Test name
Test status
Simulation time 45274870 ps
CPU time 0.65 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:26:00 PM PDT 24
Peak memory 203456 kb
Host smart-0533bdaa-579a-4dca-aeab-eeb44ed49e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424975831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
424975831
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.263244881
Short name T990
Test name
Test status
Simulation time 149900417 ps
CPU time 3.68 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:02 PM PDT 24
Peak memory 215572 kb
Host smart-09d073ec-758e-48db-9f29-5586979fb4ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263244881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.263244881
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3493378965
Short name T1011
Test name
Test status
Simulation time 71748429 ps
CPU time 1.99 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:00 PM PDT 24
Peak memory 215740 kb
Host smart-373918d7-0b7b-40fe-a3a1-cf6605dfdf3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493378965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
493378965
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1890851708
Short name T1096
Test name
Test status
Simulation time 121316817 ps
CPU time 6.55 seconds
Started May 21 12:25:38 PM PDT 24
Finished May 21 12:26:05 PM PDT 24
Peak memory 215488 kb
Host smart-bfe6a831-dea4-45c1-8425-debf798349ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890851708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1890851708
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2328488535
Short name T1082
Test name
Test status
Simulation time 242106055 ps
CPU time 3.23 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:43 PM PDT 24
Peak memory 218388 kb
Host smart-634432e1-b77b-4116-8623-65e34cfce03e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328488535 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2328488535
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3313124045
Short name T125
Test name
Test status
Simulation time 367373363 ps
CPU time 2.44 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:37 PM PDT 24
Peak memory 215360 kb
Host smart-d21cd8c5-03e8-43ee-9b0c-5a6d0b956712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313124045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
313124045
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4260474971
Short name T1021
Test name
Test status
Simulation time 47092898 ps
CPU time 0.75 seconds
Started May 21 12:25:51 PM PDT 24
Finished May 21 12:26:12 PM PDT 24
Peak memory 204092 kb
Host smart-da974ec1-061c-4141-86b6-31e8f0f86fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260474971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
260474971
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2026717886
Short name T154
Test name
Test status
Simulation time 301644871 ps
CPU time 4.2 seconds
Started May 21 12:25:57 PM PDT 24
Finished May 21 12:26:21 PM PDT 24
Peak memory 215708 kb
Host smart-3de73b90-8cff-48db-aa97-ad51cb8139ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026717886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2026717886
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2722260753
Short name T97
Test name
Test status
Simulation time 49729690 ps
CPU time 1.64 seconds
Started May 21 12:25:51 PM PDT 24
Finished May 21 12:26:13 PM PDT 24
Peak memory 215840 kb
Host smart-2bce622d-558e-4598-a17e-75199ac18c85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722260753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
722260753
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2851877586
Short name T1097
Test name
Test status
Simulation time 272839739 ps
CPU time 11.88 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 215668 kb
Host smart-d14e438f-0d73-4924-b229-80ea5578292b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851877586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2851877586
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3908834754
Short name T112
Test name
Test status
Simulation time 76433988 ps
CPU time 2.55 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:00 PM PDT 24
Peak memory 216328 kb
Host smart-5121c440-5a45-4dcf-bfea-5b219c1f6db9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908834754 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3908834754
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2206475981
Short name T126
Test name
Test status
Simulation time 137603841 ps
CPU time 2.45 seconds
Started May 21 12:25:55 PM PDT 24
Finished May 21 12:26:18 PM PDT 24
Peak memory 207636 kb
Host smart-110fad9d-9ab4-4560-b67a-6cd8b25d2604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206475981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
206475981
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2152402732
Short name T1002
Test name
Test status
Simulation time 15131883 ps
CPU time 0.71 seconds
Started May 21 12:25:55 PM PDT 24
Finished May 21 12:26:17 PM PDT 24
Peak memory 204136 kb
Host smart-a56d999f-c42b-4bea-8a42-8cdfdc768371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152402732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
152402732
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.939194965
Short name T1089
Test name
Test status
Simulation time 225772113 ps
CPU time 1.7 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 215616 kb
Host smart-8b5bf429-86a9-4936-acb3-e4bf29383e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939194965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.939194965
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1874985382
Short name T1101
Test name
Test status
Simulation time 88422708 ps
CPU time 2.13 seconds
Started May 21 12:25:57 PM PDT 24
Finished May 21 12:26:19 PM PDT 24
Peak memory 215700 kb
Host smart-2f6b7161-699a-4a9e-9d68-7a03b6a35131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874985382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
874985382
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2071524674
Short name T1080
Test name
Test status
Simulation time 439622488 ps
CPU time 6.01 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:26:03 PM PDT 24
Peak memory 215536 kb
Host smart-8cd62e68-c944-449e-9e30-460d1ac59b06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071524674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2071524674
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.240668900
Short name T564
Test name
Test status
Simulation time 95294794 ps
CPU time 0.71 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:29:59 PM PDT 24
Peak memory 204652 kb
Host smart-87e7fa88-078d-418a-a4ed-9823efdb2cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240668900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.240668900
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2314396144
Short name T219
Test name
Test status
Simulation time 366941752 ps
CPU time 6.01 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:05 PM PDT 24
Peak memory 219440 kb
Host smart-b27e338f-6e11-4e96-aced-819bdd2abcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314396144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2314396144
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3622222973
Short name T463
Test name
Test status
Simulation time 71122802 ps
CPU time 0.76 seconds
Started May 21 12:29:29 PM PDT 24
Finished May 21 12:29:48 PM PDT 24
Peak memory 206696 kb
Host smart-ff7b48fe-9e4a-484c-97cb-698847b4d555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622222973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3622222973
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2095014961
Short name T200
Test name
Test status
Simulation time 2874895106 ps
CPU time 10.84 seconds
Started May 21 12:29:33 PM PDT 24
Finished May 21 12:30:07 PM PDT 24
Peak memory 234060 kb
Host smart-07db3855-1a8e-4a76-866f-bc35d760cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095014961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2095014961
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3322807561
Short name T856
Test name
Test status
Simulation time 8056695426 ps
CPU time 43.82 seconds
Started May 21 12:29:40 PM PDT 24
Finished May 21 12:30:50 PM PDT 24
Peak memory 238044 kb
Host smart-81c6efa2-2a21-4ef6-875a-6e42ce120785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322807561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3322807561
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2388030320
Short name T809
Test name
Test status
Simulation time 2826777677 ps
CPU time 27 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 219340 kb
Host smart-ec281b45-2ef6-4ad2-8930-eda893c877cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388030320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2388030320
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3098399764
Short name T729
Test name
Test status
Simulation time 5282896106 ps
CPU time 28.1 seconds
Started May 21 12:29:38 PM PDT 24
Finished May 21 12:30:33 PM PDT 24
Peak memory 231876 kb
Host smart-5e051677-06fa-48c8-aee9-4c8c0ddbe25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098399764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3098399764
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1248518031
Short name T895
Test name
Test status
Simulation time 6216544208 ps
CPU time 12.32 seconds
Started May 21 12:29:31 PM PDT 24
Finished May 21 12:30:04 PM PDT 24
Peak memory 224536 kb
Host smart-9de31979-7360-4920-b8ca-5f9b7a0bfa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248518031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1248518031
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3750174292
Short name T618
Test name
Test status
Simulation time 337104695 ps
CPU time 5.15 seconds
Started May 21 12:29:32 PM PDT 24
Finished May 21 12:29:59 PM PDT 24
Peak memory 233724 kb
Host smart-46e8b0de-437d-41bb-9c72-58e8d245bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750174292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3750174292
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3873648117
Short name T600
Test name
Test status
Simulation time 1888215942 ps
CPU time 13.75 seconds
Started May 21 12:29:41 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 218632 kb
Host smart-344ba191-a47b-44df-af1d-76052887eeb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873648117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3873648117
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1809427929
Short name T750
Test name
Test status
Simulation time 16118027643 ps
CPU time 43.39 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 234220 kb
Host smart-82dc9ebb-2473-430a-b8be-dde7e456b6c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809427929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1809427929
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1296536625
Short name T452
Test name
Test status
Simulation time 19819758149 ps
CPU time 33.69 seconds
Started May 21 12:29:31 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 216396 kb
Host smart-15548631-8cb5-4562-a0fe-00ff1ad20f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296536625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1296536625
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2408823702
Short name T17
Test name
Test status
Simulation time 3981768023 ps
CPU time 12.24 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:12 PM PDT 24
Peak memory 216424 kb
Host smart-cbacc767-ede3-4691-b503-d6511c26676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408823702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2408823702
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4242479673
Short name T744
Test name
Test status
Simulation time 170080925 ps
CPU time 9.26 seconds
Started May 21 12:29:29 PM PDT 24
Finished May 21 12:29:57 PM PDT 24
Peak memory 216332 kb
Host smart-341e7498-6334-46aa-890f-3ff46928fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242479673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4242479673
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2645112271
Short name T915
Test name
Test status
Simulation time 15743687 ps
CPU time 0.67 seconds
Started May 21 12:29:28 PM PDT 24
Finished May 21 12:29:46 PM PDT 24
Peak memory 205740 kb
Host smart-83e52e39-8ac5-45ee-9e70-c3f89010028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645112271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2645112271
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.764836827
Short name T190
Test name
Test status
Simulation time 6445286689 ps
CPU time 8.15 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:12 PM PDT 24
Peak memory 233896 kb
Host smart-5da05b75-9c5d-425a-9751-1fe611edda33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764836827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.764836827
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4050193442
Short name T847
Test name
Test status
Simulation time 48075396 ps
CPU time 0.73 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:04 PM PDT 24
Peak memory 205292 kb
Host smart-9dd52929-d722-4496-bfc9-560d2eaeff87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050193442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
050193442
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3640884329
Short name T601
Test name
Test status
Simulation time 25302544296 ps
CPU time 14.33 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:17 PM PDT 24
Peak memory 233796 kb
Host smart-7fd993be-e853-488b-b3d8-956e86c37b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640884329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3640884329
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3634342331
Short name T665
Test name
Test status
Simulation time 15140367 ps
CPU time 0.78 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:29:59 PM PDT 24
Peak memory 206356 kb
Host smart-ecf35fdb-02b9-4d8d-8057-fddd449ca475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634342331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3634342331
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3327829273
Short name T246
Test name
Test status
Simulation time 24377854389 ps
CPU time 171.49 seconds
Started May 21 12:29:36 PM PDT 24
Finished May 21 12:32:53 PM PDT 24
Peak memory 237808 kb
Host smart-f350f346-cc73-4ad4-9979-014ef2d43c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327829273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3327829273
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2699268404
Short name T948
Test name
Test status
Simulation time 2258848322 ps
CPU time 38.16 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:36 PM PDT 24
Peak memory 236688 kb
Host smart-df7c3f2b-52cd-47e4-ae1b-4524fa4b34ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699268404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2699268404
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1056277015
Short name T328
Test name
Test status
Simulation time 5162878979 ps
CPU time 36.26 seconds
Started May 21 12:29:34 PM PDT 24
Finished May 21 12:30:33 PM PDT 24
Peak memory 236328 kb
Host smart-b86dcf41-be18-4fa9-bb05-fbcb765366d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056277015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1056277015
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3212196229
Short name T461
Test name
Test status
Simulation time 4663640444 ps
CPU time 4.26 seconds
Started May 21 12:29:33 PM PDT 24
Finished May 21 12:29:59 PM PDT 24
Peak memory 232796 kb
Host smart-c696e653-2114-422f-8950-8ab65b67aadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212196229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3212196229
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2602331530
Short name T942
Test name
Test status
Simulation time 37316517 ps
CPU time 2.41 seconds
Started May 21 12:29:32 PM PDT 24
Finished May 21 12:29:56 PM PDT 24
Peak memory 221272 kb
Host smart-78269b87-461d-4706-857b-3b6616daf128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602331530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2602331530
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2154838839
Short name T764
Test name
Test status
Simulation time 46747405206 ps
CPU time 37.04 seconds
Started May 21 12:29:34 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 235592 kb
Host smart-3a28cd84-87a8-4870-b0a6-3a17c7d92b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154838839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2154838839
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3878135652
Short name T517
Test name
Test status
Simulation time 39149765 ps
CPU time 1.04 seconds
Started May 21 12:29:38 PM PDT 24
Finished May 21 12:30:05 PM PDT 24
Peak memory 216676 kb
Host smart-e682a153-9fe5-4f7c-99a3-ab0717c8b5a5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878135652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3878135652
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1577757812
Short name T75
Test name
Test status
Simulation time 919091348 ps
CPU time 2.95 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:06 PM PDT 24
Peak memory 233568 kb
Host smart-d5db36d6-820c-4fe2-bed9-61bccb3c96cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577757812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1577757812
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2698026914
Short name T771
Test name
Test status
Simulation time 871790918 ps
CPU time 8.07 seconds
Started May 21 12:29:32 PM PDT 24
Finished May 21 12:30:02 PM PDT 24
Peak memory 218648 kb
Host smart-199291d9-7901-4572-abc0-45cda9e72746
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698026914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2698026914
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2779325967
Short name T68
Test name
Test status
Simulation time 618608354 ps
CPU time 1.07 seconds
Started May 21 12:29:33 PM PDT 24
Finished May 21 12:29:56 PM PDT 24
Peak memory 235040 kb
Host smart-4cb20a8d-2f72-4b84-80ec-2daf115686fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779325967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2779325967
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1207526919
Short name T240
Test name
Test status
Simulation time 9652929170 ps
CPU time 17.76 seconds
Started May 21 12:29:35 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 222352 kb
Host smart-e456261a-6fda-4872-b254-61a75dcc6dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207526919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1207526919
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3062619844
Short name T968
Test name
Test status
Simulation time 3666484515 ps
CPU time 16.82 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:20 PM PDT 24
Peak memory 216400 kb
Host smart-760c3e2f-0577-40e3-bb20-87aad5c9553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062619844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3062619844
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1517660837
Short name T741
Test name
Test status
Simulation time 957594319 ps
CPU time 5.02 seconds
Started May 21 12:29:33 PM PDT 24
Finished May 21 12:30:00 PM PDT 24
Peak memory 216228 kb
Host smart-c2971f0b-454a-4ac2-a9ef-8457b624c45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517660837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1517660837
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2091104591
Short name T567
Test name
Test status
Simulation time 1618733631 ps
CPU time 1.84 seconds
Started May 21 12:29:37 PM PDT 24
Finished May 21 12:30:05 PM PDT 24
Peak memory 216264 kb
Host smart-41614429-fec3-4af6-84ef-29cb04bf65da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091104591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2091104591
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2455792986
Short name T422
Test name
Test status
Simulation time 81933543 ps
CPU time 0.87 seconds
Started May 21 12:29:34 PM PDT 24
Finished May 21 12:29:58 PM PDT 24
Peak memory 205744 kb
Host smart-78142c58-0c0f-4744-b688-fd8dec3caecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455792986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2455792986
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1941757078
Short name T695
Test name
Test status
Simulation time 87395611 ps
CPU time 2.28 seconds
Started May 21 12:29:38 PM PDT 24
Finished May 21 12:30:06 PM PDT 24
Peak memory 215964 kb
Host smart-1222733f-9429-4ef5-9315-dd883b34a938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941757078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1941757078
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4175189499
Short name T478
Test name
Test status
Simulation time 13131163 ps
CPU time 0.74 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 204652 kb
Host smart-ee93915c-5ad7-4dfd-9210-429873a0fccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175189499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4175189499
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2593366945
Short name T940
Test name
Test status
Simulation time 5121549671 ps
CPU time 12.51 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 220212 kb
Host smart-81d7e6a4-0a89-4cda-830a-483dc6292175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593366945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2593366945
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.344926776
Short name T16
Test name
Test status
Simulation time 16950391 ps
CPU time 0.77 seconds
Started May 21 12:30:02 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 205616 kb
Host smart-0e67842c-9031-47b8-bcf6-86d365fef606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344926776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.344926776
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.966282595
Short name T252
Test name
Test status
Simulation time 61738483937 ps
CPU time 74.75 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 252896 kb
Host smart-b62c8206-be36-4506-996c-ca9cb05c58d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966282595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.966282595
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1062493527
Short name T523
Test name
Test status
Simulation time 57503496923 ps
CPU time 110.36 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:32:25 PM PDT 24
Peak memory 236620 kb
Host smart-dd4a2a8d-33c5-42bc-96fa-87a9d8b5c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062493527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1062493527
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2304703810
Short name T928
Test name
Test status
Simulation time 2744981624 ps
CPU time 8.87 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:42 PM PDT 24
Peak memory 217780 kb
Host smart-2d930b0e-e1c4-41b5-82c6-a0024b71157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304703810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2304703810
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1207653348
Short name T217
Test name
Test status
Simulation time 133236831 ps
CPU time 4.31 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 235100 kb
Host smart-9e2e1995-6136-4300-a40c-f90328a49f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207653348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1207653348
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3693206694
Short name T336
Test name
Test status
Simulation time 75088317 ps
CPU time 0.99 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:29 PM PDT 24
Peak memory 217976 kb
Host smart-0f715f70-0678-46ec-8c1c-6a4b7354c15b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693206694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3693206694
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.647342971
Short name T430
Test name
Test status
Simulation time 2986532920 ps
CPU time 5.15 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:33 PM PDT 24
Peak memory 233708 kb
Host smart-14b8e9cb-fc46-4405-b690-edaa13dc43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647342971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.647342971
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4058101562
Short name T689
Test name
Test status
Simulation time 3775762635 ps
CPU time 6.43 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:42 PM PDT 24
Peak memory 216380 kb
Host smart-bee1cc85-e706-4c0a-8fdb-fd0a9ef9b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058101562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4058101562
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1370518572
Short name T548
Test name
Test status
Simulation time 1943571086 ps
CPU time 6.73 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 218980 kb
Host smart-ed5822fe-4d13-4f1c-a52f-e74c1ffb9690
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1370518572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1370518572
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.704707137
Short name T963
Test name
Test status
Simulation time 1773107135 ps
CPU time 22.04 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:55 PM PDT 24
Peak memory 216316 kb
Host smart-c332de9b-e33c-4893-8840-f028827a546d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704707137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.704707137
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2304243589
Short name T692
Test name
Test status
Simulation time 320567797 ps
CPU time 3.22 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 216336 kb
Host smart-02921da7-2b3a-4256-aea9-bb53aea5fab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304243589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2304243589
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.992205841
Short name T842
Test name
Test status
Simulation time 336313203 ps
CPU time 4.1 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 216180 kb
Host smart-60713b2f-5aae-4918-9c51-bb743e3a8723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992205841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.992205841
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.641057141
Short name T416
Test name
Test status
Simulation time 84283382 ps
CPU time 0.84 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 205664 kb
Host smart-c6b03843-517a-47c4-a2f9-39f033ecd603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641057141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.641057141
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.517034918
Short name T593
Test name
Test status
Simulation time 67468185 ps
CPU time 3.02 seconds
Started May 21 12:30:00 PM PDT 24
Finished May 21 12:30:33 PM PDT 24
Peak memory 224752 kb
Host smart-622fe101-4e5d-4956-95cc-61e209a5e417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517034918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.517034918
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3508618057
Short name T853
Test name
Test status
Simulation time 11297641 ps
CPU time 0.69 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 205240 kb
Host smart-3430b8f3-8997-4d95-8317-508cd76ee782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508618057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3508618057
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1386546113
Short name T825
Test name
Test status
Simulation time 336620857 ps
CPU time 5.18 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 219392 kb
Host smart-43a9ce7d-e438-4ada-a4bd-0c0f8b0baf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386546113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1386546113
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3853743254
Short name T904
Test name
Test status
Simulation time 90488923 ps
CPU time 0.83 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:36 PM PDT 24
Peak memory 206244 kb
Host smart-450727a1-db2d-464b-95c5-1d29029e8649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853743254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3853743254
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3912990086
Short name T743
Test name
Test status
Simulation time 18709245270 ps
CPU time 173.15 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:33:31 PM PDT 24
Peak memory 254116 kb
Host smart-a3c9bcc6-4515-4feb-8815-652bfcefc3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912990086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3912990086
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4075475974
Short name T384
Test name
Test status
Simulation time 1364283105 ps
CPU time 4.22 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:41 PM PDT 24
Peak memory 224744 kb
Host smart-48d74ea9-f4fa-4d4f-89a2-b91ed035da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075475974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4075475974
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1282696224
Short name T730
Test name
Test status
Simulation time 519163727 ps
CPU time 6.23 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 232680 kb
Host smart-1a2b156d-bee1-4df6-914c-4855ad7d7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282696224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1282696224
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1825325108
Short name T869
Test name
Test status
Simulation time 3511969257 ps
CPU time 39.91 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 231436 kb
Host smart-e451b8f7-00f6-412a-abf2-2a896030362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825325108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1825325108
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2793095500
Short name T436
Test name
Test status
Simulation time 64761652 ps
CPU time 1.01 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:30:30 PM PDT 24
Peak memory 216640 kb
Host smart-5d4cc61d-bd67-4454-820d-49eee725ffe3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793095500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2793095500
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3519555868
Short name T263
Test name
Test status
Simulation time 706896651 ps
CPU time 7.9 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 240532 kb
Host smart-aeedfe36-332c-4795-9e5a-13539981a61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519555868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3519555868
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2573919150
Short name T701
Test name
Test status
Simulation time 13357270119 ps
CPU time 10.99 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 233740 kb
Host smart-ab9c4827-6e45-44d0-8bd0-b580ef0aab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573919150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2573919150
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2196544305
Short name T812
Test name
Test status
Simulation time 243265062 ps
CPU time 4.53 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 220184 kb
Host smart-e784f2a7-0c11-42e3-aa28-998f63fe4f86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2196544305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2196544305
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1749015693
Short name T56
Test name
Test status
Simulation time 409651573 ps
CPU time 3.08 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 216348 kb
Host smart-4f83d9bf-5154-4d5d-a239-dc5b6e1d0567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749015693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1749015693
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.39187563
Short name T344
Test name
Test status
Simulation time 2102693060 ps
CPU time 6.43 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:41 PM PDT 24
Peak memory 216212 kb
Host smart-be5e17a8-e8ad-42a4-a6a2-418a27863dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39187563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.39187563
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4116095510
Short name T539
Test name
Test status
Simulation time 107932485 ps
CPU time 1.2 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 216216 kb
Host smart-daaa943e-d9b5-487e-b071-4da57548aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116095510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4116095510
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.551577652
Short name T814
Test name
Test status
Simulation time 126141086 ps
CPU time 0.82 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 205744 kb
Host smart-73fc2b22-0d81-427c-bb4a-bf43f741e46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551577652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.551577652
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1086370639
Short name T299
Test name
Test status
Simulation time 7562111059 ps
CPU time 12.99 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 217796 kb
Host smart-678c7265-53c5-4044-941d-c1545cd1b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086370639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1086370639
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.793674519
Short name T528
Test name
Test status
Simulation time 37624857 ps
CPU time 0.72 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 205260 kb
Host smart-b7f28e3e-b950-4caa-9cfe-ee77164e1a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793674519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.793674519
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3767823181
Short name T390
Test name
Test status
Simulation time 712637223 ps
CPU time 5.38 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:42 PM PDT 24
Peak memory 232680 kb
Host smart-88888541-7f4c-43ec-935d-4ff6a1611c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767823181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3767823181
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1978582496
Short name T875
Test name
Test status
Simulation time 150382176 ps
CPU time 0.77 seconds
Started May 21 12:30:10 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 206348 kb
Host smart-e0153c58-f895-4e66-a2da-dd7858cb227a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978582496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1978582496
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3006236803
Short name T415
Test name
Test status
Simulation time 11513902 ps
CPU time 0.79 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 215860 kb
Host smart-0ec3ed9c-cba5-4157-84eb-d981d727c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006236803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3006236803
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2712268925
Short name T786
Test name
Test status
Simulation time 2463305809 ps
CPU time 42.83 seconds
Started May 21 12:30:06 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 238036 kb
Host smart-545b44bb-5415-4f8b-9524-22d355fba52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712268925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2712268925
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1810462896
Short name T321
Test name
Test status
Simulation time 217291935 ps
CPU time 4.71 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 232732 kb
Host smart-e2bc41f5-bfa2-41f5-9008-402a0f87c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810462896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1810462896
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2894817878
Short name T520
Test name
Test status
Simulation time 110989906 ps
CPU time 4.63 seconds
Started May 21 12:30:06 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 234604 kb
Host smart-855099e7-1d1d-4f6a-a02b-f2374313cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894817878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2894817878
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3148156292
Short name T308
Test name
Test status
Simulation time 134965938493 ps
CPU time 79.48 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 232368 kb
Host smart-5d4de615-a2a3-4153-82a1-7187590f39ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148156292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3148156292
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3537523130
Short name T868
Test name
Test status
Simulation time 16763823 ps
CPU time 1.04 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:41 PM PDT 24
Peak memory 216704 kb
Host smart-8097030c-5422-461b-bd80-78e1ffbbdf2f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537523130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3537523130
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4248575023
Short name T398
Test name
Test status
Simulation time 1872636336 ps
CPU time 4.14 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 233196 kb
Host smart-dc5d2c00-6a1e-4e0f-9b52-0f33dcafa581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248575023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4248575023
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.528470085
Short name T72
Test name
Test status
Simulation time 139905460 ps
CPU time 2.14 seconds
Started May 21 12:30:06 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 216112 kb
Host smart-b76cfc9c-6ff4-448a-9a83-839b75dba8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528470085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.528470085
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2014230537
Short name T805
Test name
Test status
Simulation time 495763133 ps
CPU time 6.7 seconds
Started May 21 12:30:11 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 220088 kb
Host smart-79e12ea4-2b8f-464c-8788-b0767417a812
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014230537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2014230537
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3833236264
Short name T232
Test name
Test status
Simulation time 148174707297 ps
CPU time 696.95 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:42:11 PM PDT 24
Peak memory 273280 kb
Host smart-d70d3013-910b-424e-9611-1194f780e784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833236264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3833236264
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1209299697
Short name T872
Test name
Test status
Simulation time 3485104338 ps
CPU time 12.66 seconds
Started May 21 12:30:06 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 216528 kb
Host smart-d381b3a7-a35e-4bb3-99c1-2ccc47be1e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209299697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1209299697
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1273294587
Short name T783
Test name
Test status
Simulation time 2942063299 ps
CPU time 11.65 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:44 PM PDT 24
Peak memory 216392 kb
Host smart-e38c0241-52ae-4e1d-b0a8-aba3ec001035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273294587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1273294587
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.474302533
Short name T532
Test name
Test status
Simulation time 211055358 ps
CPU time 2.47 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:38 PM PDT 24
Peak memory 216240 kb
Host smart-5c9d41ea-6513-4eeb-a3d7-5c3d5aa944b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474302533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.474302533
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.137943536
Short name T394
Test name
Test status
Simulation time 92100836 ps
CPU time 0.99 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:38 PM PDT 24
Peak memory 205704 kb
Host smart-571a7e37-0f87-45dc-92dc-62d9c6765def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137943536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.137943536
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.656718467
Short name T882
Test name
Test status
Simulation time 1557113822 ps
CPU time 7.57 seconds
Started May 21 12:30:13 PM PDT 24
Finished May 21 12:30:51 PM PDT 24
Peak memory 220628 kb
Host smart-75911a10-0a06-47a0-beee-c236f90033d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656718467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.656718467
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3807627758
Short name T781
Test name
Test status
Simulation time 46931148 ps
CPU time 0.7 seconds
Started May 21 12:30:19 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 204848 kb
Host smart-6e8313c6-4354-4b4b-b119-13333df2e454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807627758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3807627758
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2478274466
Short name T530
Test name
Test status
Simulation time 279693138 ps
CPU time 2.13 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 215936 kb
Host smart-95ea3c83-0bc5-40cf-ab28-4c7f35281908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478274466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2478274466
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.222632847
Short name T439
Test name
Test status
Simulation time 13151875 ps
CPU time 0.75 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:30:38 PM PDT 24
Peak memory 206664 kb
Host smart-c0f02b87-bad3-441a-89db-de7e072117ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222632847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.222632847
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1248295976
Short name T500
Test name
Test status
Simulation time 5786715013 ps
CPU time 80.71 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 250472 kb
Host smart-9a8ffd98-31cc-4533-a516-a673153af7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248295976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1248295976
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3324406531
Short name T631
Test name
Test status
Simulation time 19151809152 ps
CPU time 166.15 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:33:28 PM PDT 24
Peak memory 241404 kb
Host smart-31fb4346-11a4-4db0-a1f0-85d195e5ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324406531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3324406531
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1538824775
Short name T670
Test name
Test status
Simulation time 5912568140 ps
CPU time 19.73 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:31:02 PM PDT 24
Peak memory 217384 kb
Host smart-e0dd0dfc-6b86-42ee-aa73-5551b443bd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538824775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1538824775
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1277323748
Short name T318
Test name
Test status
Simulation time 3089294725 ps
CPU time 32.1 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:31:10 PM PDT 24
Peak memory 232780 kb
Host smart-8c0a66e1-998a-4370-aa64-0ffd6ec07d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277323748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1277323748
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1455039108
Short name T425
Test name
Test status
Simulation time 385487577 ps
CPU time 3.1 seconds
Started May 21 12:30:14 PM PDT 24
Finished May 21 12:30:47 PM PDT 24
Peak memory 218384 kb
Host smart-95400eb5-7247-4cc9-ae49-cdd03ea397c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455039108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1455039108
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2194082285
Short name T188
Test name
Test status
Simulation time 5851819505 ps
CPU time 47.41 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:31:24 PM PDT 24
Peak memory 238024 kb
Host smart-edcdc996-e948-4599-b4d7-8dbf763d1b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194082285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2194082285
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.932404401
Short name T649
Test name
Test status
Simulation time 530051645 ps
CPU time 1.09 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 216708 kb
Host smart-81671581-527c-4b1e-90ee-8dab1c2adf0c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932404401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.932404401
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2245418818
Short name T536
Test name
Test status
Simulation time 3140074364 ps
CPU time 6.6 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:44 PM PDT 24
Peak memory 224548 kb
Host smart-9fa698e8-f53b-4a82-ae81-41865ed74115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245418818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2245418818
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1213969766
Short name T297
Test name
Test status
Simulation time 6571960084 ps
CPU time 11.01 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:44 PM PDT 24
Peak memory 238868 kb
Host smart-39811b67-d35a-4caf-814f-b539ff6ce6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213969766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1213969766
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.208934580
Short name T574
Test name
Test status
Simulation time 426560419 ps
CPU time 4.94 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:30:47 PM PDT 24
Peak memory 222836 kb
Host smart-a9a6d3c2-9872-4f32-8507-4de7bb871482
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=208934580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.208934580
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1906648415
Short name T55
Test name
Test status
Simulation time 3097069342 ps
CPU time 8.01 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 216452 kb
Host smart-8b9c61a8-0e5d-44fb-9620-a55c2a496136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906648415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1906648415
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2964331987
Short name T426
Test name
Test status
Simulation time 3692998586 ps
CPU time 12.02 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 216536 kb
Host smart-a86630a6-a0ce-40d1-b5d2-f584b98db7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964331987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2964331987
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2860951308
Short name T866
Test name
Test status
Simulation time 43232858 ps
CPU time 0.74 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 205784 kb
Host smart-e0b023f1-fd52-4cbb-a7f9-82c6ac02a25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860951308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2860951308
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.934340012
Short name T573
Test name
Test status
Simulation time 25834631 ps
CPU time 0.76 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:36 PM PDT 24
Peak memory 205764 kb
Host smart-6a1277e3-af2b-46d8-8525-711aa6d5b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934340012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.934340012
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3361198045
Short name T477
Test name
Test status
Simulation time 580023021 ps
CPU time 6.9 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:30:44 PM PDT 24
Peak memory 233808 kb
Host smart-77517016-c5fb-415f-b825-aa3d85ecbcfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361198045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3361198045
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.910708231
Short name T561
Test name
Test status
Simulation time 51717875 ps
CPU time 0.7 seconds
Started May 21 12:30:19 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 204096 kb
Host smart-09cf4572-1f1c-40c3-989c-4e4b3ba07fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910708231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.910708231
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1616210741
Short name T855
Test name
Test status
Simulation time 84708612 ps
CPU time 3.06 seconds
Started May 21 12:30:19 PM PDT 24
Finished May 21 12:30:52 PM PDT 24
Peak memory 218408 kb
Host smart-883e590f-9d32-4893-b16f-dab9983307f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616210741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1616210741
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1914924149
Short name T857
Test name
Test status
Simulation time 74151596 ps
CPU time 0.79 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 206344 kb
Host smart-a3bc642e-f966-4104-91fb-2c5ded293115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914924149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1914924149
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3933407717
Short name T652
Test name
Test status
Simulation time 7075255343 ps
CPU time 35.06 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:31:18 PM PDT 24
Peak memory 251800 kb
Host smart-52a6385d-a0c3-4b93-8325-a4749b34a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933407717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3933407717
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1835775210
Short name T363
Test name
Test status
Simulation time 227342797 ps
CPU time 6.42 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 224792 kb
Host smart-226dedec-85b6-459b-9b54-a0e76e512700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835775210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1835775210
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2694817538
Short name T203
Test name
Test status
Simulation time 1095813839 ps
CPU time 4.7 seconds
Started May 21 12:30:13 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 232932 kb
Host smart-062d3a73-df56-458a-8f21-eaabfa086a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694817538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2694817538
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1580200173
Short name T974
Test name
Test status
Simulation time 6510015212 ps
CPU time 4.93 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:30:53 PM PDT 24
Peak memory 218416 kb
Host smart-d35e0947-8b6e-4efa-863a-949d319949e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580200173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1580200173
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.907819999
Short name T728
Test name
Test status
Simulation time 64226539 ps
CPU time 1.1 seconds
Started May 21 12:30:19 PM PDT 24
Finished May 21 12:30:50 PM PDT 24
Peak memory 216668 kb
Host smart-5c5c37a0-ad4a-418f-848e-ad670a98c026
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907819999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.907819999
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2960225040
Short name T462
Test name
Test status
Simulation time 2163652664 ps
CPU time 4.53 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 216668 kb
Host smart-5c45c31a-c233-469b-9b43-7cd4cb00ff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960225040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2960225040
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3866087166
Short name T201
Test name
Test status
Simulation time 462979542 ps
CPU time 3.51 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:30:47 PM PDT 24
Peak memory 224440 kb
Host smart-b3451c0a-3a9d-4d82-90fa-7245f1b566dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866087166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3866087166
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4023727451
Short name T459
Test name
Test status
Simulation time 389284892 ps
CPU time 6.69 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:30:55 PM PDT 24
Peak memory 222768 kb
Host smart-26a567d9-3390-4009-97ab-1fa61964f648
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4023727451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4023727451
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3087007035
Short name T2
Test name
Test status
Simulation time 158736066 ps
CPU time 0.88 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 206424 kb
Host smart-277263de-bd3b-4b41-ac04-f6170ba62129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087007035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3087007035
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3337929958
Short name T874
Test name
Test status
Simulation time 1971462794 ps
CPU time 5.47 seconds
Started May 21 12:30:09 PM PDT 24
Finished May 21 12:30:45 PM PDT 24
Peak memory 216324 kb
Host smart-35a858a3-ccad-4740-9a3d-b60d20b18f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337929958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3337929958
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4216882738
Short name T687
Test name
Test status
Simulation time 4495469067 ps
CPU time 15.65 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:53 PM PDT 24
Peak memory 216432 kb
Host smart-36cc0ae2-1672-45a3-b694-6f1b82f1fe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216882738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4216882738
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3595119079
Short name T389
Test name
Test status
Simulation time 345327107 ps
CPU time 1.24 seconds
Started May 21 12:30:12 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 207848 kb
Host smart-d43a9f66-5e53-4cd4-ab87-c730223fd381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595119079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3595119079
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.773841537
Short name T752
Test name
Test status
Simulation time 57970315 ps
CPU time 0.71 seconds
Started May 21 12:30:08 PM PDT 24
Finished May 21 12:30:38 PM PDT 24
Peak memory 205720 kb
Host smart-beea7069-b22d-44f5-b5cb-8397e08aa574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773841537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.773841537
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2605707237
Short name T964
Test name
Test status
Simulation time 16549070092 ps
CPU time 13.8 seconds
Started May 21 12:30:19 PM PDT 24
Finished May 21 12:31:03 PM PDT 24
Peak memory 234348 kb
Host smart-f98c085c-de6c-4508-b26c-5f4f29d45284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605707237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2605707237
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.373108801
Short name T457
Test name
Test status
Simulation time 21356180 ps
CPU time 0.68 seconds
Started May 21 12:30:16 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 204748 kb
Host smart-1e8c703b-bdbe-4edb-af87-51e5e322bdaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373108801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.373108801
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1000506826
Short name T808
Test name
Test status
Simulation time 1780611110 ps
CPU time 4.55 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:30:52 PM PDT 24
Peak memory 218440 kb
Host smart-fa3a5592-a713-4379-a07d-01dbfb76f72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000506826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1000506826
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2251272519
Short name T747
Test name
Test status
Simulation time 18723592 ps
CPU time 0.74 seconds
Started May 21 12:30:20 PM PDT 24
Finished May 21 12:30:50 PM PDT 24
Peak memory 205352 kb
Host smart-45c8a316-3c0d-4650-a138-ad6caef8c83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251272519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2251272519
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.103387421
Short name T806
Test name
Test status
Simulation time 44967601014 ps
CPU time 114.49 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:32:42 PM PDT 24
Peak memory 249396 kb
Host smart-bde99341-8e86-41e9-90ac-f5b1e7cd4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103387421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.103387421
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3363911919
Short name T626
Test name
Test status
Simulation time 4124669029 ps
CPU time 11.4 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:56 PM PDT 24
Peak memory 232760 kb
Host smart-f1acee36-8a83-419d-b6ba-5dea3f368f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363911919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3363911919
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1997768839
Short name T596
Test name
Test status
Simulation time 1059599918 ps
CPU time 11.45 seconds
Started May 21 12:30:20 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 220200 kb
Host smart-0c8834fc-30cd-4c10-a6cf-360be6ef5c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997768839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1997768839
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.186606607
Short name T511
Test name
Test status
Simulation time 74619656 ps
CPU time 2.15 seconds
Started May 21 12:30:20 PM PDT 24
Finished May 21 12:30:52 PM PDT 24
Peak memory 216056 kb
Host smart-44cd70b5-9c90-4b34-a54f-bb735415e41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186606607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.186606607
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3777945189
Short name T24
Test name
Test status
Simulation time 62692824 ps
CPU time 1.03 seconds
Started May 21 12:30:07 PM PDT 24
Finished May 21 12:30:38 PM PDT 24
Peak memory 217980 kb
Host smart-7724ed2e-7705-4a30-8e6c-47e7d8961a2b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777945189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3777945189
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1318638897
Short name T187
Test name
Test status
Simulation time 847281245 ps
CPU time 4.73 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 233800 kb
Host smart-864faca8-df18-49d9-9af8-e552f6e6467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318638897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1318638897
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1640179186
Short name T815
Test name
Test status
Simulation time 1954786508 ps
CPU time 7.18 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:52 PM PDT 24
Peak memory 218348 kb
Host smart-204f0dd7-4e15-4d14-a6dd-efe74a09cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640179186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1640179186
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3405311537
Short name T685
Test name
Test status
Simulation time 142976501 ps
CPU time 1.08 seconds
Started May 21 12:30:20 PM PDT 24
Finished May 21 12:30:51 PM PDT 24
Peak memory 206728 kb
Host smart-706652c9-e20b-4c67-99ad-35d71f98bd67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405311537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3405311537
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.152355227
Short name T10
Test name
Test status
Simulation time 1091478802 ps
CPU time 5.7 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:30:53 PM PDT 24
Peak memory 216260 kb
Host smart-5b1ab69f-a1a5-49bf-82d9-14f1a16aee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152355227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.152355227
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2556780125
Short name T666
Test name
Test status
Simulation time 6211343677 ps
CPU time 9.37 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 216368 kb
Host smart-00ce7871-8acc-4c70-9c01-38055008c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556780125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2556780125
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.89047808
Short name T962
Test name
Test status
Simulation time 12589501 ps
CPU time 0.69 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 205484 kb
Host smart-4e9a79f2-d0a7-4dca-aadd-c12e8b8498a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89047808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.89047808
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.760799334
Short name T342
Test name
Test status
Simulation time 237821555 ps
CPU time 0.86 seconds
Started May 21 12:30:20 PM PDT 24
Finished May 21 12:30:51 PM PDT 24
Peak memory 205748 kb
Host smart-ae71fd6b-88ee-4cb4-83bf-510435dce22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760799334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.760799334
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.357324494
Short name T197
Test name
Test status
Simulation time 291710744 ps
CPU time 2.56 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:47 PM PDT 24
Peak memory 219140 kb
Host smart-140336fc-1649-49ae-9388-369c1d31441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357324494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.357324494
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2946249812
Short name T364
Test name
Test status
Simulation time 158476689 ps
CPU time 0.76 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 205272 kb
Host smart-f2780baf-ed7a-4e4d-bb53-aff3bdb2f162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946249812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2946249812
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1890653941
Short name T643
Test name
Test status
Simulation time 150695748 ps
CPU time 4.42 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:30:51 PM PDT 24
Peak memory 219644 kb
Host smart-bce3ab9b-6745-4b04-b05d-81c03890a65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890653941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1890653941
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1220917836
Short name T823
Test name
Test status
Simulation time 71784857 ps
CPU time 0.81 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:30:47 PM PDT 24
Peak memory 206300 kb
Host smart-bfef0e74-dc65-4c5f-b252-e1302acfd5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220917836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1220917836
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1870843231
Short name T497
Test name
Test status
Simulation time 5578094264 ps
CPU time 40.5 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 235864 kb
Host smart-b02cf388-da28-4d66-b43c-170fbfb8088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870843231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1870843231
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2067274827
Short name T473
Test name
Test status
Simulation time 9776037355 ps
CPU time 87.3 seconds
Started May 21 12:30:16 PM PDT 24
Finished May 21 12:32:12 PM PDT 24
Peak memory 249468 kb
Host smart-541469b0-ae8e-4561-9cdf-2397466af28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067274827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2067274827
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3420203282
Short name T864
Test name
Test status
Simulation time 19792626386 ps
CPU time 61.33 seconds
Started May 21 12:30:20 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 248680 kb
Host smart-0fc1ce6b-2f6d-4702-a928-3025b407753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420203282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3420203282
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4113579559
Short name T448
Test name
Test status
Simulation time 10878843185 ps
CPU time 27.67 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 241032 kb
Host smart-64385ef4-ab1b-4447-bca4-3f717b169f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113579559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4113579559
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2196093832
Short name T213
Test name
Test status
Simulation time 2250560008 ps
CPU time 7.3 seconds
Started May 21 12:30:21 PM PDT 24
Finished May 21 12:30:58 PM PDT 24
Peak memory 233812 kb
Host smart-cf720a26-78f4-4cd6-baea-a6509956b273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196093832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2196093832
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3473367358
Short name T224
Test name
Test status
Simulation time 5529967495 ps
CPU time 19.66 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 223300 kb
Host smart-9ff713a6-41db-478c-9259-fa23ea6c9a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473367358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3473367358
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2408474579
Short name T438
Test name
Test status
Simulation time 49740730 ps
CPU time 1 seconds
Started May 21 12:30:18 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 216772 kb
Host smart-041d4461-b0da-49c0-b092-a6cf6236cdc4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408474579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2408474579
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1881483252
Short name T220
Test name
Test status
Simulation time 111577391 ps
CPU time 3.22 seconds
Started May 21 12:30:19 PM PDT 24
Finished May 21 12:30:52 PM PDT 24
Peak memory 233536 kb
Host smart-b5227858-6cd5-44bf-971f-10d49ca39f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881483252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1881483252
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1143437687
Short name T710
Test name
Test status
Simulation time 62431321 ps
CPU time 2.64 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 220892 kb
Host smart-66a61788-db79-446a-b090-e6aef5a3c50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143437687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1143437687
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2984176283
Short name T40
Test name
Test status
Simulation time 481104450 ps
CPU time 3.98 seconds
Started May 21 12:30:16 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 220476 kb
Host smart-436935bb-afa9-42ab-856a-2ba954c326c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984176283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2984176283
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3973228197
Short name T482
Test name
Test status
Simulation time 5649802583 ps
CPU time 14.76 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:59 PM PDT 24
Peak memory 216468 kb
Host smart-644e90e7-c8b3-4bd3-9ea5-3e7cebe48dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973228197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3973228197
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1790915621
Short name T732
Test name
Test status
Simulation time 475196831 ps
CPU time 1.67 seconds
Started May 21 12:30:15 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 207916 kb
Host smart-3328c779-8e66-4969-a77a-d40badd99479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790915621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1790915621
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3194036959
Short name T636
Test name
Test status
Simulation time 699754241 ps
CPU time 7.33 seconds
Started May 21 12:30:17 PM PDT 24
Finished May 21 12:30:54 PM PDT 24
Peak memory 216272 kb
Host smart-14e06278-db27-4e77-9228-26f465921641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194036959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3194036959
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2630378367
Short name T345
Test name
Test status
Simulation time 74505175 ps
CPU time 0.81 seconds
Started May 21 12:30:16 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 205720 kb
Host smart-2a849dfa-ed03-48e6-9535-85ab31f8e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630378367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2630378367
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3909078200
Short name T36
Test name
Test status
Simulation time 2370697704 ps
CPU time 3.34 seconds
Started May 21 12:30:16 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 224632 kb
Host smart-25251df5-5fd6-43a3-ba26-59849b03b437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909078200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3909078200
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.725541014
Short name T540
Test name
Test status
Simulation time 45600133 ps
CPU time 0.73 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:30:54 PM PDT 24
Peak memory 205264 kb
Host smart-3bac2c48-d292-4f10-8389-dd6b68741145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725541014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.725541014
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3063883314
Short name T804
Test name
Test status
Simulation time 150467056 ps
CPU time 3.25 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 234468 kb
Host smart-ad0c934e-456e-4572-ad27-a3edf309a3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063883314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3063883314
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3728867761
Short name T413
Test name
Test status
Simulation time 68496048 ps
CPU time 0.82 seconds
Started May 21 12:30:23 PM PDT 24
Finished May 21 12:30:53 PM PDT 24
Peak memory 206344 kb
Host smart-d2870b38-e043-45bf-acc0-f393ca9098d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728867761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3728867761
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.410515022
Short name T310
Test name
Test status
Simulation time 4729437257 ps
CPU time 26.76 seconds
Started May 21 12:30:27 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 241264 kb
Host smart-f14e4aca-82e6-4480-abaa-993cc3408e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410515022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.410515022
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2445777145
Short name T572
Test name
Test status
Simulation time 23512915220 ps
CPU time 49.08 seconds
Started May 21 12:30:26 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 221120 kb
Host smart-2ec86578-3f69-46e0-8454-dde97e93d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445777145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2445777145
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.611943693
Short name T623
Test name
Test status
Simulation time 9267443884 ps
CPU time 111.61 seconds
Started May 21 12:30:27 PM PDT 24
Finished May 21 12:32:47 PM PDT 24
Peak memory 251796 kb
Host smart-20a340e5-def9-46ae-bc75-6d9549b3800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611943693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.611943693
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2969517395
Short name T792
Test name
Test status
Simulation time 1347289977 ps
CPU time 7.14 seconds
Started May 21 12:30:23 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 232944 kb
Host smart-275c31b7-6c75-4a11-a87d-95bdb49d4382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969517395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2969517395
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2661294131
Short name T870
Test name
Test status
Simulation time 446306828 ps
CPU time 3.8 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:58 PM PDT 24
Peak memory 233700 kb
Host smart-0d01c168-6321-485b-a2b2-2adb6ef1260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661294131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2661294131
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.4293397208
Short name T467
Test name
Test status
Simulation time 5821210082 ps
CPU time 47.58 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 234312 kb
Host smart-5cb0264d-ce7e-4359-ac62-881ec5ed4d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293397208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.4293397208
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2748479881
Short name T886
Test name
Test status
Simulation time 60845694 ps
CPU time 0.98 seconds
Started May 21 12:30:23 PM PDT 24
Finished May 21 12:30:54 PM PDT 24
Peak memory 217876 kb
Host smart-263aa3d9-cda4-4533-a896-baded3270469
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748479881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2748479881
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3755985597
Short name T586
Test name
Test status
Simulation time 8332623963 ps
CPU time 9.77 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:31:03 PM PDT 24
Peak memory 234440 kb
Host smart-1bea2ed1-16b8-4654-bfb3-ec52cf586cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755985597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3755985597
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2332554027
Short name T177
Test name
Test status
Simulation time 5494618092 ps
CPU time 4.79 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:59 PM PDT 24
Peak memory 224496 kb
Host smart-0731bc78-6192-45c7-a951-b6a2094eba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332554027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2332554027
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3187347643
Short name T522
Test name
Test status
Simulation time 1366038967 ps
CPU time 5.55 seconds
Started May 21 12:30:26 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 219224 kb
Host smart-c3f7b054-0e0f-4bed-86f4-1aa1bfa66784
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187347643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3187347643
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3451630545
Short name T309
Test name
Test status
Simulation time 24934681132 ps
CPU time 276.88 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:35:30 PM PDT 24
Peak memory 252544 kb
Host smart-0cd41cd3-8b45-4acf-bd3c-30cd6d237a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451630545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3451630545
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2839787348
Short name T931
Test name
Test status
Simulation time 5278944016 ps
CPU time 35.05 seconds
Started May 21 12:30:22 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 216384 kb
Host smart-48f821d1-89f9-40c0-8f55-0e9399f9ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839787348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2839787348
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3409057662
Short name T919
Test name
Test status
Simulation time 564367580 ps
CPU time 1.53 seconds
Started May 21 12:30:22 PM PDT 24
Finished May 21 12:30:53 PM PDT 24
Peak memory 207580 kb
Host smart-477f3a53-bee9-4b77-9787-b3c29365e02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409057662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3409057662
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3773890068
Short name T682
Test name
Test status
Simulation time 19669484 ps
CPU time 1.07 seconds
Started May 21 12:30:26 PM PDT 24
Finished May 21 12:30:56 PM PDT 24
Peak memory 208108 kb
Host smart-79de36e9-4231-44e8-921d-9aedc43a01a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773890068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3773890068
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1802108950
Short name T512
Test name
Test status
Simulation time 52383365 ps
CPU time 0.7 seconds
Started May 21 12:30:28 PM PDT 24
Finished May 21 12:30:56 PM PDT 24
Peak memory 205432 kb
Host smart-ec9441bd-6427-4d40-8757-0913114a4875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802108950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1802108950
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3671715910
Short name T951
Test name
Test status
Simulation time 2382378831 ps
CPU time 10.7 seconds
Started May 21 12:30:22 PM PDT 24
Finished May 21 12:31:03 PM PDT 24
Peak memory 217584 kb
Host smart-b5d7278c-b994-403e-8e0a-5d7fe3fdf8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671715910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3671715910
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2215508134
Short name T627
Test name
Test status
Simulation time 39037291 ps
CPU time 0.74 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:55 PM PDT 24
Peak memory 205388 kb
Host smart-7b190037-abeb-43f8-9a98-f72184145920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215508134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2215508134
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.864309991
Short name T760
Test name
Test status
Simulation time 189819748 ps
CPU time 4.29 seconds
Started May 21 12:30:27 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 233688 kb
Host smart-7c980636-a3ef-4384-8458-1a6ce9e9ecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864309991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.864309991
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3975900678
Short name T958
Test name
Test status
Simulation time 120627066 ps
CPU time 0.8 seconds
Started May 21 12:30:26 PM PDT 24
Finished May 21 12:30:56 PM PDT 24
Peak memory 206408 kb
Host smart-7ae5c8c2-8270-47c4-b8bd-5a996a72cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975900678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3975900678
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1955804283
Short name T378
Test name
Test status
Simulation time 46123084525 ps
CPU time 149.11 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:33:23 PM PDT 24
Peak memory 237124 kb
Host smart-1f2647be-cce8-4ad3-aec7-f300f34cc70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955804283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1955804283
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.909303530
Short name T301
Test name
Test status
Simulation time 24954466488 ps
CPU time 204.42 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:34:19 PM PDT 24
Peak memory 255132 kb
Host smart-2a1951c3-4c23-4c8d-9014-339386d2ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909303530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.909303530
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3057546699
Short name T950
Test name
Test status
Simulation time 468337134 ps
CPU time 6.08 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 248872 kb
Host smart-c3e60734-7d8c-48aa-95cd-c8dc2add74fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057546699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3057546699
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2959602640
Short name T913
Test name
Test status
Simulation time 1159497694 ps
CPU time 4.05 seconds
Started May 21 12:30:27 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 218696 kb
Host smart-f1d0737e-b5c5-4715-8360-961e9040687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959602640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2959602640
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3830484784
Short name T414
Test name
Test status
Simulation time 226264374 ps
CPU time 2.15 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 216120 kb
Host smart-d0c39bc2-188f-4abd-b512-e2fae2401c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830484784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3830484784
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3039508004
Short name T834
Test name
Test status
Simulation time 16327249 ps
CPU time 1.01 seconds
Started May 21 12:30:28 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 216680 kb
Host smart-ed1ab76f-3751-47f8-ab4c-0dbb4d3c6ac3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039508004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3039508004
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3457073454
Short name T534
Test name
Test status
Simulation time 1938628800 ps
CPU time 3.08 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 218356 kb
Host smart-73b41e68-f53b-47f3-aaf6-8034596a952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457073454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3457073454
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1217875069
Short name T95
Test name
Test status
Simulation time 4284745731 ps
CPU time 9.99 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:31:05 PM PDT 24
Peak memory 233672 kb
Host smart-a5fafd18-9699-491f-a5be-1275bbc2c9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217875069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1217875069
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.321139849
Short name T440
Test name
Test status
Simulation time 221114099 ps
CPU time 5.18 seconds
Started May 21 12:30:22 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 218976 kb
Host smart-0f039177-234a-40e2-ac4c-67f57e69dd4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=321139849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.321139849
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1314389266
Short name T277
Test name
Test status
Simulation time 45724755867 ps
CPU time 157.96 seconds
Started May 21 12:30:26 PM PDT 24
Finished May 21 12:33:33 PM PDT 24
Peak memory 224712 kb
Host smart-81facd2a-335b-4b2b-909c-64286f61d3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314389266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1314389266
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3361014774
Short name T885
Test name
Test status
Simulation time 1397182509 ps
CPU time 4.24 seconds
Started May 21 12:30:24 PM PDT 24
Finished May 21 12:30:58 PM PDT 24
Peak memory 216364 kb
Host smart-376f0f11-d881-4ee3-b7ed-d8a788ffdbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361014774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3361014774
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1527309408
Short name T930
Test name
Test status
Simulation time 12617103 ps
CPU time 0.69 seconds
Started May 21 12:30:29 PM PDT 24
Finished May 21 12:30:58 PM PDT 24
Peak memory 205476 kb
Host smart-a7828349-50d0-4742-9466-d3802023f86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527309408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1527309408
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3895358387
Short name T19
Test name
Test status
Simulation time 17265739 ps
CPU time 0.8 seconds
Started May 21 12:30:26 PM PDT 24
Finished May 21 12:30:56 PM PDT 24
Peak memory 206412 kb
Host smart-40188f96-300e-4771-9743-698b357cca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895358387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3895358387
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.49093809
Short name T411
Test name
Test status
Simulation time 295686550 ps
CPU time 0.96 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:55 PM PDT 24
Peak memory 205812 kb
Host smart-f4f4d90c-7914-4a40-8f3d-bbbb3321cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49093809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.49093809
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.369926865
Short name T290
Test name
Test status
Simulation time 9856294790 ps
CPU time 15.24 seconds
Started May 21 12:30:27 PM PDT 24
Finished May 21 12:31:10 PM PDT 24
Peak memory 233436 kb
Host smart-6b4f9693-65bf-4f4f-ae56-e6656061e3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369926865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.369926865
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3896567476
Short name T57
Test name
Test status
Simulation time 20239594 ps
CPU time 0.68 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 205256 kb
Host smart-3abb7088-ff3a-40c0-bfeb-ef98797d33b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896567476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3896567476
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2092897201
Short name T507
Test name
Test status
Simulation time 514239414 ps
CPU time 4.94 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:07 PM PDT 24
Peak memory 216616 kb
Host smart-bf426a54-6754-4c93-86a1-2558e3d6a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092897201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2092897201
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1779868807
Short name T546
Test name
Test status
Simulation time 13909282 ps
CPU time 0.77 seconds
Started May 21 12:30:25 PM PDT 24
Finished May 21 12:30:55 PM PDT 24
Peak memory 206356 kb
Host smart-ddc10af4-49e7-455f-981e-eb6ea743713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779868807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1779868807
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1470101228
Short name T289
Test name
Test status
Simulation time 20936481826 ps
CPU time 59.91 seconds
Started May 21 12:30:36 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 256644 kb
Host smart-65ab7272-8e3d-4cce-897f-5ced2b7b0f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470101228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1470101228
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2192672883
Short name T714
Test name
Test status
Simulation time 22867078287 ps
CPU time 24.44 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:31:24 PM PDT 24
Peak memory 238952 kb
Host smart-dd4da9c0-f80a-45ac-a06a-38e2cc128433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192672883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2192672883
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1984374306
Short name T920
Test name
Test status
Simulation time 912724993 ps
CPU time 12.83 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:12 PM PDT 24
Peak memory 224396 kb
Host smart-e5e8fe03-6849-416c-a6ff-d6ad6ac3b8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984374306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1984374306
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4083494028
Short name T12
Test name
Test status
Simulation time 300723911 ps
CPU time 3.05 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:31:04 PM PDT 24
Peak memory 218340 kb
Host smart-bc5fcc92-0b9a-4ae3-9afb-c509a81ecc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083494028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4083494028
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1584865206
Short name T754
Test name
Test status
Simulation time 9061873308 ps
CPU time 75.67 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:32:24 PM PDT 24
Peak memory 233800 kb
Host smart-0f6d5cc9-a0c4-40c3-87eb-bfab164abc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584865206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1584865206
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3874399173
Short name T23
Test name
Test status
Simulation time 84082778 ps
CPU time 1.1 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 216668 kb
Host smart-b7e6bc2a-9c72-431e-a72a-6861f8bc20b7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874399173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3874399173
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2710619774
Short name T71
Test name
Test status
Simulation time 35671993 ps
CPU time 2.02 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 216704 kb
Host smart-d8ac7c1f-7293-4f5a-90a4-4ecab456282e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710619774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2710619774
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3524425390
Short name T264
Test name
Test status
Simulation time 21467614098 ps
CPU time 21.65 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 256312 kb
Host smart-1abc637b-77cf-4b40-9099-738f76268646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524425390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3524425390
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.197269871
Short name T466
Test name
Test status
Simulation time 2675338722 ps
CPU time 10.54 seconds
Started May 21 12:30:32 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 218808 kb
Host smart-b8bfd03b-306c-4cb2-b77e-83d18a7a7a3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=197269871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.197269871
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3339999600
Short name T165
Test name
Test status
Simulation time 25033261741 ps
CPU time 232.71 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:34:55 PM PDT 24
Peak memory 249604 kb
Host smart-28d125ef-c179-46d0-97c8-b794bec4c164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339999600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3339999600
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3020199770
Short name T696
Test name
Test status
Simulation time 2847718814 ps
CPU time 15.04 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:23 PM PDT 24
Peak memory 216464 kb
Host smart-403f75f9-9639-49d4-aa61-c41429cb4c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020199770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3020199770
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.202768773
Short name T347
Test name
Test status
Simulation time 29911470218 ps
CPU time 10.88 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:10 PM PDT 24
Peak memory 216352 kb
Host smart-cba823be-823b-4e89-91bd-512734ee0f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202768773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.202768773
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.601814704
Short name T644
Test name
Test status
Simulation time 39821532 ps
CPU time 0.72 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 205756 kb
Host smart-055be800-16f3-4b66-9aaf-5432572b82e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601814704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.601814704
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3287526725
Short name T73
Test name
Test status
Simulation time 33012063 ps
CPU time 0.67 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 205404 kb
Host smart-0f022df5-0bb1-4486-aa6f-fd01779fc160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287526725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3287526725
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3413596875
Short name T653
Test name
Test status
Simulation time 28775622510 ps
CPU time 17.63 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 239936 kb
Host smart-e64167e7-2ae6-45b6-983c-ab1855b3da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413596875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3413596875
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3751160329
Short name T565
Test name
Test status
Simulation time 42612355 ps
CPU time 0.74 seconds
Started May 21 12:29:42 PM PDT 24
Finished May 21 12:30:09 PM PDT 24
Peak memory 205296 kb
Host smart-aeff59fe-0d2e-4844-ab0e-55440c7cb05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751160329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
751160329
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2089660717
Short name T6
Test name
Test status
Simulation time 457196999 ps
CPU time 6.25 seconds
Started May 21 12:29:44 PM PDT 24
Finished May 21 12:30:17 PM PDT 24
Peak memory 233244 kb
Host smart-9b8a1a9c-7a66-482b-a626-e7e8012bf469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089660717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2089660717
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3799802982
Short name T706
Test name
Test status
Simulation time 192939844 ps
CPU time 0.76 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:30:11 PM PDT 24
Peak memory 206664 kb
Host smart-6dc76200-97a7-4adc-971f-e29a517dcb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799802982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3799802982
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2170591437
Short name T725
Test name
Test status
Simulation time 2599924953 ps
CPU time 11 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 236264 kb
Host smart-7c2efaa1-214a-4aa5-ab97-e030cb6ef90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170591437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2170591437
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2084189760
Short name T46
Test name
Test status
Simulation time 4072597474 ps
CPU time 78.32 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 256232 kb
Host smart-4405a8d9-d342-4700-b62d-bce4fa11edb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084189760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2084189760
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2119948678
Short name T316
Test name
Test status
Simulation time 2318529728 ps
CPU time 8.55 seconds
Started May 21 12:29:41 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 224600 kb
Host smart-cb8b1cce-6cd9-4458-9882-65495582cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119948678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2119948678
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4244684757
Short name T703
Test name
Test status
Simulation time 28757802470 ps
CPU time 36.24 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:50 PM PDT 24
Peak memory 237448 kb
Host smart-2c05ac19-6d8b-44db-9eb0-b298c56262b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244684757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4244684757
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1287794362
Short name T552
Test name
Test status
Simulation time 37529050 ps
CPU time 2.51 seconds
Started May 21 12:29:47 PM PDT 24
Finished May 21 12:30:18 PM PDT 24
Peak memory 224440 kb
Host smart-17af4bf3-abd7-40aa-acc0-56be1e5e0150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287794362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1287794362
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.979069984
Short name T911
Test name
Test status
Simulation time 26569153 ps
CPU time 1 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:30:11 PM PDT 24
Peak memory 217884 kb
Host smart-68d7f3d0-0672-4a3f-88d3-84b798d2ddce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979069984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.979069984
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2534943404
Short name T242
Test name
Test status
Simulation time 9149900466 ps
CPU time 7.61 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 233856 kb
Host smart-3c7be192-732b-4ac5-b075-08198a315e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534943404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2534943404
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1639190133
Short name T845
Test name
Test status
Simulation time 2697059087 ps
CPU time 11.64 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 238808 kb
Host smart-7933f7cf-349d-4fff-ad4e-c2204e1b08de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639190133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1639190133
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.10010636
Short name T382
Test name
Test status
Simulation time 1375649905 ps
CPU time 14.62 seconds
Started May 21 12:29:44 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 222368 kb
Host smart-1bd869b7-4644-416f-9a4d-15656572a476
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=10010636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct
.10010636
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2140873108
Short name T69
Test name
Test status
Simulation time 656068044 ps
CPU time 1.05 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:30:11 PM PDT 24
Peak memory 234912 kb
Host smart-0831c1d3-e22b-4978-9ecd-07e2d7dfd9db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140873108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2140873108
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.716126247
Short name T139
Test name
Test status
Simulation time 13756525474 ps
CPU time 67.82 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 253320 kb
Host smart-f88c46d7-8575-4c2c-b20a-029d6698f3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716126247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.716126247
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2071145676
Short name T630
Test name
Test status
Simulation time 6050162018 ps
CPU time 16.32 seconds
Started May 21 12:29:49 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 216320 kb
Host smart-aaf317f6-b384-4125-98db-0059533ae36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071145676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2071145676
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1658808130
Short name T923
Test name
Test status
Simulation time 4705276750 ps
CPU time 5.79 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:19 PM PDT 24
Peak memory 216444 kb
Host smart-a1d4e97b-9e81-4bcd-a9fa-7e3b9f8e733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658808130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1658808130
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2938014207
Short name T629
Test name
Test status
Simulation time 191768285 ps
CPU time 1.5 seconds
Started May 21 12:29:49 PM PDT 24
Finished May 21 12:30:19 PM PDT 24
Peak memory 216332 kb
Host smart-821e417d-7d41-4bb9-84f8-95e7d880fa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938014207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2938014207
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2649604154
Short name T785
Test name
Test status
Simulation time 199487916 ps
CPU time 0.95 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:15 PM PDT 24
Peak memory 205728 kb
Host smart-c1276f27-a65f-4b77-9125-7e0d97ac5c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649604154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2649604154
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2547308615
Short name T372
Test name
Test status
Simulation time 209842040 ps
CPU time 3.75 seconds
Started May 21 12:29:44 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 217564 kb
Host smart-40a9bc59-65f1-4367-9073-f249e41892b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547308615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2547308615
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3658040134
Short name T662
Test name
Test status
Simulation time 30252062 ps
CPU time 0.69 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 204588 kb
Host smart-c1ffec21-ba63-49e3-a293-0c0665e13b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658040134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3658040134
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1449355058
Short name T625
Test name
Test status
Simulation time 937515441 ps
CPU time 15.47 seconds
Started May 21 12:30:29 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 219996 kb
Host smart-4da98a98-8e7e-4dae-9a30-0ffacd91073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449355058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1449355058
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2465941621
Short name T688
Test name
Test status
Simulation time 57034185 ps
CPU time 0.76 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 206312 kb
Host smart-808a3f55-1198-45a1-aec4-8de730a65b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465941621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2465941621
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1041120597
Short name T912
Test name
Test status
Simulation time 47069597783 ps
CPU time 80.86 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:32:19 PM PDT 24
Peak memory 232908 kb
Host smart-1ceca96e-8d8e-4cbc-821c-f220ff2e3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041120597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1041120597
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.261289216
Short name T269
Test name
Test status
Simulation time 17726612188 ps
CPU time 83.15 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:32:23 PM PDT 24
Peak memory 253340 kb
Host smart-67ce472f-4dc1-4f5f-96ab-f93ca9ee8461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261289216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.261289216
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2993669589
Short name T892
Test name
Test status
Simulation time 11535840907 ps
CPU time 127.66 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:33:07 PM PDT 24
Peak memory 251488 kb
Host smart-f0f0c745-3735-434b-8912-5291aac03312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993669589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2993669589
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2123556568
Short name T471
Test name
Test status
Simulation time 703560768 ps
CPU time 10.38 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:09 PM PDT 24
Peak memory 240788 kb
Host smart-b8d2a130-e1b5-4568-b618-82098894f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123556568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2123556568
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3921397571
Short name T284
Test name
Test status
Simulation time 78994848 ps
CPU time 3.47 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:06 PM PDT 24
Peak memory 233504 kb
Host smart-24f3f96f-6545-4ba3-b8fd-30bc020047e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921397571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3921397571
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2289867259
Short name T755
Test name
Test status
Simulation time 2575403532 ps
CPU time 16.69 seconds
Started May 21 12:30:37 PM PDT 24
Finished May 21 12:31:23 PM PDT 24
Peak memory 238188 kb
Host smart-eabf7222-9611-4c98-8622-d19acb8a2dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289867259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2289867259
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2149922389
Short name T26
Test name
Test status
Simulation time 2139654262 ps
CPU time 5.17 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 228848 kb
Host smart-6c5d6f0f-c0da-4487-a108-ce61245a7ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149922389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2149922389
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2789747297
Short name T443
Test name
Test status
Simulation time 1427071002 ps
CPU time 9.59 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:12 PM PDT 24
Peak memory 222324 kb
Host smart-dc8a1f66-84fa-4338-9e5e-1350b51abddc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2789747297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2789747297
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.173191142
Short name T159
Test name
Test status
Simulation time 140649469 ps
CPU time 0.91 seconds
Started May 21 12:30:35 PM PDT 24
Finished May 21 12:31:04 PM PDT 24
Peak memory 206764 kb
Host smart-f761e908-fb53-4307-8d94-4df28d179b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173191142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.173191142
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.725897046
Short name T493
Test name
Test status
Simulation time 788436390 ps
CPU time 4.42 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:07 PM PDT 24
Peak memory 216412 kb
Host smart-5637f127-760f-4a85-aad4-ea884186f699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725897046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.725897046
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4052775660
Short name T921
Test name
Test status
Simulation time 1750601953 ps
CPU time 3.07 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 207888 kb
Host smart-c7633f54-5243-43a4-9f68-9de5b3ffe51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052775660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4052775660
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2350026757
Short name T330
Test name
Test status
Simulation time 379270059 ps
CPU time 5.44 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 216476 kb
Host smart-b94c57a6-0115-48e9-8145-c39c4c17a1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350026757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2350026757
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3660335535
Short name T664
Test name
Test status
Simulation time 109561611 ps
CPU time 0.8 seconds
Started May 21 12:30:29 PM PDT 24
Finished May 21 12:30:58 PM PDT 24
Peak memory 205720 kb
Host smart-eb4eb55d-05dd-44c0-9325-3f60f7fab8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660335535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3660335535
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.388377771
Short name T927
Test name
Test status
Simulation time 377396661 ps
CPU time 4.99 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:04 PM PDT 24
Peak memory 216560 kb
Host smart-1ff6a0c5-115c-4dc3-a988-2acc7a3d62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388377771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.388377771
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3919302661
Short name T970
Test name
Test status
Simulation time 15742878 ps
CPU time 0.71 seconds
Started May 21 12:30:40 PM PDT 24
Finished May 21 12:31:11 PM PDT 24
Peak memory 204676 kb
Host smart-9160946a-6a99-4a40-8661-5a88fd0dd57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919302661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3919302661
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3708234319
Short name T712
Test name
Test status
Simulation time 137634818 ps
CPU time 2.4 seconds
Started May 21 12:30:30 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 218368 kb
Host smart-994c8264-ef49-48db-81d7-c506e12a7f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708234319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3708234319
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3000014651
Short name T412
Test name
Test status
Simulation time 14373498 ps
CPU time 0.74 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:31:01 PM PDT 24
Peak memory 206776 kb
Host smart-b5c0da6e-317c-4391-afb4-b5796337430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000014651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3000014651
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1294175814
Short name T189
Test name
Test status
Simulation time 1918963037 ps
CPU time 47.86 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:50 PM PDT 24
Peak memory 248992 kb
Host smart-3d0f645d-7603-47e5-8017-4d4462405378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294175814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1294175814
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2114808783
Short name T941
Test name
Test status
Simulation time 76452015631 ps
CPU time 175.31 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:33:58 PM PDT 24
Peak memory 252228 kb
Host smart-e3687880-9e64-4ec3-9129-652f8f202d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114808783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2114808783
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2869026926
Short name T899
Test name
Test status
Simulation time 1287594079 ps
CPU time 13.48 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 240844 kb
Host smart-f5ad31d2-5a06-454e-9037-b4945262f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869026926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2869026926
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2391315859
Short name T961
Test name
Test status
Simulation time 1414019516 ps
CPU time 13.51 seconds
Started May 21 12:30:29 PM PDT 24
Finished May 21 12:31:11 PM PDT 24
Peak memory 234504 kb
Host smart-46a76d12-8f06-4510-8587-d982805b46a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391315859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2391315859
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2093705835
Short name T42
Test name
Test status
Simulation time 34914837110 ps
CPU time 70.99 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:32:13 PM PDT 24
Peak memory 248932 kb
Host smart-a5d841bc-4215-4b1e-968d-592eff072fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093705835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2093705835
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2658613735
Short name T878
Test name
Test status
Simulation time 31432036 ps
CPU time 2.09 seconds
Started May 21 12:30:31 PM PDT 24
Finished May 21 12:31:03 PM PDT 24
Peak memory 216092 kb
Host smart-05b9bcab-2be4-4691-8507-e64a16397d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658613735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2658613735
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1426368977
Short name T757
Test name
Test status
Simulation time 732240115 ps
CPU time 2.58 seconds
Started May 21 12:30:32 PM PDT 24
Finished May 21 12:31:05 PM PDT 24
Peak memory 217292 kb
Host smart-bb8ace0d-45b0-42ca-88d8-1f8e3eea23f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426368977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1426368977
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.20169790
Short name T831
Test name
Test status
Simulation time 2263880798 ps
CPU time 5.7 seconds
Started May 21 12:30:34 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 219736 kb
Host smart-8a899e9a-923c-48cf-bfd9-92f2ce7aa097
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=20169790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direc
t.20169790
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.382419758
Short name T858
Test name
Test status
Simulation time 3871903127 ps
CPU time 7.14 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:09 PM PDT 24
Peak memory 216232 kb
Host smart-298495cf-d143-4769-911a-1732bb84757a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382419758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.382419758
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2211204582
Short name T483
Test name
Test status
Simulation time 2070810304 ps
CPU time 5.89 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 216296 kb
Host smart-286a3190-de2c-42c4-a5b0-f27fc5b8cefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211204582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2211204582
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2595850248
Short name T794
Test name
Test status
Simulation time 51886411 ps
CPU time 1.69 seconds
Started May 21 12:30:34 PM PDT 24
Finished May 21 12:31:04 PM PDT 24
Peak memory 216236 kb
Host smart-6df7fce9-802c-46a1-b62f-aa635a9f9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595850248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2595850248
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4253456021
Short name T860
Test name
Test status
Simulation time 307981125 ps
CPU time 0.91 seconds
Started May 21 12:30:32 PM PDT 24
Finished May 21 12:31:03 PM PDT 24
Peak memory 205744 kb
Host smart-cbfd3981-3f2c-40a6-8e32-3e3c584a1eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253456021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4253456021
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3746187932
Short name T770
Test name
Test status
Simulation time 12439599080 ps
CPU time 5.96 seconds
Started May 21 12:30:33 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 216396 kb
Host smart-8476c38f-a7e3-4a7d-80df-5306bef50af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746187932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3746187932
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.482296463
Short name T583
Test name
Test status
Simulation time 12534124 ps
CPU time 0.72 seconds
Started May 21 12:30:41 PM PDT 24
Finished May 21 12:31:11 PM PDT 24
Peak memory 205612 kb
Host smart-fbad381f-8d42-4de6-bfe9-560385383dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482296463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.482296463
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1098951768
Short name T676
Test name
Test status
Simulation time 819718644 ps
CPU time 5.33 seconds
Started May 21 12:30:40 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 219432 kb
Host smart-df4303f9-3dfd-4163-9af3-53b500ef2341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098951768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1098951768
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2602777597
Short name T504
Test name
Test status
Simulation time 63318323 ps
CPU time 0.81 seconds
Started May 21 12:30:41 PM PDT 24
Finished May 21 12:31:11 PM PDT 24
Peak memory 205308 kb
Host smart-3e843cf1-f9c2-4f76-858e-dce9e3e75773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602777597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2602777597
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2919774597
Short name T925
Test name
Test status
Simulation time 23632639828 ps
CPU time 84.77 seconds
Started May 21 12:30:36 PM PDT 24
Finished May 21 12:32:30 PM PDT 24
Peak memory 240908 kb
Host smart-8a29c109-5e36-4f28-aff0-e3d946ad1143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919774597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2919774597
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3996870954
Short name T589
Test name
Test status
Simulation time 28740402603 ps
CPU time 271.36 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:35:39 PM PDT 24
Peak memory 252740 kb
Host smart-190e083d-d6cf-47f1-bc48-128fdfa8d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996870954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3996870954
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3015366573
Short name T677
Test name
Test status
Simulation time 6306190827 ps
CPU time 23.68 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 224608 kb
Host smart-8e855ffb-35aa-4c25-9756-3eb54d99e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015366573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3015366573
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3047490966
Short name T537
Test name
Test status
Simulation time 3321241994 ps
CPU time 29.26 seconds
Started May 21 12:30:44 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 218844 kb
Host smart-d863896e-a5f4-4e20-9947-9ca8c5682f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047490966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3047490966
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1616807036
Short name T334
Test name
Test status
Simulation time 838983659 ps
CPU time 2.18 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:10 PM PDT 24
Peak memory 215992 kb
Host smart-2aa7de48-2fce-48e3-8d6b-c7a88cba63ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616807036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1616807036
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3848326267
Short name T380
Test name
Test status
Simulation time 578416636 ps
CPU time 4.05 seconds
Started May 21 12:30:40 PM PDT 24
Finished May 21 12:31:14 PM PDT 24
Peak memory 218676 kb
Host smart-9d31f512-c5fd-41a6-a0fb-f24100d52e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848326267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3848326267
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.833023576
Short name T280
Test name
Test status
Simulation time 2080187532 ps
CPU time 7.4 seconds
Started May 21 12:30:37 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 227176 kb
Host smart-81272cb7-5a3b-42a9-82dc-eb9e2ed2c67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833023576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.833023576
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2647862202
Short name T388
Test name
Test status
Simulation time 231983638 ps
CPU time 3.87 seconds
Started May 21 12:30:40 PM PDT 24
Finished May 21 12:31:15 PM PDT 24
Peak memory 218444 kb
Host smart-7029dd78-f827-43f0-93c6-2c7322665c27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2647862202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2647862202
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1200067029
Short name T740
Test name
Test status
Simulation time 1326143774 ps
CPU time 10.02 seconds
Started May 21 12:30:41 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 216260 kb
Host smart-53a03ab5-8348-4cff-a468-354fc708dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200067029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1200067029
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.173597935
Short name T850
Test name
Test status
Simulation time 2344900800 ps
CPU time 5.18 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 216712 kb
Host smart-0a22718b-4752-47d0-b8bd-a8657b958c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173597935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.173597935
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.447757595
Short name T751
Test name
Test status
Simulation time 44292329 ps
CPU time 0.69 seconds
Started May 21 12:30:44 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 205356 kb
Host smart-b39b545f-8218-4ffd-87af-17d9c1b55449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447757595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.447757595
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3567803990
Short name T352
Test name
Test status
Simulation time 147367793 ps
CPU time 0.77 seconds
Started May 21 12:30:41 PM PDT 24
Finished May 21 12:31:11 PM PDT 24
Peak memory 205728 kb
Host smart-b527a27e-42af-4d88-b5f0-dca523570aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567803990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3567803990
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1161007226
Short name T204
Test name
Test status
Simulation time 1060690009 ps
CPU time 4.74 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 234236 kb
Host smart-f9b8cc1f-b16b-41fc-9864-2bf970e16947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161007226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1161007226
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.224233092
Short name T910
Test name
Test status
Simulation time 17287179 ps
CPU time 0.77 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:09 PM PDT 24
Peak memory 204644 kb
Host smart-1a7d5002-ec73-43a9-8925-a0b9cc14b0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224233092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.224233092
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2692304093
Short name T833
Test name
Test status
Simulation time 36963435542 ps
CPU time 29.9 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:40 PM PDT 24
Peak memory 233892 kb
Host smart-f59afd45-fd82-449d-aa23-a353727366ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692304093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2692304093
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2605300376
Short name T445
Test name
Test status
Simulation time 56328639 ps
CPU time 0.73 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:09 PM PDT 24
Peak memory 205328 kb
Host smart-4311320f-7c47-4372-8af1-fe041b23e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605300376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2605300376
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.896836308
Short name T313
Test name
Test status
Simulation time 1096470022 ps
CPU time 11.5 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 232632 kb
Host smart-266a8866-48d3-47b7-afcd-871496434768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896836308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.896836308
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2777332631
Short name T193
Test name
Test status
Simulation time 203876656875 ps
CPU time 409.75 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:37:58 PM PDT 24
Peak memory 256012 kb
Host smart-d395e034-df84-4095-a929-a21a62f1b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777332631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2777332631
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1182283270
Short name T791
Test name
Test status
Simulation time 2126281368 ps
CPU time 13.2 seconds
Started May 21 12:30:44 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 224500 kb
Host smart-f19d5a63-e09c-448b-bab3-380bd1cf97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182283270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1182283270
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.29282548
Short name T174
Test name
Test status
Simulation time 5646438518 ps
CPU time 26.6 seconds
Started May 21 12:30:37 PM PDT 24
Finished May 21 12:31:33 PM PDT 24
Peak memory 232780 kb
Host smart-ca6b6370-2d4c-47a5-8729-c1763f3cad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29282548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.29282548
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2719810547
Short name T524
Test name
Test status
Simulation time 27636816948 ps
CPU time 21.14 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 235028 kb
Host smart-09f63242-b98c-4a90-9aec-cabd58e2de73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719810547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2719810547
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3980977887
Short name T195
Test name
Test status
Simulation time 581332135 ps
CPU time 4.58 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:12 PM PDT 24
Peak memory 218552 kb
Host smart-cbef5dc5-8bc5-4faf-9568-c66217687613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980977887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3980977887
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.490559324
Short name T403
Test name
Test status
Simulation time 14151126883 ps
CPU time 10.01 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 217880 kb
Host smart-58e8635e-ff2e-4ad8-8943-c1c1fdd32326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490559324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.490559324
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2526305558
Short name T427
Test name
Test status
Simulation time 39801142734 ps
CPU time 15.12 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 223020 kb
Host smart-2669dc0b-bff9-4ece-a18e-c3c580477bca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526305558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2526305558
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.35523150
Short name T285
Test name
Test status
Simulation time 3030662413 ps
CPU time 41.16 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:48 PM PDT 24
Peak memory 253008 kb
Host smart-8022017a-437a-43a3-bddf-00bec90d06da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress
_all.35523150
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.649037784
Short name T88
Test name
Test status
Simulation time 18158299265 ps
CPU time 23.61 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 216504 kb
Host smart-d9df0161-4474-48e4-bb3c-2d50b3713823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649037784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.649037784
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.304592434
Short name T966
Test name
Test status
Simulation time 419767324 ps
CPU time 3.02 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:12 PM PDT 24
Peak memory 216260 kb
Host smart-bc393ece-8a14-4bed-ae84-3aa73b695627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304592434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.304592434
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.452141153
Short name T836
Test name
Test status
Simulation time 794659782 ps
CPU time 4.09 seconds
Started May 21 12:30:42 PM PDT 24
Finished May 21 12:31:15 PM PDT 24
Peak memory 216292 kb
Host smart-01a4c9d4-ee24-4ecd-863c-335cdf8f3dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452141153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.452141153
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3548749141
Short name T432
Test name
Test status
Simulation time 326808773 ps
CPU time 0.93 seconds
Started May 21 12:30:40 PM PDT 24
Finished May 21 12:31:11 PM PDT 24
Peak memory 205744 kb
Host smart-553750dc-3a38-4c70-9de4-026b0b64b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548749141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3548749141
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3741801083
Short name T215
Test name
Test status
Simulation time 1161211758 ps
CPU time 7.89 seconds
Started May 21 12:30:39 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 217708 kb
Host smart-56d9fff7-a536-440b-8d02-13166d88018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741801083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3741801083
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.716940415
Short name T748
Test name
Test status
Simulation time 23380024 ps
CPU time 0.76 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 204696 kb
Host smart-e04b7a08-1c51-464d-a02e-c96ec5dfa49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716940415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.716940415
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3492346755
Short name T173
Test name
Test status
Simulation time 284062353 ps
CPU time 2.85 seconds
Started May 21 12:30:49 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 233600 kb
Host smart-32f68fe6-96fb-4537-8670-15dff0664a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492346755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3492346755
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3829135985
Short name T645
Test name
Test status
Simulation time 32086160 ps
CPU time 0.75 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:09 PM PDT 24
Peak memory 205348 kb
Host smart-577fd392-e151-4b10-95aa-fc6f8962981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829135985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3829135985
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1145586494
Short name T202
Test name
Test status
Simulation time 104908294717 ps
CPU time 216.06 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:34:53 PM PDT 24
Peak memory 249116 kb
Host smart-6fda98f0-61d4-431b-909a-2fe9ff5e0bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145586494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1145586494
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.561991908
Short name T975
Test name
Test status
Simulation time 2161505046 ps
CPU time 35 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 241060 kb
Host smart-5a6e7198-66f3-4f2c-91ea-d6b4b04a1738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561991908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.561991908
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3925210456
Short name T456
Test name
Test status
Simulation time 747755612 ps
CPU time 9.35 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 218180 kb
Host smart-f6928e7f-ef8b-4b0d-b4e9-31c9e0e9dcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925210456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3925210456
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4173408828
Short name T916
Test name
Test status
Simulation time 90124431 ps
CPU time 2.54 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 218124 kb
Host smart-dbff67be-1bd9-42bf-83bc-88369558647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173408828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4173408828
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.946038549
Short name T182
Test name
Test status
Simulation time 23050023631 ps
CPU time 18.23 seconds
Started May 21 12:30:41 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 233508 kb
Host smart-f8863bea-58f4-4c72-b687-f629cca92bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946038549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.946038549
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1941000494
Short name T595
Test name
Test status
Simulation time 504863381 ps
CPU time 2.29 seconds
Started May 21 12:30:40 PM PDT 24
Finished May 21 12:31:12 PM PDT 24
Peak memory 224400 kb
Host smart-735b23db-745c-40ee-a09c-937b8df76bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941000494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1941000494
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4170870038
Short name T402
Test name
Test status
Simulation time 1983877342 ps
CPU time 10.42 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 221988 kb
Host smart-ca7369f9-7eca-4ed8-baf2-11192782e5a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4170870038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4170870038
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.446018706
Short name T619
Test name
Test status
Simulation time 750855651 ps
CPU time 3.32 seconds
Started May 21 12:30:37 PM PDT 24
Finished May 21 12:31:10 PM PDT 24
Peak memory 216364 kb
Host smart-2f3a8eb2-32f0-4462-aeaa-3a5866836f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446018706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.446018706
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3896535168
Short name T516
Test name
Test status
Simulation time 877178045 ps
CPU time 5.24 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 216288 kb
Host smart-7f25ee8e-9199-4696-bc7e-2124090eebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896535168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3896535168
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.570996939
Short name T131
Test name
Test status
Simulation time 274136318 ps
CPU time 1.88 seconds
Started May 21 12:30:43 PM PDT 24
Finished May 21 12:31:13 PM PDT 24
Peak memory 216332 kb
Host smart-57023fc2-9ff2-45ed-8334-f14519241d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570996939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.570996939
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.258928581
Short name T659
Test name
Test status
Simulation time 15707522 ps
CPU time 0.7 seconds
Started May 21 12:30:38 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 205744 kb
Host smart-2f3fe767-1328-4b65-8066-8ea3f9f55085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258928581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.258928581
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.823623038
Short name T707
Test name
Test status
Simulation time 18020693154 ps
CPU time 8.22 seconds
Started May 21 12:30:43 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 234352 kb
Host smart-5566b5dc-4e21-445a-b0e3-3b3e5ecab3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823623038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.823623038
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2058434547
Short name T933
Test name
Test status
Simulation time 16822982 ps
CPU time 0.69 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:14 PM PDT 24
Peak memory 205680 kb
Host smart-c25ffb5c-6722-4a74-a205-344a19b78bf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058434547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2058434547
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2982067175
Short name T78
Test name
Test status
Simulation time 38136193 ps
CPU time 0.73 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:18 PM PDT 24
Peak memory 205304 kb
Host smart-b9ebe015-6236-4cb3-9705-893385dcaf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982067175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2982067175
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1574547085
Short name T175
Test name
Test status
Simulation time 163328519778 ps
CPU time 195.81 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:34:33 PM PDT 24
Peak memory 255932 kb
Host smart-3dcfa403-308f-477b-a11c-b1a31f683391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574547085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1574547085
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.964624144
Short name T903
Test name
Test status
Simulation time 1387816501 ps
CPU time 18.05 seconds
Started May 21 12:30:47 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 240944 kb
Host smart-c05c5c8e-2c45-45b2-8fd7-bd788537f207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964624144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.964624144
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1526406204
Short name T293
Test name
Test status
Simulation time 1331134497 ps
CPU time 15.07 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 235452 kb
Host smart-f5e9d329-fbf7-4f7b-871e-f178a92cf253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526406204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1526406204
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1936112206
Short name T558
Test name
Test status
Simulation time 6375289802 ps
CPU time 10.79 seconds
Started May 21 12:30:49 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 232760 kb
Host smart-23306114-9d2e-4ed6-aaf9-65181b01d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936112206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1936112206
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1087528442
Short name T419
Test name
Test status
Simulation time 627193344 ps
CPU time 7.96 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:31:24 PM PDT 24
Peak memory 237896 kb
Host smart-5977558c-13b9-457e-b625-f430d3127e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087528442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1087528442
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2324654366
Short name T891
Test name
Test status
Simulation time 287809935 ps
CPU time 4.34 seconds
Started May 21 12:30:47 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 223656 kb
Host smart-c1524a00-69ac-4743-b922-3af18a078a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324654366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2324654366
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3600292407
Short name T852
Test name
Test status
Simulation time 212799412 ps
CPU time 2.4 seconds
Started May 21 12:30:48 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 218320 kb
Host smart-a37c64bb-52b9-43d7-be4e-2a1c79997a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600292407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3600292407
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.520689243
Short name T178
Test name
Test status
Simulation time 3301034731 ps
CPU time 11.59 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 224640 kb
Host smart-f2f95400-921d-4c5a-845e-382748871ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520689243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.520689243
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3928395730
Short name T615
Test name
Test status
Simulation time 491427146 ps
CPU time 4.24 seconds
Started May 21 12:30:44 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 218860 kb
Host smart-94c9b238-2201-439a-96db-dba4b7a2ca36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3928395730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3928395730
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4148142178
Short name T383
Test name
Test status
Simulation time 12013214352 ps
CPU time 15.48 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 216420 kb
Host smart-b33013a5-f2be-41f0-93e4-8326d576b6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148142178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4148142178
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1282912054
Short name T690
Test name
Test status
Simulation time 181427586 ps
CPU time 1.42 seconds
Started May 21 12:30:45 PM PDT 24
Finished May 21 12:31:15 PM PDT 24
Peak memory 207816 kb
Host smart-8d592b1e-9d93-4b50-bcd2-001b554e6461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282912054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1282912054
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2194667646
Short name T410
Test name
Test status
Simulation time 902339712 ps
CPU time 4.01 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:18 PM PDT 24
Peak memory 216264 kb
Host smart-c14bc0ed-b934-4b5a-9c12-52b27c7f25f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194667646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2194667646
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4204404171
Short name T691
Test name
Test status
Simulation time 55298941 ps
CPU time 0.88 seconds
Started May 21 12:30:55 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 205740 kb
Host smart-b1cb9ed2-b4cc-48f0-9c16-9f64b1c7f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204404171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4204404171
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1580215761
Short name T949
Test name
Test status
Simulation time 1256883546 ps
CPU time 4.52 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:24 PM PDT 24
Peak memory 223112 kb
Host smart-13719aa5-22dc-474b-a756-2fddebee6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580215761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1580215761
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1440473703
Short name T937
Test name
Test status
Simulation time 15597650 ps
CPU time 0.74 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:18 PM PDT 24
Peak memory 204636 kb
Host smart-1a2120e7-a2ab-416f-969f-b4225a8eb9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440473703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1440473703
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3453263013
Short name T134
Test name
Test status
Simulation time 220630976 ps
CPU time 2.24 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 216032 kb
Host smart-3f9edaff-e6bc-45f5-b474-618b093714cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453263013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3453263013
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3847562426
Short name T654
Test name
Test status
Simulation time 42284179 ps
CPU time 0.8 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 206348 kb
Host smart-ea394d2c-a65e-4e8f-b01c-8e69521b00cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847562426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3847562426
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3008312731
Short name T418
Test name
Test status
Simulation time 10499945435 ps
CPU time 33.97 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 232784 kb
Host smart-bb9c3993-f250-4237-9193-bef13c461491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008312731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3008312731
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.519652888
Short name T848
Test name
Test status
Simulation time 1036283274 ps
CPU time 29.55 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 236644 kb
Host smart-248ae41d-e2d2-4165-b314-803d26bcd50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519652888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.519652888
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2134348964
Short name T746
Test name
Test status
Simulation time 22739256360 ps
CPU time 81.1 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:32:40 PM PDT 24
Peak memory 266436 kb
Host smart-8c30d35d-834a-44a9-a2c8-635a0f3f8e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134348964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2134348964
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1083879898
Short name T314
Test name
Test status
Simulation time 946712514 ps
CPU time 10.16 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 240812 kb
Host smart-a7ff161a-348e-47ba-b766-d84e4b124528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083879898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1083879898
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3453935774
Short name T776
Test name
Test status
Simulation time 30742926 ps
CPU time 2.31 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 220920 kb
Host smart-2051a706-e9a0-4dc5-ad9c-3136dda99880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453935774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3453935774
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1618900291
Short name T15
Test name
Test status
Simulation time 277811494 ps
CPU time 2.72 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 232632 kb
Host smart-924e9ce2-20c8-448b-a6ec-5f8a3f9c906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618900291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1618900291
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1120272754
Short name T11
Test name
Test status
Simulation time 998309863 ps
CPU time 5.47 seconds
Started May 21 12:30:49 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 218352 kb
Host smart-ab357098-8656-4997-9149-4fa1542faf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120272754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1120272754
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3859575070
Short name T767
Test name
Test status
Simulation time 831074333 ps
CPU time 4.5 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 233652 kb
Host smart-82fb0f3f-e91b-4e86-93e1-d023578de69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859575070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3859575070
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3698057032
Short name T590
Test name
Test status
Simulation time 2102091037 ps
CPU time 11.97 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:30 PM PDT 24
Peak memory 220028 kb
Host smart-5e2eadcc-be10-4116-8e46-e8247c0d8dc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3698057032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3698057032
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2752077517
Short name T465
Test name
Test status
Simulation time 113855096 ps
CPU time 0.92 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 206428 kb
Host smart-c1a87d0d-8bc9-44ac-944f-281cf6ba4c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752077517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2752077517
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1929510620
Short name T545
Test name
Test status
Simulation time 2661232763 ps
CPU time 23.31 seconds
Started May 21 12:30:47 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 216440 kb
Host smart-53ec7374-dd78-4e99-b21f-2d5c20d369a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929510620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1929510620
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3975220519
Short name T501
Test name
Test status
Simulation time 14221293909 ps
CPU time 10.66 seconds
Started May 21 12:31:29 PM PDT 24
Finished May 21 12:32:02 PM PDT 24
Peak memory 216436 kb
Host smart-844483a3-35ff-4764-9f7b-bc5203aa6b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975220519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3975220519
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1598332576
Short name T332
Test name
Test status
Simulation time 772911351 ps
CPU time 2.04 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:16 PM PDT 24
Peak memory 207944 kb
Host smart-510b1aee-9cd2-4a2a-a20a-d5f86ce77517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598332576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1598332576
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2746703729
Short name T337
Test name
Test status
Simulation time 38758919 ps
CPU time 0.72 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 205728 kb
Host smart-8465e746-5107-40a9-9681-995640a3c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746703729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2746703729
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.158798915
Short name T453
Test name
Test status
Simulation time 1426762210 ps
CPU time 6.01 seconds
Started May 21 12:30:46 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 220324 kb
Host smart-dadada0e-e963-4f80-b1f0-0654b90055d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158798915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.158798915
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3777895127
Short name T817
Test name
Test status
Simulation time 12765099 ps
CPU time 0.69 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:19 PM PDT 24
Peak memory 204724 kb
Host smart-75f5c8c5-d0a8-4cd7-9ba1-f647bf1d8897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777895127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3777895127
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3802753566
Short name T93
Test name
Test status
Simulation time 294251429 ps
CPU time 2.68 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 218592 kb
Host smart-2a80e85c-068e-4eb0-85a4-8482a6d1042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802753566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3802753566
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3759709314
Short name T529
Test name
Test status
Simulation time 27604742 ps
CPU time 0.79 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 206628 kb
Host smart-b8e2c5aa-cb2e-4766-ac25-a16be7566be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759709314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3759709314
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3673186633
Short name T286
Test name
Test status
Simulation time 25201722424 ps
CPU time 78.83 seconds
Started May 21 12:30:56 PM PDT 24
Finished May 21 12:32:42 PM PDT 24
Peak memory 255864 kb
Host smart-270b31d2-3282-49c6-98a5-c3961600f973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673186633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3673186633
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3206294828
Short name T244
Test name
Test status
Simulation time 2738273119 ps
CPU time 56.65 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:32:18 PM PDT 24
Peak memory 254148 kb
Host smart-37aabe22-5698-4a0b-ad81-1ffed5218c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206294828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3206294828
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3793239281
Short name T498
Test name
Test status
Simulation time 59790935805 ps
CPU time 277.12 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:35:55 PM PDT 24
Peak memory 241076 kb
Host smart-810bae9e-596b-4b21-8c7d-2302c218038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793239281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3793239281
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.198497970
Short name T839
Test name
Test status
Simulation time 5035345786 ps
CPU time 13.82 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 239772 kb
Host smart-7c958b2a-5d1d-41b8-aad5-1f037644c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198497970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.198497970
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.36715140
Short name T694
Test name
Test status
Simulation time 1258476446 ps
CPU time 2.18 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 216084 kb
Host smart-c831008a-6aed-4bd1-bb7e-21d2a36502f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36715140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.36715140
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.996886989
Short name T896
Test name
Test status
Simulation time 5306151613 ps
CPU time 6.14 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:33 PM PDT 24
Peak memory 223048 kb
Host smart-58235ebc-3d79-41c9-95ef-674a0cdf586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996886989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.996886989
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.10646856
Short name T679
Test name
Test status
Simulation time 7531321404 ps
CPU time 7.55 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 224688 kb
Host smart-7669b84d-3dad-47c8-b2f5-b7d6fe1a8301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10646856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.10646856
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2586411809
Short name T222
Test name
Test status
Simulation time 1411014226 ps
CPU time 7.15 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 240832 kb
Host smart-a3809795-d687-4d39-a551-356e62ecd08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586411809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2586411809
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3803659453
Short name T53
Test name
Test status
Simulation time 648131076 ps
CPU time 9.42 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 220304 kb
Host smart-c2c50016-cd4d-404d-b1c1-23c37bc96bc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3803659453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3803659453
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2521644551
Short name T48
Test name
Test status
Simulation time 104110706371 ps
CPU time 508.83 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:39:49 PM PDT 24
Peak memory 257464 kb
Host smart-91902f04-a039-4239-aeaa-483a4861a5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521644551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2521644551
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3744838644
Short name T871
Test name
Test status
Simulation time 2141077887 ps
CPU time 20.91 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:46 PM PDT 24
Peak memory 216564 kb
Host smart-e4e22bd0-b50d-4a3e-bbf5-637f1f173baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744838644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3744838644
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1160229482
Short name T605
Test name
Test status
Simulation time 42864766 ps
CPU time 0.76 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 205764 kb
Host smart-eda3c018-dbd5-4f71-8948-a39d8d4b78f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160229482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1160229482
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.881098863
Short name T496
Test name
Test status
Simulation time 197900810 ps
CPU time 1.22 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:26 PM PDT 24
Peak memory 208096 kb
Host smart-5f426a6e-6235-4267-826c-b1f77cf4b815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881098863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.881098863
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.985343532
Short name T515
Test name
Test status
Simulation time 67001978 ps
CPU time 0.76 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 205740 kb
Host smart-39cc87a3-4e9c-4117-95c9-bb8fdf8c85bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985343532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.985343532
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.39385329
Short name T922
Test name
Test status
Simulation time 142919831 ps
CPU time 2.25 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 220948 kb
Host smart-999d753a-c0e1-4d65-81bc-18dc13da1ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39385329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.39385329
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3597539337
Short name T897
Test name
Test status
Simulation time 30451049 ps
CPU time 0.74 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 204604 kb
Host smart-1ebd8d5e-9fd2-40c2-9b9d-8fb750561750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597539337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3597539337
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1573238996
Short name T492
Test name
Test status
Simulation time 565429696 ps
CPU time 3.93 seconds
Started May 21 12:30:56 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 232624 kb
Host smart-dea1eff5-060c-44d3-86e7-3ab1d75e57c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573238996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1573238996
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.541088453
Short name T584
Test name
Test status
Simulation time 15582240 ps
CPU time 0.79 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 206340 kb
Host smart-881b0cec-f250-42a8-8ffa-4fa0390478cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541088453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.541088453
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4290836164
Short name T435
Test name
Test status
Simulation time 107684608038 ps
CPU time 190.88 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:34:32 PM PDT 24
Peak memory 240960 kb
Host smart-f424aee5-2d0a-477a-9a27-b24e2188502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290836164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4290836164
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.518243375
Short name T296
Test name
Test status
Simulation time 70343919183 ps
CPU time 200.93 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:34:42 PM PDT 24
Peak memory 252576 kb
Host smart-fc720779-3935-4ec6-9a83-1aa86a438c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518243375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.518243375
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3597034604
Short name T408
Test name
Test status
Simulation time 37555230284 ps
CPU time 315.96 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:36:41 PM PDT 24
Peak memory 251328 kb
Host smart-af73caa1-838a-442a-af7f-30bf310887fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597034604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3597034604
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1026421858
Short name T147
Test name
Test status
Simulation time 275164941 ps
CPU time 7.67 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 224460 kb
Host smart-e53e5776-b5f3-466b-863c-b7ec7ca5086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026421858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1026421858
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.62913672
Short name T876
Test name
Test status
Simulation time 110994072 ps
CPU time 4.34 seconds
Started May 21 12:30:56 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 233612 kb
Host smart-f7f14891-8319-4e39-96b6-3c600af2254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62913672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.62913672
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3557005819
Short name T223
Test name
Test status
Simulation time 3398249064 ps
CPU time 14.95 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:39 PM PDT 24
Peak memory 229288 kb
Host smart-a0bc8cca-7859-4fb8-9f22-72804df45645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557005819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3557005819
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1392462472
Short name T33
Test name
Test status
Simulation time 1633741955 ps
CPU time 7.14 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 220524 kb
Host smart-18984979-b403-4f5c-af3e-7f056b40e972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392462472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1392462472
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2923702567
Short name T150
Test name
Test status
Simulation time 704002294 ps
CPU time 4.68 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 233192 kb
Host smart-153fdc66-d651-4f91-935f-ac5090283b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923702567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2923702567
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1355532544
Short name T146
Test name
Test status
Simulation time 140287419 ps
CPU time 3.48 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 219748 kb
Host smart-81b370e4-6761-416a-8e12-b30055a8e97f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1355532544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1355532544
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2478609815
Short name T160
Test name
Test status
Simulation time 69293770347 ps
CPU time 194.13 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:34:32 PM PDT 24
Peak memory 252280 kb
Host smart-21a2439e-4bbd-441f-99d3-4406ed0ba6cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478609815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2478609815
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2513981039
Short name T329
Test name
Test status
Simulation time 816407764 ps
CPU time 11.75 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 216408 kb
Host smart-0518fe3d-d77c-4f84-bdd1-7b7eb3d2c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513981039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2513981039
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2859515042
Short name T742
Test name
Test status
Simulation time 1786549553 ps
CPU time 6.33 seconds
Started May 21 12:30:56 PM PDT 24
Finished May 21 12:31:30 PM PDT 24
Peak memory 216120 kb
Host smart-fefc511c-bbd9-459d-b550-34a657f67c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859515042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2859515042
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.264462938
Short name T361
Test name
Test status
Simulation time 134583739 ps
CPU time 0.81 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 206452 kb
Host smart-c89164e9-f3e5-4ee4-bf9e-89fb71ea1868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264462938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.264462938
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.664070930
Short name T602
Test name
Test status
Simulation time 15394087 ps
CPU time 0.69 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 205728 kb
Host smart-31aff2f3-35f6-4c41-a3c3-29c3af493425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664070930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.664070930
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3693498532
Short name T745
Test name
Test status
Simulation time 3122898089 ps
CPU time 12.77 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:33 PM PDT 24
Peak memory 237556 kb
Host smart-6fa7f78a-c630-4a5b-8cae-95045f9af555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693498532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3693498532
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1856859955
Short name T788
Test name
Test status
Simulation time 38166848 ps
CPU time 0.69 seconds
Started May 21 12:30:56 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 205228 kb
Host smart-9d1477c3-ff30-4905-bfac-a4e41e0af9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856859955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1856859955
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3880068222
Short name T368
Test name
Test status
Simulation time 589643734 ps
CPU time 3.4 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 233552 kb
Host smart-3e7bffdb-91a7-4089-88b6-080d310db5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880068222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3880068222
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3743809143
Short name T722
Test name
Test status
Simulation time 25976681 ps
CPU time 0.76 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 206340 kb
Host smart-10b484c7-ce17-403d-8405-c76f1cf52c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743809143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3743809143
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.612372775
Short name T935
Test name
Test status
Simulation time 183370481686 ps
CPU time 269.43 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:35:54 PM PDT 24
Peak memory 254680 kb
Host smart-8d7eb8d7-78a5-4fbd-8ca2-4e5e481b9e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612372775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.612372775
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4031047037
Short name T851
Test name
Test status
Simulation time 3049980092 ps
CPU time 23.23 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:41 PM PDT 24
Peak memory 217604 kb
Host smart-4c0357fe-eb2e-4876-aff6-77d478a126db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031047037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4031047037
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.915745205
Short name T192
Test name
Test status
Simulation time 4150304010 ps
CPU time 52.61 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:32:14 PM PDT 24
Peak memory 239740 kb
Host smart-6b48eb9f-d3b2-44e2-84e7-99aac4fbe6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915745205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.915745205
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1369521358
Short name T58
Test name
Test status
Simulation time 857785237 ps
CPU time 7.76 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 224364 kb
Host smart-34ccb8b0-b6cd-4ea2-99ac-8ba8a17c49fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369521358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1369521358
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3165192400
Short name T541
Test name
Test status
Simulation time 8301845907 ps
CPU time 6.04 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:26 PM PDT 24
Peak memory 224452 kb
Host smart-8eeab7f0-ca59-4d00-ac80-7f6258758778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165192400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3165192400
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2916781372
Short name T170
Test name
Test status
Simulation time 1351294098 ps
CPU time 6.03 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 237948 kb
Host smart-b9875250-cc91-4f20-95d8-b9b37cd1ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916781372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2916781372
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1832250290
Short name T29
Test name
Test status
Simulation time 9250433891 ps
CPU time 21 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:46 PM PDT 24
Peak memory 232772 kb
Host smart-0152c000-382f-4450-adef-158a7d9eca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832250290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1832250290
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1374396614
Short name T772
Test name
Test status
Simulation time 18723077132 ps
CPU time 9.9 seconds
Started May 21 12:30:55 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 234044 kb
Host smart-e33efa96-77c1-4774-9603-f4f014b30973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374396614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1374396614
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3048505989
Short name T929
Test name
Test status
Simulation time 4906948630 ps
CPU time 10.64 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:37 PM PDT 24
Peak memory 222892 kb
Host smart-854ad39b-a6b1-48b3-9bf0-fa2877ee10e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3048505989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3048505989
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.632382884
Short name T879
Test name
Test status
Simulation time 54250050817 ps
CPU time 154.57 seconds
Started May 21 12:31:07 PM PDT 24
Finished May 21 12:34:07 PM PDT 24
Peak memory 237356 kb
Host smart-eb6ec31f-ccdc-4e7a-acc5-632a3ae7aa60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632382884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.632382884
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1630407832
Short name T943
Test name
Test status
Simulation time 3687738946 ps
CPU time 5.85 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:30 PM PDT 24
Peak memory 216348 kb
Host smart-bf8149d0-366e-4cc9-b8a0-d27aac768bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630407832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1630407832
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1450535232
Short name T775
Test name
Test status
Simulation time 154565742 ps
CPU time 1.83 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:23 PM PDT 24
Peak memory 207872 kb
Host smart-adde3aca-aff0-4c3f-a0b6-7f335a557243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450535232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1450535232
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.93814983
Short name T385
Test name
Test status
Simulation time 235832169 ps
CPU time 4.54 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:26 PM PDT 24
Peak memory 216256 kb
Host smart-c1253757-262b-400c-8ab8-7e60b9a1e119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93814983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.93814983
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3404478164
Short name T365
Test name
Test status
Simulation time 515341668 ps
CPU time 0.86 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:20 PM PDT 24
Peak memory 206160 kb
Host smart-711c9c60-52f0-4e32-a51d-b8878a23284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404478164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3404478164
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.218732296
Short name T609
Test name
Test status
Simulation time 681379351 ps
CPU time 4.02 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 216268 kb
Host smart-6d72e216-64f6-4dd0-a940-8a4906211766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218732296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.218732296
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3999842443
Short name T420
Test name
Test status
Simulation time 19115135 ps
CPU time 0.68 seconds
Started May 21 12:29:49 PM PDT 24
Finished May 21 12:30:19 PM PDT 24
Peak memory 204628 kb
Host smart-cd231585-67e2-4fc1-a9aa-8ce5f8720628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999842443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
999842443
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1935166342
Short name T37
Test name
Test status
Simulation time 964613956 ps
CPU time 3.79 seconds
Started May 21 12:29:41 PM PDT 24
Finished May 21 12:30:11 PM PDT 24
Peak memory 218736 kb
Host smart-8463b7c5-7a94-4b3a-8b92-95f9923dcd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935166342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1935166342
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3671320921
Short name T642
Test name
Test status
Simulation time 27418292 ps
CPU time 0.79 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:13 PM PDT 24
Peak memory 206412 kb
Host smart-190d98d2-8880-4f4f-be62-a7a787adae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671320921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3671320921
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.17384145
Short name T762
Test name
Test status
Simulation time 13054265477 ps
CPU time 18.12 seconds
Started May 21 12:29:42 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 240520 kb
Host smart-50aec3f1-1865-4c8f-b0e9-5e34dcbc93a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17384145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.17384145
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4292159907
Short name T502
Test name
Test status
Simulation time 19980066837 ps
CPU time 180.93 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:33:17 PM PDT 24
Peak memory 249304 kb
Host smart-e3002cac-d7c6-4b48-9640-f95c3867bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292159907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4292159907
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1697039751
Short name T924
Test name
Test status
Simulation time 16687053018 ps
CPU time 151.95 seconds
Started May 21 12:29:47 PM PDT 24
Finished May 21 12:32:49 PM PDT 24
Peak memory 249316 kb
Host smart-4eee3b72-e464-4a63-abd0-748a5af85267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697039751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1697039751
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1225932587
Short name T787
Test name
Test status
Simulation time 3711908990 ps
CPU time 51.97 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:31:05 PM PDT 24
Peak memory 250976 kb
Host smart-999f47ed-b563-4710-9037-3321e0be00fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225932587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1225932587
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.543409166
Short name T221
Test name
Test status
Simulation time 760672958 ps
CPU time 11.22 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 234820 kb
Host smart-62a890f9-2722-47c2-9c23-20ecd410c5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543409166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.543409166
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.848374641
Short name T77
Test name
Test status
Simulation time 182471568 ps
CPU time 3.66 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 222524 kb
Host smart-6963b7a2-eaf4-4030-875c-a1eeb4881f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848374641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.848374641
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2601197276
Short name T506
Test name
Test status
Simulation time 52459779 ps
CPU time 1.06 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:14 PM PDT 24
Peak memory 216640 kb
Host smart-bc3f73cc-e14c-4b2c-a1e4-1d4a8b3cf345
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601197276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2601197276
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3640553511
Short name T300
Test name
Test status
Simulation time 7101699810 ps
CPU time 21.03 seconds
Started May 21 12:29:42 PM PDT 24
Finished May 21 12:30:29 PM PDT 24
Peak memory 237068 kb
Host smart-1e696645-b455-4521-9c0d-15606080ceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640553511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3640553511
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.952395628
Short name T702
Test name
Test status
Simulation time 14087048526 ps
CPU time 13.24 seconds
Started May 21 12:29:41 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 224084 kb
Host smart-608c8385-2b28-4ab9-951b-d6556718a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952395628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.952395628
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1170160561
Short name T503
Test name
Test status
Simulation time 1220203455 ps
CPU time 13.04 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:30:30 PM PDT 24
Peak memory 222844 kb
Host smart-72df696d-3409-46e0-8e4a-c9fb70838402
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1170160561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1170160561
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1348458966
Short name T67
Test name
Test status
Simulation time 312469387 ps
CPU time 1.08 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:15 PM PDT 24
Peak memory 235108 kb
Host smart-460f1390-a1d9-4a75-81b0-ed3cfff2afed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348458966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1348458966
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.281472166
Short name T63
Test name
Test status
Simulation time 8051756300 ps
CPU time 26.6 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:46 PM PDT 24
Peak memory 237360 kb
Host smart-51dab724-bc13-42c0-8e30-e0dac0e170bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281472166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.281472166
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3483182495
Short name T802
Test name
Test status
Simulation time 19172330495 ps
CPU time 29.83 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 216460 kb
Host smart-9b6e4cbf-e3fd-4197-88f4-4201bbd25896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483182495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3483182495
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2399938940
Short name T973
Test name
Test status
Simulation time 1245422224 ps
CPU time 2.78 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 216284 kb
Host smart-e02340e3-3c02-41fc-95b8-219ccb02d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399938940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2399938940
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.426484496
Short name T479
Test name
Test status
Simulation time 99579241 ps
CPU time 0.81 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:30:10 PM PDT 24
Peak memory 205644 kb
Host smart-309f28b2-521e-4a85-b7f7-178c84487bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426484496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.426484496
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.63371433
Short name T684
Test name
Test status
Simulation time 23337955 ps
CPU time 0.71 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:14 PM PDT 24
Peak memory 205360 kb
Host smart-bc30e868-984d-40d8-9f91-cb4dd6aca08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63371433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.63371433
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2382259680
Short name T76
Test name
Test status
Simulation time 852216721 ps
CPU time 6.85 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 218544 kb
Host smart-9d574868-b443-444e-aa8f-04fc7887eed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382259680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2382259680
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3918326599
Short name T613
Test name
Test status
Simulation time 45282785 ps
CPU time 0.78 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 204668 kb
Host smart-db5cf400-9aa2-4768-ae79-173f7079862d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918326599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3918326599
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1892241313
Short name T451
Test name
Test status
Simulation time 54407494 ps
CPU time 2.06 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:30 PM PDT 24
Peak memory 216196 kb
Host smart-b82a314a-02f6-4183-ab5c-79bbe2080c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892241313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1892241313
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3578494818
Short name T813
Test name
Test status
Simulation time 77316223 ps
CPU time 0.8 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:21 PM PDT 24
Peak memory 206368 kb
Host smart-d997111e-a17f-4026-8cb0-069f14dced38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578494818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3578494818
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3128434378
Short name T366
Test name
Test status
Simulation time 7767888797 ps
CPU time 21.46 seconds
Started May 21 12:31:03 PM PDT 24
Finished May 21 12:31:50 PM PDT 24
Peak memory 249216 kb
Host smart-1c5f68eb-3ae3-4c67-be4a-7a2b173c30c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128434378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3128434378
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.320487174
Short name T727
Test name
Test status
Simulation time 16213213797 ps
CPU time 26.82 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 234992 kb
Host smart-f694553a-8039-4ce9-84a4-b2d49c92b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320487174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.320487174
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.314844592
Short name T525
Test name
Test status
Simulation time 4499730040 ps
CPU time 84.7 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:32:51 PM PDT 24
Peak memory 264980 kb
Host smart-36b3b2a5-d8ce-4fc0-a4eb-e9aaafdea6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314844592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.314844592
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2606926019
Short name T616
Test name
Test status
Simulation time 2192007866 ps
CPU time 32.4 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:57 PM PDT 24
Peak memory 224668 kb
Host smart-9b4765b9-e83b-44b3-ae98-81186a828e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606926019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2606926019
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3167945212
Short name T576
Test name
Test status
Simulation time 3158617091 ps
CPU time 23.1 seconds
Started May 21 12:30:54 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 235452 kb
Host smart-c10a8f00-ccde-4a0d-815a-a0ac29cb80e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167945212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3167945212
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.612980837
Short name T298
Test name
Test status
Simulation time 2192814104 ps
CPU time 20.22 seconds
Started May 21 12:30:56 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 235124 kb
Host smart-1e564823-de8b-4f1d-9982-e399557897b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612980837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.612980837
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2122162115
Short name T94
Test name
Test status
Simulation time 27072226093 ps
CPU time 15.77 seconds
Started May 21 12:30:51 PM PDT 24
Finished May 21 12:31:33 PM PDT 24
Peak memory 224548 kb
Host smart-eeddbd1b-da90-47b0-aa28-7dbbe0beaf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122162115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2122162115
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2966829319
Short name T491
Test name
Test status
Simulation time 27352906127 ps
CPU time 11.02 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 224508 kb
Host smart-8ddd4356-4533-49bb-aa69-f4a09965d825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966829319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2966829319
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2526463916
Short name T428
Test name
Test status
Simulation time 974201310 ps
CPU time 10.4 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 219832 kb
Host smart-4775c71e-ea5e-4c77-a583-156a44153fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2526463916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2526463916
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.384485108
Short name T877
Test name
Test status
Simulation time 4165999985 ps
CPU time 83.98 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:32:51 PM PDT 24
Peak memory 256184 kb
Host smart-4ce5e4cd-1091-4fd5-af77-2b9268908e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384485108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.384485108
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1309180912
Short name T43
Test name
Test status
Simulation time 4123199898 ps
CPU time 7.25 seconds
Started May 21 12:30:55 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 219584 kb
Host smart-b6160da3-7133-482d-b7c2-0e23aab68ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309180912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1309180912
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1387035259
Short name T867
Test name
Test status
Simulation time 2665611663 ps
CPU time 3.25 seconds
Started May 21 12:30:52 PM PDT 24
Finished May 21 12:31:22 PM PDT 24
Peak memory 216400 kb
Host smart-6e562fbf-30e9-4c9d-8916-b25f777ed85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387035259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1387035259
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1649815674
Short name T480
Test name
Test status
Simulation time 22135352 ps
CPU time 1 seconds
Started May 21 12:30:53 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 207144 kb
Host smart-49a84f8f-233b-41db-9cc7-e79bcfe2b75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649815674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1649815674
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3172349847
Short name T865
Test name
Test status
Simulation time 18220825 ps
CPU time 0.75 seconds
Started May 21 12:30:50 PM PDT 24
Finished May 21 12:31:17 PM PDT 24
Peak memory 205812 kb
Host smart-a0988c12-4cdb-461c-a6a3-e533fb076365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172349847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3172349847
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3220020077
Short name T570
Test name
Test status
Simulation time 952604158 ps
CPU time 2.54 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 218452 kb
Host smart-4c72f57d-59aa-43d7-a3ae-d1ae38f98b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220020077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3220020077
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3780769159
Short name T718
Test name
Test status
Simulation time 22485402 ps
CPU time 0.72 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 205256 kb
Host smart-8b9926c1-154d-4817-b708-42fbb4f3dde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780769159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3780769159
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1464711438
Short name T35
Test name
Test status
Simulation time 311381732 ps
CPU time 3.78 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 234028 kb
Host smart-8db1a35d-a970-4a07-81fb-adedb038eeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464711438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1464711438
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1762244987
Short name T557
Test name
Test status
Simulation time 18440325 ps
CPU time 0.75 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 205296 kb
Host smart-7553428b-83c4-4e89-b187-7ead65584cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762244987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1762244987
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2647300913
Short name T611
Test name
Test status
Simulation time 218743518094 ps
CPU time 87.2 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:32:54 PM PDT 24
Peak memory 240904 kb
Host smart-0c58f9f0-0125-498b-b11f-70f3e4ea19e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647300913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2647300913
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.604280931
Short name T287
Test name
Test status
Simulation time 3629103190 ps
CPU time 82.9 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:32:48 PM PDT 24
Peak memory 249344 kb
Host smart-684a8ead-2d1f-46b4-8c58-a19cd2a075e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604280931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.604280931
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.661114037
Short name T449
Test name
Test status
Simulation time 990446460 ps
CPU time 5.95 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 224400 kb
Host smart-566279b8-4739-4a3b-9a7a-91c6ea324f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661114037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.661114037
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3499821986
Short name T292
Test name
Test status
Simulation time 2349396397 ps
CPU time 13.77 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:39 PM PDT 24
Peak memory 233780 kb
Host smart-d0d48573-3c49-4a13-8ffd-1dcf0109f0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499821986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3499821986
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3515845960
Short name T91
Test name
Test status
Simulation time 897276929 ps
CPU time 9.75 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 232612 kb
Host smart-d178cebe-f8a3-4b6b-917f-6a549b388582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515845960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3515845960
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.228558282
Short name T914
Test name
Test status
Simulation time 3790537107 ps
CPU time 11.81 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 219120 kb
Host smart-7ffb7742-bfb3-4aef-a5dc-bb6b8a7159ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228558282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.228558282
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3521062273
Short name T434
Test name
Test status
Simulation time 228255912 ps
CPU time 2.87 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 218516 kb
Host smart-febf0bfa-1e99-4d5c-9a4b-8fe2db78bdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521062273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3521062273
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2989444767
Short name T606
Test name
Test status
Simulation time 4704339979 ps
CPU time 6.84 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:35 PM PDT 24
Peak memory 222008 kb
Host smart-abb0c313-0561-4b5b-aff6-f97c6f37d689
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2989444767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2989444767
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3192481621
Short name T375
Test name
Test status
Simulation time 17082177 ps
CPU time 0.73 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 205512 kb
Host smart-5fb05058-1486-41d4-9b82-08aa69ab75d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192481621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3192481621
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2771718745
Short name T632
Test name
Test status
Simulation time 1468446156 ps
CPU time 6.5 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 216196 kb
Host smart-347f679a-0a24-4eaa-9839-4d9d7ba8c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771718745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2771718745
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2230456737
Short name T820
Test name
Test status
Simulation time 1366947162 ps
CPU time 4.33 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 216340 kb
Host smart-a749f15a-f827-48db-8cc2-809c5291bddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230456737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2230456737
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3635286723
Short name T819
Test name
Test status
Simulation time 42003202 ps
CPU time 0.76 seconds
Started May 21 12:31:10 PM PDT 24
Finished May 21 12:31:35 PM PDT 24
Peak memory 205692 kb
Host smart-05df3ee3-edfd-4421-bce2-b0554fd94a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635286723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3635286723
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1435423693
Short name T607
Test name
Test status
Simulation time 83108493 ps
CPU time 2.46 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 224520 kb
Host smart-cd9505cf-4ece-44c6-bd2d-7a541123cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435423693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1435423693
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1480910841
Short name T953
Test name
Test status
Simulation time 93679601 ps
CPU time 0.71 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 205288 kb
Host smart-7f1ba14f-c9b5-4fb1-afa5-52e98ba8c751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480910841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1480910841
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3444696918
Short name T354
Test name
Test status
Simulation time 267360847 ps
CPU time 2.28 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 224412 kb
Host smart-2ac86b24-8d81-4bc3-94e8-0ee9674232f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444696918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3444696918
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4028937183
Short name T391
Test name
Test status
Simulation time 96527129 ps
CPU time 0.72 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 205336 kb
Host smart-ba5e0b56-acfd-4956-b9e9-9d424693accb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028937183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4028937183
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1104517942
Short name T235
Test name
Test status
Simulation time 101630540305 ps
CPU time 53.17 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:32:18 PM PDT 24
Peak memory 224680 kb
Host smart-64f34544-f325-4756-90cf-2f77577fb264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104517942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1104517942
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3091867952
Short name T257
Test name
Test status
Simulation time 12144134178 ps
CPU time 91.22 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:32:58 PM PDT 24
Peak memory 250300 kb
Host smart-30809c21-2fae-41e3-b696-0a9fa901c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091867952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3091867952
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.240582229
Short name T135
Test name
Test status
Simulation time 43290971511 ps
CPU time 138.52 seconds
Started May 21 12:31:04 PM PDT 24
Finished May 21 12:33:49 PM PDT 24
Peak memory 252492 kb
Host smart-e364fc25-0f41-4856-a521-009203ebe7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240582229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.240582229
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2178084889
Short name T960
Test name
Test status
Simulation time 2128644807 ps
CPU time 15.96 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:41 PM PDT 24
Peak memory 235204 kb
Host smart-3821ca7d-a30f-4767-8c9d-cdb7596b3d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178084889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2178084889
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2759074473
Short name T305
Test name
Test status
Simulation time 12621507637 ps
CPU time 125.2 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:33:30 PM PDT 24
Peak memory 231904 kb
Host smart-b36c86d5-204d-41d0-aa67-15b9560ff323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759074473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2759074473
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1635216554
Short name T827
Test name
Test status
Simulation time 9134646846 ps
CPU time 8.36 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 239280 kb
Host smart-97541243-4684-41dc-994c-acd7edb427db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635216554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1635216554
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2607503901
Short name T932
Test name
Test status
Simulation time 420997457 ps
CPU time 6.68 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 233564 kb
Host smart-283284f9-36ef-47f2-8d18-bf4f906284b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607503901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2607503901
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.294744178
Short name T873
Test name
Test status
Simulation time 147213655 ps
CPU time 4.29 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 222976 kb
Host smart-1ab76170-a30b-4c2b-9801-e889852f0318
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=294744178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.294744178
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3780083043
Short name T230
Test name
Test status
Simulation time 265621516773 ps
CPU time 234.55 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:35:19 PM PDT 24
Peak memory 249268 kb
Host smart-ded1e377-5f6b-4b9a-a1ab-001f2ffa6a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780083043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3780083043
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2456831790
Short name T499
Test name
Test status
Simulation time 707940397 ps
CPU time 11.23 seconds
Started May 21 12:30:58 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 216280 kb
Host smart-200f8219-a6ce-4835-9cc6-1f816008147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456831790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2456831790
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1131933063
Short name T829
Test name
Test status
Simulation time 9633365371 ps
CPU time 9.52 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 216396 kb
Host smart-815ed220-84ff-4960-87bb-f2ff32b40ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131933063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1131933063
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2381914432
Short name T519
Test name
Test status
Simulation time 78044482 ps
CPU time 1.98 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 216348 kb
Host smart-cc049024-a66a-4b48-9735-ba247a9d7668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381914432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2381914432
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2149905462
Short name T578
Test name
Test status
Simulation time 123002442 ps
CPU time 0.77 seconds
Started May 21 12:30:59 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 205728 kb
Host smart-f1447d33-5244-44af-9286-8a03456e0a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149905462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2149905462
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.512404745
Short name T367
Test name
Test status
Simulation time 40342568754 ps
CPU time 31.5 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:59 PM PDT 24
Peak memory 238860 kb
Host smart-89a51f36-5399-4b30-b5ca-7804e2f186f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512404745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.512404745
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3533503206
Short name T592
Test name
Test status
Simulation time 61203049 ps
CPU time 0.72 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 204660 kb
Host smart-4cac65b2-19f4-41a4-b190-bea530b974b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533503206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3533503206
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2735339138
Short name T603
Test name
Test status
Simulation time 122007886 ps
CPU time 3.87 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 234588 kb
Host smart-4fc57b7c-947c-487c-add6-7ef26e182b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735339138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2735339138
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2977380754
Short name T841
Test name
Test status
Simulation time 23077156 ps
CPU time 0.78 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 206656 kb
Host smart-0f23ea85-18b7-46fb-bbbc-95ae1af7c872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977380754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2977380754
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.597956883
Short name T169
Test name
Test status
Simulation time 358692096 ps
CPU time 7.23 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 224572 kb
Host smart-997099a7-a90d-4378-a33f-a4e66ac1bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597956883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.597956883
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.378614516
Short name T311
Test name
Test status
Simulation time 24037153805 ps
CPU time 126.92 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:33:57 PM PDT 24
Peak memory 249292 kb
Host smart-1cb68423-ac88-498e-aa6e-e51226dbebf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378614516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.378614516
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2650382425
Short name T315
Test name
Test status
Simulation time 375486020 ps
CPU time 4.38 seconds
Started May 21 12:31:01 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 219724 kb
Host smart-8a89f3d4-86b6-4a38-af9f-2811328acce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650382425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2650382425
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1619115112
Short name T798
Test name
Test status
Simulation time 2226179515 ps
CPU time 13.83 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 233732 kb
Host smart-05abce83-53aa-4549-95f7-7aa4d00c2f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619115112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1619115112
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3533504859
Short name T658
Test name
Test status
Simulation time 4296721975 ps
CPU time 35.01 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 234980 kb
Host smart-55658caf-ae0c-4235-808a-8881a3fd4da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533504859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3533504859
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2457444190
Short name T208
Test name
Test status
Simulation time 5995061795 ps
CPU time 10.97 seconds
Started May 21 12:31:37 PM PDT 24
Finished May 21 12:32:08 PM PDT 24
Peak memory 236012 kb
Host smart-14310ce5-67d4-42f2-b8c8-f7f04e182c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457444190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2457444190
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4228060638
Short name T216
Test name
Test status
Simulation time 375249576 ps
CPU time 4.96 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 218856 kb
Host smart-bd9bd410-c001-413d-81cb-92c643816c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228060638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4228060638
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1231105086
Short name T144
Test name
Test status
Simulation time 1152332817 ps
CPU time 5.67 seconds
Started May 21 12:31:02 PM PDT 24
Finished May 21 12:31:33 PM PDT 24
Peak memory 221568 kb
Host smart-6c9c8b50-6465-4742-b95f-9f3e135ebf2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1231105086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1231105086
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3421502919
Short name T164
Test name
Test status
Simulation time 697670434 ps
CPU time 13.47 seconds
Started May 21 12:31:14 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 237892 kb
Host smart-e4217b93-4f93-4063-ae72-e41bb4d980a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421502919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3421502919
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.448675615
Short name T409
Test name
Test status
Simulation time 19341213 ps
CPU time 0.72 seconds
Started May 21 12:30:57 PM PDT 24
Finished May 21 12:31:25 PM PDT 24
Peak memory 205596 kb
Host smart-c270e94e-a490-4620-83f8-58f498f17700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448675615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.448675615
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3558004403
Short name T840
Test name
Test status
Simulation time 94175195 ps
CPU time 1.02 seconds
Started May 21 12:31:18 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 207644 kb
Host smart-7660e27f-f28a-4f64-ae48-4f3c2c92254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558004403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3558004403
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1648017000
Short name T656
Test name
Test status
Simulation time 17325575 ps
CPU time 0.77 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:31:27 PM PDT 24
Peak memory 205736 kb
Host smart-2d88cafb-d92a-48a4-8f45-4e5cae6c147e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648017000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1648017000
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1261974415
Short name T708
Test name
Test status
Simulation time 2215160555 ps
CPU time 1.14 seconds
Started May 21 12:31:00 PM PDT 24
Finished May 21 12:31:28 PM PDT 24
Peak memory 206856 kb
Host smart-be31b310-8720-403d-9ec0-c08da831192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261974415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1261974415
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.114100868
Short name T209
Test name
Test status
Simulation time 541674154 ps
CPU time 5.33 seconds
Started May 21 12:31:24 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 239756 kb
Host smart-a28e7362-7999-401f-860f-ee62a7630be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114100868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.114100868
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.469194040
Short name T423
Test name
Test status
Simulation time 41207806 ps
CPU time 0.79 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 205668 kb
Host smart-17f27cbd-26d3-47cf-b868-6f8ece8ed92f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469194040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.469194040
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3549808165
Short name T92
Test name
Test status
Simulation time 237109626 ps
CPU time 4.91 seconds
Started May 21 12:31:09 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 217548 kb
Host smart-4df862eb-28ee-49f3-a939-2ae3c99397df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549808165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3549808165
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2289924807
Short name T821
Test name
Test status
Simulation time 23011626 ps
CPU time 0.75 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 206396 kb
Host smart-3d3449d4-1a68-464b-82c5-bf6c2fbaf42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289924807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2289924807
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.277935357
Short name T830
Test name
Test status
Simulation time 39454247229 ps
CPU time 76.04 seconds
Started May 21 12:31:11 PM PDT 24
Finished May 21 12:32:52 PM PDT 24
Peak memory 237168 kb
Host smart-d8da76aa-887e-4653-99ed-726f0d85d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277935357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.277935357
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2531296930
Short name T239
Test name
Test status
Simulation time 16257482403 ps
CPU time 93.07 seconds
Started May 21 12:31:17 PM PDT 24
Finished May 21 12:33:15 PM PDT 24
Peak memory 257428 kb
Host smart-8ededf1c-34f0-44aa-971f-13b10749e6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531296930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2531296930
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1553335831
Short name T249
Test name
Test status
Simulation time 4710495666 ps
CPU time 95.56 seconds
Started May 21 12:31:19 PM PDT 24
Finished May 21 12:33:19 PM PDT 24
Peak memory 253652 kb
Host smart-76dd9b6e-cd69-452a-b72e-d7031bc07acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553335831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1553335831
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2585111042
Short name T356
Test name
Test status
Simulation time 153622487 ps
CPU time 7.3 seconds
Started May 21 12:31:13 PM PDT 24
Finished May 21 12:31:45 PM PDT 24
Peak memory 240176 kb
Host smart-2f5166b3-34c0-44f2-8ca7-3be65a40c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585111042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2585111042
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3050894551
Short name T638
Test name
Test status
Simulation time 1716102764 ps
CPU time 14.22 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 234656 kb
Host smart-08a08cb6-0d97-406e-be78-c38fad6e2311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050894551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3050894551
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2006234534
Short name T681
Test name
Test status
Simulation time 3821344325 ps
CPU time 44.26 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:32:17 PM PDT 24
Peak memory 240688 kb
Host smart-2a6ef6f5-246c-48cc-bd2c-50bcce6d7e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006234534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2006234534
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3771760928
Short name T723
Test name
Test status
Simulation time 36304963 ps
CPU time 2.44 seconds
Started May 21 12:31:03 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 221176 kb
Host smart-fa34bb23-628f-44b0-8505-e1ec9cf813fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771760928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3771760928
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4045667906
Short name T401
Test name
Test status
Simulation time 6832419841 ps
CPU time 10.49 seconds
Started May 21 12:31:10 PM PDT 24
Finished May 21 12:31:46 PM PDT 24
Peak memory 233760 kb
Host smart-a677f545-4b64-4704-ab2d-298b25cdb9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045667906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4045667906
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2251081400
Short name T149
Test name
Test status
Simulation time 811835475 ps
CPU time 5.51 seconds
Started May 21 12:31:05 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 222824 kb
Host smart-dd3aba04-3b80-420d-bb74-b0fe5ff50775
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2251081400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2251081400
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3673622619
Short name T555
Test name
Test status
Simulation time 63921772 ps
CPU time 0.98 seconds
Started May 21 12:31:13 PM PDT 24
Finished May 21 12:31:40 PM PDT 24
Peak memory 206732 kb
Host smart-a1a4c45b-02c9-4d72-90b1-c9bde1e1d3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673622619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3673622619
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1466524661
Short name T597
Test name
Test status
Simulation time 6707840729 ps
CPU time 38.37 seconds
Started May 21 12:31:13 PM PDT 24
Finished May 21 12:32:16 PM PDT 24
Peak memory 216548 kb
Host smart-156920e4-cec9-468e-9fc8-576f22f9f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466524661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1466524661
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1090342872
Short name T737
Test name
Test status
Simulation time 732918590 ps
CPU time 2.08 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:40 PM PDT 24
Peak memory 216100 kb
Host smart-380403dc-097b-4faa-a814-073691b1aaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090342872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1090342872
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3647306745
Short name T800
Test name
Test status
Simulation time 934827077 ps
CPU time 3.99 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 216304 kb
Host smart-40e76075-6ddf-4d5d-9408-b8051c8807fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647306745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3647306745
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.499159848
Short name T474
Test name
Test status
Simulation time 87217996 ps
CPU time 0.84 seconds
Started May 21 12:31:03 PM PDT 24
Finished May 21 12:31:30 PM PDT 24
Peak memory 205652 kb
Host smart-340690e4-9c0a-4b8a-9477-3c2160f11381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499159848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.499159848
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2002661103
Short name T303
Test name
Test status
Simulation time 12874517333 ps
CPU time 9.45 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 221812 kb
Host smart-71d687b0-7a04-4c9b-94b8-32d6ccc6a9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002661103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2002661103
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.139462487
Short name T458
Test name
Test status
Simulation time 39022696 ps
CPU time 0.69 seconds
Started May 21 12:31:04 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 205576 kb
Host smart-a74789b8-ed0c-4d35-a0ae-36b2ecff6fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139462487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.139462487
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.279372161
Short name T761
Test name
Test status
Simulation time 108846045 ps
CPU time 3.25 seconds
Started May 21 12:31:10 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 234012 kb
Host smart-5c4c709b-8e27-4012-9666-47f312f88da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279372161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.279372161
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3336994896
Short name T832
Test name
Test status
Simulation time 17048824 ps
CPU time 0.79 seconds
Started May 21 12:31:06 PM PDT 24
Finished May 21 12:31:32 PM PDT 24
Peak memory 206684 kb
Host smart-1872a594-71b6-4abb-a8d9-920460652d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336994896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3336994896
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.715021473
Short name T130
Test name
Test status
Simulation time 8077069971 ps
CPU time 82.83 seconds
Started May 21 12:31:07 PM PDT 24
Finished May 21 12:32:55 PM PDT 24
Peak memory 254904 kb
Host smart-8f4947c4-57e5-46e9-936a-212dc76f57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715021473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.715021473
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2922606715
Short name T566
Test name
Test status
Simulation time 4881280021 ps
CPU time 37.61 seconds
Started May 21 12:31:26 PM PDT 24
Finished May 21 12:32:27 PM PDT 24
Peak memory 238984 kb
Host smart-9dc7c8a2-601e-4c94-948b-2436157b9d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922606715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2922606715
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1053490003
Short name T323
Test name
Test status
Simulation time 805356777 ps
CPU time 17.39 seconds
Started May 21 12:31:07 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 232768 kb
Host smart-cceb7a1e-72d7-4772-8de6-0552de71d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053490003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1053490003
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2649019540
Short name T132
Test name
Test status
Simulation time 2613614325 ps
CPU time 3.36 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 218560 kb
Host smart-fd7690a2-3363-4c4d-b0e8-297696828c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649019540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2649019540
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1544689135
Short name T406
Test name
Test status
Simulation time 4398320731 ps
CPU time 40.11 seconds
Started May 21 12:31:21 PM PDT 24
Finished May 21 12:32:24 PM PDT 24
Peak memory 233904 kb
Host smart-3afa3a71-6a7f-4661-9cae-4b9025d6eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544689135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1544689135
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.799405265
Short name T674
Test name
Test status
Simulation time 402873098 ps
CPU time 2.2 seconds
Started May 21 12:31:06 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 216000 kb
Host smart-fbfa94cf-a193-43bf-a655-e8a8d751c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799405265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.799405265
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3956457142
Short name T909
Test name
Test status
Simulation time 83608030454 ps
CPU time 14.15 seconds
Started May 21 12:32:29 PM PDT 24
Finished May 21 12:32:51 PM PDT 24
Peak memory 229900 kb
Host smart-7d07f486-a15e-4350-800e-742378f7120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956457142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3956457142
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1432980053
Short name T661
Test name
Test status
Simulation time 197654040 ps
CPU time 4.13 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 220708 kb
Host smart-128332bd-156d-4b96-8af1-57925aa22a73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1432980053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1432980053
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3115239562
Short name T228
Test name
Test status
Simulation time 100210182750 ps
CPU time 245.35 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 263468 kb
Host smart-7f50f4f0-13a3-42e9-890d-c6cd66bed955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115239562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3115239562
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3609191354
Short name T883
Test name
Test status
Simulation time 11009901366 ps
CPU time 18.47 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 216568 kb
Host smart-ac4505a1-0fcb-484f-a47b-1f7ab49f0da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609191354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3609191354
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4168761328
Short name T357
Test name
Test status
Simulation time 1974787497 ps
CPU time 3.64 seconds
Started May 21 12:32:12 PM PDT 24
Finished May 21 12:32:17 PM PDT 24
Peak memory 214576 kb
Host smart-5a3cbbed-902c-4457-84c0-e0df3f45e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168761328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4168761328
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2221294528
Short name T335
Test name
Test status
Simulation time 606135638 ps
CPU time 3.56 seconds
Started May 21 12:31:13 PM PDT 24
Finished May 21 12:31:43 PM PDT 24
Peak memory 216288 kb
Host smart-549f3d2d-61ff-4521-b53c-86e331121dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221294528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2221294528
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1476742440
Short name T441
Test name
Test status
Simulation time 46753771 ps
CPU time 0.87 seconds
Started May 21 12:31:04 PM PDT 24
Finished May 21 12:31:31 PM PDT 24
Peak memory 205848 kb
Host smart-fddfa8e5-3dd3-49b8-9d8f-afbd23b45d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476742440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1476742440
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.275157019
Short name T196
Test name
Test status
Simulation time 351990890 ps
CPU time 5.76 seconds
Started May 21 12:32:29 PM PDT 24
Finished May 21 12:32:36 PM PDT 24
Peak memory 239740 kb
Host smart-bd470502-7c25-4414-90cf-f48320b62e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275157019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.275157019
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1581299772
Short name T488
Test name
Test status
Simulation time 14032539 ps
CPU time 0.73 seconds
Started May 21 12:31:11 PM PDT 24
Finished May 21 12:31:37 PM PDT 24
Peak memory 205312 kb
Host smart-f108f690-ebf1-4434-a86c-5bd7bc8e39de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581299772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1581299772
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1311450475
Short name T614
Test name
Test status
Simulation time 479454361 ps
CPU time 3.3 seconds
Started May 21 12:32:27 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 218252 kb
Host smart-cd09ab34-b940-4ecd-bcdc-8421cc79b457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311450475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1311450475
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.476722626
Short name T678
Test name
Test status
Simulation time 62885296 ps
CPU time 0.76 seconds
Started May 21 12:31:07 PM PDT 24
Finished May 21 12:31:33 PM PDT 24
Peak memory 206692 kb
Host smart-fd16533d-76d2-4dde-b4b9-7bc93994802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476722626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.476722626
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.250716723
Short name T260
Test name
Test status
Simulation time 5851975796 ps
CPU time 35.07 seconds
Started May 21 12:31:07 PM PDT 24
Finished May 21 12:32:07 PM PDT 24
Peak memory 240380 kb
Host smart-67f6ba86-cc48-4c24-8ace-97bf626fff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250716723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.250716723
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3552573541
Short name T225
Test name
Test status
Simulation time 262651712562 ps
CPU time 624.24 seconds
Started May 21 12:31:05 PM PDT 24
Finished May 21 12:41:56 PM PDT 24
Peak memory 249988 kb
Host smart-9b7711d7-4b95-4c96-9eb3-acc9c8e95f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552573541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3552573541
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3036226479
Short name T766
Test name
Test status
Simulation time 7251039609 ps
CPU time 86.86 seconds
Started May 21 12:31:07 PM PDT 24
Finished May 21 12:32:59 PM PDT 24
Peak memory 252400 kb
Host smart-026f317c-04b0-4abe-a3ab-edd0595c261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036226479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3036226479
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2469362654
Short name T793
Test name
Test status
Simulation time 3793889054 ps
CPU time 51.64 seconds
Started May 21 12:31:21 PM PDT 24
Finished May 21 12:32:36 PM PDT 24
Peak memory 234696 kb
Host smart-03e69aa1-f461-4f93-81db-115dbb185820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469362654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2469362654
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3632785507
Short name T669
Test name
Test status
Simulation time 70875157 ps
CPU time 3.41 seconds
Started May 21 12:31:05 PM PDT 24
Finished May 21 12:31:34 PM PDT 24
Peak memory 234120 kb
Host smart-6ce4591f-c693-4f97-96a0-83ef546363c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632785507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3632785507
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.242918031
Short name T893
Test name
Test status
Simulation time 3926948294 ps
CPU time 21.54 seconds
Started May 21 12:31:22 PM PDT 24
Finished May 21 12:32:07 PM PDT 24
Peak memory 232704 kb
Host smart-57a99f19-d731-477c-a1eb-d2420d376b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242918031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.242918031
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3489789068
Short name T259
Test name
Test status
Simulation time 3007136180 ps
CPU time 4.49 seconds
Started May 21 12:31:26 PM PDT 24
Finished May 21 12:31:54 PM PDT 24
Peak memory 236276 kb
Host smart-4bba8163-db96-4d6d-852d-29f005e462a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489789068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3489789068
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.854828854
Short name T599
Test name
Test status
Simulation time 250012854 ps
CPU time 2.56 seconds
Started May 21 12:31:09 PM PDT 24
Finished May 21 12:31:37 PM PDT 24
Peak memory 218576 kb
Host smart-660fa479-eb36-488e-91ee-d30b5da652ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854828854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.854828854
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.742728975
Short name T404
Test name
Test status
Simulation time 195499020 ps
CPU time 4.02 seconds
Started May 21 12:31:22 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 222484 kb
Host smart-3d8bd0fb-1b13-4780-b740-bcc1da2ea22a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=742728975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.742728975
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2748530240
Short name T513
Test name
Test status
Simulation time 13231680728 ps
CPU time 132.54 seconds
Started May 21 12:31:22 PM PDT 24
Finished May 21 12:33:58 PM PDT 24
Peak memory 249292 kb
Host smart-7e3b6a66-74b3-4bd7-a467-cbcf5783c876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748530240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2748530240
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2242913935
Short name T956
Test name
Test status
Simulation time 11902516969 ps
CPU time 25.75 seconds
Started May 21 12:31:09 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 216504 kb
Host smart-4b433926-c440-428d-afd3-67ccfdaf08b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242913935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2242913935
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.607153651
Short name T577
Test name
Test status
Simulation time 20431776450 ps
CPU time 14.02 seconds
Started May 21 12:31:04 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 216376 kb
Host smart-5b3cf0b0-b948-46eb-8fd4-c2239bcb3764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607153651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.607153651
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1337500703
Short name T890
Test name
Test status
Simulation time 11931826 ps
CPU time 0.69 seconds
Started May 21 12:31:30 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 205348 kb
Host smart-b81c0aeb-f29c-4e53-8734-9a50901baff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337500703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1337500703
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3955060784
Short name T655
Test name
Test status
Simulation time 56012780 ps
CPU time 0.76 seconds
Started May 21 12:31:03 PM PDT 24
Finished May 21 12:31:29 PM PDT 24
Peak memory 205816 kb
Host smart-3d93c736-1857-4afc-a77b-fdc51d0fc92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955060784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3955060784
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3217670665
Short name T889
Test name
Test status
Simulation time 9483516818 ps
CPU time 35.99 seconds
Started May 21 12:31:06 PM PDT 24
Finished May 21 12:32:08 PM PDT 24
Peak memory 240952 kb
Host smart-af16d9fc-df75-4d10-82af-085cf4fc644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217670665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3217670665
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2003376563
Short name T359
Test name
Test status
Simulation time 37971153 ps
CPU time 0.69 seconds
Started May 21 12:31:24 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 205248 kb
Host smart-a30acc04-a093-42af-9443-8d0c1dc23528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003376563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2003376563
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2238190448
Short name T563
Test name
Test status
Simulation time 104576019 ps
CPU time 2.22 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:31:48 PM PDT 24
Peak memory 216080 kb
Host smart-fd22e10e-9594-4671-8458-897ed9514624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238190448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2238190448
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1167461765
Short name T705
Test name
Test status
Simulation time 45374494 ps
CPU time 0.83 seconds
Started May 21 12:32:12 PM PDT 24
Finished May 21 12:32:15 PM PDT 24
Peak memory 205084 kb
Host smart-dc85d206-e36b-493b-b931-0fed1cca46f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167461765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1167461765
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2064778814
Short name T266
Test name
Test status
Simulation time 91874534730 ps
CPU time 96.21 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:33:14 PM PDT 24
Peak memory 249104 kb
Host smart-c64de60f-1626-4397-81c9-c683efef034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064778814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2064778814
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.652957881
Short name T28
Test name
Test status
Simulation time 19393353905 ps
CPU time 158.2 seconds
Started May 21 12:31:10 PM PDT 24
Finished May 21 12:34:14 PM PDT 24
Peak memory 241044 kb
Host smart-0650ffef-a527-4511-b80c-50edeaf995ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652957881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.652957881
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.40222237
Short name T697
Test name
Test status
Simulation time 10634549129 ps
CPU time 25.33 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:32:09 PM PDT 24
Peak memory 217776 kb
Host smart-0a7a01cf-d2ad-4832-9834-eb934f1cb5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40222237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.40222237
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2375285629
Short name T569
Test name
Test status
Simulation time 1054434657 ps
CPU time 9.6 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 235196 kb
Host smart-712a31ff-3f02-4b82-b2ad-407c87f450fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375285629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2375285629
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2442040014
Short name T531
Test name
Test status
Simulation time 2156071514 ps
CPU time 11.41 seconds
Started May 21 12:31:21 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 233680 kb
Host smart-8d58b406-853c-46fb-b817-3478afc6d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442040014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2442040014
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2126577143
Short name T549
Test name
Test status
Simulation time 1945386809 ps
CPU time 29.72 seconds
Started May 21 12:31:11 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 236140 kb
Host smart-79470ebf-8ddd-46c7-b678-256c669d9da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126577143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2126577143
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1750070311
Short name T262
Test name
Test status
Simulation time 2008606244 ps
CPU time 7.71 seconds
Started May 21 12:31:17 PM PDT 24
Finished May 21 12:31:50 PM PDT 24
Peak memory 233336 kb
Host smart-d70e65b2-db55-4e01-9a48-faf686474e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750070311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1750070311
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1606220106
Short name T647
Test name
Test status
Simulation time 724291733 ps
CPU time 6.75 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:31:57 PM PDT 24
Peak memory 236904 kb
Host smart-7c9107f4-83be-4571-8718-cbf60f506a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606220106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1606220106
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4269847474
Short name T908
Test name
Test status
Simulation time 218485075 ps
CPU time 4.12 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 218772 kb
Host smart-383b8be5-2058-41b2-9f3b-cef4d85f804a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4269847474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4269847474
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.976331057
Short name T849
Test name
Test status
Simulation time 219949211 ps
CPU time 1.18 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 206916 kb
Host smart-208852fc-60ae-436b-a17a-2811bdf1f396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976331057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.976331057
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2512407851
Short name T326
Test name
Test status
Simulation time 352351407 ps
CPU time 3.45 seconds
Started May 21 12:31:09 PM PDT 24
Finished May 21 12:31:37 PM PDT 24
Peak memory 216368 kb
Host smart-13517db5-61a9-4cad-8e6b-8562fadf0445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512407851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2512407851
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1736279912
Short name T79
Test name
Test status
Simulation time 82476760 ps
CPU time 0.67 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 205452 kb
Host smart-f15fd343-da1f-4122-974e-00559c70e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736279912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1736279912
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1292629242
Short name T810
Test name
Test status
Simulation time 277225637 ps
CPU time 1.79 seconds
Started May 21 12:31:08 PM PDT 24
Finished May 21 12:31:35 PM PDT 24
Peak memory 216384 kb
Host smart-a3bec274-8322-403e-abbf-347fa67febb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292629242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1292629242
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2648013109
Short name T542
Test name
Test status
Simulation time 19133601 ps
CPU time 0.71 seconds
Started May 21 12:32:31 PM PDT 24
Finished May 21 12:32:34 PM PDT 24
Peak memory 205624 kb
Host smart-14b2d02a-2726-49f1-a65a-5d01f791c2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648013109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2648013109
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.219472621
Short name T675
Test name
Test status
Simulation time 14142672457 ps
CPU time 15.36 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 232728 kb
Host smart-7910145b-a293-45dc-adc4-bc25721d5deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219472621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.219472621
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1645476791
Short name T371
Test name
Test status
Simulation time 12438898 ps
CPU time 0.75 seconds
Started May 21 12:31:10 PM PDT 24
Finished May 21 12:31:36 PM PDT 24
Peak memory 205296 kb
Host smart-27122969-12ad-4768-9aa7-63e4f58857c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645476791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1645476791
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4116350345
Short name T7
Test name
Test status
Simulation time 4228877456 ps
CPU time 13.5 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 236188 kb
Host smart-e00cf4f4-2c78-4e0a-9ee4-aefdead27e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116350345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4116350345
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4231206552
Short name T907
Test name
Test status
Simulation time 21536124 ps
CPU time 0.75 seconds
Started May 21 12:31:51 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 206700 kb
Host smart-dded65e6-513e-4803-907c-577997ef5412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231206552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4231206552
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.73913945
Short name T238
Test name
Test status
Simulation time 10193002252 ps
CPU time 70.04 seconds
Started May 21 12:31:14 PM PDT 24
Finished May 21 12:32:50 PM PDT 24
Peak memory 256156 kb
Host smart-2276fbf4-cfc9-4837-a1a8-edeb4e5d2171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73913945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.73913945
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2961961834
Short name T444
Test name
Test status
Simulation time 7886522110 ps
CPU time 37.86 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:32:32 PM PDT 24
Peak memory 249300 kb
Host smart-7f3294ed-9a92-4c6e-949d-cece1599fd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961961834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2961961834
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2879052388
Short name T25
Test name
Test status
Simulation time 33425116042 ps
CPU time 96.79 seconds
Started May 21 12:31:11 PM PDT 24
Finished May 21 12:33:13 PM PDT 24
Peak memory 252772 kb
Host smart-5f44463b-095b-48fb-af90-059e5069705c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879052388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2879052388
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4238018949
Short name T635
Test name
Test status
Simulation time 49621364354 ps
CPU time 56.87 seconds
Started May 21 12:31:15 PM PDT 24
Finished May 21 12:32:38 PM PDT 24
Peak memory 240912 kb
Host smart-92b12433-7160-49e7-987e-053290888d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238018949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4238018949
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3763580520
Short name T648
Test name
Test status
Simulation time 42343453 ps
CPU time 2.71 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:40 PM PDT 24
Peak memory 234056 kb
Host smart-b06e2864-1058-4bd2-a7ff-38a7e7e34817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763580520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3763580520
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1362776047
Short name T505
Test name
Test status
Simulation time 3528164135 ps
CPU time 5.81 seconds
Started May 21 12:31:13 PM PDT 24
Finished May 21 12:31:45 PM PDT 24
Peak memory 233644 kb
Host smart-9a439488-6c85-4948-9b93-2c9ad3b37d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362776047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1362776047
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2565208600
Short name T360
Test name
Test status
Simulation time 140496864 ps
CPU time 2.31 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:31:48 PM PDT 24
Peak memory 220920 kb
Host smart-d0d6808d-a214-42ca-930f-0ce7c1fe5e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565208600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2565208600
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.819726847
Short name T304
Test name
Test status
Simulation time 11107244158 ps
CPU time 8.63 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:46 PM PDT 24
Peak memory 236300 kb
Host smart-26300020-45a9-4c49-8faf-88be18729887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819726847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.819726847
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3003181710
Short name T533
Test name
Test status
Simulation time 426843205 ps
CPU time 5.34 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:43 PM PDT 24
Peak memory 220228 kb
Host smart-3cce1436-d2e3-4a14-809e-b9d865389bac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3003181710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3003181710
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.326615566
Short name T338
Test name
Test status
Simulation time 99557034 ps
CPU time 1.04 seconds
Started May 21 12:31:22 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 206740 kb
Host smart-f20e3c6b-deb5-4ae9-b15b-8de96d8ff21c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326615566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.326615566
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4007227812
Short name T324
Test name
Test status
Simulation time 3023173312 ps
CPU time 30.16 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:32:08 PM PDT 24
Peak memory 216692 kb
Host smart-a6ba62bf-e251-472a-afa3-74c37a9878b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007227812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4007227812
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.116895246
Short name T622
Test name
Test status
Simulation time 1637323899 ps
CPU time 4.4 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 216588 kb
Host smart-536151af-9315-4ae9-9683-d16bfa4f68cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116895246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.116895246
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.255194268
Short name T562
Test name
Test status
Simulation time 1980451281 ps
CPU time 2.54 seconds
Started May 21 12:31:26 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 216484 kb
Host smart-1f5f869e-dfb9-4776-8f0a-4273a105c54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255194268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.255194268
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3472268450
Short name T455
Test name
Test status
Simulation time 159566883 ps
CPU time 1.1 seconds
Started May 21 12:31:15 PM PDT 24
Finished May 21 12:31:42 PM PDT 24
Peak memory 206796 kb
Host smart-1f602d4b-5a9d-4dd7-a956-1c3596e1c286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472268450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3472268450
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4269648999
Short name T166
Test name
Test status
Simulation time 3492964132 ps
CPU time 9.96 seconds
Started May 21 12:31:35 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 218764 kb
Host smart-720c1141-4b20-4e2e-841d-af9da5963316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269648999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4269648999
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1907472955
Short name T349
Test name
Test status
Simulation time 133514979 ps
CPU time 0.75 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 205288 kb
Host smart-39d8e4f7-045e-4184-a863-4397de2cd742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907472955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1907472955
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2140772186
Short name T571
Test name
Test status
Simulation time 192104753 ps
CPU time 3.54 seconds
Started May 21 12:31:34 PM PDT 24
Finished May 21 12:31:59 PM PDT 24
Peak memory 218448 kb
Host smart-3c70cf00-b243-453f-a5de-00faf6626dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140772186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2140772186
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3497014701
Short name T526
Test name
Test status
Simulation time 46732370 ps
CPU time 0.8 seconds
Started May 21 12:31:11 PM PDT 24
Finished May 21 12:31:37 PM PDT 24
Peak memory 206348 kb
Host smart-0ca647ef-7ace-4ed9-b57a-c0a73ae90297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497014701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3497014701
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1402363173
Short name T668
Test name
Test status
Simulation time 4297764705 ps
CPU time 45.39 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:32:29 PM PDT 24
Peak memory 257348 kb
Host smart-618592d5-e687-49e7-909f-88dc5c510217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402363173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1402363173
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4262758455
Short name T331
Test name
Test status
Simulation time 13409830250 ps
CPU time 70.82 seconds
Started May 21 12:31:26 PM PDT 24
Finished May 21 12:33:00 PM PDT 24
Peak memory 249288 kb
Host smart-21e073ba-c671-421a-b420-6bffccf9594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262758455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4262758455
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1216981272
Short name T711
Test name
Test status
Simulation time 12282000071 ps
CPU time 103.87 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 249160 kb
Host smart-ab83d4f9-76f8-43d4-a76b-a7de1c092b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216981272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1216981272
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.298205140
Short name T319
Test name
Test status
Simulation time 2624340506 ps
CPU time 44.18 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:43 PM PDT 24
Peak memory 239972 kb
Host smart-cd4c333c-f94d-414c-b315-f08b99c583e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298205140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.298205140
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3997256363
Short name T214
Test name
Test status
Simulation time 251914158 ps
CPU time 4.68 seconds
Started May 21 12:31:22 PM PDT 24
Finished May 21 12:31:50 PM PDT 24
Peak memory 233556 kb
Host smart-0d120374-3592-4682-9389-e8e3ca662d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997256363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3997256363
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1919694330
Short name T518
Test name
Test status
Simulation time 1481787586 ps
CPU time 15.46 seconds
Started May 21 12:31:10 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 239128 kb
Host smart-6fa030d5-5263-44be-805c-e91e02536b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919694330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1919694330
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2995163152
Short name T27
Test name
Test status
Simulation time 14789462038 ps
CPU time 11.08 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 233724 kb
Host smart-6e5bedaf-c31d-48db-b98b-ed453dcdd234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995163152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2995163152
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2889760267
Short name T538
Test name
Test status
Simulation time 1226733276 ps
CPU time 3.31 seconds
Started May 21 12:31:16 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 233628 kb
Host smart-c73bc5da-9ee3-4310-a8be-7480b178cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889760267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2889760267
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.461973169
Short name T41
Test name
Test status
Simulation time 7194672172 ps
CPU time 15.58 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:32:02 PM PDT 24
Peak memory 219356 kb
Host smart-4e26f7a6-d62c-4a39-bebc-5c4cc2e9015b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=461973169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.461973169
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1591378610
Short name T161
Test name
Test status
Simulation time 11463636484 ps
CPU time 141.14 seconds
Started May 21 12:31:29 PM PDT 24
Finished May 21 12:34:13 PM PDT 24
Peak memory 249780 kb
Host smart-377aad2d-b040-4cbf-a8eb-ed5201f9ddcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591378610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1591378610
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2210041318
Short name T346
Test name
Test status
Simulation time 15030480 ps
CPU time 0.72 seconds
Started May 21 12:31:13 PM PDT 24
Finished May 21 12:31:39 PM PDT 24
Peak memory 205568 kb
Host smart-658c5e50-2f43-4742-bded-0fd7ac684081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210041318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2210041318
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1848257102
Short name T551
Test name
Test status
Simulation time 29414786 ps
CPU time 0.72 seconds
Started May 21 12:31:12 PM PDT 24
Finished May 21 12:31:38 PM PDT 24
Peak memory 205432 kb
Host smart-97a7a70a-f73e-4657-bf15-21ffa6b544d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848257102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1848257102
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4205795748
Short name T582
Test name
Test status
Simulation time 431093955 ps
CPU time 4.84 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 216440 kb
Host smart-77520e6e-a24b-44ff-ac21-5e01ef490352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205795748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4205795748
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1983679529
Short name T544
Test name
Test status
Simulation time 39605170 ps
CPU time 0.8 seconds
Started May 21 12:32:29 PM PDT 24
Finished May 21 12:32:31 PM PDT 24
Peak memory 204688 kb
Host smart-0781c4cb-65fa-417d-aee4-120f8a673251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983679529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1983679529
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3571867388
Short name T185
Test name
Test status
Simulation time 210654095 ps
CPU time 2.58 seconds
Started May 21 12:31:19 PM PDT 24
Finished May 21 12:31:46 PM PDT 24
Peak memory 219000 kb
Host smart-99471ea5-47a5-4540-9851-974e6efcbd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571867388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3571867388
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.719426982
Short name T339
Test name
Test status
Simulation time 15960070 ps
CPU time 0.73 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 205216 kb
Host smart-1a188bdb-fa4f-4b44-9da0-3c3771a49b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719426982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.719426982
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2822350046
Short name T693
Test name
Test status
Simulation time 342451647 ps
CPU time 4.1 seconds
Started May 21 12:29:47 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 218224 kb
Host smart-0281207f-e5a0-4d3a-8a3a-7ab1c61abef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822350046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2822350046
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.907295603
Short name T341
Test name
Test status
Simulation time 17228091 ps
CPU time 0.78 seconds
Started May 21 12:29:44 PM PDT 24
Finished May 21 12:30:12 PM PDT 24
Peak memory 206360 kb
Host smart-6facb533-bcd7-4805-905c-b7355bcef1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907295603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.907295603
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3662886059
Short name T905
Test name
Test status
Simulation time 6692395332 ps
CPU time 82.59 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:31:39 PM PDT 24
Peak memory 255740 kb
Host smart-475427f5-37ba-4ec8-a4f0-247bb4074d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662886059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3662886059
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1251216054
Short name T965
Test name
Test status
Simulation time 22824998861 ps
CPU time 51.56 seconds
Started May 21 12:29:47 PM PDT 24
Finished May 21 12:31:08 PM PDT 24
Peak memory 239876 kb
Host smart-48c7ccf7-6c72-4865-90b3-0273166cb235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251216054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1251216054
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.562095388
Short name T971
Test name
Test status
Simulation time 6656093845 ps
CPU time 80.92 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:31:40 PM PDT 24
Peak memory 241068 kb
Host smart-f714f8e8-88db-4acc-817b-60ee46fa1e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562095388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
562095388
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.857204285
Short name T148
Test name
Test status
Simulation time 10460072589 ps
CPU time 23.35 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:36 PM PDT 24
Peak memory 232784 kb
Host smart-526a7e4c-8a3b-43e5-b6ba-9233b81fdf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857204285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.857204285
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2416340513
Short name T509
Test name
Test status
Simulation time 6914368906 ps
CPU time 13.4 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:30:30 PM PDT 24
Peak memory 218468 kb
Host smart-8a2240f5-baf2-47cf-9bfc-6017b70161f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416340513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2416340513
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.5172019
Short name T739
Test name
Test status
Simulation time 14138573407 ps
CPU time 153.76 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:32:51 PM PDT 24
Peak memory 238160 kb
Host smart-1023d763-67d3-4853-8eeb-75157593ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5172019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.5172019
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3162173008
Short name T376
Test name
Test status
Simulation time 63738233 ps
CPU time 1.03 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 216668 kb
Host smart-2023af23-09cb-4383-afa8-210ced6ab3bf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162173008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3162173008
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1300624098
Short name T495
Test name
Test status
Simulation time 28967211 ps
CPU time 1.95 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 216056 kb
Host smart-81741478-900c-438d-8799-40292913fd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300624098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1300624098
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.383950813
Short name T489
Test name
Test status
Simulation time 548758763 ps
CPU time 4.63 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 234012 kb
Host smart-41fbf0ab-2a6e-4104-be04-009c6b02cf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383950813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.383950813
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2895876063
Short name T777
Test name
Test status
Simulation time 1553180385 ps
CPU time 11.85 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 222868 kb
Host smart-467b800e-8811-4814-a511-ffdb4862ac51
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895876063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2895876063
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2845900868
Short name T65
Test name
Test status
Simulation time 219753908 ps
CPU time 1.01 seconds
Started May 21 12:29:45 PM PDT 24
Finished May 21 12:30:15 PM PDT 24
Peak memory 235032 kb
Host smart-c7e635be-3c2f-41fe-8aa8-d1e90857a69c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845900868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2845900868
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1898768573
Short name T245
Test name
Test status
Simulation time 130861813630 ps
CPU time 288.72 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:35:07 PM PDT 24
Peak memory 265768 kb
Host smart-4a499b4b-1098-49e5-83eb-1757bdafb4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898768573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1898768573
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4258716000
Short name T472
Test name
Test status
Simulation time 3726732763 ps
CPU time 19.08 seconds
Started May 21 12:29:47 PM PDT 24
Finished May 21 12:30:36 PM PDT 24
Peak memory 216448 kb
Host smart-12ec8b88-479e-4879-a49a-b4a84dc76457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258716000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4258716000
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3553790374
Short name T74
Test name
Test status
Simulation time 6675179217 ps
CPU time 7.25 seconds
Started May 21 12:29:43 PM PDT 24
Finished May 21 12:30:17 PM PDT 24
Peak memory 216480 kb
Host smart-13765ba6-de9e-493e-8c3d-e94b92b2cb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553790374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3553790374
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2239999286
Short name T673
Test name
Test status
Simulation time 146169752 ps
CPU time 0.92 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:30:18 PM PDT 24
Peak memory 207048 kb
Host smart-bb63e0a1-c67b-420e-bb45-117a239444e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239999286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2239999286
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4034050128
Short name T374
Test name
Test status
Simulation time 27817987 ps
CPU time 0.78 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:16 PM PDT 24
Peak memory 205660 kb
Host smart-edec72da-8e70-4f48-ba3c-46a5b98ef621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034050128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4034050128
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2383318288
Short name T133
Test name
Test status
Simulation time 7683971965 ps
CPU time 22.92 seconds
Started May 21 12:29:46 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 238000 kb
Host smart-745a17c5-1bea-4755-a7bc-eddb1c93bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383318288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2383318288
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.852223018
Short name T446
Test name
Test status
Simulation time 52399770 ps
CPU time 0.68 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 205268 kb
Host smart-c4d19f98-dff4-4e86-b5bc-f4fee2a98cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852223018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.852223018
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1055415840
Short name T954
Test name
Test status
Simulation time 418668020 ps
CPU time 3.84 seconds
Started May 21 12:31:18 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 234796 kb
Host smart-7daff65f-3c51-4d6b-9a16-aa405e52d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055415840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1055415840
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2421839755
Short name T355
Test name
Test status
Simulation time 19159821 ps
CPU time 0.76 seconds
Started May 21 12:31:22 PM PDT 24
Finished May 21 12:31:46 PM PDT 24
Peak memory 205464 kb
Host smart-30115071-a65c-4afa-9166-2d26aafaeca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421839755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2421839755
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2734110533
Short name T768
Test name
Test status
Simulation time 22210490763 ps
CPU time 52.35 seconds
Started May 21 12:31:37 PM PDT 24
Finished May 21 12:32:49 PM PDT 24
Peak memory 237736 kb
Host smart-bcd8642a-dccb-44c4-8f00-da83e2752ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734110533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2734110533
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.889319656
Short name T80
Test name
Test status
Simulation time 12392119431 ps
CPU time 77.17 seconds
Started May 21 12:31:19 PM PDT 24
Finished May 21 12:33:00 PM PDT 24
Peak memory 252180 kb
Host smart-6bde6e00-8491-4114-b41e-ee65b744157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889319656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.889319656
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.22454068
Short name T136
Test name
Test status
Simulation time 41549178595 ps
CPU time 217.57 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:35:21 PM PDT 24
Peak memory 249496 kb
Host smart-39f57da0-49d5-44f5-8627-07408daff12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22454068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.22454068
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3745569829
Short name T527
Test name
Test status
Simulation time 2471173143 ps
CPU time 10.38 seconds
Started May 21 12:31:34 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 224592 kb
Host smart-1ef5ff4f-0302-4602-98b0-13e3f937e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745569829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3745569829
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2163447932
Short name T945
Test name
Test status
Simulation time 4235291254 ps
CPU time 20.92 seconds
Started May 21 12:31:30 PM PDT 24
Finished May 21 12:32:14 PM PDT 24
Peak memory 234944 kb
Host smart-e81511f5-b750-4d17-a9ef-e3b351672337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163447932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2163447932
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.398569643
Short name T884
Test name
Test status
Simulation time 459961417 ps
CPU time 6.77 seconds
Started May 21 12:31:18 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 233816 kb
Host smart-06c397a9-b64d-497d-a13f-b24b065f5b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398569643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.398569643
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3243420351
Short name T934
Test name
Test status
Simulation time 343293636 ps
CPU time 2.38 seconds
Started May 21 12:31:24 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 218748 kb
Host smart-4edff263-03f5-4d2c-9fba-39ddea8f8ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243420351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3243420351
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1274452853
Short name T393
Test name
Test status
Simulation time 493393476 ps
CPU time 3.66 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 235708 kb
Host smart-9e86b9a9-b47f-457c-a24c-c6519deffebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274452853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1274452853
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1610347349
Short name T39
Test name
Test status
Simulation time 97802904 ps
CPU time 3.38 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 220336 kb
Host smart-6580bd0b-3b43-4e65-9829-ab88a4de4f69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610347349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1610347349
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.169115109
Short name T514
Test name
Test status
Simulation time 2918856630 ps
CPU time 13.04 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:12 PM PDT 24
Peak memory 216408 kb
Host smart-960baea6-c528-4208-963d-3e9bee6c7e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169115109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.169115109
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3879637907
Short name T392
Test name
Test status
Simulation time 715012934 ps
CPU time 5.33 seconds
Started May 21 12:31:30 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 216284 kb
Host smart-0ee42199-c7e4-4fea-bd71-7d304dbb3f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879637907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3879637907
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.531239829
Short name T8
Test name
Test status
Simulation time 33150286 ps
CPU time 1.15 seconds
Started May 21 12:31:29 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 216244 kb
Host smart-4ff0a44e-a5fa-4ee6-8ad4-bb57c76c8cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531239829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.531239829
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.505865107
Short name T780
Test name
Test status
Simulation time 19646541 ps
CPU time 0.75 seconds
Started May 21 12:31:19 PM PDT 24
Finished May 21 12:31:44 PM PDT 24
Peak memory 205736 kb
Host smart-6feeb200-b941-4311-906e-e2c96ece22ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505865107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.505865107
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1609398946
Short name T281
Test name
Test status
Simulation time 320455925 ps
CPU time 2.63 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 224244 kb
Host smart-56f1ed99-55ad-4b25-8e66-233d80d709de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609398946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1609398946
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1843739055
Short name T333
Test name
Test status
Simulation time 49394621 ps
CPU time 0.73 seconds
Started May 21 12:31:41 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 204672 kb
Host smart-a3550bb6-82cb-4330-9815-c3a0a2193fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843739055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1843739055
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1631508711
Short name T396
Test name
Test status
Simulation time 124853106 ps
CPU time 3.65 seconds
Started May 21 12:31:30 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 219664 kb
Host smart-551d1e0d-613e-40b0-b12d-6186ea7beb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631508711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1631508711
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1797318540
Short name T400
Test name
Test status
Simulation time 20649011 ps
CPU time 0.77 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:48 PM PDT 24
Peak memory 206712 kb
Host smart-5125e3bb-cf77-4532-87b8-9d859b1540ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797318540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1797318540
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.42438329
Short name T210
Test name
Test status
Simulation time 24374761843 ps
CPU time 119.29 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:33:53 PM PDT 24
Peak memory 253972 kb
Host smart-42a7b629-f09b-4b43-9b94-7ee23de528bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42438329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.42438329
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.379241287
Short name T880
Test name
Test status
Simulation time 4164243149 ps
CPU time 22.25 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 223748 kb
Host smart-c3b5e70b-d2cc-41bb-a87e-6a9919ad8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379241287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.379241287
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.4140851606
Short name T283
Test name
Test status
Simulation time 7379646210 ps
CPU time 61.08 seconds
Started May 21 12:31:19 PM PDT 24
Finished May 21 12:32:44 PM PDT 24
Peak memory 241212 kb
Host smart-0ef85bf4-32c5-45c9-9c03-ca6af9f24a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140851606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.4140851606
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1151791265
Short name T843
Test name
Test status
Simulation time 8430335906 ps
CPU time 28.62 seconds
Started May 21 12:31:41 PM PDT 24
Finished May 21 12:32:28 PM PDT 24
Peak memory 232712 kb
Host smart-69e1bfef-7757-4c3c-adfd-47cdc3d26cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151791265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1151791265
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3758150807
Short name T484
Test name
Test status
Simulation time 1492361066 ps
CPU time 6.73 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 233596 kb
Host smart-015fce5c-085d-40c6-864e-f99b147422cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758150807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3758150807
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2723224634
Short name T362
Test name
Test status
Simulation time 105342289 ps
CPU time 2.67 seconds
Started May 21 12:31:31 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 218556 kb
Host smart-ec16d575-312c-426c-b21f-744cf0a24f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723224634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2723224634
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.567839035
Short name T247
Test name
Test status
Simulation time 906928750 ps
CPU time 3.43 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:31:47 PM PDT 24
Peak memory 234588 kb
Host smart-64ca8653-1e56-4683-95ca-955ad5865df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567839035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.567839035
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4109011235
Short name T460
Test name
Test status
Simulation time 30621616419 ps
CPU time 22.17 seconds
Started May 21 12:31:37 PM PDT 24
Finished May 21 12:32:19 PM PDT 24
Peak memory 232776 kb
Host smart-dbdcfe42-fb72-412c-bb8a-1048d878e083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109011235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4109011235
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1779655923
Short name T918
Test name
Test status
Simulation time 976079729 ps
CPU time 5.44 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 222896 kb
Host smart-2e5074d9-bada-4dd6-abe3-47ba57337da0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1779655923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1779655923
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3993176452
Short name T258
Test name
Test status
Simulation time 54892782588 ps
CPU time 120.4 seconds
Started May 21 12:31:35 PM PDT 24
Finished May 21 12:33:57 PM PDT 24
Peak memory 251352 kb
Host smart-e6b81277-0bd3-4c53-8d29-b70fbdcf17f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993176452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3993176452
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.669988812
Short name T816
Test name
Test status
Simulation time 9563381892 ps
CPU time 14.05 seconds
Started May 21 12:31:16 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 216392 kb
Host smart-c84b7855-c7df-4233-945f-13d72fcf7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669988812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.669988812
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2058298137
Short name T967
Test name
Test status
Simulation time 14652222940 ps
CPU time 13.95 seconds
Started May 21 12:31:20 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 216448 kb
Host smart-3bc00c28-28af-4725-ad86-e9411a5b4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058298137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2058298137
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.191175992
Short name T795
Test name
Test status
Simulation time 251988006 ps
CPU time 1.74 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 216412 kb
Host smart-77ed3592-b46c-4b3c-b831-5f750a94e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191175992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.191175992
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.69730921
Short name T358
Test name
Test status
Simulation time 86690541 ps
CPU time 1.02 seconds
Started May 21 12:31:35 PM PDT 24
Finished May 21 12:31:57 PM PDT 24
Peak memory 205952 kb
Host smart-c0bb8d33-ce43-44c7-986f-8302e7849bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69730921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.69730921
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3941755978
Short name T521
Test name
Test status
Simulation time 2635606051 ps
CPU time 8.73 seconds
Started May 21 12:31:18 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 218676 kb
Host smart-e1e6ba0a-88f7-4ce9-8430-3e234122d749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941755978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3941755978
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.910678645
Short name T719
Test name
Test status
Simulation time 102825771 ps
CPU time 0.72 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:48 PM PDT 24
Peak memory 205548 kb
Host smart-c5d36e9f-a213-4b6a-adf9-6c3b11471a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910678645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.910678645
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.327468404
Short name T769
Test name
Test status
Simulation time 369315453 ps
CPU time 5.02 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 218564 kb
Host smart-5a2c9091-0d96-423f-a3bc-319a1a7dc267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327468404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.327468404
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.833296863
Short name T715
Test name
Test status
Simulation time 46859727 ps
CPU time 0.79 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 206688 kb
Host smart-b6ae3a3d-efde-4233-83ef-0b9700dc006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833296863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.833296863
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3224489789
Short name T789
Test name
Test status
Simulation time 46431471286 ps
CPU time 131.23 seconds
Started May 21 12:31:24 PM PDT 24
Finished May 21 12:33:58 PM PDT 24
Peak memory 249152 kb
Host smart-61826b4c-ccf4-4f18-9e61-7e4bba86ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224489789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3224489789
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2095401052
Short name T946
Test name
Test status
Simulation time 2233383022 ps
CPU time 25.23 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:32:12 PM PDT 24
Peak memory 234348 kb
Host smart-f16f1099-c5b3-4900-918b-226febc62467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095401052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2095401052
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1223242898
Short name T20
Test name
Test status
Simulation time 5115555242 ps
CPU time 79.37 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:34:46 PM PDT 24
Peak memory 249172 kb
Host smart-7024ad65-1777-40ef-b728-979a40d99bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223242898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1223242898
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.652536591
Short name T947
Test name
Test status
Simulation time 432059485 ps
CPU time 5.04 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 224388 kb
Host smart-d0082797-c86c-427f-a38e-4ae1a76720be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652536591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.652536591
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4270616276
Short name T90
Test name
Test status
Simulation time 300416503 ps
CPU time 3.54 seconds
Started May 21 12:33:10 PM PDT 24
Finished May 21 12:33:31 PM PDT 24
Peak memory 233524 kb
Host smart-02626986-16ae-4494-b937-28eaa7212fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270616276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4270616276
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2819320958
Short name T612
Test name
Test status
Simulation time 17332026063 ps
CPU time 38.54 seconds
Started May 21 12:31:35 PM PDT 24
Finished May 21 12:32:35 PM PDT 24
Peak memory 231792 kb
Host smart-c853e2f3-86ca-4118-82a9-61d88264ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819320958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2819320958
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.746435191
Short name T236
Test name
Test status
Simulation time 311174481 ps
CPU time 4.4 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 216700 kb
Host smart-2891a0a8-8cd4-4c08-a331-49fc63df445d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746435191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.746435191
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2838023091
Short name T906
Test name
Test status
Simulation time 190687543 ps
CPU time 2.44 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 232652 kb
Host smart-f223567d-d546-4ed5-b29b-065d94f6f663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838023091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2838023091
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.651980627
Short name T145
Test name
Test status
Simulation time 193921360 ps
CPU time 4.54 seconds
Started May 21 12:31:23 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 218512 kb
Host smart-cede0de3-b2cd-4b37-b398-c62f6bdd9b03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651980627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.651980627
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2516230573
Short name T977
Test name
Test status
Simulation time 54627070 ps
CPU time 1.06 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 206876 kb
Host smart-3a10c12c-5df4-46f0-a7f1-8b1370f550eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516230573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2516230573
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3797467419
Short name T818
Test name
Test status
Simulation time 497893367 ps
CPU time 3.67 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:31:54 PM PDT 24
Peak memory 216364 kb
Host smart-19f62b25-d42b-4e13-ab5b-9764cd940027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797467419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3797467419
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2198697081
Short name T424
Test name
Test status
Simulation time 428611260 ps
CPU time 2.6 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 216108 kb
Host smart-072a93f2-995b-493b-bb39-3bb6926d0c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198697081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2198697081
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2652870136
Short name T421
Test name
Test status
Simulation time 51646452 ps
CPU time 0.97 seconds
Started May 21 12:31:41 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 206980 kb
Host smart-bd487a04-0193-48fa-845d-a105706906f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652870136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2652870136
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1561050535
Short name T822
Test name
Test status
Simulation time 33068580 ps
CPU time 0.69 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 205248 kb
Host smart-b50f0b1f-c432-4208-89b9-87c868aa8036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561050535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1561050535
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3402109896
Short name T774
Test name
Test status
Simulation time 42769764165 ps
CPU time 30.9 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:32:21 PM PDT 24
Peak memory 232820 kb
Host smart-c6cc9d1c-e551-4883-96a7-87e6fd15db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402109896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3402109896
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.4043287399
Short name T944
Test name
Test status
Simulation time 597705185 ps
CPU time 2.29 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 218268 kb
Host smart-89a8dd6d-07bc-4acd-94e4-3dec73bca59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043287399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.4043287399
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.703682943
Short name T900
Test name
Test status
Simulation time 36664307 ps
CPU time 0.78 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 206316 kb
Host smart-01e6d7ab-971d-4285-b8c5-8bb95a152205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703682943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.703682943
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1322517633
Short name T637
Test name
Test status
Simulation time 5429123639 ps
CPU time 41.67 seconds
Started May 21 12:33:12 PM PDT 24
Finished May 21 12:34:12 PM PDT 24
Peak memory 233656 kb
Host smart-7c98b818-1de9-4880-ab50-145bc8f2ca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322517633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1322517633
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.579543252
Short name T49
Test name
Test status
Simulation time 21642701229 ps
CPU time 230.77 seconds
Started May 21 12:31:24 PM PDT 24
Finished May 21 12:35:37 PM PDT 24
Peak memory 265644 kb
Host smart-5e0e2c72-c84a-4e07-bf83-c7f0b4f86e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579543252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.579543252
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2177257229
Short name T735
Test name
Test status
Simulation time 20493259089 ps
CPU time 164.9 seconds
Started May 21 12:32:33 PM PDT 24
Finished May 21 12:35:23 PM PDT 24
Peak memory 248172 kb
Host smart-1fcf291d-164c-4edf-88dc-fec8fe3d8d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177257229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2177257229
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.362201115
Short name T859
Test name
Test status
Simulation time 967576910 ps
CPU time 11.83 seconds
Started May 21 12:31:38 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 232560 kb
Host smart-cfbe2395-3f94-47bb-815e-d9e2ddb0c4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362201115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.362201115
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3371615489
Short name T763
Test name
Test status
Simulation time 1189062961 ps
CPU time 11.08 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 234748 kb
Host smart-a3dff15f-5957-4c1e-a5b3-132290324860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371615489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3371615489
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3833114443
Short name T199
Test name
Test status
Simulation time 4834117314 ps
CPU time 31.35 seconds
Started May 21 12:31:26 PM PDT 24
Finished May 21 12:32:21 PM PDT 24
Peak memory 226372 kb
Host smart-e4ec71b9-d296-405b-9a5c-80160c5172af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833114443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3833114443
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.259934513
Short name T957
Test name
Test status
Simulation time 4342962835 ps
CPU time 16.97 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:16 PM PDT 24
Peak memory 233612 kb
Host smart-6b5c34bf-0ffb-4d5b-92b7-d984af2bc583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259934513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.259934513
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3688502555
Short name T59
Test name
Test status
Simulation time 99265839 ps
CPU time 2.83 seconds
Started May 21 12:31:44 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 233704 kb
Host smart-0be977e2-7656-4cd6-8d5c-ee993360ea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688502555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3688502555
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3134794641
Short name T353
Test name
Test status
Simulation time 548389898 ps
CPU time 5.51 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:07 PM PDT 24
Peak memory 222856 kb
Host smart-149242d6-7fbb-4fce-885b-80eb27224290
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3134794641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3134794641
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.432811599
Short name T162
Test name
Test status
Simulation time 83352945398 ps
CPU time 192.12 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:35:10 PM PDT 24
Peak memory 249320 kb
Host smart-b1842324-05d0-4236-9a8c-5555e45f95d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432811599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.432811599
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.790537182
Short name T634
Test name
Test status
Simulation time 13639655836 ps
CPU time 8.91 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:59 PM PDT 24
Peak memory 216428 kb
Host smart-40f5b05f-76f7-46ee-9d3f-f797b9854b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790537182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.790537182
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2696492487
Short name T454
Test name
Test status
Simulation time 2613209237 ps
CPU time 7.17 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:33:03 PM PDT 24
Peak memory 215908 kb
Host smart-45a38ce0-a6b7-46c9-9807-e8ee48baf508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696492487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2696492487
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2233410376
Short name T442
Test name
Test status
Simulation time 200658227 ps
CPU time 0.91 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 206356 kb
Host smart-b04440aa-ade4-4b5b-90c3-c77804f86a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233410376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2233410376
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2659223055
Short name T468
Test name
Test status
Simulation time 218356106 ps
CPU time 0.81 seconds
Started May 21 12:31:28 PM PDT 24
Finished May 21 12:31:51 PM PDT 24
Peak memory 206772 kb
Host smart-c681442f-1210-449f-8d84-52b573602e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659223055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2659223055
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2754175649
Short name T560
Test name
Test status
Simulation time 15641795393 ps
CPU time 17.12 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 239772 kb
Host smart-490e8949-10fc-40f8-8a93-085bab82134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754175649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2754175649
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1660648088
Short name T351
Test name
Test status
Simulation time 45245626 ps
CPU time 0.71 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 204740 kb
Host smart-15e8c3e9-8fb9-4ddf-87a5-d6a70493de0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660648088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1660648088
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.443932525
Short name T704
Test name
Test status
Simulation time 129842474 ps
CPU time 3.13 seconds
Started May 21 12:31:41 PM PDT 24
Finished May 21 12:32:03 PM PDT 24
Peak memory 218480 kb
Host smart-3688f937-47ca-4462-a79a-d42fc08a9528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443932525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.443932525
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2485698728
Short name T799
Test name
Test status
Simulation time 17571106 ps
CPU time 0.74 seconds
Started May 21 12:33:11 PM PDT 24
Finished May 21 12:33:29 PM PDT 24
Peak memory 205192 kb
Host smart-414ecdb1-108b-4c61-a4b1-e08d7aec886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485698728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2485698728
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1266410599
Short name T508
Test name
Test status
Simulation time 6320872099 ps
CPU time 78.8 seconds
Started May 21 12:31:38 PM PDT 24
Finished May 21 12:33:17 PM PDT 24
Peak memory 253936 kb
Host smart-b0f99c82-0381-48ee-bf38-86a1ad32233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266410599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1266410599
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3713562640
Short name T887
Test name
Test status
Simulation time 9440511917 ps
CPU time 76.48 seconds
Started May 21 12:32:47 PM PDT 24
Finished May 21 12:34:12 PM PDT 24
Peak memory 236396 kb
Host smart-c170cadf-6b15-4f34-ac65-89c1957d2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713562640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3713562640
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2596512264
Short name T713
Test name
Test status
Simulation time 3129922059 ps
CPU time 27.46 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:26 PM PDT 24
Peak memory 240916 kb
Host smart-6508da7d-c67a-4198-be37-689b9cd14d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596512264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2596512264
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1142315874
Short name T936
Test name
Test status
Simulation time 457546340 ps
CPU time 4.75 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:52 PM PDT 24
Peak memory 219624 kb
Host smart-87c71b17-353f-4d3f-8a92-611ce4bd646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142315874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1142315874
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.610053214
Short name T720
Test name
Test status
Simulation time 391230085 ps
CPU time 4.73 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 218072 kb
Host smart-86acdb01-6550-4a7b-a7b7-939fd4b35784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610053214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.610053214
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.934373609
Short name T237
Test name
Test status
Simulation time 22852650044 ps
CPU time 33.24 seconds
Started May 21 12:32:33 PM PDT 24
Finished May 21 12:33:11 PM PDT 24
Peak memory 239588 kb
Host smart-507cf4f7-af90-4646-be88-ca383ba05364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934373609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.934373609
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1797271336
Short name T765
Test name
Test status
Simulation time 51998708 ps
CPU time 2.1 seconds
Started May 21 12:31:30 PM PDT 24
Finished May 21 12:31:54 PM PDT 24
Peak memory 216144 kb
Host smart-e6e9c20f-bbaf-468d-b47b-951671366a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797271336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1797271336
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1775072940
Short name T433
Test name
Test status
Simulation time 105905454 ps
CPU time 4.21 seconds
Started May 21 12:31:35 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 222760 kb
Host smart-133ac4f3-b245-4a30-babf-c430c212aa39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1775072940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1775072940
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3508793556
Short name T180
Test name
Test status
Simulation time 31599588619 ps
CPU time 309.12 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:37:08 PM PDT 24
Peak memory 256824 kb
Host smart-59e69222-4e85-4d29-99bb-d11c4808bd69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508793556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3508793556
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1025730656
Short name T672
Test name
Test status
Simulation time 4237792396 ps
CPU time 5.88 seconds
Started May 21 12:31:27 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 216552 kb
Host smart-bc534601-2ebc-4c04-b59b-36b2bea6b7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025730656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1025730656
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2826059471
Short name T89
Test name
Test status
Simulation time 3402244681 ps
CPU time 11.05 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 216400 kb
Host smart-31d77eb4-4a17-4b94-b255-cc093651db12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826059471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2826059471
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4212710259
Short name T405
Test name
Test status
Simulation time 225539065 ps
CPU time 2.6 seconds
Started May 21 12:31:24 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 216352 kb
Host smart-af23b96a-85c0-4ce2-b96b-c0eb36bd4e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212710259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4212710259
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.89300709
Short name T429
Test name
Test status
Simulation time 17520258 ps
CPU time 0.82 seconds
Started May 21 12:31:25 PM PDT 24
Finished May 21 12:31:49 PM PDT 24
Peak memory 205648 kb
Host smart-0b787290-b90e-45e5-8a36-cf82b7b275c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89300709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.89300709
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.780122379
Short name T731
Test name
Test status
Simulation time 3153185863 ps
CPU time 11.24 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 231016 kb
Host smart-eda795ae-24d9-43f2-aba7-df02013bb5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780122379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.780122379
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1965003141
Short name T700
Test name
Test status
Simulation time 60958447 ps
CPU time 0.78 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 205648 kb
Host smart-535a97ab-76e5-4621-b03f-b53e3063da45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965003141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1965003141
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3683090667
Short name T698
Test name
Test status
Simulation time 299626596 ps
CPU time 4.24 seconds
Started May 21 12:31:34 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 218404 kb
Host smart-540b7fbe-6170-43ac-8174-d7a3b2f8b208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683090667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3683090667
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1876475373
Short name T340
Test name
Test status
Simulation time 32736760 ps
CPU time 0.77 seconds
Started May 21 12:31:34 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 206672 kb
Host smart-d66db379-b795-4a39-871a-2c08a5fd93a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876475373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1876475373
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3483459295
Short name T248
Test name
Test status
Simulation time 11951159355 ps
CPU time 138.85 seconds
Started May 21 12:32:53 PM PDT 24
Finished May 21 12:35:22 PM PDT 24
Peak memory 252240 kb
Host smart-6f53d4c1-9177-4ba1-9c76-31c433abfcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483459295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3483459295
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.939950457
Short name T206
Test name
Test status
Simulation time 63416898156 ps
CPU time 296.28 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:36:51 PM PDT 24
Peak memory 257112 kb
Host smart-7483d382-7543-4653-8842-5bdec0a9d0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939950457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.939950457
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.31914233
Short name T251
Test name
Test status
Simulation time 179157865777 ps
CPU time 298.38 seconds
Started May 21 12:31:34 PM PDT 24
Finished May 21 12:36:54 PM PDT 24
Peak memory 249688 kb
Host smart-a29be5a9-1d77-4c8f-a312-da4468df599d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31914233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.31914233
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1511603213
Short name T143
Test name
Test status
Simulation time 2674231898 ps
CPU time 34.76 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:34 PM PDT 24
Peak memory 248520 kb
Host smart-e053c9b9-0063-4ce9-bb63-0388f7916331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511603213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1511603213
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1250540512
Short name T683
Test name
Test status
Simulation time 1791294310 ps
CPU time 6.73 seconds
Started May 21 12:31:36 PM PDT 24
Finished May 21 12:32:03 PM PDT 24
Peak memory 234072 kb
Host smart-bc67be4a-e4de-4a0c-bb0e-f9e687aa3ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250540512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1250540512
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1765964303
Short name T796
Test name
Test status
Simulation time 1434096631 ps
CPU time 23.4 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:32:18 PM PDT 24
Peak memory 233284 kb
Host smart-e556f9d9-eaa7-4d7d-9f16-6c2ff3b6efbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765964303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1765964303
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3569666422
Short name T476
Test name
Test status
Simulation time 3102646237 ps
CPU time 9.44 seconds
Started May 21 12:31:35 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 240608 kb
Host smart-029d3cbd-253d-4a70-aa70-9705ba618c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569666422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3569666422
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1100648330
Short name T598
Test name
Test status
Simulation time 4609013347 ps
CPU time 8.08 seconds
Started May 21 12:31:36 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 218632 kb
Host smart-b2fb7e59-8582-4290-85c4-97d4a84f3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100648330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1100648330
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2372367553
Short name T863
Test name
Test status
Simulation time 8045929812 ps
CPU time 20.41 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:19 PM PDT 24
Peak memory 223140 kb
Host smart-55d5cb04-9b5f-41cf-8426-8e6e772a8e88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2372367553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2372367553
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3060801204
Short name T172
Test name
Test status
Simulation time 31290137816 ps
CPU time 41.23 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:41 PM PDT 24
Peak memory 223844 kb
Host smart-af98f5d2-fd58-4bcf-8c0a-55b2c19c9182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060801204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3060801204
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3685213021
Short name T397
Test name
Test status
Simulation time 1071476839 ps
CPU time 12.26 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:11 PM PDT 24
Peak memory 216360 kb
Host smart-987df351-25e8-4d1b-89f8-f487384642a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685213021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3685213021
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1317182323
Short name T591
Test name
Test status
Simulation time 1137778411 ps
CPU time 2.72 seconds
Started May 21 12:31:29 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 216188 kb
Host smart-3a6da743-fe33-4877-a1a5-9a319c14e744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317182323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1317182323
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.726041806
Short name T469
Test name
Test status
Simulation time 204306990 ps
CPU time 1.24 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:31:56 PM PDT 24
Peak memory 208180 kb
Host smart-e9240e72-fcf8-4588-8f71-eddb217810b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726041806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.726041806
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.474031360
Short name T485
Test name
Test status
Simulation time 110763215 ps
CPU time 0.81 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:02 PM PDT 24
Peak memory 206060 kb
Host smart-ef25b279-c33e-43c2-bf73-46f8a88f5e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474031360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.474031360
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1729177188
Short name T753
Test name
Test status
Simulation time 2361896691 ps
CPU time 7.78 seconds
Started May 21 12:31:36 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 224224 kb
Host smart-4927c000-85fe-4c6e-8c18-3ac7bd4a05e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729177188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1729177188
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1523378071
Short name T734
Test name
Test status
Simulation time 35387279 ps
CPU time 0.71 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 205688 kb
Host smart-23eae25e-b7ee-4c4a-a986-a3befef4001f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523378071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1523378071
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.610708545
Short name T191
Test name
Test status
Simulation time 167940937 ps
CPU time 3.15 seconds
Started May 21 12:32:51 PM PDT 24
Finished May 21 12:33:03 PM PDT 24
Peak memory 218068 kb
Host smart-b2b18b2d-9bfe-4d70-ad32-ea498b29cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610708545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.610708545
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1517050987
Short name T663
Test name
Test status
Simulation time 34172849 ps
CPU time 0.81 seconds
Started May 21 12:31:34 PM PDT 24
Finished May 21 12:31:57 PM PDT 24
Peak memory 206368 kb
Host smart-30898dcb-8bcd-4a5a-9c9e-e9fec2b08384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517050987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1517050987
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3626887186
Short name T44
Test name
Test status
Simulation time 134917791015 ps
CPU time 85.55 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:33:27 PM PDT 24
Peak memory 249176 kb
Host smart-4d7acdbb-f09e-4240-9910-4faf4c684db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626887186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3626887186
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.603069209
Short name T580
Test name
Test status
Simulation time 12329826131 ps
CPU time 111.88 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 249616 kb
Host smart-d4f96529-7fe4-40e0-883b-dfc6970f59f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603069209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.603069209
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2260151425
Short name T86
Test name
Test status
Simulation time 55797531175 ps
CPU time 52.05 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:55 PM PDT 24
Peak memory 249300 kb
Host smart-02cdb662-c679-4c5a-bbac-9c3d51c45947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260151425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2260151425
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.962796480
Short name T726
Test name
Test status
Simulation time 6486694255 ps
CPU time 26.78 seconds
Started May 21 12:31:44 PM PDT 24
Finished May 21 12:32:29 PM PDT 24
Peak memory 236088 kb
Host smart-1847491e-7d71-4a04-a766-a50b320f3b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962796480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.962796480
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2113809523
Short name T650
Test name
Test status
Simulation time 725862358 ps
CPU time 7.47 seconds
Started May 21 12:31:36 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 219544 kb
Host smart-b8ff5b5e-dfb0-4056-b5ba-2b2f05c0263b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113809523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2113809523
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2525426275
Short name T291
Test name
Test status
Simulation time 10469360037 ps
CPU time 29.21 seconds
Started May 21 12:31:32 PM PDT 24
Finished May 21 12:32:23 PM PDT 24
Peak memory 228692 kb
Host smart-433a6158-7775-4c2a-af41-39004b1613a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525426275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2525426275
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.940622041
Short name T54
Test name
Test status
Simulation time 1958660546 ps
CPU time 6.1 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 218912 kb
Host smart-286824e3-844c-430c-83a8-698b55472950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940622041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.940622041
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3866208151
Short name T749
Test name
Test status
Simulation time 123229118 ps
CPU time 2.69 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 233628 kb
Host smart-7620d6e9-b350-476c-9007-b782f1b4cfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866208151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3866208151
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1028924778
Short name T657
Test name
Test status
Simulation time 482922292 ps
CPU time 3.38 seconds
Started May 21 12:31:36 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 219024 kb
Host smart-2fd86108-e09f-4e8e-b0f0-bb9205f69d74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1028924778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1028924778
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3577959393
Short name T510
Test name
Test status
Simulation time 93245518022 ps
CPU time 258.71 seconds
Started May 21 12:31:37 PM PDT 24
Finished May 21 12:36:16 PM PDT 24
Peak memory 264604 kb
Host smart-36d38be1-c395-4f9e-a513-f0eca44ec544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577959393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3577959393
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3061396497
Short name T620
Test name
Test status
Simulation time 1695380882 ps
CPU time 22.52 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:25 PM PDT 24
Peak memory 216296 kb
Host smart-16342197-f877-43a5-a8a6-ec2d972c6e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061396497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3061396497
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1929679653
Short name T917
Test name
Test status
Simulation time 4627382116 ps
CPU time 14.26 seconds
Started May 21 12:31:33 PM PDT 24
Finished May 21 12:32:09 PM PDT 24
Peak memory 216376 kb
Host smart-2005db7a-ef8e-489a-affa-d36e8546e2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929679653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1929679653
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2516980560
Short name T348
Test name
Test status
Simulation time 325299544 ps
CPU time 3.17 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 216224 kb
Host smart-a75ad830-9e34-474e-ab70-fb92d6c5dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516980560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2516980560
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2197087079
Short name T952
Test name
Test status
Simulation time 88918293 ps
CPU time 0.95 seconds
Started May 21 12:31:31 PM PDT 24
Finished May 21 12:31:54 PM PDT 24
Peak memory 205744 kb
Host smart-f3619d8d-f509-4e0b-9a96-0a2fd508aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197087079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2197087079
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1354154512
Short name T826
Test name
Test status
Simulation time 375368847 ps
CPU time 4.68 seconds
Started May 21 12:31:36 PM PDT 24
Finished May 21 12:32:02 PM PDT 24
Peak memory 233988 kb
Host smart-60cfbd67-98a8-44f6-a770-5a0b7f415d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354154512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1354154512
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1351874455
Short name T888
Test name
Test status
Simulation time 29849555 ps
CPU time 0.79 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:03 PM PDT 24
Peak memory 205348 kb
Host smart-16b9f899-d262-41d8-baf4-4a7fc0814188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351874455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1351874455
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2659240482
Short name T179
Test name
Test status
Simulation time 171946115 ps
CPU time 4.09 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 234144 kb
Host smart-ec83122a-ba4a-4ab1-a7aa-0235540dc949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659240482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2659240482
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.138210448
Short name T617
Test name
Test status
Simulation time 28415363 ps
CPU time 0.77 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:03 PM PDT 24
Peak memory 205316 kb
Host smart-3bc25761-c9c2-4492-a192-87c332ba3269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138210448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.138210448
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.651856669
Short name T464
Test name
Test status
Simulation time 11994095221 ps
CPU time 95.07 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:33:37 PM PDT 24
Peak memory 249148 kb
Host smart-92e99e64-9741-4ae6-b343-ae3d0c9f375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651856669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.651856669
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.939588593
Short name T671
Test name
Test status
Simulation time 2332637103 ps
CPU time 32.63 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:33 PM PDT 24
Peak memory 217356 kb
Host smart-71a11027-bae5-4c21-b61a-1f13788b3f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939588593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.939588593
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.421158175
Short name T325
Test name
Test status
Simulation time 10616107627 ps
CPU time 23.91 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:25 PM PDT 24
Peak memory 217536 kb
Host smart-b8500c3a-0098-4cea-b9bb-12006a23733a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421158175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.421158175
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1725474435
Short name T320
Test name
Test status
Simulation time 1121376578 ps
CPU time 18.3 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:20 PM PDT 24
Peak memory 236108 kb
Host smart-20308261-bb15-48de-89d3-57b5e6c1b434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725474435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1725474435
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.181626691
Short name T646
Test name
Test status
Simulation time 150733315 ps
CPU time 5.23 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:07 PM PDT 24
Peak memory 234872 kb
Host smart-6f818e48-0749-4af6-b76f-60c19bed8312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181626691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.181626691
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2849623249
Short name T302
Test name
Test status
Simulation time 10823339955 ps
CPU time 94.86 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:33:36 PM PDT 24
Peak memory 240936 kb
Host smart-992f4e86-21ae-4763-b8f6-262133cf871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849623249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2849623249
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2249944685
Short name T756
Test name
Test status
Simulation time 687699178 ps
CPU time 3.53 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 233124 kb
Host smart-5f3b14a7-06a0-4c77-acb1-201686fd27c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249944685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2249944685
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3890667360
Short name T709
Test name
Test status
Simulation time 28233691894 ps
CPU time 17.58 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:19 PM PDT 24
Peak memory 233784 kb
Host smart-6c8ddb84-9d78-49db-b9b9-c70ca1bdf039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890667360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3890667360
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3631455852
Short name T959
Test name
Test status
Simulation time 929323733 ps
CPU time 5.71 seconds
Started May 21 12:31:45 PM PDT 24
Finished May 21 12:32:08 PM PDT 24
Peak memory 218832 kb
Host smart-372a87ea-7a1d-4788-bbbb-fd2e1a051d47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3631455852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3631455852
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4255681998
Short name T278
Test name
Test status
Simulation time 4289817629 ps
CPU time 75.13 seconds
Started May 21 12:31:45 PM PDT 24
Finished May 21 12:33:18 PM PDT 24
Peak memory 252792 kb
Host smart-3eb5ad42-2f2b-475d-833f-d8b2c9e1dcdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255681998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4255681998
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1663937666
Short name T894
Test name
Test status
Simulation time 1008610792 ps
CPU time 8.71 seconds
Started May 21 12:31:45 PM PDT 24
Finished May 21 12:32:11 PM PDT 24
Peak memory 216244 kb
Host smart-f311bd28-2a7f-4154-9667-4f2c5cfb0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663937666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1663937666
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.676737889
Short name T87
Test name
Test status
Simulation time 64580747064 ps
CPU time 13.99 seconds
Started May 21 12:31:38 PM PDT 24
Finished May 21 12:32:12 PM PDT 24
Peak memory 216388 kb
Host smart-da2bec4e-be9c-4992-8683-94f523c83134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676737889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.676737889
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2515954204
Short name T844
Test name
Test status
Simulation time 72819538 ps
CPU time 1.61 seconds
Started May 21 12:31:49 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 216176 kb
Host smart-9c9b2f70-0b45-4dcd-b984-5034912c0669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515954204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2515954204
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4255393565
Short name T641
Test name
Test status
Simulation time 138476210 ps
CPU time 1.03 seconds
Started May 21 12:31:37 PM PDT 24
Finished May 21 12:31:58 PM PDT 24
Peak memory 205728 kb
Host smart-ce8cf180-46ad-49c1-a469-74238c8cbbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255393565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4255393565
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3076667744
Short name T604
Test name
Test status
Simulation time 8935458620 ps
CPU time 7.34 seconds
Started May 21 12:31:45 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 217456 kb
Host smart-ae256484-1ddd-4c50-9b8d-24dd000d5efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076667744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3076667744
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2671415851
Short name T487
Test name
Test status
Simulation time 33355945 ps
CPU time 0.72 seconds
Started May 21 12:31:39 PM PDT 24
Finished May 21 12:31:59 PM PDT 24
Peak memory 205352 kb
Host smart-cbdd3ab4-3c6a-441c-a55b-e85b4d7fa006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671415851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2671415851
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2107043544
Short name T724
Test name
Test status
Simulation time 450943332 ps
CPU time 2.59 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 218412 kb
Host smart-5fb25a8e-7ed4-4a03-9ba2-f49860f8d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107043544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2107043544
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3963153617
Short name T350
Test name
Test status
Simulation time 15179760 ps
CPU time 0.73 seconds
Started May 21 12:31:48 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 206620 kb
Host smart-92957411-0fd1-4b8b-91bb-9d0546aebab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963153617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3963153617
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1823321432
Short name T343
Test name
Test status
Simulation time 8960455962 ps
CPU time 44.55 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:46 PM PDT 24
Peak memory 237412 kb
Host smart-1df350e5-229f-409e-ba2d-00aa73fbec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823321432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1823321432
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1265835516
Short name T854
Test name
Test status
Simulation time 5868936113 ps
CPU time 35.33 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:39 PM PDT 24
Peak memory 240568 kb
Host smart-e93eea5a-e307-43e4-835d-ba926d32ac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265835516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1265835516
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.67635100
Short name T18
Test name
Test status
Simulation time 34983655202 ps
CPU time 304.92 seconds
Started May 21 12:31:53 PM PDT 24
Finished May 21 12:37:11 PM PDT 24
Peak memory 251108 kb
Host smart-7bbe993a-d16a-4faf-9ec4-ed961ebda4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67635100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.67635100
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3652446084
Short name T837
Test name
Test status
Simulation time 871622844 ps
CPU time 9.98 seconds
Started May 21 12:31:44 PM PDT 24
Finished May 21 12:32:12 PM PDT 24
Peak memory 232644 kb
Host smart-5a912ae4-5e8b-4550-8594-dc016bbfc7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652446084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3652446084
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2105064764
Short name T807
Test name
Test status
Simulation time 159254508 ps
CPU time 3.02 seconds
Started May 21 12:31:37 PM PDT 24
Finished May 21 12:32:00 PM PDT 24
Peak memory 224400 kb
Host smart-948b4973-0c49-4f3c-842a-51e74918b1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105064764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2105064764
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1084262594
Short name T782
Test name
Test status
Simulation time 629801184 ps
CPU time 9.25 seconds
Started May 21 12:31:44 PM PDT 24
Finished May 21 12:32:11 PM PDT 24
Peak memory 240852 kb
Host smart-3a5d5604-6723-4434-bf7c-d9c8c72b0b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084262594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1084262594
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.616794683
Short name T881
Test name
Test status
Simulation time 107741895 ps
CPU time 2.17 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 216012 kb
Host smart-da9d9adb-8618-47c0-8d59-d45e9f79e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616794683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.616794683
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.472986334
Short name T846
Test name
Test status
Simulation time 2462816585 ps
CPU time 6.24 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 233260 kb
Host smart-189a3790-b0d8-466f-b1d7-758a76caab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472986334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.472986334
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.112939511
Short name T902
Test name
Test status
Simulation time 1103905222 ps
CPU time 15.15 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:18 PM PDT 24
Peak memory 219236 kb
Host smart-85654567-06e5-4f92-9800-21f68f3c1fc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112939511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.112939511
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1203878507
Short name T377
Test name
Test status
Simulation time 59003920 ps
CPU time 1.09 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 206976 kb
Host smart-35d84311-d377-498b-a83f-6614ac0a9e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203878507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1203878507
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1880332743
Short name T651
Test name
Test status
Simulation time 9332652177 ps
CPU time 12.34 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:13 PM PDT 24
Peak memory 216420 kb
Host smart-4c0df289-d8e6-4d8c-95c9-f3b5cec45e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880332743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1880332743
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3393152189
Short name T938
Test name
Test status
Simulation time 11520456540 ps
CPU time 3.14 seconds
Started May 21 12:31:40 PM PDT 24
Finished May 21 12:32:02 PM PDT 24
Peak memory 207956 kb
Host smart-a42ec78a-dea7-4b2f-836a-9f808ead89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393152189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3393152189
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1615907093
Short name T370
Test name
Test status
Simulation time 56527756 ps
CPU time 2.9 seconds
Started May 21 12:31:41 PM PDT 24
Finished May 21 12:32:03 PM PDT 24
Peak memory 216372 kb
Host smart-791e924d-b8bc-499a-b2ea-089de1f863c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615907093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1615907093
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2870901904
Short name T581
Test name
Test status
Simulation time 55219606 ps
CPU time 0.91 seconds
Started May 21 12:31:43 PM PDT 24
Finished May 21 12:32:03 PM PDT 24
Peak memory 205732 kb
Host smart-cff81fa8-b47d-4542-a4d9-6fd83a699214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870901904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2870901904
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.36154165
Short name T205
Test name
Test status
Simulation time 8098409270 ps
CPU time 7.99 seconds
Started May 21 12:31:44 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 220120 kb
Host smart-dbf7f771-2ecd-4ca5-a51f-34cc884fd014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36154165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.36154165
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1281161909
Short name T790
Test name
Test status
Simulation time 12475936 ps
CPU time 0.71 seconds
Started May 21 12:31:50 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 205604 kb
Host smart-d673a117-78d3-4d3e-890c-97ca95b5e85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281161909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1281161909
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2929530174
Short name T811
Test name
Test status
Simulation time 335443293 ps
CPU time 2.52 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:05 PM PDT 24
Peak memory 218708 kb
Host smart-43b67dac-1050-4d0d-b86b-5acedefa5eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929530174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2929530174
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1642868767
Short name T417
Test name
Test status
Simulation time 13915306 ps
CPU time 0.75 seconds
Started May 21 12:31:46 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 205648 kb
Host smart-a2e42c87-37f3-4ad3-8889-f57cc2a2c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642868767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1642868767
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.556648744
Short name T554
Test name
Test status
Simulation time 3904341151 ps
CPU time 55.22 seconds
Started May 21 12:31:49 PM PDT 24
Finished May 21 12:32:59 PM PDT 24
Peak memory 254400 kb
Host smart-a8dc9eb2-d894-4593-ac1c-92e7749c7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556648744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.556648744
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2077032298
Short name T926
Test name
Test status
Simulation time 12229535130 ps
CPU time 77.36 seconds
Started May 21 12:31:49 PM PDT 24
Finished May 21 12:33:22 PM PDT 24
Peak memory 224656 kb
Host smart-0be5fa3a-75c5-4755-9a9d-d62a69f146fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077032298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2077032298
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1557416592
Short name T129
Test name
Test status
Simulation time 484424915103 ps
CPU time 308.04 seconds
Started May 21 12:31:50 PM PDT 24
Finished May 21 12:37:13 PM PDT 24
Peak memory 253012 kb
Host smart-d0b7d8ba-e46b-4dff-a50a-eafddb367d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557416592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1557416592
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.175942442
Short name T5
Test name
Test status
Simulation time 277387785 ps
CPU time 6.35 seconds
Started May 21 12:31:49 PM PDT 24
Finished May 21 12:32:11 PM PDT 24
Peak memory 232688 kb
Host smart-bf6c4e63-9715-4913-aa3e-d767bb270883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175942442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.175942442
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2704199796
Short name T667
Test name
Test status
Simulation time 62511072 ps
CPU time 2.75 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:07 PM PDT 24
Peak memory 233124 kb
Host smart-dd8efcdd-b653-4a72-abf6-cfcdabd9c67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704199796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2704199796
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2140823325
Short name T288
Test name
Test status
Simulation time 27189922117 ps
CPU time 51.23 seconds
Started May 21 12:31:51 PM PDT 24
Finished May 21 12:32:56 PM PDT 24
Peak memory 229388 kb
Host smart-150318e9-d094-4699-826b-6c281f3d4d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140823325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2140823325
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2813718026
Short name T211
Test name
Test status
Simulation time 220260787 ps
CPU time 3.74 seconds
Started May 21 12:31:48 PM PDT 24
Finished May 21 12:32:08 PM PDT 24
Peak memory 224344 kb
Host smart-5be9ac13-0486-4a34-9044-da10d75a023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813718026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2813718026
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.631502328
Short name T38
Test name
Test status
Simulation time 7458509909 ps
CPU time 20.8 seconds
Started May 21 12:31:47 PM PDT 24
Finished May 21 12:32:25 PM PDT 24
Peak memory 237968 kb
Host smart-a5f7b119-85ed-4e0c-8071-85a40cbd6435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631502328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.631502328
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1977016190
Short name T556
Test name
Test status
Simulation time 206291071 ps
CPU time 4.44 seconds
Started May 21 12:31:52 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 222884 kb
Host smart-e0da1f27-4ac7-457f-a7ad-e8c18cdbc6c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1977016190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1977016190
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3702429877
Short name T369
Test name
Test status
Simulation time 2398676170 ps
CPU time 6.93 seconds
Started May 21 12:32:58 PM PDT 24
Finished May 21 12:33:16 PM PDT 24
Peak memory 216308 kb
Host smart-d64f7f69-c8cc-4113-9fc5-67f2f6d6a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702429877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3702429877
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1115153613
Short name T803
Test name
Test status
Simulation time 39383180175 ps
CPU time 11.26 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:13 PM PDT 24
Peak memory 216388 kb
Host smart-af39b708-fae9-4fe7-a2a4-e2d60e7f718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115153613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1115153613
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1721047601
Short name T167
Test name
Test status
Simulation time 433285808 ps
CPU time 3.19 seconds
Started May 21 12:31:42 PM PDT 24
Finished May 21 12:32:04 PM PDT 24
Peak memory 216452 kb
Host smart-3ccc665f-2376-421f-a237-dcb5b5a1377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721047601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1721047601
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3195166017
Short name T736
Test name
Test status
Simulation time 212529007 ps
CPU time 0.92 seconds
Started May 21 12:31:41 PM PDT 24
Finished May 21 12:32:01 PM PDT 24
Peak memory 206068 kb
Host smart-06ad8058-bf4b-4e26-bf9e-2a8d43420f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195166017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3195166017
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2410672666
Short name T838
Test name
Test status
Simulation time 16805774125 ps
CPU time 7.2 seconds
Started May 21 12:31:53 PM PDT 24
Finished May 21 12:32:13 PM PDT 24
Peak memory 220708 kb
Host smart-44969f06-27f8-40ba-bc82-7c5cf35d160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410672666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2410672666
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1586163079
Short name T60
Test name
Test status
Simulation time 48869694 ps
CPU time 0.76 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 204660 kb
Host smart-212cd6d8-4d12-4310-bc5c-5a6019803837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586163079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
586163079
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2070152775
Short name T587
Test name
Test status
Simulation time 31830462 ps
CPU time 2.56 seconds
Started May 21 12:29:55 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 221456 kb
Host smart-417b99ca-b218-4696-ba9e-6b120d88b246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070152775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2070152775
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1357114226
Short name T386
Test name
Test status
Simulation time 17846274 ps
CPU time 0.77 seconds
Started May 21 12:29:49 PM PDT 24
Finished May 21 12:30:19 PM PDT 24
Peak memory 206688 kb
Host smart-c3f3737f-5398-41b6-be27-99994604989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357114226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1357114226
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.29974174
Short name T621
Test name
Test status
Simulation time 41205264 ps
CPU time 0.72 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 215748 kb
Host smart-8f20f8cb-f0f7-444e-8eab-d1293fafcead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29974174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.29974174
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4121561530
Short name T194
Test name
Test status
Simulation time 11789970472 ps
CPU time 95.99 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:31:55 PM PDT 24
Peak memory 254476 kb
Host smart-c3675c34-48bd-458d-9160-cca9923a7fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121561530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4121561530
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1556269699
Short name T70
Test name
Test status
Simulation time 23342718956 ps
CPU time 119.11 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:32:21 PM PDT 24
Peak memory 254772 kb
Host smart-a6037e53-e5f8-4612-a79a-abc20cf265c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556269699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1556269699
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4196012056
Short name T779
Test name
Test status
Simulation time 66940467 ps
CPU time 3.72 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 232628 kb
Host smart-e1b58c9b-a128-4a2c-8637-35cb036db8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196012056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4196012056
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3712622491
Short name T183
Test name
Test status
Simulation time 254289076 ps
CPU time 2.33 seconds
Started May 21 12:29:54 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 224312 kb
Host smart-5ef18acf-0094-4c13-bf4e-2c59d4a529dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712622491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3712622491
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2608845762
Short name T9
Test name
Test status
Simulation time 101164250 ps
CPU time 2.25 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:24 PM PDT 24
Peak memory 232556 kb
Host smart-2ce6136b-a938-4f70-b14c-a3c4662af286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608845762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2608845762
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3381121078
Short name T399
Test name
Test status
Simulation time 18158063 ps
CPU time 1.01 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 216584 kb
Host smart-8ca43635-9722-4b07-99d8-70fce98fa9bf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381121078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3381121078
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3264252233
Short name T861
Test name
Test status
Simulation time 28026783421 ps
CPU time 11.74 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 233704 kb
Host smart-517891d4-3d0b-4cfa-a940-5eee9b0b0fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264252233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3264252233
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3960016265
Short name T282
Test name
Test status
Simulation time 1188801234 ps
CPU time 6.16 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:28 PM PDT 24
Peak memory 233152 kb
Host smart-4960e6c5-8e22-4311-baaa-8307f514b229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960016265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3960016265
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4200371147
Short name T553
Test name
Test status
Simulation time 136012958 ps
CPU time 3.91 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 222656 kb
Host smart-b4b7ba25-47ce-4eda-842a-c9c0a8ed693e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4200371147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4200371147
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.798953676
Short name T181
Test name
Test status
Simulation time 28884224344 ps
CPU time 315.49 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:35:51 PM PDT 24
Peak memory 264904 kb
Host smart-9fe5800b-7504-4e85-859e-35255498fd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798953676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.798953676
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4141258203
Short name T633
Test name
Test status
Simulation time 113780076 ps
CPU time 0.71 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 205400 kb
Host smart-949a5847-962d-4fb8-9229-ecd4bf0c5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141258203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4141258203
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2961730822
Short name T976
Test name
Test status
Simulation time 1487621091 ps
CPU time 7.35 seconds
Started May 21 12:29:48 PM PDT 24
Finished May 21 12:30:24 PM PDT 24
Peak memory 216272 kb
Host smart-a4bcc2e9-4d83-42db-8ba0-138399c7e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961730822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2961730822
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3737801104
Short name T828
Test name
Test status
Simulation time 137886966 ps
CPU time 1.49 seconds
Started May 21 12:29:57 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 216520 kb
Host smart-7d269eed-fb0f-4d5d-8806-2ffcd55c66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737801104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3737801104
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.394954985
Short name T373
Test name
Test status
Simulation time 16675635 ps
CPU time 0.72 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 205336 kb
Host smart-f58d6abd-f426-45b6-8d87-cf372dd02592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394954985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.394954985
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.999020764
Short name T797
Test name
Test status
Simulation time 270624784 ps
CPU time 4.21 seconds
Started May 21 12:29:54 PM PDT 24
Finished May 21 12:30:28 PM PDT 24
Peak memory 234164 kb
Host smart-9d59cc81-9589-453b-a159-36b29395eeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999020764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.999020764
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2343077398
Short name T379
Test name
Test status
Simulation time 45820818 ps
CPU time 0.73 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 205256 kb
Host smart-6d326140-23ee-42ca-bb46-08e3380602ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343077398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
343077398
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1024214641
Short name T151
Test name
Test status
Simulation time 404808327 ps
CPU time 4.81 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 219700 kb
Host smart-28267e79-4566-4124-a104-43cd6c86ec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024214641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1024214641
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.934940932
Short name T699
Test name
Test status
Simulation time 25416808 ps
CPU time 0.74 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 206336 kb
Host smart-d24810e9-4621-46bb-974e-6b9d472d8101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934940932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.934940932
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1614189456
Short name T265
Test name
Test status
Simulation time 4354151293 ps
CPU time 37.91 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:31:00 PM PDT 24
Peak memory 249164 kb
Host smart-03d2cb91-6808-4a73-995b-d3887c3bf177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614189456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1614189456
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2353108309
Short name T138
Test name
Test status
Simulation time 83482833356 ps
CPU time 439.14 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:37:40 PM PDT 24
Peak memory 266980 kb
Host smart-422d3ae6-11b2-439a-9cbf-ac2a9c3ca694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353108309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2353108309
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2695523566
Short name T759
Test name
Test status
Simulation time 1211102444 ps
CPU time 4.05 seconds
Started May 21 12:29:56 PM PDT 24
Finished May 21 12:30:29 PM PDT 24
Peak memory 217284 kb
Host smart-8c7df562-f9ff-4166-a375-76e3239e6b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695523566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2695523566
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2103050613
Short name T801
Test name
Test status
Simulation time 98181443 ps
CPU time 3.05 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 224468 kb
Host smart-5efd6c3a-139b-4fdb-8dd1-df933753ae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103050613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2103050613
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2705912802
Short name T103
Test name
Test status
Simulation time 1989599334 ps
CPU time 4.72 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 218644 kb
Host smart-0fd74d07-a00e-490b-94c8-90d5b01fdf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705912802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2705912802
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3063604439
Short name T835
Test name
Test status
Simulation time 1155673447 ps
CPU time 15.93 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 234852 kb
Host smart-cc64f939-39b1-4e58-9131-b038e8fe3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063604439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3063604439
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1180785005
Short name T535
Test name
Test status
Simulation time 127152341 ps
CPU time 0.99 seconds
Started May 21 12:29:55 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 217888 kb
Host smart-938eaa1d-d8bc-4c01-8527-b00f690ccaeb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180785005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1180785005
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3929810645
Short name T680
Test name
Test status
Simulation time 3411935198 ps
CPU time 11.21 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 236980 kb
Host smart-29e8fd79-6b14-4263-8356-b4651f62486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929810645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3929810645
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3775252306
Short name T312
Test name
Test status
Simulation time 169753872 ps
CPU time 2.72 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:30:33 PM PDT 24
Peak memory 218688 kb
Host smart-9b26b2b5-b023-4ea8-af73-f58e957c1ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775252306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3775252306
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3536383958
Short name T972
Test name
Test status
Simulation time 2173046597 ps
CPU time 7.14 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:29 PM PDT 24
Peak memory 221736 kb
Host smart-c4f84251-1c49-493d-b0cb-714ad325a8d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3536383958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3536383958
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3537940048
Short name T253
Test name
Test status
Simulation time 39035425621 ps
CPU time 234.6 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:34:15 PM PDT 24
Peak memory 256308 kb
Host smart-04381e12-a9a2-48f3-8490-dea05eb15a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537940048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3537940048
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4265223260
Short name T327
Test name
Test status
Simulation time 2073147548 ps
CPU time 28.7 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:56 PM PDT 24
Peak memory 216264 kb
Host smart-4d843396-415e-4ff7-808e-64370bb8c178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265223260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4265223260
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2213087593
Short name T639
Test name
Test status
Simulation time 7637056575 ps
CPU time 22.34 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:30:52 PM PDT 24
Peak memory 216404 kb
Host smart-b3a2382e-b9dd-4035-8fec-24ce9ca6a917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213087593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2213087593
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2895852270
Short name T862
Test name
Test status
Simulation time 785354103 ps
CPU time 7.81 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:28 PM PDT 24
Peak memory 216380 kb
Host smart-df0c8c67-f85d-446d-a11c-f9420185f23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895852270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2895852270
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1734120810
Short name T575
Test name
Test status
Simulation time 29165988 ps
CPU time 0.79 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 205744 kb
Host smart-f137d5f8-9b19-4223-8941-bc444576a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734120810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1734120810
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.204136898
Short name T279
Test name
Test status
Simulation time 33018175005 ps
CPU time 26.45 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 227120 kb
Host smart-0e3bbc12-a5e0-4cd7-911b-c149f47ba114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204136898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.204136898
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.203709693
Short name T61
Test name
Test status
Simulation time 40663408 ps
CPU time 0.7 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 204748 kb
Host smart-bc0d87ea-e2a8-4a77-b071-ee1f3b110264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203709693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.203709693
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.40295350
Short name T628
Test name
Test status
Simulation time 660556223 ps
CPU time 4.43 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:24 PM PDT 24
Peak memory 219592 kb
Host smart-a1e592cb-456b-4d6c-a9eb-1d3ba519a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40295350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.40295350
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3882044722
Short name T758
Test name
Test status
Simulation time 32858885 ps
CPU time 0.78 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 205328 kb
Host smart-b0f22ef8-952c-4f0a-985d-b8834550933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882044722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3882044722
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2954417029
Short name T588
Test name
Test status
Simulation time 63295991974 ps
CPU time 109.32 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:32:10 PM PDT 24
Peak memory 257424 kb
Host smart-83054aa3-1524-4358-9cbc-003d4c09ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954417029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2954417029
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3522768638
Short name T738
Test name
Test status
Simulation time 498292785020 ps
CPU time 211.96 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:33:54 PM PDT 24
Peak memory 254652 kb
Host smart-2c74dad7-198e-4a8e-8fef-f32dfe98bdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522768638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3522768638
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1729383987
Short name T447
Test name
Test status
Simulation time 30433201504 ps
CPU time 149.25 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:32:50 PM PDT 24
Peak memory 249480 kb
Host smart-5df1f117-4815-4852-ba37-c1846c7662d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729383987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1729383987
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.392613243
Short name T295
Test name
Test status
Simulation time 95080346 ps
CPU time 4.13 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 232692 kb
Host smart-e45170d7-3c96-402c-b277-f52d40a58514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392613243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.392613243
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4037776316
Short name T608
Test name
Test status
Simulation time 367954504 ps
CPU time 6.79 seconds
Started May 21 12:29:55 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 233376 kb
Host smart-8c0aa0b9-1dc5-4a02-ada7-1d3827fce10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037776316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4037776316
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.484117692
Short name T176
Test name
Test status
Simulation time 3682656170 ps
CPU time 28.68 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:49 PM PDT 24
Peak memory 219336 kb
Host smart-96afd130-d2ae-4e25-b1a5-a7e1db5878e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484117692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.484117692
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.906285692
Short name T568
Test name
Test status
Simulation time 119020042 ps
CPU time 1.03 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:22 PM PDT 24
Peak memory 216764 kb
Host smart-e4b5d3a1-223c-4d2f-aa22-af54dd3e2d61
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906285692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.906285692
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.474739899
Short name T955
Test name
Test status
Simulation time 888508876 ps
CPU time 4.67 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 233060 kb
Host smart-1297bdce-535c-4578-9336-3e98a02e3b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474739899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
474739899
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.6946347
Short name T470
Test name
Test status
Simulation time 2863684524 ps
CPU time 7.87 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:30 PM PDT 24
Peak memory 224588 kb
Host smart-27577558-d501-4ea0-87ab-782f13a0ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6946347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.6946347
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2831323035
Short name T778
Test name
Test status
Simulation time 1105982173 ps
CPU time 4.02 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:26 PM PDT 24
Peak memory 222320 kb
Host smart-2ce0d197-a15e-41a4-8723-6b81d82ab777
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2831323035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2831323035
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.77784872
Short name T773
Test name
Test status
Simulation time 24571710125 ps
CPU time 23.04 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:43 PM PDT 24
Peak memory 216488 kb
Host smart-d89cf328-b68d-4d9d-9637-df310fa6b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77784872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.77784872
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3306499588
Short name T543
Test name
Test status
Simulation time 44986109 ps
CPU time 0.74 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 205472 kb
Host smart-913b73ad-71b0-4678-b1f6-c03d6f31a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306499588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3306499588
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2572164294
Short name T395
Test name
Test status
Simulation time 137104647 ps
CPU time 1.55 seconds
Started May 21 12:29:51 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 216208 kb
Host smart-45f0dc1b-4bfc-420b-9c8b-d06c83c95dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572164294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2572164294
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4219377737
Short name T407
Test name
Test status
Simulation time 51356764 ps
CPU time 0.81 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:24 PM PDT 24
Peak memory 205756 kb
Host smart-4acbac4b-0bed-4df2-aa12-450ee67a83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219377737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4219377737
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.474782559
Short name T481
Test name
Test status
Simulation time 70163590 ps
CPU time 2.13 seconds
Started May 21 12:29:53 PM PDT 24
Finished May 21 12:30:25 PM PDT 24
Peak memory 217368 kb
Host smart-2c8e0dac-3878-4161-8472-cd5c18ccbfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474782559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.474782559
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1395918514
Short name T579
Test name
Test status
Simulation time 23505931 ps
CPU time 0.69 seconds
Started May 21 12:30:01 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 204644 kb
Host smart-82a196e3-fac9-4925-bdfa-4782f8aa1139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395918514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
395918514
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.38902172
Short name T594
Test name
Test status
Simulation time 3084627328 ps
CPU time 7.14 seconds
Started May 21 12:30:02 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 234596 kb
Host smart-a7db17e9-d891-4308-8e80-af5dbbc67489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38902172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.38902172
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.348088446
Short name T168
Test name
Test status
Simulation time 47884582 ps
CPU time 0.78 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:21 PM PDT 24
Peak memory 206716 kb
Host smart-ae7bdfaa-8e39-4da5-ba43-7940aa4d249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348088446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.348088446
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1121358276
Short name T229
Test name
Test status
Simulation time 5242320928 ps
CPU time 95.32 seconds
Started May 21 12:30:02 PM PDT 24
Finished May 21 12:32:06 PM PDT 24
Peak memory 252060 kb
Host smart-4fc07e9f-de32-4cb3-8ee9-e5236e043a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121358276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1121358276
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.4077724151
Short name T550
Test name
Test status
Simulation time 33574287012 ps
CPU time 271.21 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:35:00 PM PDT 24
Peak memory 252444 kb
Host smart-7255ec5f-1062-4511-a7fb-eadc58f8ce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077724151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4077724151
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1525522001
Short name T254
Test name
Test status
Simulation time 9128175945 ps
CPU time 85.82 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:31:53 PM PDT 24
Peak memory 249272 kb
Host smart-0568e37c-0ba9-4b7a-b4a9-7ba42f8cd4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525522001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1525522001
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3249457556
Short name T547
Test name
Test status
Simulation time 4215818375 ps
CPU time 18.96 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:54 PM PDT 24
Peak memory 234260 kb
Host smart-3269a5f8-defd-47c0-a6a8-b5a2e00c8dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249457556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3249457556
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1388729876
Short name T307
Test name
Test status
Simulation time 850122297 ps
CPU time 11.41 seconds
Started May 21 12:30:06 PM PDT 24
Finished May 21 12:30:48 PM PDT 24
Peak memory 232724 kb
Host smart-f28068d3-828a-4034-a9fb-45742e5e6ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388729876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1388729876
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2176442721
Short name T716
Test name
Test status
Simulation time 56876278 ps
CPU time 0.97 seconds
Started May 21 12:29:52 PM PDT 24
Finished May 21 12:30:23 PM PDT 24
Peak memory 217820 kb
Host smart-c4744d8a-962f-4953-b09d-3fa6cc355144
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176442721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2176442721
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3757339756
Short name T212
Test name
Test status
Simulation time 2479438791 ps
CPU time 8.02 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:41 PM PDT 24
Peak memory 227212 kb
Host smart-088a9d7d-2b00-4a45-9037-ddc42df2ee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757339756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3757339756
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1319741362
Short name T640
Test name
Test status
Simulation time 126772676 ps
CPU time 2.31 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:37 PM PDT 24
Peak memory 220968 kb
Host smart-43103f42-28b8-43ad-adbc-21ed724a5539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319741362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1319741362
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2044656715
Short name T494
Test name
Test status
Simulation time 294196057 ps
CPU time 4.99 seconds
Started May 21 12:30:00 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 219060 kb
Host smart-58bac211-1a00-446f-bd4c-790f82b7a7be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2044656715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2044656715
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1869306401
Short name T163
Test name
Test status
Simulation time 197436889 ps
CPU time 0.98 seconds
Started May 21 12:30:00 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 206776 kb
Host smart-4af40b61-0f3b-47f1-897d-810ae11b2994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869306401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1869306401
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1056882083
Short name T431
Test name
Test status
Simulation time 9505890018 ps
CPU time 13.47 seconds
Started May 21 12:29:50 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 216372 kb
Host smart-acf3d60d-dc3c-4652-a796-48a9a1b6fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056882083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1056882083
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.165879060
Short name T486
Test name
Test status
Simulation time 4413123403 ps
CPU time 4.61 seconds
Started May 21 12:29:58 PM PDT 24
Finished May 21 12:30:32 PM PDT 24
Peak memory 216396 kb
Host smart-d28840e0-8bd1-4d1d-aef3-4784ff216dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165879060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.165879060
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1504491451
Short name T939
Test name
Test status
Simulation time 259818974 ps
CPU time 1.27 seconds
Started May 21 12:29:57 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 216412 kb
Host smart-9ff09f57-131e-4fb6-87b8-83e52588c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504491451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1504491451
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3067024317
Short name T898
Test name
Test status
Simulation time 30709371 ps
CPU time 0.83 seconds
Started May 21 12:29:57 PM PDT 24
Finished May 21 12:30:27 PM PDT 24
Peak memory 205816 kb
Host smart-ca738cfe-9971-4251-b4c1-f6df7c5c0c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067024317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3067024317
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.377712765
Short name T387
Test name
Test status
Simulation time 19825022017 ps
CPU time 22.46 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:30:51 PM PDT 24
Peak memory 256908 kb
Host smart-71e8223d-6e55-42f2-97c2-9df2e67fba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377712765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.377712765
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2317993059
Short name T381
Test name
Test status
Simulation time 16356363 ps
CPU time 0.76 seconds
Started May 21 12:30:02 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 204780 kb
Host smart-29358429-8b13-497e-9197-e41a669e2c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317993059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
317993059
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2916972196
Short name T624
Test name
Test status
Simulation time 445420466 ps
CPU time 2.2 seconds
Started May 21 12:29:57 PM PDT 24
Finished May 21 12:30:29 PM PDT 24
Peak memory 218440 kb
Host smart-e73880b0-660b-4533-b20f-a095f85b3344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916972196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2916972196
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.220541760
Short name T717
Test name
Test status
Simulation time 20566220 ps
CPU time 0.81 seconds
Started May 21 12:30:02 PM PDT 24
Finished May 21 12:30:31 PM PDT 24
Peak memory 206332 kb
Host smart-9b9591ef-bf61-4971-9db0-cecd83ce923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220541760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.220541760
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1695552226
Short name T733
Test name
Test status
Simulation time 9603598671 ps
CPU time 18.8 seconds
Started May 21 12:29:56 PM PDT 24
Finished May 21 12:30:44 PM PDT 24
Peak memory 235328 kb
Host smart-62804bf4-bd20-4810-84ee-2c2b1f3e514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695552226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1695552226
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1651689456
Short name T490
Test name
Test status
Simulation time 1578650599 ps
CPU time 24.27 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:59 PM PDT 24
Peak memory 217448 kb
Host smart-3fba9e17-b3e0-4659-bd1d-efaa69c5744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651689456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1651689456
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2146887885
Short name T243
Test name
Test status
Simulation time 152634505915 ps
CPU time 263.37 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:34:57 PM PDT 24
Peak memory 257112 kb
Host smart-ee5e3a16-cbe0-4733-ac22-73a8d2e5880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146887885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2146887885
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1518314354
Short name T610
Test name
Test status
Simulation time 753539117 ps
CPU time 10.5 seconds
Started May 21 12:30:02 PM PDT 24
Finished May 21 12:30:41 PM PDT 24
Peak memory 233552 kb
Host smart-967adb98-dd7b-4c58-802f-6f59d4059875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518314354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1518314354
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3618607089
Short name T784
Test name
Test status
Simulation time 193244851 ps
CPU time 5.21 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:40 PM PDT 24
Peak memory 219912 kb
Host smart-2f2a0f30-df91-42dd-9bcf-0c8c5db9fe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618607089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3618607089
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1016495179
Short name T198
Test name
Test status
Simulation time 156076946971 ps
CPU time 123.57 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:32:32 PM PDT 24
Peak memory 234580 kb
Host smart-1b5949be-21fa-4bea-a388-630b152f7c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016495179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1016495179
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3199860398
Short name T585
Test name
Test status
Simulation time 50690238 ps
CPU time 0.98 seconds
Started May 21 12:29:57 PM PDT 24
Finished May 21 12:30:28 PM PDT 24
Peak memory 216648 kb
Host smart-226a4fc1-d088-45ef-871d-d08208c8c2bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199860398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3199860398
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2909180107
Short name T824
Test name
Test status
Simulation time 621345143 ps
CPU time 3.9 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:39 PM PDT 24
Peak memory 234932 kb
Host smart-cf351628-af81-4934-ba71-67806d591a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909180107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2909180107
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1650462490
Short name T437
Test name
Test status
Simulation time 434633435 ps
CPU time 2.52 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:38 PM PDT 24
Peak memory 233480 kb
Host smart-a441ea8f-3cf8-46d1-8c8c-2de4e1afbad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650462490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1650462490
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3504240356
Short name T475
Test name
Test status
Simulation time 4888752028 ps
CPU time 11.25 seconds
Started May 21 12:30:04 PM PDT 24
Finished May 21 12:30:47 PM PDT 24
Peak memory 222476 kb
Host smart-c408d763-4004-4750-a49a-b262c02e4e8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3504240356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3504240356
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2395507618
Short name T30
Test name
Test status
Simulation time 68769837454 ps
CPU time 166.02 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:33:15 PM PDT 24
Peak memory 240848 kb
Host smart-fa343449-ed4d-48c3-a99a-288a2b07ead8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395507618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2395507618
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.427253884
Short name T969
Test name
Test status
Simulation time 16757952 ps
CPU time 0.7 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:33 PM PDT 24
Peak memory 205432 kb
Host smart-1e996e86-9f24-498b-985f-0d7a6c2f55b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427253884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.427253884
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3536018599
Short name T901
Test name
Test status
Simulation time 8342454829 ps
CPU time 6.88 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 216460 kb
Host smart-7dd7d0f5-b466-4d37-af19-cfafbaaed4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536018599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3536018599
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3725914905
Short name T450
Test name
Test status
Simulation time 36961087 ps
CPU time 0.67 seconds
Started May 21 12:30:05 PM PDT 24
Finished May 21 12:30:35 PM PDT 24
Peak memory 205372 kb
Host smart-12e30de1-53f0-4773-96c5-2ab483cfe28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725914905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3725914905
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2492106635
Short name T559
Test name
Test status
Simulation time 110692499 ps
CPU time 0.87 seconds
Started May 21 12:30:03 PM PDT 24
Finished May 21 12:30:34 PM PDT 24
Peak memory 205748 kb
Host smart-619c05e7-e1cd-4a26-97c4-7d413c8d9ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492106635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2492106635
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2019559514
Short name T686
Test name
Test status
Simulation time 31622084260 ps
CPU time 28.34 seconds
Started May 21 12:29:59 PM PDT 24
Finished May 21 12:30:57 PM PDT 24
Peak memory 235932 kb
Host smart-4cde8e0f-199c-440d-b4a9-6a16e2733778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019559514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2019559514
Directory /workspace/9.spi_device_upload/latest
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