Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3976055	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4113477

1

T1

3484

T2

895

T3

2232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4602771	1			T1	5206		T2	6		T3	2646
values[0x0]	1740593	1			T1	446		T2	452		T3	450
values[0x1]	1746168	1			T1	465		T2	442		T3	463

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2805620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5283912

1

T1

4022

T2

896

T3

2514

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30217	1			T1	9		T3	9		T4	23
valid_sources[0x01]	36655	1			T1	10		T2	5		T3	12
valid_sources[0x02]	29759	1			T1	4		T2	3		T3	39
valid_sources[0x03]	29293	1			T1	12		T2	3		T3	35
valid_sources[0x04]	27688	1			T1	9		T2	4		T3	24
valid_sources[0x05]	29339	1			T1	22		T2	1		T4	14
valid_sources[0x06]	33649	1			T1	28		T2	3		T3	29
valid_sources[0x07]	32362	1			T1	21		T2	5		T3	2
valid_sources[0x08]	32332	1			T1	21		T3	12		T4	36
valid_sources[0x09]	32785	1			T1	6		T2	3		T3	20
valid_sources[0x0a]	31369	1			T1	25		T2	4		T3	18
valid_sources[0x0b]	29930	1			T1	20		T2	4		T3	7
valid_sources[0x0c]	34329	1			T1	121		T2	4		T3	6
valid_sources[0x0d]	29092	1			T1	28		T2	2		T3	14
valid_sources[0x0e]	30520	1			T1	40		T2	3		T3	30
valid_sources[0x0f]	28834	1			T2	5		T3	4		T4	15
valid_sources[0x10]	31703	1			T1	9		T2	3		T3	26
valid_sources[0x11]	31807	1			T1	40		T2	3		T3	10
valid_sources[0x12]	29885	1			T1	14		T2	2		T3	3
valid_sources[0x13]	32839	1			T1	3		T2	2		T3	4
valid_sources[0x14]	39998	1			T1	7		T2	2		T3	28
valid_sources[0x15]	32813	1			T1	9		T2	9		T3	15
valid_sources[0x16]	28904	1			T1	17		T2	6		T3	6
valid_sources[0x17]	30545	1			T1	5		T2	2		T3	1
valid_sources[0x18]	29209	1			T1	29		T2	2		T3	3
valid_sources[0x19]	28988	1			T1	84		T2	9		T3	7
valid_sources[0x1a]	29934	1			T1	30		T2	4		T3	14
valid_sources[0x1b]	29542	1			T1	75		T2	6		T4	30
valid_sources[0x1c]	33903	1			T1	25		T2	3		T3	31
valid_sources[0x1d]	30324	1			T1	75		T2	4		T3	25
valid_sources[0x1e]	29263	1			T1	20		T2	4		T3	1
valid_sources[0x1f]	28230	1			T1	9		T2	4		T3	3
valid_sources[0x20]	30100	1			T1	7		T2	2		T3	15
valid_sources[0x21]	34649	1			T1	2		T3	1		T4	14
valid_sources[0x22]	31679	1			T1	33		T2	2		T3	47
valid_sources[0x23]	30106	1			T1	25		T2	2		T3	4
valid_sources[0x24]	31710	1			T1	14		T2	9		T3	11
valid_sources[0x25]	30839	1			T1	10		T2	4		T3	1
valid_sources[0x26]	27351	1			T2	4		T3	23		T4	32
valid_sources[0x27]	45973	1			T1	33		T2	1		T3	10
valid_sources[0x28]	31853	1			T2	6		T3	43		T4	43
valid_sources[0x29]	29524	1			T1	40		T2	7		T3	17
valid_sources[0x2a]	28472	1			T1	15		T2	3		T3	11
valid_sources[0x2b]	30949	1			T1	23		T2	3		T3	11
valid_sources[0x2c]	29982	1			T1	21		T2	3		T3	5
valid_sources[0x2d]	30374	1			T1	11		T2	2		T3	10
valid_sources[0x2e]	37085	1			T2	4		T3	23		T4	63
valid_sources[0x2f]	32592	1			T1	15		T2	8		T3	18
valid_sources[0x30]	36036	1			T1	4		T2	4		T3	3
valid_sources[0x31]	34724	1			T1	9		T2	4		T3	44
valid_sources[0x32]	28569	1			T1	19		T2	3		T3	12
valid_sources[0x33]	41592	1			T1	4		T2	4		T3	26
valid_sources[0x34]	31350	1			T1	36		T2	2		T3	14
valid_sources[0x35]	34281	1			T1	45		T3	6		T4	19
valid_sources[0x36]	28440	1			T1	34		T2	3		T3	1
valid_sources[0x37]	31386	1			T1	27		T2	3		T3	5
valid_sources[0x38]	33647	1			T1	28		T2	2		T3	1
valid_sources[0x39]	33130	1			T1	10		T2	1		T3	12
valid_sources[0x3a]	27377	1			T1	22		T2	3		T4	10
valid_sources[0x3b]	29922	1			T1	4		T2	1		T3	13
valid_sources[0x3c]	30366	1			T1	12		T2	5		T3	7
valid_sources[0x3d]	29968	1			T1	36		T2	4		T3	21
valid_sources[0x3e]	29149	1			T1	19		T2	1		T3	26
valid_sources[0x3f]	36861	1			T1	66		T2	3		T3	6
valid_sources[0x40]	38198	1			T1	9		T2	2		T3	8
valid_sources[0x41]	28120	1			T1	28		T2	4		T3	26
valid_sources[0x42]	28161	1			T1	17		T2	2		T4	19
valid_sources[0x43]	61222	1			T1	18		T2	2		T3	4
valid_sources[0x44]	29944	1			T1	29		T2	1		T3	6
valid_sources[0x45]	29713	1			T1	2		T2	5		T3	1
valid_sources[0x46]	29623	1			T1	37		T2	2		T3	42
valid_sources[0x47]	33947	1			T1	14		T2	7		T3	32
valid_sources[0x48]	30131	1			T1	12		T2	1		T3	1
valid_sources[0x49]	32216	1			T1	4		T2	1		T3	3
valid_sources[0x4a]	31887	1			T1	26		T2	3		T3	13
valid_sources[0x4b]	30821	1			T1	25		T2	5		T4	7
valid_sources[0x4c]	30346	1			T1	14		T2	2		T3	1
valid_sources[0x4d]	31915	1			T1	11		T2	5		T3	1
valid_sources[0x4e]	30838	1			T1	19		T2	3		T3	4
valid_sources[0x4f]	33166	1			T1	1		T2	4		T3	7
valid_sources[0x50]	31664	1			T1	14		T2	7		T3	18
valid_sources[0x51]	30502	1			T1	44		T2	5		T3	9
valid_sources[0x52]	30022	1			T1	9		T2	1		T3	9
valid_sources[0x53]	29240	1			T1	26		T2	7		T3	24
valid_sources[0x54]	30001	1			T1	37		T2	1		T3	49
valid_sources[0x55]	29345	1			T1	4		T2	1		T3	25
valid_sources[0x56]	29749	1			T1	86		T2	4		T3	25
valid_sources[0x57]	30814	1			T1	14		T2	2		T3	4
valid_sources[0x58]	30300	1			T1	30		T2	7		T4	21
valid_sources[0x59]	31008	1			T1	44		T2	8		T3	14
valid_sources[0x5a]	28632	1			T1	46		T2	2		T3	21
valid_sources[0x5b]	28209	1			T1	24		T2	1		T3	4
valid_sources[0x5c]	29527	1			T1	8		T2	3		T3	9
valid_sources[0x5d]	45442	1			T1	12		T4	56		T6	10
valid_sources[0x5e]	27858	1			T1	40		T2	4		T3	8
valid_sources[0x5f]	31945	1			T2	1		T4	90		T9	2
valid_sources[0x60]	30943	1			T1	13		T2	2		T3	19
valid_sources[0x61]	31234	1			T1	34		T3	31		T4	15
valid_sources[0x62]	28575	1			T1	27		T2	6		T4	25
valid_sources[0x63]	27636	1			T1	19		T2	6		T3	65
valid_sources[0x64]	32004	1			T1	8		T2	5		T3	1
valid_sources[0x65]	29163	1			T1	6		T2	5		T3	8
valid_sources[0x66]	31518	1			T1	29		T2	7		T3	24
valid_sources[0x67]	31582	1			T1	48		T2	5		T3	9
valid_sources[0x68]	33393	1			T1	27		T2	3		T3	62
valid_sources[0x69]	30960	1			T1	28		T2	8		T3	31
valid_sources[0x6a]	30094	1			T1	34		T2	2		T3	9
valid_sources[0x6b]	36191	1			T1	18		T2	3		T3	15
valid_sources[0x6c]	30278	1			T1	21		T2	4		T3	22
valid_sources[0x6d]	34711	1			T1	30		T2	1		T3	30
valid_sources[0x6e]	33505	1			T1	49		T2	2		T3	15
valid_sources[0x6f]	28521	1			T1	14		T2	3		T3	18
valid_sources[0x70]	29170	1			T1	7		T3	3		T4	10
valid_sources[0x71]	37555	1			T1	10		T2	1		T3	24
valid_sources[0x72]	29439	1			T1	54		T2	2		T3	9
valid_sources[0x73]	34573	1			T1	29		T2	7		T3	6
valid_sources[0x74]	28876	1			T1	3		T2	8		T3	14
valid_sources[0x75]	31549	1			T1	16		T2	3		T3	7
valid_sources[0x76]	32093	1			T1	20		T2	1		T3	4
valid_sources[0x77]	30757	1			T1	24		T2	5		T3	17
valid_sources[0x78]	31793	1			T1	48		T2	4		T3	52
valid_sources[0x79]	30039	1			T1	19		T3	15		T4	42
valid_sources[0x7a]	31000	1			T1	4		T2	4		T4	34
valid_sources[0x7b]	31920	1			T1	7		T2	4		T3	22
valid_sources[0x7c]	29987	1			T1	41		T2	4		T3	18
valid_sources[0x7d]	32587	1			T1	4		T2	3		T3	4
valid_sources[0x7e]	30079	1			T1	5		T2	5		T3	8
valid_sources[0x7f]	31929	1			T1	24		T2	7		T3	17
valid_sources[0x80]	30820	1			T1	25		T2	4		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

999169

1

T1

2579

T2

3

T3

1322

values[0x0]

all_enables

biggest_size

1567874

1

T1

444

T2

451

T3

449

values[0x1]

all_enables

biggest_size

1546434

1

T1

461

T2

441

T3

461