Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3995647

1

T1

2633

T2

5

T3

1327

full_word

4112579

1

T1

3484

T2

895

T3

2232

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8107806	1			T1	6117		T2	900		T3	3559
auto[TlIntgErrCmd]	149	1			T88	12		T89	3		T90	5
auto[TlIntgErrData]	130	1			T88	10		T89	1		T90	6
auto[TlIntgErrBoth]	141	1			T88	8		T89	6		T90	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4604170

1

T1

5206

T2

6

T3

2646

auto[1]

3504056

1

T1

911

T2

894

T3

913

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3604748	1			T1	2627		T2	3		T3	1324
auto[TlIntgErrNone]	partial	auto[1]	390507	1			T1	6		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	999254	1			T1	2579		T2	3		T3	1322
auto[TlIntgErrNone]	full_word	auto[1]	3113297	1			T1	905		T2	892		T3	910
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T88	5		T89	1		T90	1
auto[TlIntgErrCmd]	partial	auto[1]	92	1			T88	7		T89	2		T90	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T262	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T263	1		T264	1		T265	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T88	2		T90	5		T108	5
auto[TlIntgErrData]	partial	auto[1]	62	1			T88	7		T90	1		T108	9
auto[TlIntgErrData]	full_word	auto[0]	6	1			T266	1		T267	3		T263	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T88	1		T89	1		T262	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T88	4		T89	2		T90	5
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T88	3		T89	3		T90	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T262	1		T266	1		T268	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T88	1		T89	1		T269	2