Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457760384	2518024	0	0
DepthKnown_A	457760384	457629268	0	0
RvalidKnown_A	457760384	457629268	0	0
WreadyKnown_A	457760384	457629268	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	2518024	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	1668	0	0
T4	300408	0	0	0
T5	1200	0	0	0
T6	1774	100	0	0
T7	8409	0	0	0
T8	41520	1663	0	0
T9	234974	1663	0	0
T10	101438	0	0	0
T11	0	16634	0	0
T12	0	1343	0	0
T13	0	1668	0	0
T14	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457760384	2911207	0	0
DepthKnown_A	457760384	457629268	0	0
RvalidKnown_A	457760384	457629268	0	0
WreadyKnown_A	457760384	457629268	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	2911207	0	0
T1	92852	832	0	0
T2	404322	3731	0	0
T3	62661	837	0	0
T4	300408	0	0	0
T5	1200	0	0	0
T6	1774	100	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	832	0	0
T10	101438	0	0	0
T11	0	11648	0	0
T12	0	3990	0	0
T13	0	837	0	0
T14	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457760384	166612	0	0
DepthKnown_A	457760384	457629268	0	0
RvalidKnown_A	457760384	457629268	0	0
WreadyKnown_A	457760384	457629268	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	166612	0	0
T4	300408	540	0	0
T5	1200	0	0	0
T6	1774	100	0	0
T7	8409	0	0	0
T8	41520	0	0	0
T9	234974	98	0	0
T10	101438	558	0	0
T11	0	230	0	0
T12	44383	0	0	0
T16	2969	2	0	0
T17	0	433	0	0
T18	0	873	0	0
T23	0	100	0	0
T30	0	912	0	0
T31	1190	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457760384	390124	0	0
DepthKnown_A	457760384	457629268	0	0
RvalidKnown_A	457760384	457629268	0	0
WreadyKnown_A	457760384	457629268	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	390124	0	0
T4	300408	540	0	0
T5	1200	0	0	0
T6	1774	100	0	0
T7	8409	0	0	0
T8	41520	0	0	0
T9	234974	98	0	0
T10	101438	558	0	0
T11	0	230	0	0
T12	44383	0	0	0
T16	2969	2	0	0
T17	0	433	0	0
T18	0	873	0	0
T23	0	367	0	0
T30	0	912	0	0
T31	1190	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457760384	6743048	0	0
DepthKnown_A	457760384	457629268	0	0
RvalidKnown_A	457760384	457629268	0	0
WreadyKnown_A	457760384	457629268	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	6743048	0	0
T1	92852	5286	0	0
T2	404322	68	0	0
T3	62661	2727	0	0
T4	300408	6042	0	0
T5	1200	12	0	0
T6	1774	1	0	0
T7	8409	1	0	0
T8	41520	744	0	0
T9	234974	375	0	0
T10	101438	3217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457760384	15135898	0	0
DepthKnown_A	457760384	457629268	0	0
RvalidKnown_A	457760384	457629268	0	0
WreadyKnown_A	457760384	457629268	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	15135898	0	0
T1	92852	5285	0	0
T2	404322	316	0	0
T3	62661	11867	0	0
T4	300408	5999	0	0
T5	1200	27	0	0
T6	1774	1	0	0
T7	8409	1	0	0
T8	41520	744	0	0
T9	234974	375	0	0
T10	101438	3187	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457760384	457629268	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0