Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T16
1	0	Covered	T4,T10,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T16
1	0	Unreachable
1	1	Covered	T4,T10,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T15
1	0	Covered	T9,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T9,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	719847020	586162198	0	0
CheckNGreaterZero_A	2775	2775	0	0
GntImpliesReady_A	719847020	3197081	0	0
GntImpliesValid_A	719847020	3197081	0	0
GrantKnown_A	719847020	586162198	0	0
IdxKnown_A	719847020	586162198	0	0
IndexIsCorrect_A	719847020	3197081	0	0
LockArbDecision_A	719847020	0	0	0
NoReadyValidNoGrant_A	719847020	0	0	0
ReadyAndValidImplyGrant_A	719847020	3197081	0	0
ReqAndReadyImplyGrant_A	719847020	3197081	0	0
ReqImpliesValid_A	719847020	3197081	0	0
ReqStaysHighUntilGranted0_M	719847020	0	0	0
RoundRobin_A	719847020	6	0	925
ValidKnown_A	719847020	586162198	0	0
gen_data_port_assertion.DataFlow_A	719847020	3197081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	586162198	0	0
T1	122717	122421	0	0
T2	535528	535335	0	0
T3	76941	76424	0	0
T4	449864	372687	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	66630	53926	0	0
T9	386542	310677	0	0
T10	290036	192870	0	0
T11	828820	823787	0	0
T12	136008	68004	0	0
T13	2610	2610	0	0
T14	0	48704	0	0
T16	3368	1360	0	0
T17	113512	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2775	2775	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	586162198	0	0
T1	122717	122421	0	0
T2	535528	535335	0	0
T3	76941	76424	0	0
T4	449864	372687	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	66630	53926	0	0
T9	386542	310677	0	0
T10	290036	192870	0	0
T11	828820	823787	0	0
T12	136008	68004	0	0
T13	2610	2610	0	0
T14	0	48704	0	0
T16	3368	1360	0	0
T17	113512	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	586162198	0	0
T1	122717	122421	0	0
T2	535528	535335	0	0
T3	76941	76424	0	0
T4	449864	372687	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	66630	53926	0	0
T9	386542	310677	0	0
T10	290036	192870	0	0
T11	828820	823787	0	0
T12	136008	68004	0	0
T13	2610	2610	0	0
T14	0	48704	0	0
T16	3368	1360	0	0
T17	113512	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	6	0	925
T25	0	1	0	0
T26	0	1	0	0
T32	248734	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	8324	0	0	1
T50	19734	0	0	1
T51	810	0	0	1
T52	382339	0	0	1
T53	2004	0	0	1
T54	3273	0	0	1
T55	15113	0	0	1
T56	406957	0	0	1
T57	1432	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	586162198	0	0
T1	122717	122421	0	0
T2	535528	535335	0	0
T3	76941	76424	0	0
T4	449864	372687	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	66630	53926	0	0
T9	386542	310677	0	0
T10	290036	192870	0	0
T11	828820	823787	0	0
T12	136008	68004	0	0
T13	2610	2610	0	0
T14	0	48704	0	0
T16	3368	1360	0	0
T17	113512	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719847020	3197081	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	375136	4703	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	54075	832	0	0
T9	386542	1334	0	0
T10	290036	4009	0	0
T11	1657640	1590	0	0
T12	136008	1088	0	0
T13	5220	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	3368	72	0	0
T17	113512	2325	0	0
T18	211036	4529	0	0
T19	1105	0	0	0
T28	0	401	0	0
T29	0	9381	0	0
T30	0	5598	0	0
T32	0	9951	0	0
T40	0	1551	0	0
T44	0	3544	0	0
T45	0	1890	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T16
1	0	Covered	T4,T10,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T16
1	0	Unreachable
1	1	Covered	T4,T10,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T10,T16
0	0	1	Unreachable
0	0	0	Covered	T4,T10,T16

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132336295	26923199	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	132336295	631069	0	0
GntImpliesValid_A	132336295	631069	0	0
GrantKnown_A	132336295	26923199	0	0
IdxKnown_A	132336295	26923199	0	0
IndexIsCorrect_A	132336295	631069	0	0
LockArbDecision_A	132336295	0	0	0
NoReadyValidNoGrant_A	132336295	0	0	0
ReadyAndValidImplyGrant_A	132336295	631069	0	0
ReqAndReadyImplyGrant_A	132336295	631069	0	0
ReqImpliesValid_A	132336295	631069	0	0
ReqStaysHighUntilGranted0_M	132336295	0	0	0
RoundRobin_A	132336295	0	0	0
ValidKnown_A	132336295	26923199	0	0
gen_data_port_assertion.DataFlow_A	132336295	631069	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	26923199	0	0
T4	74728	72336	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	91504	0	0
T11	828820	38304	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	1360	0	0
T17	56756	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	26923199	0	0
T4	74728	72336	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	91504	0	0
T11	828820	38304	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	1360	0	0
T17	56756	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	26923199	0	0
T4	74728	72336	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	91504	0	0
T11	828820	38304	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	1360	0	0
T17	56756	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	26923199	0	0
T4	74728	72336	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	91504	0	0
T11	828820	38304	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	1360	0	0
T17	56756	55288	0	0
T18	105518	99960	0	0
T19	0	792	0	0
T20	0	936	0	0
T22	0	720	0	0
T30	0	105080	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	631069	0	0
T4	74728	3184	0	0
T8	12555	0	0	0
T9	75784	0	0	0
T10	94299	2844	0	0
T11	828820	1273	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T16	1684	40	0	0
T17	56756	2325	0	0
T18	105518	4529	0	0
T28	0	401	0	0
T29	0	7375	0	0
T30	0	4822	0	0
T44	0	444	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T11,T15
1	0	Covered	T9,T11,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T9,T11,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T9,T11,T15
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132336295	104148868	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	132336295	565455	0	0
GntImpliesValid_A	132336295	565455	0	0
GrantKnown_A	132336295	104148868	0	0
IdxKnown_A	132336295	104148868	0	0
IndexIsCorrect_A	132336295	565455	0	0
LockArbDecision_A	132336295	0	0	0
NoReadyValidNoGrant_A	132336295	0	0	0
ReadyAndValidImplyGrant_A	132336295	565455	0	0
ReqAndReadyImplyGrant_A	132336295	565455	0	0
ReqImpliesValid_A	132336295	565455	0	0
ReqStaysHighUntilGranted0_M	132336295	0	0	0
RoundRobin_A	132336295	0	0	0
ValidKnown_A	132336295	104148868	0	0
gen_data_port_assertion.DataFlow_A	132336295	565455	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	104148868	0	0
T1	29865	29648	0	0
T2	131206	131090	0	0
T3	14280	13824	0	0
T4	74728	0	0	0
T8	12555	12482	0	0
T9	75784	75784	0	0
T10	94299	0	0	0
T11	0	785483	0	0
T12	68004	68004	0	0
T13	0	2610	0	0
T14	0	48704	0	0
T15	0	320381	0	0
T16	1684	0	0	0
T17	56756	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	104148868	0	0
T1	29865	29648	0	0
T2	131206	131090	0	0
T3	14280	13824	0	0
T4	74728	0	0	0
T8	12555	12482	0	0
T9	75784	75784	0	0
T10	94299	0	0	0
T11	0	785483	0	0
T12	68004	68004	0	0
T13	0	2610	0	0
T14	0	48704	0	0
T15	0	320381	0	0
T16	1684	0	0	0
T17	56756	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	104148868	0	0
T1	29865	29648	0	0
T2	131206	131090	0	0
T3	14280	13824	0	0
T4	74728	0	0	0
T8	12555	12482	0	0
T9	75784	75784	0	0
T10	94299	0	0	0
T11	0	785483	0	0
T12	68004	68004	0	0
T13	0	2610	0	0
T14	0	48704	0	0
T15	0	320381	0	0
T16	1684	0	0	0
T17	56756	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	104148868	0	0
T1	29865	29648	0	0
T2	131206	131090	0	0
T3	14280	13824	0	0
T4	74728	0	0	0
T8	12555	12482	0	0
T9	75784	75784	0	0
T10	94299	0	0	0
T11	0	785483	0	0
T12	68004	68004	0	0
T13	0	2610	0	0
T14	0	48704	0	0
T15	0	320381	0	0
T16	1684	0	0	0
T17	56756	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132336295	565455	0	0
T9	75784	400	0	0
T10	94299	0	0	0
T11	828820	317	0	0
T12	68004	0	0	0
T13	2610	0	0	0
T14	48704	0	0	0
T15	0	2	0	0
T16	1684	0	0	0
T17	56756	0	0	0
T18	105518	0	0	0
T19	1105	0	0	0
T29	0	2006	0	0
T30	0	776	0	0
T32	0	9951	0	0
T35	0	1760	0	0
T40	0	1551	0	0
T44	0	3100	0	0
T45	0	1890	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455174430	455090131	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	455174430	2000557	0	0
GntImpliesValid_A	455174430	2000557	0	0
GrantKnown_A	455174430	455090131	0	0
IdxKnown_A	455174430	455090131	0	0
IndexIsCorrect_A	455174430	2000557	0	0
LockArbDecision_A	455174430	0	0	0
NoReadyValidNoGrant_A	455174430	0	0	0
ReadyAndValidImplyGrant_A	455174430	2000557	0	0
ReqAndReadyImplyGrant_A	455174430	2000557	0	0
ReqImpliesValid_A	455174430	2000557	0	0
ReqStaysHighUntilGranted0_M	455174430	0	0	0
RoundRobin_A	455174430	6	0	925
ValidKnown_A	455174430	455090131	0	0
gen_data_port_assertion.DataFlow_A	455174430	2000557	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	455090131	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	455090131	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	455090131	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	6	0	925
T25	0	1	0	0
T26	0	1	0	0
T32	248734	1	0	1
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	8324	0	0	1
T50	19734	0	0	1
T51	810	0	0	1
T52	382339	0	0	1
T53	2004	0	0	1
T54	3273	0	0	1
T55	15113	0	0	1
T56	406957	0	0	1
T57	1432	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	455090131	0	0
T1	92852	92773	0	0
T2	404322	404245	0	0
T3	62661	62600	0	0
T4	300408	300351	0	0
T5	1200	1133	0	0
T6	1774	1675	0	0
T7	8409	6222	0	0
T8	41520	41444	0	0
T9	234974	234893	0	0
T10	101438	101366	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455174430	2000557	0	0
T1	92852	832	0	0
T2	404322	832	0	0
T3	62661	832	0	0
T4	300408	1519	0	0
T5	1200	0	0	0
T6	1774	200	0	0
T7	8409	0	0	0
T8	41520	832	0	0
T9	234974	934	0	0
T10	101438	1165	0	0
T12	0	1088	0	0
T16	0	32	0	0