Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
3909 |
0 |
0 |
T85 |
2022 |
4 |
0 |
0 |
T86 |
13626 |
7 |
0 |
0 |
T87 |
15111 |
196 |
0 |
0 |
T88 |
78781 |
4 |
0 |
0 |
T90 |
54393 |
4 |
0 |
0 |
T91 |
5707 |
9 |
0 |
0 |
T92 |
4631 |
3 |
0 |
0 |
T106 |
8149 |
4 |
0 |
0 |
T107 |
5275 |
2 |
0 |
0 |
T108 |
29110 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2138 |
0 |
0 |
T86 |
13626 |
23 |
0 |
0 |
T105 |
15100 |
8 |
0 |
0 |
T112 |
7048 |
1 |
0 |
0 |
T115 |
11206 |
12 |
0 |
0 |
T138 |
11712 |
9 |
0 |
0 |
T142 |
7020 |
25 |
0 |
0 |
T143 |
6597 |
4 |
0 |
0 |
T144 |
12578 |
59 |
0 |
0 |
T145 |
6876 |
9 |
0 |
0 |
T146 |
9015 |
5 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
1990 |
0 |
0 |
T86 |
13626 |
31 |
0 |
0 |
T105 |
15100 |
12 |
0 |
0 |
T112 |
7048 |
9 |
0 |
0 |
T115 |
11206 |
17 |
0 |
0 |
T138 |
11712 |
11 |
0 |
0 |
T142 |
7020 |
34 |
0 |
0 |
T143 |
6597 |
10 |
0 |
0 |
T144 |
12578 |
9 |
0 |
0 |
T145 |
6876 |
31 |
0 |
0 |
T146 |
9015 |
9 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2785 |
0 |
0 |
T86 |
13626 |
39 |
0 |
0 |
T105 |
15100 |
40 |
0 |
0 |
T112 |
7048 |
3 |
0 |
0 |
T115 |
11206 |
13 |
0 |
0 |
T138 |
11712 |
18 |
0 |
0 |
T142 |
7020 |
14 |
0 |
0 |
T143 |
6597 |
5 |
0 |
0 |
T144 |
12578 |
65 |
0 |
0 |
T145 |
6876 |
25 |
0 |
0 |
T146 |
9015 |
3 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
12659 |
0 |
0 |
T86 |
13626 |
260 |
0 |
0 |
T105 |
15100 |
237 |
0 |
0 |
T112 |
7048 |
37 |
0 |
0 |
T115 |
11206 |
288 |
0 |
0 |
T138 |
11712 |
402 |
0 |
0 |
T142 |
7020 |
15 |
0 |
0 |
T143 |
6597 |
16 |
0 |
0 |
T144 |
12578 |
24 |
0 |
0 |
T146 |
9015 |
7 |
0 |
0 |
T147 |
68559 |
1822 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
11477 |
0 |
0 |
T86 |
13626 |
135 |
0 |
0 |
T105 |
15100 |
148 |
0 |
0 |
T112 |
7048 |
75 |
0 |
0 |
T115 |
11206 |
453 |
0 |
0 |
T138 |
11712 |
315 |
0 |
0 |
T142 |
7020 |
11 |
0 |
0 |
T143 |
6597 |
1 |
0 |
0 |
T144 |
12578 |
20 |
0 |
0 |
T145 |
6876 |
9 |
0 |
0 |
T146 |
9015 |
13 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
11407 |
0 |
0 |
T86 |
13626 |
128 |
0 |
0 |
T105 |
15100 |
15 |
0 |
0 |
T112 |
7048 |
168 |
0 |
0 |
T115 |
11206 |
135 |
0 |
0 |
T138 |
11712 |
289 |
0 |
0 |
T142 |
7020 |
20 |
0 |
0 |
T144 |
12578 |
40 |
0 |
0 |
T145 |
6876 |
11 |
0 |
0 |
T146 |
9015 |
74 |
0 |
0 |
T147 |
68559 |
1040 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
11354 |
0 |
0 |
T86 |
13626 |
228 |
0 |
0 |
T105 |
15100 |
133 |
0 |
0 |
T112 |
7048 |
65 |
0 |
0 |
T115 |
11206 |
285 |
0 |
0 |
T138 |
11712 |
186 |
0 |
0 |
T142 |
7020 |
10 |
0 |
0 |
T143 |
6597 |
30 |
0 |
0 |
T144 |
12578 |
108 |
0 |
0 |
T145 |
6876 |
4 |
0 |
0 |
T146 |
9015 |
121 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
11103 |
0 |
0 |
T86 |
13626 |
90 |
0 |
0 |
T105 |
15100 |
136 |
0 |
0 |
T115 |
11206 |
268 |
0 |
0 |
T138 |
11712 |
143 |
0 |
0 |
T142 |
7020 |
6 |
0 |
0 |
T143 |
6597 |
4 |
0 |
0 |
T144 |
12578 |
34 |
0 |
0 |
T145 |
6876 |
13 |
0 |
0 |
T146 |
9015 |
6 |
0 |
0 |
T147 |
68559 |
1204 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
11976 |
0 |
0 |
T86 |
13626 |
157 |
0 |
0 |
T105 |
15100 |
214 |
0 |
0 |
T112 |
7048 |
70 |
0 |
0 |
T115 |
11206 |
134 |
0 |
0 |
T138 |
11712 |
240 |
0 |
0 |
T142 |
7020 |
14 |
0 |
0 |
T143 |
6597 |
18 |
0 |
0 |
T144 |
12578 |
21 |
0 |
0 |
T145 |
6876 |
11 |
0 |
0 |
T146 |
9015 |
73 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
10885 |
0 |
0 |
T86 |
13626 |
29 |
0 |
0 |
T105 |
15100 |
255 |
0 |
0 |
T112 |
7048 |
117 |
0 |
0 |
T115 |
11206 |
147 |
0 |
0 |
T138 |
11712 |
6 |
0 |
0 |
T142 |
7020 |
39 |
0 |
0 |
T143 |
6597 |
5 |
0 |
0 |
T144 |
12578 |
48 |
0 |
0 |
T145 |
6876 |
19 |
0 |
0 |
T146 |
9015 |
60 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
12350 |
0 |
0 |
T86 |
13626 |
128 |
0 |
0 |
T105 |
15100 |
116 |
0 |
0 |
T115 |
11206 |
141 |
0 |
0 |
T138 |
11712 |
264 |
0 |
0 |
T142 |
7020 |
37 |
0 |
0 |
T143 |
6597 |
8 |
0 |
0 |
T144 |
12578 |
38 |
0 |
0 |
T145 |
6876 |
5 |
0 |
0 |
T146 |
9015 |
47 |
0 |
0 |
T147 |
68559 |
915 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6206 |
0 |
0 |
T86 |
13626 |
144 |
0 |
0 |
T105 |
15100 |
47 |
0 |
0 |
T112 |
7048 |
17 |
0 |
0 |
T115 |
11206 |
124 |
0 |
0 |
T138 |
11712 |
68 |
0 |
0 |
T142 |
7020 |
38 |
0 |
0 |
T143 |
6597 |
23 |
0 |
0 |
T144 |
12578 |
65 |
0 |
0 |
T145 |
6876 |
16 |
0 |
0 |
T146 |
9015 |
25 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5611 |
0 |
0 |
T86 |
13626 |
20 |
0 |
0 |
T105 |
15100 |
102 |
0 |
0 |
T112 |
7048 |
72 |
0 |
0 |
T115 |
11206 |
14 |
0 |
0 |
T138 |
11712 |
100 |
0 |
0 |
T142 |
7020 |
43 |
0 |
0 |
T143 |
6597 |
5 |
0 |
0 |
T144 |
12578 |
32 |
0 |
0 |
T145 |
6876 |
1 |
0 |
0 |
T146 |
9015 |
85 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6186 |
0 |
0 |
T86 |
13626 |
71 |
0 |
0 |
T105 |
15100 |
150 |
0 |
0 |
T112 |
7048 |
16 |
0 |
0 |
T115 |
11206 |
135 |
0 |
0 |
T138 |
11712 |
142 |
0 |
0 |
T142 |
7020 |
17 |
0 |
0 |
T144 |
12578 |
30 |
0 |
0 |
T145 |
6876 |
7 |
0 |
0 |
T146 |
9015 |
22 |
0 |
0 |
T147 |
68559 |
564 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5633 |
0 |
0 |
T86 |
13626 |
59 |
0 |
0 |
T87 |
15111 |
1 |
0 |
0 |
T105 |
15100 |
65 |
0 |
0 |
T112 |
7048 |
9 |
0 |
0 |
T115 |
11206 |
8 |
0 |
0 |
T138 |
11712 |
139 |
0 |
0 |
T142 |
7020 |
20 |
0 |
0 |
T143 |
6597 |
24 |
0 |
0 |
T144 |
12578 |
12 |
0 |
0 |
T145 |
6876 |
8 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6017 |
0 |
0 |
T86 |
13626 |
73 |
0 |
0 |
T87 |
15111 |
1 |
0 |
0 |
T105 |
15100 |
106 |
0 |
0 |
T112 |
7048 |
24 |
0 |
0 |
T115 |
11206 |
102 |
0 |
0 |
T138 |
11712 |
116 |
0 |
0 |
T142 |
7020 |
34 |
0 |
0 |
T143 |
6597 |
7 |
0 |
0 |
T144 |
12578 |
60 |
0 |
0 |
T145 |
6876 |
4 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6285 |
0 |
0 |
T86 |
13626 |
121 |
0 |
0 |
T105 |
15100 |
158 |
0 |
0 |
T112 |
7048 |
5 |
0 |
0 |
T115 |
11206 |
158 |
0 |
0 |
T138 |
11712 |
91 |
0 |
0 |
T142 |
7020 |
9 |
0 |
0 |
T143 |
6597 |
14 |
0 |
0 |
T144 |
12578 |
19 |
0 |
0 |
T145 |
6876 |
1 |
0 |
0 |
T146 |
9015 |
39 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5734 |
0 |
0 |
T86 |
13626 |
116 |
0 |
0 |
T105 |
15100 |
103 |
0 |
0 |
T112 |
7048 |
57 |
0 |
0 |
T115 |
11206 |
118 |
0 |
0 |
T138 |
11712 |
77 |
0 |
0 |
T142 |
7020 |
26 |
0 |
0 |
T143 |
6597 |
2 |
0 |
0 |
T144 |
12578 |
30 |
0 |
0 |
T145 |
6876 |
18 |
0 |
0 |
T146 |
9015 |
14 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5847 |
0 |
0 |
T86 |
13626 |
61 |
0 |
0 |
T105 |
15100 |
73 |
0 |
0 |
T112 |
7048 |
23 |
0 |
0 |
T115 |
11206 |
61 |
0 |
0 |
T138 |
11712 |
126 |
0 |
0 |
T142 |
7020 |
10 |
0 |
0 |
T143 |
6597 |
28 |
0 |
0 |
T144 |
12578 |
29 |
0 |
0 |
T145 |
6876 |
16 |
0 |
0 |
T146 |
9015 |
16 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6149 |
0 |
0 |
T86 |
13626 |
73 |
0 |
0 |
T105 |
15100 |
61 |
0 |
0 |
T112 |
7048 |
37 |
0 |
0 |
T115 |
11206 |
9 |
0 |
0 |
T138 |
11712 |
105 |
0 |
0 |
T142 |
7020 |
30 |
0 |
0 |
T143 |
6597 |
5 |
0 |
0 |
T144 |
12578 |
90 |
0 |
0 |
T145 |
6876 |
22 |
0 |
0 |
T146 |
9015 |
47 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6026 |
0 |
0 |
T86 |
13626 |
82 |
0 |
0 |
T105 |
15100 |
25 |
0 |
0 |
T112 |
7048 |
12 |
0 |
0 |
T115 |
11206 |
110 |
0 |
0 |
T138 |
11712 |
171 |
0 |
0 |
T142 |
7020 |
2 |
0 |
0 |
T143 |
6597 |
15 |
0 |
0 |
T144 |
12578 |
4 |
0 |
0 |
T145 |
6876 |
16 |
0 |
0 |
T146 |
9015 |
33 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5273 |
0 |
0 |
T86 |
13626 |
81 |
0 |
0 |
T105 |
15100 |
79 |
0 |
0 |
T112 |
7048 |
35 |
0 |
0 |
T115 |
11206 |
62 |
0 |
0 |
T138 |
11712 |
63 |
0 |
0 |
T142 |
7020 |
45 |
0 |
0 |
T143 |
6597 |
1 |
0 |
0 |
T144 |
12578 |
14 |
0 |
0 |
T145 |
6876 |
10 |
0 |
0 |
T146 |
9015 |
6 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5877 |
0 |
0 |
T86 |
13626 |
66 |
0 |
0 |
T87 |
15111 |
4 |
0 |
0 |
T105 |
15100 |
115 |
0 |
0 |
T112 |
7048 |
20 |
0 |
0 |
T115 |
11206 |
12 |
0 |
0 |
T138 |
11712 |
8 |
0 |
0 |
T142 |
7020 |
6 |
0 |
0 |
T143 |
6597 |
32 |
0 |
0 |
T144 |
12578 |
24 |
0 |
0 |
T146 |
9015 |
60 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5933 |
0 |
0 |
T86 |
13626 |
12 |
0 |
0 |
T97 |
12296 |
1 |
0 |
0 |
T105 |
15100 |
62 |
0 |
0 |
T115 |
11206 |
46 |
0 |
0 |
T138 |
11712 |
83 |
0 |
0 |
T142 |
7020 |
35 |
0 |
0 |
T144 |
12578 |
79 |
0 |
0 |
T145 |
6876 |
9 |
0 |
0 |
T146 |
9015 |
32 |
0 |
0 |
T147 |
68559 |
489 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6372 |
0 |
0 |
T86 |
13626 |
89 |
0 |
0 |
T105 |
15100 |
96 |
0 |
0 |
T112 |
7048 |
20 |
0 |
0 |
T115 |
11206 |
153 |
0 |
0 |
T138 |
11712 |
153 |
0 |
0 |
T142 |
7020 |
13 |
0 |
0 |
T143 |
6597 |
22 |
0 |
0 |
T144 |
12578 |
3 |
0 |
0 |
T146 |
9015 |
11 |
0 |
0 |
T147 |
68559 |
630 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6129 |
0 |
0 |
T86 |
13626 |
114 |
0 |
0 |
T105 |
15100 |
78 |
0 |
0 |
T112 |
7048 |
36 |
0 |
0 |
T115 |
11206 |
135 |
0 |
0 |
T138 |
11712 |
79 |
0 |
0 |
T142 |
7020 |
16 |
0 |
0 |
T143 |
6597 |
10 |
0 |
0 |
T144 |
12578 |
41 |
0 |
0 |
T145 |
6876 |
13 |
0 |
0 |
T146 |
9015 |
25 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6216 |
0 |
0 |
T86 |
13626 |
112 |
0 |
0 |
T87 |
15111 |
7 |
0 |
0 |
T105 |
15100 |
156 |
0 |
0 |
T112 |
7048 |
33 |
0 |
0 |
T115 |
11206 |
164 |
0 |
0 |
T138 |
11712 |
84 |
0 |
0 |
T142 |
7020 |
38 |
0 |
0 |
T143 |
6597 |
12 |
0 |
0 |
T144 |
12578 |
10 |
0 |
0 |
T145 |
6876 |
4 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6286 |
0 |
0 |
T86 |
13626 |
129 |
0 |
0 |
T105 |
15100 |
115 |
0 |
0 |
T112 |
7048 |
21 |
0 |
0 |
T115 |
11206 |
51 |
0 |
0 |
T138 |
11712 |
142 |
0 |
0 |
T142 |
7020 |
65 |
0 |
0 |
T143 |
6597 |
16 |
0 |
0 |
T144 |
12578 |
45 |
0 |
0 |
T145 |
6876 |
9 |
0 |
0 |
T146 |
9015 |
36 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5998 |
0 |
0 |
T86 |
13626 |
90 |
0 |
0 |
T105 |
15100 |
71 |
0 |
0 |
T112 |
7048 |
19 |
0 |
0 |
T115 |
11206 |
75 |
0 |
0 |
T138 |
11712 |
102 |
0 |
0 |
T142 |
7020 |
17 |
0 |
0 |
T144 |
12578 |
27 |
0 |
0 |
T145 |
6876 |
15 |
0 |
0 |
T146 |
9015 |
40 |
0 |
0 |
T147 |
68559 |
393 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5615 |
0 |
0 |
T86 |
13626 |
79 |
0 |
0 |
T105 |
15100 |
76 |
0 |
0 |
T112 |
7048 |
63 |
0 |
0 |
T115 |
11206 |
52 |
0 |
0 |
T138 |
11712 |
109 |
0 |
0 |
T143 |
6597 |
4 |
0 |
0 |
T144 |
12578 |
18 |
0 |
0 |
T145 |
6876 |
15 |
0 |
0 |
T146 |
9015 |
39 |
0 |
0 |
T147 |
68559 |
532 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5683 |
0 |
0 |
T86 |
13626 |
175 |
0 |
0 |
T105 |
15100 |
115 |
0 |
0 |
T112 |
7048 |
1 |
0 |
0 |
T115 |
11206 |
162 |
0 |
0 |
T138 |
11712 |
53 |
0 |
0 |
T142 |
7020 |
48 |
0 |
0 |
T143 |
6597 |
15 |
0 |
0 |
T144 |
12578 |
73 |
0 |
0 |
T145 |
6876 |
16 |
0 |
0 |
T146 |
9015 |
42 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5824 |
0 |
0 |
T86 |
13626 |
15 |
0 |
0 |
T105 |
15100 |
113 |
0 |
0 |
T112 |
7048 |
24 |
0 |
0 |
T115 |
11206 |
8 |
0 |
0 |
T138 |
11712 |
41 |
0 |
0 |
T142 |
7020 |
15 |
0 |
0 |
T144 |
12578 |
14 |
0 |
0 |
T145 |
6876 |
13 |
0 |
0 |
T146 |
9015 |
40 |
0 |
0 |
T147 |
68559 |
465 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6174 |
0 |
0 |
T86 |
13626 |
80 |
0 |
0 |
T105 |
15100 |
69 |
0 |
0 |
T112 |
7048 |
18 |
0 |
0 |
T115 |
11206 |
55 |
0 |
0 |
T138 |
11712 |
139 |
0 |
0 |
T142 |
7020 |
49 |
0 |
0 |
T143 |
6597 |
22 |
0 |
0 |
T144 |
12578 |
18 |
0 |
0 |
T145 |
6876 |
8 |
0 |
0 |
T146 |
9015 |
27 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
6470 |
0 |
0 |
T86 |
13626 |
122 |
0 |
0 |
T105 |
15100 |
88 |
0 |
0 |
T112 |
7048 |
37 |
0 |
0 |
T115 |
11206 |
168 |
0 |
0 |
T138 |
11712 |
73 |
0 |
0 |
T142 |
7020 |
15 |
0 |
0 |
T144 |
12578 |
34 |
0 |
0 |
T145 |
6876 |
4 |
0 |
0 |
T146 |
9015 |
30 |
0 |
0 |
T147 |
68559 |
446 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5896 |
0 |
0 |
T86 |
13626 |
55 |
0 |
0 |
T105 |
15100 |
88 |
0 |
0 |
T112 |
7048 |
24 |
0 |
0 |
T115 |
11206 |
98 |
0 |
0 |
T138 |
11712 |
147 |
0 |
0 |
T142 |
7020 |
12 |
0 |
0 |
T143 |
6597 |
1 |
0 |
0 |
T144 |
12578 |
33 |
0 |
0 |
T145 |
6876 |
18 |
0 |
0 |
T146 |
9015 |
7 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2606 |
0 |
0 |
T86 |
13626 |
25 |
0 |
0 |
T87 |
15111 |
3 |
0 |
0 |
T105 |
15100 |
35 |
0 |
0 |
T112 |
7048 |
27 |
0 |
0 |
T115 |
11206 |
19 |
0 |
0 |
T138 |
11712 |
13 |
0 |
0 |
T142 |
7020 |
18 |
0 |
0 |
T143 |
6597 |
24 |
0 |
0 |
T144 |
12578 |
33 |
0 |
0 |
T145 |
6876 |
24 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2480 |
0 |
0 |
T86 |
13626 |
21 |
0 |
0 |
T87 |
15111 |
4 |
0 |
0 |
T105 |
15100 |
23 |
0 |
0 |
T112 |
7048 |
2 |
0 |
0 |
T115 |
11206 |
22 |
0 |
0 |
T138 |
11712 |
22 |
0 |
0 |
T142 |
7020 |
9 |
0 |
0 |
T143 |
6597 |
6 |
0 |
0 |
T144 |
12578 |
17 |
0 |
0 |
T146 |
9015 |
28 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2374 |
0 |
0 |
T86 |
13626 |
27 |
0 |
0 |
T97 |
12296 |
1 |
0 |
0 |
T105 |
15100 |
17 |
0 |
0 |
T115 |
11206 |
25 |
0 |
0 |
T138 |
11712 |
29 |
0 |
0 |
T142 |
7020 |
15 |
0 |
0 |
T143 |
6597 |
9 |
0 |
0 |
T144 |
12578 |
27 |
0 |
0 |
T145 |
6876 |
1 |
0 |
0 |
T146 |
9015 |
9 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2399 |
0 |
0 |
T86 |
13626 |
19 |
0 |
0 |
T105 |
15100 |
34 |
0 |
0 |
T112 |
7048 |
14 |
0 |
0 |
T115 |
11206 |
10 |
0 |
0 |
T138 |
11712 |
16 |
0 |
0 |
T143 |
6597 |
6 |
0 |
0 |
T144 |
12578 |
36 |
0 |
0 |
T145 |
6876 |
10 |
0 |
0 |
T146 |
9015 |
6 |
0 |
0 |
T147 |
68559 |
118 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
3044 |
0 |
0 |
T86 |
13626 |
39 |
0 |
0 |
T105 |
15100 |
25 |
0 |
0 |
T112 |
7048 |
11 |
0 |
0 |
T115 |
11206 |
27 |
0 |
0 |
T138 |
11712 |
10 |
0 |
0 |
T142 |
7020 |
34 |
0 |
0 |
T143 |
6597 |
16 |
0 |
0 |
T144 |
12578 |
20 |
0 |
0 |
T145 |
6876 |
17 |
0 |
0 |
T146 |
9015 |
21 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
5056 |
0 |
0 |
T33 |
0 |
16 |
0 |
0 |
T37 |
310333 |
42 |
0 |
0 |
T83 |
70625 |
0 |
0 |
0 |
T132 |
0 |
16 |
0 |
0 |
T148 |
0 |
15 |
0 |
0 |
T149 |
0 |
72 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T151 |
0 |
37 |
0 |
0 |
T152 |
0 |
50 |
0 |
0 |
T153 |
0 |
14 |
0 |
0 |
T154 |
0 |
37 |
0 |
0 |
T155 |
2326 |
0 |
0 |
0 |
T156 |
2096 |
0 |
0 |
0 |
T157 |
17374 |
0 |
0 |
0 |
T158 |
1657 |
0 |
0 |
0 |
T159 |
32940 |
0 |
0 |
0 |
T160 |
8833 |
0 |
0 |
0 |
T161 |
242582 |
0 |
0 |
0 |
T162 |
53478 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2417 |
0 |
0 |
T86 |
13626 |
9 |
0 |
0 |
T105 |
15100 |
26 |
0 |
0 |
T112 |
7048 |
1 |
0 |
0 |
T115 |
11206 |
20 |
0 |
0 |
T138 |
11712 |
23 |
0 |
0 |
T142 |
7020 |
49 |
0 |
0 |
T143 |
6597 |
7 |
0 |
0 |
T144 |
12578 |
48 |
0 |
0 |
T145 |
6876 |
23 |
0 |
0 |
T146 |
9015 |
8 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2538 |
0 |
0 |
T86 |
13626 |
23 |
0 |
0 |
T105 |
15100 |
24 |
0 |
0 |
T112 |
7048 |
5 |
0 |
0 |
T115 |
11206 |
9 |
0 |
0 |
T138 |
11712 |
16 |
0 |
0 |
T142 |
7020 |
29 |
0 |
0 |
T143 |
6597 |
19 |
0 |
0 |
T144 |
12578 |
23 |
0 |
0 |
T145 |
6876 |
26 |
0 |
0 |
T146 |
9015 |
12 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2123 |
0 |
0 |
T86 |
13626 |
28 |
0 |
0 |
T105 |
15100 |
22 |
0 |
0 |
T112 |
7048 |
13 |
0 |
0 |
T115 |
11206 |
14 |
0 |
0 |
T138 |
11712 |
9 |
0 |
0 |
T142 |
7020 |
6 |
0 |
0 |
T143 |
6597 |
16 |
0 |
0 |
T144 |
12578 |
29 |
0 |
0 |
T145 |
6876 |
9 |
0 |
0 |
T146 |
9015 |
12 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2109 |
0 |
0 |
T86 |
13626 |
17 |
0 |
0 |
T105 |
15100 |
25 |
0 |
0 |
T112 |
7048 |
9 |
0 |
0 |
T115 |
11206 |
9 |
0 |
0 |
T138 |
11712 |
17 |
0 |
0 |
T143 |
6597 |
15 |
0 |
0 |
T144 |
12578 |
15 |
0 |
0 |
T145 |
6876 |
10 |
0 |
0 |
T146 |
9015 |
9 |
0 |
0 |
T147 |
68559 |
62 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2060 |
0 |
0 |
T86 |
13626 |
25 |
0 |
0 |
T105 |
15100 |
23 |
0 |
0 |
T112 |
7048 |
3 |
0 |
0 |
T115 |
11206 |
15 |
0 |
0 |
T138 |
11712 |
11 |
0 |
0 |
T142 |
7020 |
2 |
0 |
0 |
T143 |
6597 |
6 |
0 |
0 |
T144 |
12578 |
84 |
0 |
0 |
T145 |
6876 |
6 |
0 |
0 |
T146 |
9015 |
2 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2006 |
0 |
0 |
T86 |
13626 |
26 |
0 |
0 |
T105 |
15100 |
34 |
0 |
0 |
T112 |
7048 |
2 |
0 |
0 |
T115 |
11206 |
7 |
0 |
0 |
T138 |
11712 |
13 |
0 |
0 |
T142 |
7020 |
16 |
0 |
0 |
T143 |
6597 |
11 |
0 |
0 |
T144 |
12578 |
36 |
0 |
0 |
T145 |
6876 |
16 |
0 |
0 |
T146 |
9015 |
4 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2982 |
0 |
0 |
T86 |
13626 |
48 |
0 |
0 |
T105 |
15100 |
39 |
0 |
0 |
T112 |
7048 |
5 |
0 |
0 |
T115 |
11206 |
44 |
0 |
0 |
T138 |
11712 |
59 |
0 |
0 |
T142 |
7020 |
42 |
0 |
0 |
T143 |
6597 |
20 |
0 |
0 |
T144 |
12578 |
28 |
0 |
0 |
T145 |
6876 |
7 |
0 |
0 |
T146 |
9015 |
8 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2217 |
0 |
0 |
T86 |
13626 |
29 |
0 |
0 |
T105 |
15100 |
30 |
0 |
0 |
T112 |
7048 |
5 |
0 |
0 |
T115 |
11206 |
14 |
0 |
0 |
T138 |
11712 |
19 |
0 |
0 |
T142 |
7020 |
23 |
0 |
0 |
T143 |
6597 |
13 |
0 |
0 |
T144 |
12578 |
45 |
0 |
0 |
T145 |
6876 |
39 |
0 |
0 |
T147 |
68559 |
64 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
3620 |
0 |
0 |
T86 |
13626 |
39 |
0 |
0 |
T105 |
15100 |
41 |
0 |
0 |
T112 |
7048 |
9 |
0 |
0 |
T115 |
11206 |
11 |
0 |
0 |
T138 |
11712 |
15 |
0 |
0 |
T142 |
7020 |
29 |
0 |
0 |
T143 |
6597 |
4 |
0 |
0 |
T144 |
12578 |
57 |
0 |
0 |
T145 |
6876 |
7 |
0 |
0 |
T146 |
9015 |
15 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2398 |
0 |
0 |
T86 |
13626 |
26 |
0 |
0 |
T105 |
15100 |
27 |
0 |
0 |
T112 |
7048 |
6 |
0 |
0 |
T115 |
11206 |
23 |
0 |
0 |
T138 |
11712 |
17 |
0 |
0 |
T142 |
7020 |
23 |
0 |
0 |
T143 |
6597 |
14 |
0 |
0 |
T144 |
12578 |
37 |
0 |
0 |
T145 |
6876 |
23 |
0 |
0 |
T146 |
9015 |
5 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2120 |
0 |
0 |
T86 |
13626 |
31 |
0 |
0 |
T105 |
15100 |
12 |
0 |
0 |
T112 |
7048 |
7 |
0 |
0 |
T115 |
11206 |
12 |
0 |
0 |
T138 |
11712 |
16 |
0 |
0 |
T142 |
7020 |
14 |
0 |
0 |
T143 |
6597 |
5 |
0 |
0 |
T144 |
12578 |
18 |
0 |
0 |
T145 |
6876 |
31 |
0 |
0 |
T146 |
9015 |
11 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2124 |
0 |
0 |
T86 |
13626 |
33 |
0 |
0 |
T97 |
12296 |
1 |
0 |
0 |
T105 |
15100 |
35 |
0 |
0 |
T112 |
7048 |
1 |
0 |
0 |
T115 |
11206 |
8 |
0 |
0 |
T138 |
11712 |
15 |
0 |
0 |
T142 |
7020 |
5 |
0 |
0 |
T143 |
6597 |
23 |
0 |
0 |
T144 |
12578 |
29 |
0 |
0 |
T145 |
6876 |
21 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2165 |
0 |
0 |
T86 |
13626 |
33 |
0 |
0 |
T105 |
15100 |
18 |
0 |
0 |
T115 |
11206 |
9 |
0 |
0 |
T138 |
11712 |
14 |
0 |
0 |
T142 |
7020 |
8 |
0 |
0 |
T143 |
6597 |
35 |
0 |
0 |
T144 |
12578 |
33 |
0 |
0 |
T145 |
6876 |
16 |
0 |
0 |
T146 |
9015 |
17 |
0 |
0 |
T147 |
68559 |
69 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2098 |
0 |
0 |
T86 |
13626 |
19 |
0 |
0 |
T105 |
15100 |
31 |
0 |
0 |
T112 |
7048 |
8 |
0 |
0 |
T115 |
11206 |
8 |
0 |
0 |
T138 |
11712 |
5 |
0 |
0 |
T142 |
7020 |
5 |
0 |
0 |
T143 |
6597 |
8 |
0 |
0 |
T144 |
12578 |
42 |
0 |
0 |
T145 |
6876 |
13 |
0 |
0 |
T146 |
9015 |
9 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2118 |
0 |
0 |
T86 |
13626 |
15 |
0 |
0 |
T105 |
15100 |
23 |
0 |
0 |
T115 |
11206 |
13 |
0 |
0 |
T138 |
11712 |
6 |
0 |
0 |
T142 |
7020 |
40 |
0 |
0 |
T143 |
6597 |
18 |
0 |
0 |
T144 |
12578 |
28 |
0 |
0 |
T145 |
6876 |
3 |
0 |
0 |
T146 |
9015 |
3 |
0 |
0 |
T147 |
68559 |
76 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
457760384 |
2040 |
0 |
0 |
T86 |
13626 |
25 |
0 |
0 |
T105 |
15100 |
14 |
0 |
0 |
T112 |
7048 |
6 |
0 |
0 |
T115 |
11206 |
13 |
0 |
0 |
T138 |
11712 |
10 |
0 |
0 |
T142 |
7020 |
9 |
0 |
0 |
T143 |
6597 |
9 |
0 |
0 |
T144 |
12578 |
23 |
0 |
0 |
T146 |
9015 |
18 |
0 |
0 |
T147 |
68559 |
39 |
0 |
0 |