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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.92 98.34 94.20 98.61 89.36 97.12 95.81 98.02


Total test records in report: 1100
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T117 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2305506715 May 23 01:19:47 PM PDT 24 May 23 01:20:22 PM PDT 24 4387926629 ps
T118 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1535618686 May 23 01:19:40 PM PDT 24 May 23 01:19:44 PM PDT 24 65657554 ps
T1018 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1837813520 May 23 01:19:52 PM PDT 24 May 23 01:20:00 PM PDT 24 43633250 ps
T1019 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1853330399 May 23 01:19:26 PM PDT 24 May 23 01:19:31 PM PDT 24 262162536 ps
T1020 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.120277078 May 23 01:19:57 PM PDT 24 May 23 01:20:00 PM PDT 24 14453712 ps
T119 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1674143897 May 23 01:19:38 PM PDT 24 May 23 01:19:42 PM PDT 24 22990026 ps
T1021 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2779656435 May 23 01:19:30 PM PDT 24 May 23 01:19:37 PM PDT 24 167305991 ps
T1022 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.161730789 May 23 01:19:34 PM PDT 24 May 23 01:19:37 PM PDT 24 46517655 ps
T1023 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3533257429 May 23 01:19:32 PM PDT 24 May 23 01:19:37 PM PDT 24 96075377 ps
T267 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3874732603 May 23 01:19:48 PM PDT 24 May 23 01:20:11 PM PDT 24 831649546 ps
T98 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3740889795 May 23 01:19:25 PM PDT 24 May 23 01:19:28 PM PDT 24 243339247 ps
T1024 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1636467172 May 23 01:19:26 PM PDT 24 May 23 01:19:34 PM PDT 24 570920186 ps
T103 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1843417798 May 23 01:19:30 PM PDT 24 May 23 01:19:36 PM PDT 24 174019835 ps
T1025 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1874853429 May 23 01:19:29 PM PDT 24 May 23 01:19:31 PM PDT 24 16959786 ps
T1026 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3068593612 May 23 01:19:36 PM PDT 24 May 23 01:19:40 PM PDT 24 17870827 ps
T1027 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.407185703 May 23 01:19:38 PM PDT 24 May 23 01:19:42 PM PDT 24 15401074 ps
T1028 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4044405587 May 23 01:19:29 PM PDT 24 May 23 01:19:34 PM PDT 24 70521405 ps
T1029 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1982211920 May 23 01:19:45 PM PDT 24 May 23 01:19:50 PM PDT 24 385424763 ps
T1030 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2585220410 May 23 01:19:38 PM PDT 24 May 23 01:19:45 PM PDT 24 180315628 ps
T1031 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.676110 May 23 01:19:47 PM PDT 24 May 23 01:19:49 PM PDT 24 16663818 ps
T1032 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2106253053 May 23 01:19:57 PM PDT 24 May 23 01:20:00 PM PDT 24 15748916 ps
T268 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4208144766 May 23 01:19:31 PM PDT 24 May 23 01:19:56 PM PDT 24 1023274139 ps
T1033 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3920285211 May 23 01:19:37 PM PDT 24 May 23 01:19:42 PM PDT 24 116554609 ps
T120 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3683375152 May 23 01:19:29 PM PDT 24 May 23 01:19:32 PM PDT 24 29807008 ps
T1034 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.832506567 May 23 01:19:43 PM PDT 24 May 23 01:19:46 PM PDT 24 60927556 ps
T73 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4034660924 May 23 01:19:33 PM PDT 24 May 23 01:19:36 PM PDT 24 22851160 ps
T1035 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2560308548 May 23 01:19:47 PM PDT 24 May 23 01:19:50 PM PDT 24 127763767 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1255626056 May 23 01:19:28 PM PDT 24 May 23 01:19:45 PM PDT 24 3554632393 ps
T1037 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.41046590 May 23 01:19:55 PM PDT 24 May 23 01:19:58 PM PDT 24 67502104 ps
T1038 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1035164631 May 23 01:19:41 PM PDT 24 May 23 01:19:47 PM PDT 24 224756892 ps
T1039 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.912420258 May 23 01:19:51 PM PDT 24 May 23 01:20:07 PM PDT 24 579192234 ps
T1040 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.833794659 May 23 01:19:33 PM PDT 24 May 23 01:19:37 PM PDT 24 39207644 ps
T1041 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2002238592 May 23 01:19:25 PM PDT 24 May 23 01:19:30 PM PDT 24 682818540 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2301204637 May 23 01:19:34 PM PDT 24 May 23 01:20:15 PM PDT 24 2853146915 ps
T263 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.386494671 May 23 01:19:34 PM PDT 24 May 23 01:19:52 PM PDT 24 1363674235 ps
T1042 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.332115095 May 23 01:19:44 PM PDT 24 May 23 01:19:50 PM PDT 24 121738999 ps
T264 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2309073552 May 23 01:19:38 PM PDT 24 May 23 01:19:56 PM PDT 24 677088667 ps
T1043 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3993779629 May 23 01:20:00 PM PDT 24 May 23 01:20:04 PM PDT 24 15756441 ps
T1044 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3289320313 May 23 01:19:45 PM PDT 24 May 23 01:19:47 PM PDT 24 11359979 ps
T1045 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2145211372 May 23 01:19:50 PM PDT 24 May 23 01:19:52 PM PDT 24 77095933 ps
T1046 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1997074265 May 23 01:19:39 PM PDT 24 May 23 01:19:43 PM PDT 24 334579579 ps
T1047 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.538857835 May 23 01:20:05 PM PDT 24 May 23 01:20:09 PM PDT 24 12643146 ps
T74 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2150358772 May 23 01:19:25 PM PDT 24 May 23 01:19:28 PM PDT 24 41371993 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2941500287 May 23 01:19:38 PM PDT 24 May 23 01:19:43 PM PDT 24 478066075 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3328467721 May 23 01:19:25 PM PDT 24 May 23 01:19:40 PM PDT 24 2254200376 ps
T1050 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1766296908 May 23 01:19:54 PM PDT 24 May 23 01:19:57 PM PDT 24 53897903 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2697100557 May 23 01:19:43 PM PDT 24 May 23 01:19:48 PM PDT 24 278844978 ps
T1052 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.495038411 May 23 01:19:33 PM PDT 24 May 23 01:19:38 PM PDT 24 136831618 ps
T1053 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3212483609 May 23 01:19:52 PM PDT 24 May 23 01:19:54 PM PDT 24 11065586 ps
T1054 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1717956286 May 23 01:19:46 PM PDT 24 May 23 01:19:50 PM PDT 24 108847663 ps
T1055 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3725385744 May 23 01:19:59 PM PDT 24 May 23 01:20:02 PM PDT 24 171429908 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.316589635 May 23 01:19:32 PM PDT 24 May 23 01:19:37 PM PDT 24 99233561 ps
T1057 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.980976630 May 23 01:20:18 PM PDT 24 May 23 01:20:20 PM PDT 24 47909803 ps
T265 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3814602984 May 23 01:19:31 PM PDT 24 May 23 01:19:49 PM PDT 24 2791162383 ps
T1058 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.145541567 May 23 01:19:37 PM PDT 24 May 23 01:19:41 PM PDT 24 19566798 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3784636046 May 23 01:19:37 PM PDT 24 May 23 01:19:42 PM PDT 24 101177532 ps
T260 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1657961654 May 23 01:19:42 PM PDT 24 May 23 01:19:48 PM PDT 24 340255493 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2512298567 May 23 01:19:25 PM PDT 24 May 23 01:19:30 PM PDT 24 149284896 ps
T1061 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3117983969 May 23 01:19:32 PM PDT 24 May 23 01:19:39 PM PDT 24 370748698 ps
T1062 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3840398942 May 23 01:19:43 PM PDT 24 May 23 01:19:45 PM PDT 24 42021753 ps
T1063 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2851638654 May 23 01:19:34 PM PDT 24 May 23 01:19:40 PM PDT 24 88288502 ps
T1064 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4020147148 May 23 01:19:37 PM PDT 24 May 23 01:19:43 PM PDT 24 87475848 ps
T1065 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3121094678 May 23 01:19:36 PM PDT 24 May 23 01:19:43 PM PDT 24 62191088 ps
T1066 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3951787517 May 23 01:19:33 PM PDT 24 May 23 01:19:38 PM PDT 24 98726151 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3507102017 May 23 01:19:47 PM PDT 24 May 23 01:19:51 PM PDT 24 107823081 ps
T1068 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.146176151 May 23 01:19:46 PM PDT 24 May 23 01:19:53 PM PDT 24 26135177 ps
T1069 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2630764966 May 23 01:19:54 PM PDT 24 May 23 01:19:57 PM PDT 24 67315867 ps
T1070 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.816091636 May 23 01:19:36 PM PDT 24 May 23 01:19:42 PM PDT 24 112022349 ps
T1071 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2891867261 May 23 01:19:45 PM PDT 24 May 23 01:19:49 PM PDT 24 297422306 ps
T1072 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.202603336 May 23 01:19:34 PM PDT 24 May 23 01:19:45 PM PDT 24 181879713 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3447865140 May 23 01:19:37 PM PDT 24 May 23 01:19:41 PM PDT 24 811746265 ps
T261 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.119199159 May 23 01:19:28 PM PDT 24 May 23 01:19:35 PM PDT 24 423269615 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4177620696 May 23 01:19:29 PM PDT 24 May 23 01:19:32 PM PDT 24 75660628 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2079323166 May 23 01:19:43 PM PDT 24 May 23 01:19:56 PM PDT 24 407332790 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3436749911 May 23 01:19:31 PM PDT 24 May 23 01:19:41 PM PDT 24 513135770 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3112039483 May 23 01:19:29 PM PDT 24 May 23 01:19:33 PM PDT 24 75071736 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1447447824 May 23 01:19:43 PM PDT 24 May 23 01:19:52 PM PDT 24 440229210 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3664233499 May 23 01:19:31 PM PDT 24 May 23 01:19:36 PM PDT 24 223627776 ps
T1080 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.924196107 May 23 01:19:29 PM PDT 24 May 23 01:19:44 PM PDT 24 11330315978 ps
T1081 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.357853860 May 23 01:19:48 PM PDT 24 May 23 01:19:50 PM PDT 24 51811384 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.968462347 May 23 01:19:26 PM PDT 24 May 23 01:19:30 PM PDT 24 693205997 ps
T1083 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.172392217 May 23 01:19:36 PM PDT 24 May 23 01:19:40 PM PDT 24 81759480 ps
T1084 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1584017846 May 23 01:19:39 PM PDT 24 May 23 01:19:45 PM PDT 24 110568946 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1651673711 May 23 01:19:32 PM PDT 24 May 23 01:19:36 PM PDT 24 14675308 ps
T1086 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.569218578 May 23 01:19:39 PM PDT 24 May 23 01:19:46 PM PDT 24 820215997 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3159725502 May 23 01:19:34 PM PDT 24 May 23 01:19:39 PM PDT 24 84152219 ps
T1088 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1954379077 May 23 01:19:39 PM PDT 24 May 23 01:19:44 PM PDT 24 215982324 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2180637717 May 23 01:19:33 PM PDT 24 May 23 01:19:44 PM PDT 24 1422918029 ps
T75 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2014056714 May 23 01:19:28 PM PDT 24 May 23 01:19:30 PM PDT 24 141381406 ps
T1090 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3777187888 May 23 01:19:33 PM PDT 24 May 23 01:19:37 PM PDT 24 66745822 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2772937184 May 23 01:19:24 PM PDT 24 May 23 01:19:38 PM PDT 24 2643063792 ps
T1092 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.223461346 May 23 01:19:29 PM PDT 24 May 23 01:19:32 PM PDT 24 72564694 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2207542321 May 23 01:19:29 PM PDT 24 May 23 01:19:31 PM PDT 24 13334217 ps
T1094 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.728677915 May 23 01:20:09 PM PDT 24 May 23 01:20:12 PM PDT 24 39234089 ps
T1095 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3400608787 May 23 01:19:58 PM PDT 24 May 23 01:20:01 PM PDT 24 12526715 ps
T1096 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.864490737 May 23 01:19:35 PM PDT 24 May 23 01:19:39 PM PDT 24 68171212 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3357421319 May 23 01:19:32 PM PDT 24 May 23 01:19:36 PM PDT 24 30595037 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4009738266 May 23 01:19:33 PM PDT 24 May 23 01:19:38 PM PDT 24 57793395 ps
T1099 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1532188258 May 23 01:19:46 PM PDT 24 May 23 01:19:48 PM PDT 24 30430586 ps
T1100 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.852352408 May 23 01:19:46 PM PDT 24 May 23 01:19:48 PM PDT 24 75205310 ps

Test location /workspace/coverage/default/21.spi_device_upload.1289742603
Short name T9
Test name
Test status
Simulation time 2422365515 ps
CPU time 11.86 seconds
Started May 23 01:24:35 PM PDT 24
Finished May 23 01:24:48 PM PDT 24
Peak memory 235548 kb
Host smart-724a815e-a8fd-4ede-8c1f-73bedaf14845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289742603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1289742603
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1701745172
Short name T11
Test name
Test status
Simulation time 68877801475 ps
CPU time 304.26 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:30:56 PM PDT 24
Peak memory 255376 kb
Host smart-f23e2be3-9633-4324-abfb-a041b80ba871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701745172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1701745172
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4261896813
Short name T29
Test name
Test status
Simulation time 26098962879 ps
CPU time 124.21 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:26:26 PM PDT 24
Peak memory 252324 kb
Host smart-39e937af-d50c-4eae-92cf-5ac49141c159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261896813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4261896813
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3382670278
Short name T86
Test name
Test status
Simulation time 143451729 ps
CPU time 3.5 seconds
Started May 23 01:19:41 PM PDT 24
Finished May 23 01:19:47 PM PDT 24
Peak memory 217572 kb
Host smart-621b8317-6ee5-44ed-b0fa-41af4fe295e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382670278 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3382670278
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1675192641
Short name T33
Test name
Test status
Simulation time 221131904125 ps
CPU time 501.12 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:33:58 PM PDT 24
Peak memory 265784 kb
Host smart-a217ea81-e3e1-45d4-8e03-ec268c4b0a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675192641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1675192641
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3839905413
Short name T163
Test name
Test status
Simulation time 10245441190 ps
CPU time 111.38 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:27:42 PM PDT 24
Peak memory 249256 kb
Host smart-7479603e-438c-4173-807c-f36ae8e3bd81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839905413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3839905413
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2678820429
Short name T61
Test name
Test status
Simulation time 35472264 ps
CPU time 0.74 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 216144 kb
Host smart-9891b929-749e-41eb-954b-a96855194eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678820429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2678820429
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.856516856
Short name T18
Test name
Test status
Simulation time 8644000853 ps
CPU time 31.51 seconds
Started May 23 01:24:33 PM PDT 24
Finished May 23 01:25:05 PM PDT 24
Peak memory 216412 kb
Host smart-995cf0ee-3db1-42e9-9ff5-3f9d6213d842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856516856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.856516856
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1342679562
Short name T70
Test name
Test status
Simulation time 5607922497 ps
CPU time 112.16 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:26:30 PM PDT 24
Peak memory 266144 kb
Host smart-4fca65c4-a227-4fd3-a806-8426bfbccdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342679562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1342679562
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2446863073
Short name T175
Test name
Test status
Simulation time 31294908675 ps
CPU time 350.79 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:31:41 PM PDT 24
Peak memory 249624 kb
Host smart-19579548-8a64-486d-8440-deaeae0b0e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446863073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2446863073
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2394242623
Short name T7
Test name
Test status
Simulation time 171626787 ps
CPU time 1.29 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:23:47 PM PDT 24
Peak memory 235140 kb
Host smart-cdb7f85e-99e7-43eb-a0fe-4e88bed4c37e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394242623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2394242623
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3782913017
Short name T46
Test name
Test status
Simulation time 25891563726 ps
CPU time 282.16 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:30:31 PM PDT 24
Peak memory 249372 kb
Host smart-d692b8ec-95db-4fcc-9d73-77511d22f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782913017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3782913017
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1620111400
Short name T132
Test name
Test status
Simulation time 88720679080 ps
CPU time 819 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:37:46 PM PDT 24
Peak memory 275908 kb
Host smart-fe3d2449-2621-46df-96ce-4bf78bc190c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620111400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1620111400
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2953798825
Short name T52
Test name
Test status
Simulation time 3823416504 ps
CPU time 44.9 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:52 PM PDT 24
Peak memory 232804 kb
Host smart-c9b76769-0d7a-4ed1-a186-801eb291121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953798825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2953798825
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3078391595
Short name T37
Test name
Test status
Simulation time 119360617625 ps
CPU time 314.93 seconds
Started May 23 01:23:29 PM PDT 24
Finished May 23 01:28:46 PM PDT 24
Peak memory 254704 kb
Host smart-a28a4da8-bfef-4f5a-aac4-9b9aa2dcfda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078391595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3078391595
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3755644540
Short name T262
Test name
Test status
Simulation time 834434173 ps
CPU time 21.19 seconds
Started May 23 01:19:26 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 217572 kb
Host smart-549368e6-9c9d-4146-9b2a-e8c6f28234cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755644540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3755644540
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3323036682
Short name T310
Test name
Test status
Simulation time 2916677792 ps
CPU time 29.9 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:26:21 PM PDT 24
Peak memory 216400 kb
Host smart-cc73b847-6f4d-4b37-b448-0efb070d6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323036682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3323036682
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3369616005
Short name T69
Test name
Test status
Simulation time 7916773976 ps
CPU time 171.9 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:26:57 PM PDT 24
Peak memory 283708 kb
Host smart-baa66132-71de-4aee-88a9-e08a3cbb92d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369616005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3369616005
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1674143897
Short name T119
Test name
Test status
Simulation time 22990026 ps
CPU time 1.32 seconds
Started May 23 01:19:38 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 207424 kb
Host smart-b2fa4cb8-731b-4b73-b1eb-7254fee4e5b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674143897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1674143897
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.316272403
Short name T172
Test name
Test status
Simulation time 281792344681 ps
CPU time 702.44 seconds
Started May 23 01:26:07 PM PDT 24
Finished May 23 01:37:50 PM PDT 24
Peak memory 282192 kb
Host smart-34e4a547-f442-4322-bef5-20d187900794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316272403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.316272403
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2276128847
Short name T96
Test name
Test status
Simulation time 189914771 ps
CPU time 4.38 seconds
Started May 23 01:19:48 PM PDT 24
Finished May 23 01:19:53 PM PDT 24
Peak memory 215892 kb
Host smart-fba05dbd-bfc3-4dd4-9599-ca326c378427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276128847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2276128847
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3795310729
Short name T36
Test name
Test status
Simulation time 35447097254 ps
CPU time 314.44 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:29:28 PM PDT 24
Peak memory 273260 kb
Host smart-393bc4dc-81a3-4cde-bad7-9f9dd39425a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795310729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3795310729
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4059864737
Short name T23
Test name
Test status
Simulation time 31150781 ps
CPU time 1.14 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 217884 kb
Host smart-a0bc63fa-b1f3-46f1-9720-d0a1c662cd6d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059864737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4059864737
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2741325957
Short name T24
Test name
Test status
Simulation time 581051045974 ps
CPU time 302.19 seconds
Started May 23 01:25:17 PM PDT 24
Finished May 23 01:30:20 PM PDT 24
Peak memory 264048 kb
Host smart-37307426-7b51-4896-b081-1814a97ae333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741325957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2741325957
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3193470671
Short name T270
Test name
Test status
Simulation time 279130538229 ps
CPU time 571.31 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:33:31 PM PDT 24
Peak memory 271432 kb
Host smart-c61e19e0-3df1-4a53-ac81-40b6bf17efbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193470671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3193470671
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2813126887
Short name T230
Test name
Test status
Simulation time 91490010816 ps
CPU time 562.83 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:35:16 PM PDT 24
Peak memory 282244 kb
Host smart-8fe87f56-7d3c-44a2-88f4-1d4950d4b216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813126887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2813126887
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1928289154
Short name T122
Test name
Test status
Simulation time 96332602557 ps
CPU time 219.58 seconds
Started May 23 01:23:47 PM PDT 24
Finished May 23 01:27:28 PM PDT 24
Peak memory 249316 kb
Host smart-5152b02f-72b1-4116-b966-382959fe80a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928289154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1928289154
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2463043298
Short name T176
Test name
Test status
Simulation time 95964380821 ps
CPU time 222.74 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:27:20 PM PDT 24
Peak memory 264104 kb
Host smart-d3003a7e-9603-4e40-ba82-f8e2dcf76e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463043298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2463043298
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2466872108
Short name T232
Test name
Test status
Simulation time 23278879719 ps
CPU time 227.66 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:28:14 PM PDT 24
Peak memory 256880 kb
Host smart-45a9442c-01ff-40fb-b4c7-c5e22da69b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466872108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2466872108
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1806945759
Short name T328
Test name
Test status
Simulation time 14422556 ps
CPU time 0.74 seconds
Started May 23 01:23:30 PM PDT 24
Finished May 23 01:23:31 PM PDT 24
Peak memory 205360 kb
Host smart-653f1033-eacd-4acf-881e-7c61b5fb1e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806945759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
806945759
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1657961654
Short name T260
Test name
Test status
Simulation time 340255493 ps
CPU time 4.5 seconds
Started May 23 01:19:42 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 215836 kb
Host smart-ad425790-8754-48c6-8449-de7f92fd0311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657961654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1657961654
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1521721564
Short name T237
Test name
Test status
Simulation time 72195179447 ps
CPU time 688.92 seconds
Started May 23 01:24:45 PM PDT 24
Finished May 23 01:36:15 PM PDT 24
Peak memory 257564 kb
Host smart-0011be8e-31d8-480b-8447-fc9d66a9c5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521721564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1521721564
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.721097763
Short name T217
Test name
Test status
Simulation time 50654151254 ps
CPU time 483.77 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:33:00 PM PDT 24
Peak memory 265792 kb
Host smart-30433d2f-8fad-4ebd-b3bf-1b74732c668a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721097763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.721097763
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4060951856
Short name T19
Test name
Test status
Simulation time 79082885 ps
CPU time 0.93 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 205860 kb
Host smart-c7151e7d-c24c-4130-9738-fe38ac8f440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060951856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4060951856
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1988126605
Short name T269
Test name
Test status
Simulation time 3347976925 ps
CPU time 22.58 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:57 PM PDT 24
Peak memory 216144 kb
Host smart-2af5ae33-43f9-4e9c-b612-7a926b98d0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988126605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1988126605
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.386494671
Short name T263
Test name
Test status
Simulation time 1363674235 ps
CPU time 14.38 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:52 PM PDT 24
Peak memory 216192 kb
Host smart-a5466c8c-829c-4d46-a32d-0b324679e3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386494671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.386494671
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.571468044
Short name T250
Test name
Test status
Simulation time 30973110031 ps
CPU time 348.46 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:29:54 PM PDT 24
Peak memory 272036 kb
Host smart-20c10fc5-d898-429c-b312-2eae56a5e84e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571468044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.571468044
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4099378201
Short name T302
Test name
Test status
Simulation time 1020537907 ps
CPU time 10.02 seconds
Started May 23 01:24:08 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 224508 kb
Host smart-8f1b2b07-24ad-445f-8652-d92636c1f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099378201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4099378201
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3714404128
Short name T220
Test name
Test status
Simulation time 30091474876 ps
CPU time 361.83 seconds
Started May 23 01:24:56 PM PDT 24
Finished May 23 01:31:01 PM PDT 24
Peak memory 273924 kb
Host smart-10cddcf9-ba36-40e9-9fc1-ba4fffc2f035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714404128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3714404128
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2804453454
Short name T226
Test name
Test status
Simulation time 19635906388 ps
CPU time 243.85 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:28:03 PM PDT 24
Peak memory 265640 kb
Host smart-767e6d62-c98a-489c-81b7-5ee2d71b741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804453454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2804453454
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2376762184
Short name T84
Test name
Test status
Simulation time 1616846833 ps
CPU time 5.59 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:13 PM PDT 24
Peak memory 233752 kb
Host smart-90338e5d-ea56-4127-b6ea-1d92e4de8fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376762184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2376762184
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.870840817
Short name T34
Test name
Test status
Simulation time 2074647018 ps
CPU time 7.47 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:25:01 PM PDT 24
Peak memory 217068 kb
Host smart-83b7b0a9-60ca-4dd3-8fb2-fa789440c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870840817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.870840817
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3147763965
Short name T173
Test name
Test status
Simulation time 3124437067 ps
CPU time 67.44 seconds
Started May 23 01:24:10 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 255804 kb
Host smart-3990c352-e3db-451f-921a-1ebb4c8b8460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147763965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3147763965
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2821332062
Short name T240
Test name
Test status
Simulation time 47061215168 ps
CPU time 458.02 seconds
Started May 23 01:24:09 PM PDT 24
Finished May 23 01:31:49 PM PDT 24
Peak memory 253020 kb
Host smart-0ade646e-6b74-4f19-9aa9-7940dcba3363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821332062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2821332062
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1266378523
Short name T919
Test name
Test status
Simulation time 421109590784 ps
CPU time 1006.36 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:41:11 PM PDT 24
Peak memory 289488 kb
Host smart-7a66394c-e224-49da-9906-b3e0b1beabb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266378523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1266378523
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3955853916
Short name T68
Test name
Test status
Simulation time 47346513948 ps
CPU time 292.83 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:29:11 PM PDT 24
Peak memory 251812 kb
Host smart-ff671abc-abaf-42ae-b6a1-b70d1e47034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955853916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3955853916
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2582406998
Short name T300
Test name
Test status
Simulation time 17715879416 ps
CPU time 63.34 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 237812 kb
Host smart-3b36f56c-da4e-4aed-a3f1-3312b78fe22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582406998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2582406998
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3443870189
Short name T238
Test name
Test status
Simulation time 96286257164 ps
CPU time 439.82 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:32:20 PM PDT 24
Peak memory 249396 kb
Host smart-382f0035-2fa6-4970-b8b0-5d188eedd4ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443870189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3443870189
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2207382351
Short name T249
Test name
Test status
Simulation time 9316945147 ps
CPU time 42.62 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:24:29 PM PDT 24
Peak memory 250252 kb
Host smart-7aedeb37-0142-45cb-8622-ac0af2c2d76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207382351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2207382351
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2913531658
Short name T193
Test name
Test status
Simulation time 1227470698146 ps
CPU time 769.53 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:36:52 PM PDT 24
Peak memory 266536 kb
Host smart-713de9c5-05d8-47d5-8e13-6950bfca7ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913531658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2913531658
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2150358772
Short name T74
Test name
Test status
Simulation time 41371993 ps
CPU time 1.37 seconds
Started May 23 01:19:25 PM PDT 24
Finished May 23 01:19:28 PM PDT 24
Peak memory 207444 kb
Host smart-3aa39c81-6c6e-4e73-a6fe-59ff1c83b757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150358772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2150358772
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4139151216
Short name T101
Test name
Test status
Simulation time 353372240 ps
CPU time 4.04 seconds
Started May 23 01:19:40 PM PDT 24
Finished May 23 01:19:46 PM PDT 24
Peak memory 215800 kb
Host smart-8ef190f8-3425-4876-bfaa-f32ee8341b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139151216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4139151216
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2450474492
Short name T997
Test name
Test status
Simulation time 116332489 ps
CPU time 8.2 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:49 PM PDT 24
Peak memory 215684 kb
Host smart-dabd9395-8d6c-455f-9c4d-89fc2256ae3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450474492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2450474492
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3156324768
Short name T984
Test name
Test status
Simulation time 716110005 ps
CPU time 12.07 seconds
Started May 23 01:19:23 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 207432 kb
Host smart-3cc5d400-fc0d-4868-876d-ece1906d26ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156324768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3156324768
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3278821326
Short name T1017
Test name
Test status
Simulation time 29794948 ps
CPU time 1.86 seconds
Started May 23 01:19:25 PM PDT 24
Finished May 23 01:19:28 PM PDT 24
Peak memory 215716 kb
Host smart-7fa61302-8221-4cdc-a503-f3dc055623bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278821326 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3278821326
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.204580281
Short name T1014
Test name
Test status
Simulation time 153086358 ps
CPU time 1.42 seconds
Started May 23 01:19:21 PM PDT 24
Finished May 23 01:19:23 PM PDT 24
Peak memory 207532 kb
Host smart-e96893cd-9064-45fb-b597-ae47dd40fe2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204580281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.204580281
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.907742542
Short name T1004
Test name
Test status
Simulation time 43040319 ps
CPU time 0.76 seconds
Started May 23 01:19:28 PM PDT 24
Finished May 23 01:19:30 PM PDT 24
Peak memory 203804 kb
Host smart-8f46e4a4-7b16-47cd-8bda-eb9ed9931203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907742542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.907742542
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3159725502
Short name T1087
Test name
Test status
Simulation time 84152219 ps
CPU time 1.89 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:39 PM PDT 24
Peak memory 215864 kb
Host smart-d2cded8f-dcae-465e-ab9b-939b8238e287
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159725502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3159725502
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.653784737
Short name T990
Test name
Test status
Simulation time 36440318 ps
CPU time 0.7 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 203764 kb
Host smart-b3c81184-1fd2-48ae-ba64-82206e8739ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653784737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.653784737
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2314548745
Short name T144
Test name
Test status
Simulation time 262052864 ps
CPU time 2.86 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 215684 kb
Host smart-74e0db88-7006-4397-bb36-7f5f8537082c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314548745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2314548745
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.119199159
Short name T261
Test name
Test status
Simulation time 423269615 ps
CPU time 5.54 seconds
Started May 23 01:19:28 PM PDT 24
Finished May 23 01:19:35 PM PDT 24
Peak memory 216792 kb
Host smart-3c5d54a4-e4f3-451c-a1c1-9983ec96516b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119199159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.119199159
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4245770932
Short name T108
Test name
Test status
Simulation time 294059000 ps
CPU time 18.16 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:51 PM PDT 24
Peak memory 215844 kb
Host smart-78fb8be6-250d-403a-aa03-74bce77d71eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245770932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4245770932
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3328467721
Short name T1049
Test name
Test status
Simulation time 2254200376 ps
CPU time 13.52 seconds
Started May 23 01:19:25 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 215920 kb
Host smart-a52331e5-4a53-412c-9e25-a03d3825f61e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328467721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3328467721
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2772937184
Short name T1091
Test name
Test status
Simulation time 2643063792 ps
CPU time 13.3 seconds
Started May 23 01:19:24 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 207544 kb
Host smart-15764ac7-b896-49c2-ac54-c0147b66dcd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772937184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2772937184
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1834541186
Short name T72
Test name
Test status
Simulation time 89265232 ps
CPU time 1.34 seconds
Started May 23 01:19:27 PM PDT 24
Finished May 23 01:19:29 PM PDT 24
Peak memory 207352 kb
Host smart-f95efe11-6d8a-4a6e-a13a-ed03df1df6cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834541186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1834541186
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.316589635
Short name T1056
Test name
Test status
Simulation time 99233561 ps
CPU time 2.62 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 217408 kb
Host smart-db6e16a8-3ae6-4746-8881-da28bbcf95e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316589635 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.316589635
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.319500622
Short name T1007
Test name
Test status
Simulation time 284005160 ps
CPU time 2.24 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 207584 kb
Host smart-4fd75f3e-c8e7-457b-9c0d-fa687a33625a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319500622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.319500622
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.74937061
Short name T1012
Test name
Test status
Simulation time 147932109 ps
CPU time 0.75 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:34 PM PDT 24
Peak memory 203908 kb
Host smart-368221bc-778b-4bfd-840f-e6ea72389cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74937061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.74937061
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4177620696
Short name T1074
Test name
Test status
Simulation time 75660628 ps
CPU time 1.71 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:32 PM PDT 24
Peak memory 215776 kb
Host smart-4a9587d5-a42b-4d08-a529-2d8ab98d600d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177620696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4177620696
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2022486523
Short name T987
Test name
Test status
Simulation time 18589353 ps
CPU time 0.69 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:34 PM PDT 24
Peak memory 203772 kb
Host smart-678a6462-da1c-49e5-9a68-0cd08786aee8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022486523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2022486523
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2608287031
Short name T145
Test name
Test status
Simulation time 286579342 ps
CPU time 1.87 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:35 PM PDT 24
Peak memory 215696 kb
Host smart-1b424ddf-4139-4ce1-81c6-828745faedf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608287031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2608287031
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1843417798
Short name T103
Test name
Test status
Simulation time 174019835 ps
CPU time 3.37 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 215788 kb
Host smart-3e3687e7-57ee-47cd-b530-b7dff8389c0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843417798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
843417798
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3533257429
Short name T1023
Test name
Test status
Simulation time 96075377 ps
CPU time 2.47 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 216892 kb
Host smart-520aa938-afd8-4c79-b113-36f87dd38955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533257429 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3533257429
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1535618686
Short name T118
Test name
Test status
Simulation time 65657554 ps
CPU time 2.15 seconds
Started May 23 01:19:40 PM PDT 24
Finished May 23 01:19:44 PM PDT 24
Peak memory 215816 kb
Host smart-70673782-6eae-409a-8b7b-05f127667006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535618686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1535618686
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.120277078
Short name T1020
Test name
Test status
Simulation time 14453712 ps
CPU time 0.74 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:00 PM PDT 24
Peak memory 204172 kb
Host smart-339dc72f-39de-4cca-afab-abf224dee5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120277078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.120277078
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3117983969
Short name T1061
Test name
Test status
Simulation time 370748698 ps
CPU time 4.29 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:39 PM PDT 24
Peak memory 215668 kb
Host smart-2f5b29de-c1d1-4889-9b42-8ec9f658776f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117983969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3117983969
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4142788717
Short name T97
Test name
Test status
Simulation time 1366310127 ps
CPU time 3.37 seconds
Started May 23 01:19:35 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 215824 kb
Host smart-8333fb15-2d90-48ac-ac60-93650ed6fcfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142788717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4142788717
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4208144766
Short name T268
Test name
Test status
Simulation time 1023274139 ps
CPU time 22.78 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:56 PM PDT 24
Peak memory 215864 kb
Host smart-7bd08544-1737-4078-8d36-88526e5394a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208144766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4208144766
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3507102017
Short name T1067
Test name
Test status
Simulation time 107823081 ps
CPU time 2.69 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:19:51 PM PDT 24
Peak memory 217120 kb
Host smart-766392a8-b619-4d83-8c26-fce3490855c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507102017 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3507102017
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3777187888
Short name T1090
Test name
Test status
Simulation time 66745822 ps
CPU time 1.25 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 207440 kb
Host smart-d5751733-2000-4a4e-ad7a-39a6b7fcbb6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777187888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3777187888
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1856711679
Short name T1013
Test name
Test status
Simulation time 31244178 ps
CPU time 0.74 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 204188 kb
Host smart-41bb37b6-1901-44d4-ba73-df01e615af4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856711679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1856711679
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1035164631
Short name T1038
Test name
Test status
Simulation time 224756892 ps
CPU time 3.96 seconds
Started May 23 01:19:41 PM PDT 24
Finished May 23 01:19:47 PM PDT 24
Peak memory 215784 kb
Host smart-b070340e-aee1-4963-bcf4-ae8bdf2d95ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035164631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1035164631
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3874732603
Short name T267
Test name
Test status
Simulation time 831649546 ps
CPU time 22.53 seconds
Started May 23 01:19:48 PM PDT 24
Finished May 23 01:20:11 PM PDT 24
Peak memory 215932 kb
Host smart-f6b34fd1-66e3-4240-9000-615e14271c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874732603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3874732603
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3297879881
Short name T92
Test name
Test status
Simulation time 128705779 ps
CPU time 1.7 seconds
Started May 23 01:19:42 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 215840 kb
Host smart-03880736-1ac3-4534-8dd5-3f4c33cc0383
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297879881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3297879881
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.187991072
Short name T138
Test name
Test status
Simulation time 488121956 ps
CPU time 2.86 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 215652 kb
Host smart-bc92e000-8f93-4d06-8848-ea5b4bd5e90e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187991072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.187991072
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.852352408
Short name T1100
Test name
Test status
Simulation time 75205310 ps
CPU time 0.68 seconds
Started May 23 01:19:46 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 204264 kb
Host smart-26f3ab96-d86a-401c-9725-9392061df9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852352408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.852352408
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.495038411
Short name T1052
Test name
Test status
Simulation time 136831618 ps
CPU time 1.8 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 207688 kb
Host smart-417dba3b-a300-4926-8baa-962ed0e61df1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495038411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.495038411
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2026752443
Short name T99
Test name
Test status
Simulation time 27600408 ps
CPU time 1.54 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 215908 kb
Host smart-2df8e5b0-51c3-4d1d-a232-6663ae239247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026752443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2026752443
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1447447824
Short name T1078
Test name
Test status
Simulation time 440229210 ps
CPU time 7.15 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:52 PM PDT 24
Peak memory 215764 kb
Host smart-0383e924-54b7-4fb3-9126-277ed4c02023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447447824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1447447824
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4020147148
Short name T1064
Test name
Test status
Simulation time 87475848 ps
CPU time 2.89 seconds
Started May 23 01:19:37 PM PDT 24
Finished May 23 01:19:43 PM PDT 24
Peak memory 215772 kb
Host smart-2472dcd8-73bf-4ef1-952e-37b3a399e121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020147148 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4020147148
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3466250649
Short name T989
Test name
Test status
Simulation time 23523521 ps
CPU time 0.74 seconds
Started May 23 01:19:42 PM PDT 24
Finished May 23 01:19:44 PM PDT 24
Peak memory 204000 kb
Host smart-35cdfa92-0664-45e4-8576-94cb9adad1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466250649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3466250649
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1954379077
Short name T1088
Test name
Test status
Simulation time 215982324 ps
CPU time 3.01 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:44 PM PDT 24
Peak memory 215844 kb
Host smart-a40ff5bd-7a3a-400e-8d46-eafae4695b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954379077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1954379077
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.71400792
Short name T105
Test name
Test status
Simulation time 222097421 ps
CPU time 3.73 seconds
Started May 23 01:19:49 PM PDT 24
Finished May 23 01:19:54 PM PDT 24
Peak memory 217952 kb
Host smart-bb7d2871-25c4-41f0-92b4-806dda24e170
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71400792 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.71400792
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2222333603
Short name T114
Test name
Test status
Simulation time 374520444 ps
CPU time 2.69 seconds
Started May 23 01:19:42 PM PDT 24
Finished May 23 01:19:46 PM PDT 24
Peak memory 215628 kb
Host smart-f0a47828-8ae5-44ad-9f56-0a627aa2451b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222333603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2222333603
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3736988823
Short name T991
Test name
Test status
Simulation time 107591181 ps
CPU time 0.79 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 203912 kb
Host smart-55612794-38b5-4333-81c2-70650a114ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736988823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3736988823
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1584017846
Short name T1084
Test name
Test status
Simulation time 110568946 ps
CPU time 2.95 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 215768 kb
Host smart-1f824d0f-fab4-4e76-a2b2-7412bf72fcae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584017846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1584017846
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.569218578
Short name T1086
Test name
Test status
Simulation time 820215997 ps
CPU time 4.56 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:46 PM PDT 24
Peak memory 215896 kb
Host smart-a270e302-f250-4e39-9322-538a81397a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569218578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.569218578
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.433570258
Short name T90
Test name
Test status
Simulation time 543960447 ps
CPU time 14.89 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:53 PM PDT 24
Peak memory 215924 kb
Host smart-91ed30ad-0709-4fc0-ad02-015550235cac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433570258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.433570258
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3920285211
Short name T1033
Test name
Test status
Simulation time 116554609 ps
CPU time 1.77 seconds
Started May 23 01:19:37 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 215908 kb
Host smart-d0994bbc-bf28-4088-b770-e837962aa8d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920285211 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3920285211
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2137804636
Short name T993
Test name
Test status
Simulation time 109441448 ps
CPU time 1.92 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:43 PM PDT 24
Peak memory 215788 kb
Host smart-05d01275-aa48-4def-a2b8-5817ef9b468c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137804636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2137804636
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3068593612
Short name T1026
Test name
Test status
Simulation time 17870827 ps
CPU time 0.77 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 204156 kb
Host smart-ec5e7292-ba21-4f06-a29c-9aa651cc1c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068593612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3068593612
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.319592752
Short name T137
Test name
Test status
Simulation time 251777805 ps
CPU time 1.74 seconds
Started May 23 01:19:35 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 216388 kb
Host smart-0bb82f2b-d824-43e0-af8b-be096777aabf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319592752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.319592752
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.332115095
Short name T1042
Test name
Test status
Simulation time 121738999 ps
CPU time 4.07 seconds
Started May 23 01:19:44 PM PDT 24
Finished May 23 01:19:50 PM PDT 24
Peak memory 216836 kb
Host smart-fb45952c-9c7d-48b4-9e66-de7f95c9ae05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332115095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.332115095
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1106806155
Short name T266
Test name
Test status
Simulation time 292592467 ps
CPU time 19.25 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:58 PM PDT 24
Peak memory 215712 kb
Host smart-01d61924-fa0c-473f-8b98-2bc206849efb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106806155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1106806155
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3850716672
Short name T107
Test name
Test status
Simulation time 211102034 ps
CPU time 1.86 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 215872 kb
Host smart-66952973-a48c-4833-a98f-0790c2b5ee96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850716672 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3850716672
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2183049091
Short name T115
Test name
Test status
Simulation time 487216248 ps
CPU time 2.84 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:19:49 PM PDT 24
Peak memory 207476 kb
Host smart-7a560642-61d8-4e21-91b7-7f92528b59c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183049091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2183049091
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.161730789
Short name T1022
Test name
Test status
Simulation time 46517655 ps
CPU time 0.7 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 204248 kb
Host smart-b8869a6d-9902-4f62-b9ca-a4d7c16cb136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161730789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.161730789
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3597773434
Short name T142
Test name
Test status
Simulation time 73159389 ps
CPU time 1.84 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 215828 kb
Host smart-4e384edf-6f4b-4f7f-a775-b8d4ba3b54e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597773434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3597773434
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1872505831
Short name T89
Test name
Test status
Simulation time 290236674 ps
CPU time 7.99 seconds
Started May 23 01:19:38 PM PDT 24
Finished May 23 01:19:49 PM PDT 24
Peak memory 215764 kb
Host smart-e8c780e1-3729-4f5e-a80f-1d3c3f423241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872505831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1872505831
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.306897449
Short name T91
Test name
Test status
Simulation time 58858667 ps
CPU time 4.09 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:19:56 PM PDT 24
Peak memory 218228 kb
Host smart-cda60d29-62be-4446-93fb-74443fd6f2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306897449 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.306897449
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.864490737
Short name T1096
Test name
Test status
Simulation time 68171212 ps
CPU time 1.33 seconds
Started May 23 01:19:35 PM PDT 24
Finished May 23 01:19:39 PM PDT 24
Peak memory 215792 kb
Host smart-a52e251c-03e4-49fb-9ffb-4d466ca8e2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864490737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.864490737
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.113217068
Short name T1011
Test name
Test status
Simulation time 69313011 ps
CPU time 0.75 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 203996 kb
Host smart-8005a42c-1470-4b4d-be01-7300a5628b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113217068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.113217068
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.832506567
Short name T1034
Test name
Test status
Simulation time 60927556 ps
CPU time 1.79 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:46 PM PDT 24
Peak memory 215704 kb
Host smart-593a808f-75ef-4937-b47f-dda5b733596f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832506567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.832506567
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2697100557
Short name T1051
Test name
Test status
Simulation time 278844978 ps
CPU time 3.65 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 215976 kb
Host smart-303e4565-d5bb-4fc3-ae9f-fcf5bd605eed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697100557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2697100557
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3247997891
Short name T88
Test name
Test status
Simulation time 3151346299 ps
CPU time 21.46 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:57 PM PDT 24
Peak memory 215944 kb
Host smart-09f8c4f8-59aa-4c08-be9d-0ece301605c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247997891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3247997891
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2494994335
Short name T106
Test name
Test status
Simulation time 131460781 ps
CPU time 2.86 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 216860 kb
Host smart-83e66f94-b0bc-41bd-b93f-02c436cce6e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494994335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2494994335
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1997074265
Short name T1046
Test name
Test status
Simulation time 334579579 ps
CPU time 2.14 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:43 PM PDT 24
Peak memory 215648 kb
Host smart-359c1636-6a21-40b8-a8f5-22be7fa717c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997074265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1997074265
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.407185703
Short name T1027
Test name
Test status
Simulation time 15401074 ps
CPU time 0.72 seconds
Started May 23 01:19:38 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 204232 kb
Host smart-ea1c0fdb-bc03-4252-a47f-394862e7e6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407185703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.407185703
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3121094678
Short name T1065
Test name
Test status
Simulation time 62191088 ps
CPU time 3.83 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:43 PM PDT 24
Peak memory 215700 kb
Host smart-e1c59211-dad0-47f8-89ec-da76954c1c7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121094678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3121094678
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2389450719
Short name T93
Test name
Test status
Simulation time 130802145 ps
CPU time 3.65 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 215864 kb
Host smart-fc12be0f-f3d4-446a-bce9-47ef391f1d21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389450719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2389450719
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.912420258
Short name T1039
Test name
Test status
Simulation time 579192234 ps
CPU time 14.19 seconds
Started May 23 01:19:51 PM PDT 24
Finished May 23 01:20:07 PM PDT 24
Peak memory 215892 kb
Host smart-8db98966-6627-41cf-9342-37d6b865d94e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912420258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.912420258
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.816091636
Short name T1070
Test name
Test status
Simulation time 112022349 ps
CPU time 2.19 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 216728 kb
Host smart-34426946-596b-4ff0-8caf-45d17878dd0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816091636 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.816091636
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.172392217
Short name T1083
Test name
Test status
Simulation time 81759480 ps
CPU time 1.31 seconds
Started May 23 01:19:36 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 207432 kb
Host smart-7c6df77a-bdbc-4ff6-97ce-d5f341a2d852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172392217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.172392217
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3878016965
Short name T1006
Test name
Test status
Simulation time 60720647 ps
CPU time 0.74 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:19:58 PM PDT 24
Peak memory 203916 kb
Host smart-dfc23b20-7773-4313-92f1-c2b9090f874a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878016965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3878016965
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1717956286
Short name T1054
Test name
Test status
Simulation time 108847663 ps
CPU time 3.02 seconds
Started May 23 01:19:46 PM PDT 24
Finished May 23 01:19:50 PM PDT 24
Peak memory 215824 kb
Host smart-90e37da8-af44-4ba0-b074-1b811e891291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717956286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1717956286
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2830521907
Short name T87
Test name
Test status
Simulation time 629737546 ps
CPU time 4.12 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 215680 kb
Host smart-e3fda7ba-eac8-4b3f-948b-a3a0182dca70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830521907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2830521907
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2079323166
Short name T1075
Test name
Test status
Simulation time 407332790 ps
CPU time 11.65 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:56 PM PDT 24
Peak memory 215704 kb
Host smart-0d8b8fde-7272-47ea-86eb-3b5019421fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079323166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2079323166
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1772791781
Short name T116
Test name
Test status
Simulation time 1664902639 ps
CPU time 21.79 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:58 PM PDT 24
Peak memory 215652 kb
Host smart-e8dde383-8626-4bb1-8e90-b231d1b31414
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772791781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1772791781
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2619610199
Short name T1010
Test name
Test status
Simulation time 1814717567 ps
CPU time 37.45 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:20:12 PM PDT 24
Peak memory 215656 kb
Host smart-fe9fa8f5-2ee8-483b-8bc9-fa8e0f7b6b52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619610199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2619610199
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4034660924
Short name T73
Test name
Test status
Simulation time 22851160 ps
CPU time 0.96 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 207164 kb
Host smart-d71fddc1-a97b-491f-a84d-1cc2ddb3c6d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034660924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4034660924
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2512298567
Short name T1060
Test name
Test status
Simulation time 149284896 ps
CPU time 3.17 seconds
Started May 23 01:19:25 PM PDT 24
Finished May 23 01:19:30 PM PDT 24
Peak memory 217604 kb
Host smart-ce095e57-e191-463c-a5bc-5ae4114555a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512298567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2512298567
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.985134776
Short name T113
Test name
Test status
Simulation time 126264528 ps
CPU time 2.27 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 215628 kb
Host smart-f040bc8d-e673-45f7-949e-2c1bbb6b881e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985134776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.985134776
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.833794659
Short name T1040
Test name
Test status
Simulation time 39207644 ps
CPU time 0.69 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 203820 kb
Host smart-e41bccd3-1e9e-4d55-8b91-24f74b22db7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833794659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.833794659
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3112039483
Short name T1077
Test name
Test status
Simulation time 75071736 ps
CPU time 1.61 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:33 PM PDT 24
Peak memory 215676 kb
Host smart-4454d45e-137f-495f-a79a-bfa721096813
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112039483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3112039483
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3291541327
Short name T998
Test name
Test status
Simulation time 10390998 ps
CPU time 0.67 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:33 PM PDT 24
Peak memory 204144 kb
Host smart-1b74f301-155e-4b1a-8bf9-e6c71a25c70c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291541327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3291541327
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1853330399
Short name T1019
Test name
Test status
Simulation time 262162536 ps
CPU time 4.11 seconds
Started May 23 01:19:26 PM PDT 24
Finished May 23 01:19:31 PM PDT 24
Peak memory 215828 kb
Host smart-dcaff91d-9255-432c-902d-9b33241255e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853330399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1853330399
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3740889795
Short name T98
Test name
Test status
Simulation time 243339247 ps
CPU time 2.18 seconds
Started May 23 01:19:25 PM PDT 24
Finished May 23 01:19:28 PM PDT 24
Peak memory 215760 kb
Host smart-fa0bcf1f-3618-4b02-b7f9-2d38051e8179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740889795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
740889795
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3436749911
Short name T1076
Test name
Test status
Simulation time 513135770 ps
CPU time 7.2 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 215864 kb
Host smart-8f4f58e4-8323-4560-be2d-76099f62933a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436749911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3436749911
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3111892548
Short name T1016
Test name
Test status
Simulation time 46944064 ps
CPU time 0.86 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:00 PM PDT 24
Peak memory 203996 kb
Host smart-7c40b9e3-eaf2-41ae-9c0d-ce3950f5a5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111892548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3111892548
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.529748708
Short name T985
Test name
Test status
Simulation time 34800699 ps
CPU time 0.74 seconds
Started May 23 01:19:46 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 203964 kb
Host smart-c63db8ed-0054-4b07-b9ca-df30c52a8a7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529748708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.529748708
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3840398942
Short name T1062
Test name
Test status
Simulation time 42021753 ps
CPU time 0.76 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 204068 kb
Host smart-75bfd2c0-640a-40a2-892c-3fbbc947ca14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840398942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3840398942
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.570681394
Short name T1009
Test name
Test status
Simulation time 47845814 ps
CPU time 0.75 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:19:54 PM PDT 24
Peak memory 203932 kb
Host smart-68aeb0dd-8a48-4972-824d-0aadcd7cf349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570681394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.570681394
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.538857835
Short name T1047
Test name
Test status
Simulation time 12643146 ps
CPU time 0.72 seconds
Started May 23 01:20:05 PM PDT 24
Finished May 23 01:20:09 PM PDT 24
Peak memory 204268 kb
Host smart-4f243497-4c67-404b-93d9-59c9a5910a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538857835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.538857835
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.122387695
Short name T1015
Test name
Test status
Simulation time 39244629 ps
CPU time 0.76 seconds
Started May 23 01:19:39 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 204008 kb
Host smart-bef06232-0c4c-4a76-a9cc-ca16c416ebfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122387695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.122387695
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.980976630
Short name T1057
Test name
Test status
Simulation time 47909803 ps
CPU time 0.81 seconds
Started May 23 01:20:18 PM PDT 24
Finished May 23 01:20:20 PM PDT 24
Peak memory 204252 kb
Host smart-67b89232-a0dd-4634-8ba9-465410b182bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980976630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.980976630
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1143041
Short name T1001
Test name
Test status
Simulation time 51093614 ps
CPU time 0.82 seconds
Started May 23 01:19:43 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 203928 kb
Host smart-a72921d8-3ba8-4c05-bc9c-f25c0193fccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.1143041
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2630764966
Short name T1069
Test name
Test status
Simulation time 67315867 ps
CPU time 0.74 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:19:57 PM PDT 24
Peak memory 203832 kb
Host smart-39f15dd2-c7f0-4b3a-931d-f1bc720b4dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630764966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2630764966
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3852356549
Short name T983
Test name
Test status
Simulation time 41900050 ps
CPU time 0.72 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 203924 kb
Host smart-d2ff9622-4093-4fe9-b003-0e8888e71969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852356549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3852356549
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1636467172
Short name T1024
Test name
Test status
Simulation time 570920186 ps
CPU time 7.52 seconds
Started May 23 01:19:26 PM PDT 24
Finished May 23 01:19:34 PM PDT 24
Peak memory 207368 kb
Host smart-a3e0bffa-8264-4130-9c0d-4ef9c74c9093
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636467172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1636467172
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.924196107
Short name T1080
Test name
Test status
Simulation time 11330315978 ps
CPU time 13.76 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:44 PM PDT 24
Peak memory 207536 kb
Host smart-e5e441ca-b0df-4f77-b775-acc94772e20d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924196107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.924196107
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3357421319
Short name T1097
Test name
Test status
Simulation time 30595037 ps
CPU time 1.2 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 207184 kb
Host smart-d241245f-4fc0-46ae-aa15-dbc7113fe9ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357421319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3357421319
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3951787517
Short name T1066
Test name
Test status
Simulation time 98726151 ps
CPU time 1.7 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 216736 kb
Host smart-0418fdcd-38c7-4d33-a9da-654c9a689171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951787517 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3951787517
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2601178754
Short name T112
Test name
Test status
Simulation time 70507756 ps
CPU time 1.97 seconds
Started May 23 01:19:28 PM PDT 24
Finished May 23 01:19:31 PM PDT 24
Peak memory 215756 kb
Host smart-0be6fdff-b3a0-4053-afd0-0df9ba1eb555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601178754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
601178754
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1064247981
Short name T1008
Test name
Test status
Simulation time 113413375 ps
CPU time 0.7 seconds
Started May 23 01:19:22 PM PDT 24
Finished May 23 01:19:24 PM PDT 24
Peak memory 203844 kb
Host smart-f1bc3d45-eef8-4fb3-b0bc-d01c05613484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064247981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
064247981
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3784636046
Short name T1059
Test name
Test status
Simulation time 101177532 ps
CPU time 2.14 seconds
Started May 23 01:19:37 PM PDT 24
Finished May 23 01:19:42 PM PDT 24
Peak memory 215684 kb
Host smart-82812483-a888-47f8-a8dd-121cde2ffd60
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784636046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3784636046
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2005727031
Short name T996
Test name
Test status
Simulation time 33213439 ps
CPU time 0.67 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 203740 kb
Host smart-e31df706-c92b-41ca-a88f-8eae4b1c0167
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005727031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2005727031
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3567424464
Short name T136
Test name
Test status
Simulation time 30879273 ps
CPU time 1.65 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:32 PM PDT 24
Peak memory 215732 kb
Host smart-00700a7c-f6ec-4b7e-81a0-dae676a84de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567424464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3567424464
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3664233499
Short name T1079
Test name
Test status
Simulation time 223627776 ps
CPU time 1.66 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 215748 kb
Host smart-66d110a3-8dab-4ba7-b76d-7e0716c7ab7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664233499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
664233499
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4247832806
Short name T1000
Test name
Test status
Simulation time 17667575 ps
CPU time 0.76 seconds
Started May 23 01:20:06 PM PDT 24
Finished May 23 01:20:09 PM PDT 24
Peak memory 204036 kb
Host smart-a70ecb0b-523e-47d5-a0ee-5b60720747e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247832806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4247832806
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3289320313
Short name T1044
Test name
Test status
Simulation time 11359979 ps
CPU time 0.73 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:19:47 PM PDT 24
Peak memory 204244 kb
Host smart-cfb6db47-bd64-4b77-9c7d-bf1ca6c5a9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289320313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3289320313
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.676110
Short name T1031
Test name
Test status
Simulation time 16663818 ps
CPU time 0.75 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:19:49 PM PDT 24
Peak memory 204260 kb
Host smart-4977e6c6-e31b-4110-8c2d-cefd3875bcf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.676110
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1837813520
Short name T1018
Test name
Test status
Simulation time 43633250 ps
CPU time 0.71 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:20:00 PM PDT 24
Peak memory 203832 kb
Host smart-fdede6fb-8017-4be9-b796-4aba01c8d087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837813520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1837813520
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.899833976
Short name T1002
Test name
Test status
Simulation time 14774391 ps
CPU time 0.71 seconds
Started May 23 01:20:12 PM PDT 24
Finished May 23 01:20:14 PM PDT 24
Peak memory 203832 kb
Host smart-2d0a9e7a-34e4-4ca6-b82f-c89102d2f84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899833976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.899833976
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3837797334
Short name T1005
Test name
Test status
Simulation time 14691450 ps
CPU time 0.7 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 203828 kb
Host smart-bd6e0f71-c017-4f15-970e-83780f8cc766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837797334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3837797334
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3725385744
Short name T1055
Test name
Test status
Simulation time 171429908 ps
CPU time 0.72 seconds
Started May 23 01:19:59 PM PDT 24
Finished May 23 01:20:02 PM PDT 24
Peak memory 203884 kb
Host smart-40d380a5-ce9e-4ad9-aa85-f5888136ae70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725385744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3725385744
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3205394321
Short name T1003
Test name
Test status
Simulation time 14821351 ps
CPU time 0.73 seconds
Started May 23 01:19:49 PM PDT 24
Finished May 23 01:19:57 PM PDT 24
Peak memory 204008 kb
Host smart-966539b5-13af-405e-8945-d4fe470d1535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205394321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3205394321
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.146176151
Short name T1068
Test name
Test status
Simulation time 26135177 ps
CPU time 0.78 seconds
Started May 23 01:19:46 PM PDT 24
Finished May 23 01:19:53 PM PDT 24
Peak memory 204192 kb
Host smart-adba8be8-ddcd-47d6-ad96-b0e51b80b45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146176151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.146176151
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3807093187
Short name T995
Test name
Test status
Simulation time 50184405 ps
CPU time 0.8 seconds
Started May 23 01:20:01 PM PDT 24
Finished May 23 01:20:05 PM PDT 24
Peak memory 204260 kb
Host smart-1a73694f-907e-41e5-b03c-f785c6a0a7f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807093187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3807093187
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2305506715
Short name T117
Test name
Test status
Simulation time 4387926629 ps
CPU time 22.99 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:20:22 PM PDT 24
Peak memory 215912 kb
Host smart-8427390b-cebd-4ffe-a98d-2bb7bce463c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305506715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2305506715
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2301204637
Short name T121
Test name
Test status
Simulation time 2853146915 ps
CPU time 38.74 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:20:15 PM PDT 24
Peak memory 207680 kb
Host smart-7f02c3a2-72ed-4a4a-9644-1a251b1be357
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301204637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2301204637
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2014056714
Short name T75
Test name
Test status
Simulation time 141381406 ps
CPU time 1.18 seconds
Started May 23 01:19:28 PM PDT 24
Finished May 23 01:19:30 PM PDT 24
Peak memory 207544 kb
Host smart-06798e1c-94df-4545-9c54-9459fe139a6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014056714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2014056714
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.341636261
Short name T104
Test name
Test status
Simulation time 188056430 ps
CPU time 3.28 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 218640 kb
Host smart-ae2c23e1-84ae-4a0d-bb6f-e1765274367c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341636261 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.341636261
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3683375152
Short name T120
Test name
Test status
Simulation time 29807008 ps
CPU time 1.87 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:32 PM PDT 24
Peak memory 207500 kb
Host smart-b4b64f09-e5d2-4949-85dd-f2c35202d61a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683375152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
683375152
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2207542321
Short name T1093
Test name
Test status
Simulation time 13334217 ps
CPU time 0.74 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:31 PM PDT 24
Peak memory 204268 kb
Host smart-24c396e2-e732-4b7b-9f9b-a83f77004e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207542321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
207542321
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4009738266
Short name T1098
Test name
Test status
Simulation time 57793395 ps
CPU time 1.75 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 215740 kb
Host smart-afbf6eb3-00ac-4d0c-bace-b462fa570f5c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009738266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4009738266
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.596105287
Short name T999
Test name
Test status
Simulation time 20986292 ps
CPU time 0.68 seconds
Started May 23 01:19:35 PM PDT 24
Finished May 23 01:19:39 PM PDT 24
Peak memory 203780 kb
Host smart-732d986f-4600-49c5-851c-e35ec2ba73fe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596105287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.596105287
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3063637981
Short name T143
Test name
Test status
Simulation time 74158161 ps
CPU time 1.75 seconds
Started May 23 01:19:35 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 207632 kb
Host smart-26eede7c-69cd-409b-a3c2-55ad5ee0df2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063637981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3063637981
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.968462347
Short name T1082
Test name
Test status
Simulation time 693205997 ps
CPU time 2.55 seconds
Started May 23 01:19:26 PM PDT 24
Finished May 23 01:19:30 PM PDT 24
Peak memory 215872 kb
Host smart-18733552-7a4b-4fc7-bb14-b040c7329f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968462347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.968462347
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1255626056
Short name T1036
Test name
Test status
Simulation time 3554632393 ps
CPU time 15.44 seconds
Started May 23 01:19:28 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 224092 kb
Host smart-cbf70130-b20a-426f-9ecc-1d0d74547937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255626056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1255626056
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.41046590
Short name T1037
Test name
Test status
Simulation time 67502104 ps
CPU time 0.69 seconds
Started May 23 01:19:55 PM PDT 24
Finished May 23 01:19:58 PM PDT 24
Peak memory 204260 kb
Host smart-828e79a7-bf65-4d0f-a375-16c4d5d52c2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.41046590
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2145211372
Short name T1045
Test name
Test status
Simulation time 77095933 ps
CPU time 0.75 seconds
Started May 23 01:19:50 PM PDT 24
Finished May 23 01:19:52 PM PDT 24
Peak memory 204152 kb
Host smart-ad8bee1c-3e7f-4421-b8b8-d093f59c5282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145211372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2145211372
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3212483609
Short name T1053
Test name
Test status
Simulation time 11065586 ps
CPU time 0.71 seconds
Started May 23 01:19:52 PM PDT 24
Finished May 23 01:19:54 PM PDT 24
Peak memory 204000 kb
Host smart-827bf8a5-ba36-45ed-b23c-d0c16123121d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212483609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3212483609
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1766296908
Short name T1050
Test name
Test status
Simulation time 53897903 ps
CPU time 0.68 seconds
Started May 23 01:19:54 PM PDT 24
Finished May 23 01:19:57 PM PDT 24
Peak memory 203928 kb
Host smart-23ef2db1-ed76-4246-884f-81e5ddd85956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766296908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1766296908
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3400608787
Short name T1095
Test name
Test status
Simulation time 12526715 ps
CPU time 0.75 seconds
Started May 23 01:19:58 PM PDT 24
Finished May 23 01:20:01 PM PDT 24
Peak memory 203988 kb
Host smart-5c2344ad-da05-47e8-baa4-78e9f49cef42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400608787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3400608787
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2106253053
Short name T1032
Test name
Test status
Simulation time 15748916 ps
CPU time 0.8 seconds
Started May 23 01:19:57 PM PDT 24
Finished May 23 01:20:00 PM PDT 24
Peak memory 203992 kb
Host smart-2409d5b8-800e-462d-9a06-70cc94f0b271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106253053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2106253053
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.728677915
Short name T1094
Test name
Test status
Simulation time 39234089 ps
CPU time 0.73 seconds
Started May 23 01:20:09 PM PDT 24
Finished May 23 01:20:12 PM PDT 24
Peak memory 204172 kb
Host smart-1de5fc8f-ea86-4c7c-8f24-a2fc32733503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728677915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.728677915
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3993779629
Short name T1043
Test name
Test status
Simulation time 15756441 ps
CPU time 0.71 seconds
Started May 23 01:20:00 PM PDT 24
Finished May 23 01:20:04 PM PDT 24
Peak memory 203844 kb
Host smart-d92f6b14-2645-4ea8-a81b-de9faf9667df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993779629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3993779629
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.357853860
Short name T1081
Test name
Test status
Simulation time 51811384 ps
CPU time 0.71 seconds
Started May 23 01:19:48 PM PDT 24
Finished May 23 01:19:50 PM PDT 24
Peak memory 203924 kb
Host smart-c60b0d9d-1720-4de4-b3aa-88588aa47a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357853860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.357853860
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2573184123
Short name T988
Test name
Test status
Simulation time 15876153 ps
CPU time 0.7 seconds
Started May 23 01:20:07 PM PDT 24
Finished May 23 01:20:10 PM PDT 24
Peak memory 203816 kb
Host smart-0f9b2998-9343-4112-a714-c20033b2ab04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573184123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2573184123
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2226387300
Short name T85
Test name
Test status
Simulation time 224714739 ps
CPU time 1.78 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:33 PM PDT 24
Peak memory 215872 kb
Host smart-c07b8295-d562-417e-a210-178c0e64d90b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226387300 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2226387300
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.634244072
Short name T986
Test name
Test status
Simulation time 58243041 ps
CPU time 1.75 seconds
Started May 23 01:19:22 PM PDT 24
Finished May 23 01:19:25 PM PDT 24
Peak memory 215696 kb
Host smart-bfd60482-def4-4ee4-9ff0-7341995f8002
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634244072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.634244072
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3384941826
Short name T992
Test name
Test status
Simulation time 59224554 ps
CPU time 0.71 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:31 PM PDT 24
Peak memory 203972 kb
Host smart-5ebc1f90-726e-4feb-885c-b84b5bc2caec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384941826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
384941826
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2002238592
Short name T1041
Test name
Test status
Simulation time 682818540 ps
CPU time 4.14 seconds
Started May 23 01:19:25 PM PDT 24
Finished May 23 01:19:30 PM PDT 24
Peak memory 215808 kb
Host smart-324f1046-954b-400d-b819-d7694e8f1939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002238592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2002238592
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2992713901
Short name T102
Test name
Test status
Simulation time 159986639 ps
CPU time 2.74 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:38 PM PDT 24
Peak memory 215868 kb
Host smart-b3d1c77f-7f20-4b60-8ea2-a77588ca191a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992713901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
992713901
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2872124150
Short name T147
Test name
Test status
Simulation time 692539276 ps
CPU time 15.63 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:52 PM PDT 24
Peak memory 215904 kb
Host smart-b813bec3-d5c7-401d-9187-9a1dbdde8f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872124150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2872124150
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4044405587
Short name T1028
Test name
Test status
Simulation time 70521405 ps
CPU time 2.59 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:34 PM PDT 24
Peak memory 218308 kb
Host smart-0b9dc0c1-09cd-4f8f-97e5-d85abff22196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044405587 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4044405587
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2246461479
Short name T111
Test name
Test status
Simulation time 64516299 ps
CPU time 1.39 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:19:50 PM PDT 24
Peak memory 207316 kb
Host smart-5ec08e24-ff8e-4d6d-af15-c95a74182afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246461479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
246461479
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1651673711
Short name T1085
Test name
Test status
Simulation time 14675308 ps
CPU time 0.75 seconds
Started May 23 01:19:32 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 204228 kb
Host smart-8018a227-fc0f-4537-a12e-7dcb9ad9210d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651673711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
651673711
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1176548211
Short name T994
Test name
Test status
Simulation time 631932367 ps
CPU time 4.14 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:36 PM PDT 24
Peak memory 215796 kb
Host smart-db211b77-14e1-4cee-95bd-e73550534131
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176548211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1176548211
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2952345042
Short name T100
Test name
Test status
Simulation time 109234368 ps
CPU time 1.77 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:34 PM PDT 24
Peak memory 215932 kb
Host smart-b1424288-eba6-4c07-a05f-1085df62546e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952345042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
952345042
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2309073552
Short name T264
Test name
Test status
Simulation time 677088667 ps
CPU time 15.84 seconds
Started May 23 01:19:38 PM PDT 24
Finished May 23 01:19:56 PM PDT 24
Peak memory 215784 kb
Host smart-72eed694-be2a-4706-905f-e35727f63293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309073552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2309073552
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.223461346
Short name T1092
Test name
Test status
Simulation time 72564694 ps
CPU time 1.37 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:32 PM PDT 24
Peak memory 215684 kb
Host smart-9fb9b447-e430-4fac-90c9-5635a4fcfc63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223461346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.223461346
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1874853429
Short name T1025
Test name
Test status
Simulation time 16959786 ps
CPU time 0.74 seconds
Started May 23 01:19:29 PM PDT 24
Finished May 23 01:19:31 PM PDT 24
Peak memory 203928 kb
Host smart-f4c562b2-529d-4078-823e-4ec836f48d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874853429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
874853429
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2779656435
Short name T1021
Test name
Test status
Simulation time 167305991 ps
CPU time 4.26 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:37 PM PDT 24
Peak memory 215716 kb
Host smart-ac86790a-bb22-43c8-b6c7-c88650b2f156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779656435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2779656435
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2851638654
Short name T1063
Test name
Test status
Simulation time 88288502 ps
CPU time 3 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 216896 kb
Host smart-15109e42-0f88-4d5e-add6-01ab8d6f216a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851638654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
851638654
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3814602984
Short name T265
Test name
Test status
Simulation time 2791162383 ps
CPU time 15.67 seconds
Started May 23 01:19:31 PM PDT 24
Finished May 23 01:19:49 PM PDT 24
Peak memory 216028 kb
Host smart-faec96b4-0c81-40c7-88d2-f79cb8f9271e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814602984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3814602984
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3447865140
Short name T1073
Test name
Test status
Simulation time 811746265 ps
CPU time 1.74 seconds
Started May 23 01:19:37 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 215776 kb
Host smart-969744c0-f40e-40c8-a67f-e9d56e03e732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447865140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3447865140
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2891867261
Short name T1071
Test name
Test status
Simulation time 297422306 ps
CPU time 2.56 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:19:49 PM PDT 24
Peak memory 220724 kb
Host smart-4232815f-91b9-4261-9ab7-3849d8275517
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891867261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
891867261
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.145541567
Short name T1058
Test name
Test status
Simulation time 19566798 ps
CPU time 0.69 seconds
Started May 23 01:19:37 PM PDT 24
Finished May 23 01:19:41 PM PDT 24
Peak memory 203844 kb
Host smart-ab44a746-b08b-4d1a-a994-d9065d85964e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145541567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.145541567
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4004883443
Short name T135
Test name
Test status
Simulation time 84824184 ps
CPU time 2.89 seconds
Started May 23 01:19:30 PM PDT 24
Finished May 23 01:19:35 PM PDT 24
Peak memory 215740 kb
Host smart-47675e60-4da7-4c28-9a6f-144962a97c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004883443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4004883443
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2560308548
Short name T1035
Test name
Test status
Simulation time 127763767 ps
CPU time 2.17 seconds
Started May 23 01:19:47 PM PDT 24
Finished May 23 01:19:50 PM PDT 24
Peak memory 215972 kb
Host smart-0df1f731-dc7e-462d-96ac-b49edefa2db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560308548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
560308548
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.202603336
Short name T1072
Test name
Test status
Simulation time 181879713 ps
CPU time 6.95 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 215800 kb
Host smart-74921fd2-1531-4528-8dee-e1bb7740aba7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202603336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.202603336
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3479176128
Short name T146
Test name
Test status
Simulation time 93944429 ps
CPU time 2.37 seconds
Started May 23 01:19:34 PM PDT 24
Finished May 23 01:19:40 PM PDT 24
Peak memory 216736 kb
Host smart-cf5b638e-79c2-48d9-8137-72b16852228d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479176128 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3479176128
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2941500287
Short name T1048
Test name
Test status
Simulation time 478066075 ps
CPU time 2.51 seconds
Started May 23 01:19:38 PM PDT 24
Finished May 23 01:19:43 PM PDT 24
Peak memory 215732 kb
Host smart-fcda9505-11ae-4c2d-b1a3-d943a819ad80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941500287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
941500287
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1532188258
Short name T1099
Test name
Test status
Simulation time 30430586 ps
CPU time 0.75 seconds
Started May 23 01:19:46 PM PDT 24
Finished May 23 01:19:48 PM PDT 24
Peak memory 204096 kb
Host smart-1fafbaa2-877f-4922-8ce2-962125379f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532188258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
532188258
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1982211920
Short name T1029
Test name
Test status
Simulation time 385424763 ps
CPU time 4.19 seconds
Started May 23 01:19:45 PM PDT 24
Finished May 23 01:19:50 PM PDT 24
Peak memory 215756 kb
Host smart-60c6fa82-9382-46dd-bb0c-c307665f818d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982211920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1982211920
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2585220410
Short name T1030
Test name
Test status
Simulation time 180315628 ps
CPU time 4.41 seconds
Started May 23 01:19:38 PM PDT 24
Finished May 23 01:19:45 PM PDT 24
Peak memory 216900 kb
Host smart-a1dee90b-57d8-4776-ad29-4556a48620a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585220410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
585220410
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2180637717
Short name T1089
Test name
Test status
Simulation time 1422918029 ps
CPU time 8.31 seconds
Started May 23 01:19:33 PM PDT 24
Finished May 23 01:19:44 PM PDT 24
Peak memory 215740 kb
Host smart-6763ccd7-790e-4f50-9994-d2f6579978c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180637717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2180637717
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1642650644
Short name T573
Test name
Test status
Simulation time 12016623 ps
CPU time 0.77 seconds
Started May 23 01:23:31 PM PDT 24
Finished May 23 01:23:33 PM PDT 24
Peak memory 204780 kb
Host smart-1da35a45-3147-47d6-b88f-7dd86863b4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642650644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
642650644
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2757201117
Short name T611
Test name
Test status
Simulation time 4825284905 ps
CPU time 14.31 seconds
Started May 23 01:23:29 PM PDT 24
Finished May 23 01:23:44 PM PDT 24
Peak memory 221328 kb
Host smart-fd52731b-197b-4ffb-a41c-7a92558b0035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757201117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2757201117
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3261231022
Short name T871
Test name
Test status
Simulation time 13034207 ps
CPU time 0.81 seconds
Started May 23 01:23:30 PM PDT 24
Finished May 23 01:23:32 PM PDT 24
Peak memory 206472 kb
Host smart-1d9cb572-ae6a-4275-bbb0-cc595cdc5e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261231022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3261231022
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.185219605
Short name T228
Test name
Test status
Simulation time 65555107642 ps
CPU time 444.49 seconds
Started May 23 01:23:36 PM PDT 24
Finished May 23 01:31:02 PM PDT 24
Peak memory 253064 kb
Host smart-3d41b7ba-585b-463e-b1bd-eb742fb6aefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185219605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.185219605
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1896865268
Short name T219
Test name
Test status
Simulation time 28873966495 ps
CPU time 275.33 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:28:12 PM PDT 24
Peak memory 249684 kb
Host smart-4cfd3569-8a4c-440b-a140-a1ab2ea9aad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896865268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1896865268
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3137643789
Short name T180
Test name
Test status
Simulation time 30007649780 ps
CPU time 118.96 seconds
Started May 23 01:23:32 PM PDT 24
Finished May 23 01:25:32 PM PDT 24
Peak memory 240848 kb
Host smart-7ecc614b-d56f-4f28-a372-a967033d2515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137643789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3137643789
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3722625804
Short name T863
Test name
Test status
Simulation time 77133677 ps
CPU time 2.29 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:38 PM PDT 24
Peak memory 224520 kb
Host smart-497ef445-8af0-45ac-ad4b-c6d97cb2e71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722625804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3722625804
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4222869724
Short name T109
Test name
Test status
Simulation time 280536472 ps
CPU time 3.43 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:39 PM PDT 24
Peak memory 233748 kb
Host smart-9580dfac-09df-457a-afab-0e10321f381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222869724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4222869724
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1570488949
Short name T885
Test name
Test status
Simulation time 638275885 ps
CPU time 9.33 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:23:46 PM PDT 24
Peak memory 217700 kb
Host smart-c30381b6-13c5-483f-8184-9ec72f842f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570488949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1570488949
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1137461872
Short name T27
Test name
Test status
Simulation time 91069337 ps
CPU time 1.14 seconds
Started May 23 01:23:36 PM PDT 24
Finished May 23 01:23:39 PM PDT 24
Peak memory 216732 kb
Host smart-f8262c7d-d53d-4414-9fcc-b3f5a7bc5b01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137461872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1137461872
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1237828783
Short name T819
Test name
Test status
Simulation time 28534627475 ps
CPU time 18.01 seconds
Started May 23 01:23:32 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 235092 kb
Host smart-be9067ed-5df0-4d28-ab69-4ad58d8f4697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237828783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1237828783
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1923290077
Short name T603
Test name
Test status
Simulation time 51135320473 ps
CPU time 35.95 seconds
Started May 23 01:23:36 PM PDT 24
Finished May 23 01:24:14 PM PDT 24
Peak memory 229832 kb
Host smart-4e255428-4ede-435f-ae0e-246dcca60fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923290077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1923290077
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2488214575
Short name T926
Test name
Test status
Simulation time 3959462141 ps
CPU time 8.43 seconds
Started May 23 01:23:30 PM PDT 24
Finished May 23 01:23:40 PM PDT 24
Peak memory 220020 kb
Host smart-52d4067c-0cf7-4257-95c5-cbca3b4c1640
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2488214575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2488214575
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3532029766
Short name T63
Test name
Test status
Simulation time 427801994 ps
CPU time 1.17 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 235172 kb
Host smart-a9206206-85b4-4cf3-bbc6-8401677ae75f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532029766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3532029766
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.759297636
Short name T154
Test name
Test status
Simulation time 6322227124 ps
CPU time 85.8 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 256940 kb
Host smart-a06c2da9-6761-4e17-8501-d02f5508c394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759297636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.759297636
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.822252753
Short name T920
Test name
Test status
Simulation time 3794616974 ps
CPU time 6.4 seconds
Started May 23 01:23:33 PM PDT 24
Finished May 23 01:23:41 PM PDT 24
Peak memory 216568 kb
Host smart-726825dc-d67d-4f03-b8a5-9fc3ef71f147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822252753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.822252753
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1922762657
Short name T470
Test name
Test status
Simulation time 456027417 ps
CPU time 1.7 seconds
Started May 23 01:23:28 PM PDT 24
Finished May 23 01:23:31 PM PDT 24
Peak memory 207972 kb
Host smart-b56c638f-0f43-41bc-9bbc-521354b31dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922762657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1922762657
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.386058428
Short name T805
Test name
Test status
Simulation time 861874534 ps
CPU time 9 seconds
Started May 23 01:23:33 PM PDT 24
Finished May 23 01:23:43 PM PDT 24
Peak memory 217456 kb
Host smart-f66db3e8-2146-47d0-aea5-798be05f8e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386058428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.386058428
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2248203172
Short name T792
Test name
Test status
Simulation time 96022528 ps
CPU time 0.76 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:36 PM PDT 24
Peak memory 205748 kb
Host smart-c8e727e5-79d1-4400-87a9-f53ce1c12d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248203172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2248203172
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.654008808
Short name T283
Test name
Test status
Simulation time 3240482794 ps
CPU time 13.41 seconds
Started May 23 01:23:31 PM PDT 24
Finished May 23 01:23:45 PM PDT 24
Peak memory 236956 kb
Host smart-32b3103c-8865-45b3-846b-d4341180acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654008808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.654008808
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1541075999
Short name T896
Test name
Test status
Simulation time 1165507882 ps
CPU time 6.2 seconds
Started May 23 01:23:31 PM PDT 24
Finished May 23 01:23:39 PM PDT 24
Peak memory 233700 kb
Host smart-7a02fd50-d448-41df-827f-256b162803d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541075999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1541075999
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.600837368
Short name T566
Test name
Test status
Simulation time 18788380 ps
CPU time 0.82 seconds
Started May 23 01:23:32 PM PDT 24
Finished May 23 01:23:34 PM PDT 24
Peak memory 206716 kb
Host smart-67fe96b5-e078-444b-8159-690d41d8e847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600837368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.600837368
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1615820741
Short name T834
Test name
Test status
Simulation time 1955572045 ps
CPU time 35.83 seconds
Started May 23 01:23:32 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 237944 kb
Host smart-075cc3a2-13bd-43d9-9071-82f8677031ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615820741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1615820741
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2458031465
Short name T280
Test name
Test status
Simulation time 97636532840 ps
CPU time 198.72 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:26:55 PM PDT 24
Peak memory 265712 kb
Host smart-4eb7800b-03cc-4427-b027-2f790320c5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458031465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2458031465
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2808603917
Short name T680
Test name
Test status
Simulation time 249964648 ps
CPU time 6.18 seconds
Started May 23 01:23:32 PM PDT 24
Finished May 23 01:23:40 PM PDT 24
Peak memory 224560 kb
Host smart-2c3b34af-2fb7-4d00-9a7e-55672b81c5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808603917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2808603917
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2485835954
Short name T190
Test name
Test status
Simulation time 431096477 ps
CPU time 3.83 seconds
Started May 23 01:23:33 PM PDT 24
Finished May 23 01:23:39 PM PDT 24
Peak memory 220528 kb
Host smart-2e72ba41-74f7-4fb1-b5d0-758cd8f464f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485835954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2485835954
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1138873838
Short name T701
Test name
Test status
Simulation time 1503608563 ps
CPU time 7.28 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:23:44 PM PDT 24
Peak memory 233876 kb
Host smart-242ebd9f-e132-4adb-90e2-90cc27c814fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138873838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1138873838
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2431600386
Short name T6
Test name
Test status
Simulation time 18888395 ps
CPU time 1.06 seconds
Started May 23 01:23:30 PM PDT 24
Finished May 23 01:23:32 PM PDT 24
Peak memory 216692 kb
Host smart-1180ea65-d33f-4542-8fb7-e9f23958e94c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431600386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2431600386
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2661854864
Short name T877
Test name
Test status
Simulation time 693408336 ps
CPU time 5.54 seconds
Started May 23 01:23:31 PM PDT 24
Finished May 23 01:23:38 PM PDT 24
Peak memory 233212 kb
Host smart-643c3a45-8d3e-456f-b3df-07e3e8313258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661854864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2661854864
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2226628871
Short name T56
Test name
Test status
Simulation time 9689706484 ps
CPU time 14.98 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:50 PM PDT 24
Peak memory 219084 kb
Host smart-0374cd25-4258-4a99-9ac0-dc1eb08db1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226628871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2226628871
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.974622613
Short name T774
Test name
Test status
Simulation time 689176991 ps
CPU time 4.74 seconds
Started May 23 01:23:32 PM PDT 24
Finished May 23 01:23:38 PM PDT 24
Peak memory 222420 kb
Host smart-0376ddc1-4640-47d7-a278-0cb720c51713
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974622613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.974622613
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3199316714
Short name T64
Test name
Test status
Simulation time 504985930 ps
CPU time 1.25 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 235084 kb
Host smart-f3e835e3-ac07-4b1c-a3bf-a2ef384be688
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199316714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3199316714
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.884533902
Short name T744
Test name
Test status
Simulation time 19805244 ps
CPU time 0.8 seconds
Started May 23 01:23:36 PM PDT 24
Finished May 23 01:23:39 PM PDT 24
Peak memory 205652 kb
Host smart-0916b4d0-7135-46ee-a43e-15fa85ecf5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884533902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.884533902
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4131853517
Short name T809
Test name
Test status
Simulation time 5339073435 ps
CPU time 12.78 seconds
Started May 23 01:23:31 PM PDT 24
Finished May 23 01:23:45 PM PDT 24
Peak memory 216592 kb
Host smart-0305ec70-93f4-45ff-b5d0-8b945f966df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131853517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4131853517
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2445882609
Short name T506
Test name
Test status
Simulation time 71629000 ps
CPU time 1.21 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 216304 kb
Host smart-1f0cf29d-0800-4ea0-9436-99d31c28eed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445882609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2445882609
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2389198739
Short name T358
Test name
Test status
Simulation time 86859456 ps
CPU time 0.85 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:36 PM PDT 24
Peak memory 205764 kb
Host smart-2b190f5a-77ce-43ea-817d-cf7f8b066348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389198739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2389198739
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2343525378
Short name T186
Test name
Test status
Simulation time 52183638269 ps
CPU time 36.29 seconds
Started May 23 01:23:33 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 239580 kb
Host smart-946115fb-6b77-48fe-bada-7169dba63fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343525378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2343525378
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.850821067
Short name T757
Test name
Test status
Simulation time 12676291 ps
CPU time 0.77 seconds
Started May 23 01:24:14 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 204772 kb
Host smart-2e780d26-83a0-47c4-a9c8-8de960c937ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850821067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.850821067
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2132093393
Short name T196
Test name
Test status
Simulation time 150655770 ps
CPU time 3.02 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:24:12 PM PDT 24
Peak memory 218844 kb
Host smart-8994f35f-854a-4e78-b2bb-73ff9a11c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132093393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2132093393
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2669789958
Short name T655
Test name
Test status
Simulation time 36154990 ps
CPU time 0.78 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 205444 kb
Host smart-008245f3-ffb3-4f59-a539-b47c9dd4ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669789958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2669789958
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1322546214
Short name T921
Test name
Test status
Simulation time 12038945576 ps
CPU time 116.29 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:26:02 PM PDT 24
Peak memory 249168 kb
Host smart-ec4f758a-3481-4db5-9875-c4dd901cc9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322546214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1322546214
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2530601130
Short name T959
Test name
Test status
Simulation time 38375198865 ps
CPU time 170.55 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:27:00 PM PDT 24
Peak memory 241220 kb
Host smart-391527f4-5bc0-462e-bb5f-c79e0f8adc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530601130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2530601130
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.389994394
Short name T634
Test name
Test status
Simulation time 25514712911 ps
CPU time 235.94 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:28:21 PM PDT 24
Peak memory 250872 kb
Host smart-68aefb1f-ee0b-4326-8731-595f770d52ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389994394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.389994394
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1531536101
Short name T699
Test name
Test status
Simulation time 663232972 ps
CPU time 4.31 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:24:14 PM PDT 24
Peak memory 236856 kb
Host smart-592982ee-8ccc-4aac-8486-ff6f203ba383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531536101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1531536101
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3701899904
Short name T179
Test name
Test status
Simulation time 265069819 ps
CPU time 2.9 seconds
Started May 23 01:24:10 PM PDT 24
Finished May 23 01:24:15 PM PDT 24
Peak memory 232748 kb
Host smart-7ac5250f-b2e4-4765-bbbe-e1183204d18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701899904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3701899904
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2719067443
Short name T727
Test name
Test status
Simulation time 1817949674 ps
CPU time 18.64 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 240620 kb
Host smart-72db5c6d-da02-414e-8e3d-f4bc9e963ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719067443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2719067443
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.503463060
Short name T584
Test name
Test status
Simulation time 57784041 ps
CPU time 1.16 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:04 PM PDT 24
Peak memory 216724 kb
Host smart-47069888-17e5-49c6-a4f9-4f234fec8af5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503463060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.503463060
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.481319288
Short name T822
Test name
Test status
Simulation time 823207158 ps
CPU time 6.04 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 224464 kb
Host smart-9a5b1d82-4e6e-4e49-9295-cde8a6c62968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481319288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.481319288
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4121494772
Short name T541
Test name
Test status
Simulation time 442581181 ps
CPU time 2.37 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 218456 kb
Host smart-178ecbcb-5c63-4fc6-8b46-801f195a1ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121494772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4121494772
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.356745605
Short name T693
Test name
Test status
Simulation time 63989183 ps
CPU time 3.59 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:30 PM PDT 24
Peak memory 220664 kb
Host smart-cd7bac3f-02d4-4685-9b08-82284fc44bee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=356745605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.356745605
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.520872977
Short name T448
Test name
Test status
Simulation time 6075280573 ps
CPU time 39.98 seconds
Started May 23 01:24:12 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 216464 kb
Host smart-b3b761e3-2e43-4555-959f-19d6dc939899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520872977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.520872977
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2530339591
Short name T736
Test name
Test status
Simulation time 9525671454 ps
CPU time 13.63 seconds
Started May 23 01:24:10 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 216500 kb
Host smart-330a914b-aa1e-480f-ac3b-c5f2c5373769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530339591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2530339591
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1602446660
Short name T53
Test name
Test status
Simulation time 20466890 ps
CPU time 0.84 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 205868 kb
Host smart-d3d2faaf-6122-4f96-9051-0bd78143693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602446660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1602446660
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2576944262
Short name T364
Test name
Test status
Simulation time 75251277 ps
CPU time 0.76 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 205860 kb
Host smart-a2af5201-2448-4bbc-83c6-3d02bcab7dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576944262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2576944262
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.155249727
Short name T368
Test name
Test status
Simulation time 252724143 ps
CPU time 5.87 seconds
Started May 23 01:24:08 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 234184 kb
Host smart-ef9f38eb-ebeb-4b5a-b64b-e25be9a49007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155249727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.155249727
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.148952965
Short name T351
Test name
Test status
Simulation time 14866020 ps
CPU time 0.73 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:00 PM PDT 24
Peak memory 205404 kb
Host smart-3896a671-b557-42a9-b5a2-98e2c962928f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148952965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.148952965
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4287603768
Short name T450
Test name
Test status
Simulation time 20497780 ps
CPU time 0.78 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:24 PM PDT 24
Peak memory 206476 kb
Host smart-a5907a90-cc12-4fb2-bce7-763890702785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287603768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4287603768
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.531528758
Short name T856
Test name
Test status
Simulation time 16366614496 ps
CPU time 31.71 seconds
Started May 23 01:24:06 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 232824 kb
Host smart-8df00897-e00d-457e-901e-f6b6b45e59ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531528758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.531528758
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.415209467
Short name T859
Test name
Test status
Simulation time 58301223066 ps
CPU time 158.1 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:26:40 PM PDT 24
Peak memory 249376 kb
Host smart-f278e6dc-24a5-450f-812c-3b4c4686dc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415209467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.415209467
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2737491539
Short name T71
Test name
Test status
Simulation time 8899566279 ps
CPU time 50.28 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:53 PM PDT 24
Peak memory 257300 kb
Host smart-c600460a-9928-464b-ba60-ae82483b1a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737491539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2737491539
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4155897259
Short name T929
Test name
Test status
Simulation time 172658032 ps
CPU time 3.67 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 217564 kb
Host smart-cf42bbc0-64b8-4b54-89d2-d31422240c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155897259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4155897259
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3317474873
Short name T901
Test name
Test status
Simulation time 19397026309 ps
CPU time 46.95 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:25:00 PM PDT 24
Peak memory 228900 kb
Host smart-29c0e761-fd3a-4207-831d-2b37b147d088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317474873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3317474873
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3770084725
Short name T668
Test name
Test status
Simulation time 50775295 ps
CPU time 1.03 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 216676 kb
Host smart-2dbd0c40-25a9-430b-a86e-2b4728652067
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770084725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3770084725
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.4280526604
Short name T229
Test name
Test status
Simulation time 2069654647 ps
CPU time 6.01 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:19 PM PDT 24
Peak memory 236084 kb
Host smart-3b7011bc-b24b-48d1-b1e4-cd8c932d7f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280526604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.4280526604
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1017344038
Short name T832
Test name
Test status
Simulation time 1318580547 ps
CPU time 8.41 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:21 PM PDT 24
Peak memory 216644 kb
Host smart-0c249125-2e37-4173-9905-93878060572f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017344038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1017344038
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2263688689
Short name T862
Test name
Test status
Simulation time 2113153947 ps
CPU time 7.66 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 218824 kb
Host smart-a99adfed-7ed6-47f3-a57d-20b1bc93ea3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2263688689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2263688689
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4079180760
Short name T812
Test name
Test status
Simulation time 5776660746 ps
CPU time 29.28 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 216428 kb
Host smart-29d610cf-c919-4f00-89ef-619be84085a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079180760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4079180760
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.838022594
Short name T76
Test name
Test status
Simulation time 281427187 ps
CPU time 1.87 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 216068 kb
Host smart-5b54e8b2-e107-4bfe-9558-95c4126ac300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838022594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.838022594
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1904089438
Short name T373
Test name
Test status
Simulation time 150078325 ps
CPU time 1.33 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 216428 kb
Host smart-8b89955e-972a-4827-bdea-dc87dfcc2b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904089438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1904089438
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.465417026
Short name T81
Test name
Test status
Simulation time 60913668 ps
CPU time 0.78 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:14 PM PDT 24
Peak memory 205752 kb
Host smart-efaa4059-f108-4628-8528-000205f4ddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465417026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.465417026
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1082058262
Short name T486
Test name
Test status
Simulation time 15201867673 ps
CPU time 19.48 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 222444 kb
Host smart-9ad71919-d1f9-4741-ab83-5d479cafe07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082058262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1082058262
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3797791790
Short name T456
Test name
Test status
Simulation time 22393405 ps
CPU time 0.74 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 205380 kb
Host smart-4927bc30-551f-47fb-9293-386902f67fba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797791790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3797791790
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2750770200
Short name T850
Test name
Test status
Simulation time 1910968180 ps
CPU time 6.16 seconds
Started May 23 01:24:12 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 233268 kb
Host smart-1721d488-0dfa-466f-b07b-bf7fe1e06f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750770200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2750770200
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1006310076
Short name T646
Test name
Test status
Simulation time 49445155 ps
CPU time 0.75 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 205752 kb
Host smart-6da43098-60f3-4b21-957a-6aa4cda2b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006310076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1006310076
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2191734378
Short name T898
Test name
Test status
Simulation time 7659390901 ps
CPU time 46.17 seconds
Started May 23 01:24:05 PM PDT 24
Finished May 23 01:24:53 PM PDT 24
Peak memory 249244 kb
Host smart-387f5b6f-0c2f-47ac-a198-68f7ca57317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191734378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2191734378
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4196084332
Short name T939
Test name
Test status
Simulation time 3212303454 ps
CPU time 14.1 seconds
Started May 23 01:24:05 PM PDT 24
Finished May 23 01:24:21 PM PDT 24
Peak memory 241056 kb
Host smart-2ae2a4a0-47ed-401c-a889-72db7cab2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196084332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4196084332
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1165518776
Short name T748
Test name
Test status
Simulation time 463829379 ps
CPU time 5.03 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 240416 kb
Host smart-f5fa62d8-de6c-4192-b8b0-8e3bd6025413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165518776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1165518776
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.215098118
Short name T676
Test name
Test status
Simulation time 1556560833 ps
CPU time 7.54 seconds
Started May 23 01:24:13 PM PDT 24
Finished May 23 01:24:22 PM PDT 24
Peak memory 219484 kb
Host smart-878c14a7-c476-4cf5-bd26-87bfd5d8f50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215098118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.215098118
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.478644487
Short name T572
Test name
Test status
Simulation time 280020736 ps
CPU time 5.98 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:11 PM PDT 24
Peak memory 233788 kb
Host smart-0c5404c0-ab9a-4f01-afa6-0fb4762cdb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478644487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.478644487
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.4282957526
Short name T730
Test name
Test status
Simulation time 21035873 ps
CPU time 1.11 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:03 PM PDT 24
Peak memory 216700 kb
Host smart-0e166ff5-3f7d-4708-b10d-bdab2adb15ed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282957526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.4282957526
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.401698509
Short name T672
Test name
Test status
Simulation time 24435710773 ps
CPU time 31.59 seconds
Started May 23 01:24:05 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 235396 kb
Host smart-6b2f4fcb-2c5d-400c-83c1-a4a7a7a40a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401698509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.401698509
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4039465163
Short name T709
Test name
Test status
Simulation time 3836031530 ps
CPU time 7.45 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 224612 kb
Host smart-e40f0369-eb74-4e6c-ac35-a2a58583b018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039465163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4039465163
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3143726182
Short name T354
Test name
Test status
Simulation time 4177233410 ps
CPU time 6.3 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 223108 kb
Host smart-1588b7e4-b05b-4432-9840-34b06f0c2af1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3143726182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3143726182
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.486134465
Short name T412
Test name
Test status
Simulation time 1555853490 ps
CPU time 3.64 seconds
Started May 23 01:24:13 PM PDT 24
Finished May 23 01:24:18 PM PDT 24
Peak memory 216288 kb
Host smart-f21e33d6-1ab3-4997-a01d-3698dcd17193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486134465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.486134465
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.840859855
Short name T532
Test name
Test status
Simulation time 7628408340 ps
CPU time 11.58 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:14 PM PDT 24
Peak memory 216444 kb
Host smart-c265ade0-8a24-4ab6-b22b-b46b78687595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840859855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.840859855
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2396515552
Short name T907
Test name
Test status
Simulation time 19194757 ps
CPU time 1.02 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 207136 kb
Host smart-bd6dc725-fa5e-4707-bb08-31ebf9bd1ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396515552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2396515552
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.374001935
Short name T403
Test name
Test status
Simulation time 24717657 ps
CPU time 0.74 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 205768 kb
Host smart-5b749523-17c7-4932-8362-1748fb0a4ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374001935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.374001935
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1401624760
Short name T398
Test name
Test status
Simulation time 325751293 ps
CPU time 3.29 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 236348 kb
Host smart-594db3cc-195b-427c-a770-3a51c4862c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401624760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1401624760
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.72393009
Short name T559
Test name
Test status
Simulation time 116859262 ps
CPU time 0.77 seconds
Started May 23 01:24:06 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 204676 kb
Host smart-1dd0eb44-f5a6-4afc-a62c-047642a972ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72393009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.72393009
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1369663816
Short name T605
Test name
Test status
Simulation time 64427067 ps
CPU time 2.47 seconds
Started May 23 01:24:06 PM PDT 24
Finished May 23 01:24:11 PM PDT 24
Peak memory 221300 kb
Host smart-06685554-12ba-4930-a07b-f53c0711fd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369663816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1369663816
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4270702903
Short name T343
Test name
Test status
Simulation time 33814600 ps
CPU time 0.71 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 205356 kb
Host smart-22906759-0b00-4024-a440-7c73d1a176df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270702903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4270702903
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.876495317
Short name T544
Test name
Test status
Simulation time 10241554757 ps
CPU time 44.86 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 249836 kb
Host smart-a1d08c25-5a10-489a-87b8-e01ca0d270a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876495317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.876495317
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.837520898
Short name T66
Test name
Test status
Simulation time 31159898089 ps
CPU time 57.86 seconds
Started May 23 01:24:16 PM PDT 24
Finished May 23 01:25:15 PM PDT 24
Peak memory 249404 kb
Host smart-ec78bcad-cfee-4857-aad9-e68f7b888063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837520898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.837520898
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.819603314
Short name T728
Test name
Test status
Simulation time 7843517088 ps
CPU time 23.2 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:46 PM PDT 24
Peak memory 241120 kb
Host smart-bc084c80-8d75-401a-a914-2f5249920e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819603314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.819603314
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3011908990
Short name T934
Test name
Test status
Simulation time 2184567083 ps
CPU time 9.62 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:31 PM PDT 24
Peak memory 232908 kb
Host smart-1a20af1b-3f60-4f17-8282-575d65d9d3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011908990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3011908990
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1695473464
Short name T682
Test name
Test status
Simulation time 1922594861 ps
CPU time 8 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 224504 kb
Host smart-ddd46637-8afe-4fb5-bc5f-8d1c2c9b98ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695473464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1695473464
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.4215705653
Short name T637
Test name
Test status
Simulation time 127434760 ps
CPU time 1.11 seconds
Started May 23 01:24:05 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 216728 kb
Host smart-2e668f69-8a8c-4891-88fc-27edb1c2637d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215705653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.4215705653
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1189789260
Short name T199
Test name
Test status
Simulation time 171242884 ps
CPU time 2.76 seconds
Started May 23 01:24:07 PM PDT 24
Finished May 23 01:24:12 PM PDT 24
Peak memory 233536 kb
Host smart-aa0955c4-701a-4083-98f2-5f8bcb289757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189789260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1189789260
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2355692412
Short name T401
Test name
Test status
Simulation time 106084151 ps
CPU time 2.53 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 221388 kb
Host smart-1126995c-ab19-4cb8-a0d4-9feb620c0a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355692412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2355692412
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1534177061
Short name T442
Test name
Test status
Simulation time 7434461693 ps
CPU time 21.85 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:23 PM PDT 24
Peak memory 220336 kb
Host smart-6f3e21ca-0283-4286-a910-1f05894a0fb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1534177061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1534177061
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3114168119
Short name T397
Test name
Test status
Simulation time 12563868662 ps
CPU time 27.54 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:33 PM PDT 24
Peak memory 216504 kb
Host smart-063e0def-a2e0-4b55-8590-707badb3e353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114168119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3114168119
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3389354958
Short name T616
Test name
Test status
Simulation time 5048309379 ps
CPU time 15.66 seconds
Started May 23 01:24:15 PM PDT 24
Finished May 23 01:24:32 PM PDT 24
Peak memory 216372 kb
Host smart-30a1b5f1-9337-4950-a49a-de7588110271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389354958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3389354958
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1436690949
Short name T376
Test name
Test status
Simulation time 28804240 ps
CPU time 0.7 seconds
Started May 23 01:24:15 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 205496 kb
Host smart-27e1318b-5df5-4095-868e-7c375ae63d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436690949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1436690949
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3676162157
Short name T594
Test name
Test status
Simulation time 175947015 ps
CPU time 1.02 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 206792 kb
Host smart-1d57ec06-8396-46a7-9094-83d59706cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676162157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3676162157
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4039840027
Short name T13
Test name
Test status
Simulation time 85995584 ps
CPU time 2.68 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 232688 kb
Host smart-bf858d81-8fb2-4238-9681-159362a1ba89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039840027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4039840027
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.967239878
Short name T400
Test name
Test status
Simulation time 14086897 ps
CPU time 0.74 seconds
Started May 23 01:24:25 PM PDT 24
Finished May 23 01:24:28 PM PDT 24
Peak memory 205388 kb
Host smart-5ad1faac-b10e-4732-8b7b-d7a5790dbcd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967239878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.967239878
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.751996825
Short name T753
Test name
Test status
Simulation time 1566626898 ps
CPU time 4.96 seconds
Started May 23 01:24:09 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 234268 kb
Host smart-cc7b6307-287d-41a2-8745-7df9179e901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751996825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.751996825
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2740071824
Short name T437
Test name
Test status
Simulation time 20503478 ps
CPU time 0.82 seconds
Started May 23 01:24:17 PM PDT 24
Finished May 23 01:24:19 PM PDT 24
Peak memory 206384 kb
Host smart-cdfde7fd-e2c2-4407-817a-9c6ce17b9547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740071824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2740071824
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3119258776
Short name T928
Test name
Test status
Simulation time 25168644 ps
CPU time 0.77 seconds
Started May 23 01:24:17 PM PDT 24
Finished May 23 01:24:19 PM PDT 24
Peak memory 215980 kb
Host smart-e541a8d6-7058-47bc-a107-885c7c618fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119258776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3119258776
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3733218961
Short name T30
Test name
Test status
Simulation time 66892723000 ps
CPU time 204.51 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:27:46 PM PDT 24
Peak memory 249412 kb
Host smart-147884d3-da57-4c5d-9092-7100d0b658e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733218961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3733218961
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2001219965
Short name T44
Test name
Test status
Simulation time 5908591289 ps
CPU time 43.02 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 252588 kb
Host smart-3570bea3-65ed-4ff1-a782-4fa3e6ea3427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001219965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2001219965
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2949284028
Short name T515
Test name
Test status
Simulation time 615005347 ps
CPU time 10.21 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:23 PM PDT 24
Peak memory 240940 kb
Host smart-440448f9-4c6e-4837-8cd0-3aeef7b680c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949284028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2949284028
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1320575623
Short name T157
Test name
Test status
Simulation time 186855041 ps
CPU time 4.5 seconds
Started May 23 01:24:10 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 232704 kb
Host smart-dd0f4141-2f4a-4469-857d-1dcb2575570c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320575623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1320575623
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.443056005
Short name T814
Test name
Test status
Simulation time 6547044863 ps
CPU time 25.05 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:51 PM PDT 24
Peak memory 232508 kb
Host smart-2adc594a-e6fe-4637-8671-711c37f26286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443056005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.443056005
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1621548382
Short name T518
Test name
Test status
Simulation time 130826687 ps
CPU time 1.1 seconds
Started May 23 01:24:14 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 216764 kb
Host smart-d0c9bdfd-ce38-4842-bdc6-af9ed7bc0858
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621548382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1621548382
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3391830924
Short name T242
Test name
Test status
Simulation time 921909022 ps
CPU time 8.57 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:33 PM PDT 24
Peak memory 240132 kb
Host smart-50c8a232-bd38-4013-8f48-659fd16ee5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391830924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3391830924
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.75523248
Short name T167
Test name
Test status
Simulation time 68441522 ps
CPU time 2.49 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:24 PM PDT 24
Peak memory 233232 kb
Host smart-497d7dd5-c7a2-4568-b46c-ca451ee14c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75523248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.75523248
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3589842380
Short name T705
Test name
Test status
Simulation time 4531197547 ps
CPU time 7.82 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:32 PM PDT 24
Peak memory 220116 kb
Host smart-9602e84a-ee59-4a8b-a380-5f71ccd2dc72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589842380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3589842380
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3688738594
Short name T568
Test name
Test status
Simulation time 1115295791 ps
CPU time 16.76 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:22 PM PDT 24
Peak memory 216436 kb
Host smart-6a9f5e9f-d2f2-4298-8ad1-08a57fed745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688738594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3688738594
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3408126955
Short name T949
Test name
Test status
Simulation time 54686244288 ps
CPU time 13.2 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 216412 kb
Host smart-f8a60744-c15d-4546-b139-49f8a043de29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408126955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3408126955
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1099010556
Short name T918
Test name
Test status
Simulation time 133429182 ps
CPU time 5.59 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:18 PM PDT 24
Peak memory 216304 kb
Host smart-df06585c-eee9-428d-b9b7-9b10dde341ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099010556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1099010556
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2298740437
Short name T332
Test name
Test status
Simulation time 26770572 ps
CPU time 0.81 seconds
Started May 23 01:24:08 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 205844 kb
Host smart-95dab238-aa19-4f8a-b8d6-e0dd452b9124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298740437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2298740437
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3324965410
Short name T818
Test name
Test status
Simulation time 5438520291 ps
CPU time 17.03 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 224544 kb
Host smart-090916da-fcda-4292-86b4-700d61c0c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324965410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3324965410
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1014373035
Short name T842
Test name
Test status
Simulation time 15430510 ps
CPU time 0.74 seconds
Started May 23 01:24:17 PM PDT 24
Finished May 23 01:24:19 PM PDT 24
Peak memory 205740 kb
Host smart-9eb4cb7a-ee96-4895-8275-bae955a66e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014373035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1014373035
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.895469721
Short name T1
Test name
Test status
Simulation time 3201875683 ps
CPU time 14.32 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 221636 kb
Host smart-05e00f5c-40d4-4d1d-9ce8-3f154292ebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895469721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.895469721
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3459324542
Short name T527
Test name
Test status
Simulation time 17420272 ps
CPU time 0.81 seconds
Started May 23 01:24:09 PM PDT 24
Finished May 23 01:24:12 PM PDT 24
Peak memory 206496 kb
Host smart-6949307a-e03a-4e47-94a8-ec0375aaa878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459324542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3459324542
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.110305646
Short name T464
Test name
Test status
Simulation time 59979010868 ps
CPU time 91.22 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:25:50 PM PDT 24
Peak memory 236040 kb
Host smart-e413e762-b2dd-4a4b-b40f-79a849f0169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110305646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.110305646
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3207472667
Short name T962
Test name
Test status
Simulation time 37930385071 ps
CPU time 117.89 seconds
Started May 23 01:24:12 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 254168 kb
Host smart-d4c65e0c-f920-4b63-935c-c1fd07be64ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207472667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3207472667
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2317675935
Short name T914
Test name
Test status
Simulation time 1961197199 ps
CPU time 5.58 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 233936 kb
Host smart-a52b4c30-b720-46a5-8284-5e98242d8065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317675935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2317675935
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.179656633
Short name T704
Test name
Test status
Simulation time 749264075 ps
CPU time 7.08 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:31 PM PDT 24
Peak memory 237592 kb
Host smart-a9e3d916-ff7e-456c-aba9-2ad72eaf339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179656633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.179656633
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3518284372
Short name T578
Test name
Test status
Simulation time 196098987 ps
CPU time 1.16 seconds
Started May 23 01:24:11 PM PDT 24
Finished May 23 01:24:14 PM PDT 24
Peak memory 216740 kb
Host smart-38b80c96-0cfe-4847-83b1-767dceacb736
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518284372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3518284372
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.888833206
Short name T658
Test name
Test status
Simulation time 1136400723 ps
CPU time 6.55 seconds
Started May 23 01:24:09 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 233684 kb
Host smart-b2bde322-5af2-4e0f-8a2b-59390593a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888833206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.888833206
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4182599669
Short name T975
Test name
Test status
Simulation time 1780662474 ps
CPU time 12.75 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:38 PM PDT 24
Peak memory 227824 kb
Host smart-f95ad47e-08a3-4de8-bd11-992687dcb619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182599669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4182599669
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1194881267
Short name T714
Test name
Test status
Simulation time 857584013 ps
CPU time 6.38 seconds
Started May 23 01:24:12 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 220208 kb
Host smart-eb5aef8a-7bc8-47a5-bd06-22d499afa4ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1194881267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1194881267
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1151920885
Short name T151
Test name
Test status
Simulation time 19635407169 ps
CPU time 29.65 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 251260 kb
Host smart-66454b42-115b-465b-9020-00131d22c12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151920885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1151920885
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1031680087
Short name T633
Test name
Test status
Simulation time 1618737357 ps
CPU time 13.78 seconds
Started May 23 01:24:16 PM PDT 24
Finished May 23 01:24:30 PM PDT 24
Peak memory 216784 kb
Host smart-bf3e15eb-c757-456c-a7f3-0cb2af9992a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031680087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1031680087
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2886890743
Short name T916
Test name
Test status
Simulation time 5265459142 ps
CPU time 5 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 216472 kb
Host smart-d4813f32-99b2-45b5-a5f8-1ecff36d56dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886890743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2886890743
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2257779401
Short name T644
Test name
Test status
Simulation time 42293111 ps
CPU time 0.83 seconds
Started May 23 01:24:12 PM PDT 24
Finished May 23 01:24:15 PM PDT 24
Peak memory 206540 kb
Host smart-4c041ccd-f2bd-406c-bfee-667ae5ffcff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257779401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2257779401
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.485802028
Short name T439
Test name
Test status
Simulation time 43303462 ps
CPU time 0.89 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:23 PM PDT 24
Peak memory 205772 kb
Host smart-4871011c-6fdf-41d8-b0ff-08241dcdd03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485802028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.485802028
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4071523292
Short name T630
Test name
Test status
Simulation time 784851285 ps
CPU time 2.29 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:23 PM PDT 24
Peak memory 207940 kb
Host smart-66049e7b-411b-4629-9f0c-7f4d03b016cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071523292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4071523292
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4069599310
Short name T552
Test name
Test status
Simulation time 24224424 ps
CPU time 0.69 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 205292 kb
Host smart-9ec2ebde-21d6-42b3-a61a-6132df289171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069599310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4069599310
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.843435532
Short name T758
Test name
Test status
Simulation time 58386623 ps
CPU time 2.04 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 216060 kb
Host smart-700ea197-e57c-45d1-971a-32498c466e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843435532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.843435532
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.604464741
Short name T909
Test name
Test status
Simulation time 25765709 ps
CPU time 0.74 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 206492 kb
Host smart-961643dd-ccd3-43d1-88b0-5e585568ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604464741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.604464741
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1217840057
Short name T184
Test name
Test status
Simulation time 87416901314 ps
CPU time 178.25 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:27:22 PM PDT 24
Peak memory 249500 kb
Host smart-9fe6f8d6-8749-4933-88ba-bee2137641db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217840057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1217840057
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4273746283
Short name T838
Test name
Test status
Simulation time 8951736781 ps
CPU time 58.81 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:25:23 PM PDT 24
Peak memory 252744 kb
Host smart-23138a4e-05ae-4208-86e8-09973b5c2f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273746283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4273746283
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.374009601
Short name T195
Test name
Test status
Simulation time 29758357314 ps
CPU time 278.63 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:29:04 PM PDT 24
Peak memory 250548 kb
Host smart-bba12723-f8bb-4801-801b-098c11cbb79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374009601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.374009601
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3901990641
Short name T425
Test name
Test status
Simulation time 5921367967 ps
CPU time 24.26 seconds
Started May 23 01:24:12 PM PDT 24
Finished May 23 01:24:38 PM PDT 24
Peak memory 224568 kb
Host smart-2f147cc3-e2ca-4a98-a770-f3ff98e1bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901990641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3901990641
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.634777294
Short name T642
Test name
Test status
Simulation time 143438044 ps
CPU time 3.57 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:29 PM PDT 24
Peak memory 219488 kb
Host smart-e98da9a6-e5b9-4aae-817b-2a622f9b8192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634777294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.634777294
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1513798507
Short name T166
Test name
Test status
Simulation time 9106767015 ps
CPU time 13.18 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:34 PM PDT 24
Peak memory 233796 kb
Host smart-b60a566c-e296-42a2-9e19-acea5e09304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513798507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1513798507
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3623945205
Short name T731
Test name
Test status
Simulation time 82535389 ps
CPU time 1.06 seconds
Started May 23 01:24:17 PM PDT 24
Finished May 23 01:24:19 PM PDT 24
Peak memory 216688 kb
Host smart-45210104-5c42-4e1d-9197-17a4891ef678
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623945205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3623945205
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1084499091
Short name T550
Test name
Test status
Simulation time 586057084 ps
CPU time 4.51 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 218672 kb
Host smart-53206b91-56f4-429a-905c-27b6861de39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084499091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1084499091
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2324653056
Short name T569
Test name
Test status
Simulation time 1427250455 ps
CPU time 7.52 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:33 PM PDT 24
Peak memory 233500 kb
Host smart-2e544d9c-a382-45cc-8284-d484fdb9b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324653056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2324653056
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3696265540
Short name T979
Test name
Test status
Simulation time 222717004 ps
CPU time 4.5 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:28 PM PDT 24
Peak memory 219188 kb
Host smart-e01e2143-7b76-4c7b-95b1-3976f898ece5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696265540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3696265540
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4007766137
Short name T864
Test name
Test status
Simulation time 10735388927 ps
CPU time 55.65 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 216452 kb
Host smart-824ff376-a2a5-43a5-ba9c-1df9d6d523aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007766137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4007766137
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1285367121
Short name T422
Test name
Test status
Simulation time 220242777 ps
CPU time 1.98 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:23 PM PDT 24
Peak memory 216328 kb
Host smart-994b51dd-9361-48f2-b052-40369b7d3960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285367121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1285367121
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3940239435
Short name T692
Test name
Test status
Simulation time 60788986 ps
CPU time 1.49 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:22 PM PDT 24
Peak memory 216392 kb
Host smart-6dd081a5-3a1c-4382-b5fc-4f08a0d3fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940239435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3940239435
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.64979503
Short name T394
Test name
Test status
Simulation time 200828483 ps
CPU time 0.99 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:21 PM PDT 24
Peak memory 206876 kb
Host smart-8259c7aa-983b-4d8e-865b-5880440dbd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64979503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.64979503
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.801879504
Short name T212
Test name
Test status
Simulation time 6404928420 ps
CPU time 21.56 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:44 PM PDT 24
Peak memory 228840 kb
Host smart-02bb3f6d-7941-4f7d-a7d4-7322ebd44b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801879504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.801879504
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.173997834
Short name T558
Test name
Test status
Simulation time 13907085 ps
CPU time 0.75 seconds
Started May 23 01:24:13 PM PDT 24
Finished May 23 01:24:15 PM PDT 24
Peak memory 204780 kb
Host smart-eb64c32a-36b3-40bd-afbc-88c0109712c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173997834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.173997834
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1745951068
Short name T741
Test name
Test status
Simulation time 1413595462 ps
CPU time 15.69 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:42 PM PDT 24
Peak memory 220588 kb
Host smart-0de32e85-8d7a-4d97-8e2e-ae545df77b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745951068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1745951068
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2024021607
Short name T880
Test name
Test status
Simulation time 48150055 ps
CPU time 0.74 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 205352 kb
Host smart-acbf61ab-4cee-4b02-844d-aa8f5749ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024021607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2024021607
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.82767566
Short name T257
Test name
Test status
Simulation time 29714271477 ps
CPU time 40.68 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 253752 kb
Host smart-0a32c755-9fcf-4c4a-a458-f9de79b45d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82767566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.82767566
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1533512015
Short name T650
Test name
Test status
Simulation time 46742641120 ps
CPU time 86.74 seconds
Started May 23 01:24:15 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 224824 kb
Host smart-57597195-e124-459a-8527-de37954853a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533512015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1533512015
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2185580300
Short name T414
Test name
Test status
Simulation time 867095548 ps
CPU time 8.38 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:32 PM PDT 24
Peak memory 224416 kb
Host smart-a3ea05f4-cbb9-415b-a913-ea556bf15d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185580300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2185580300
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1574679702
Short name T274
Test name
Test status
Simulation time 3370780823 ps
CPU time 17.48 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 218588 kb
Host smart-3b4848e8-85a2-4bdc-a6ff-b874d38e0782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574679702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1574679702
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.371202413
Short name T836
Test name
Test status
Simulation time 25461569947 ps
CPU time 38.38 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:25:05 PM PDT 24
Peak memory 235128 kb
Host smart-6be68fc6-030c-467c-8fc0-e5ce5c3d4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371202413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.371202413
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4021068941
Short name T933
Test name
Test status
Simulation time 237367304 ps
CPU time 1.07 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 216744 kb
Host smart-d58c0ea5-c948-4ad8-865a-01c186028449
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021068941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4021068941
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3386808519
Short name T895
Test name
Test status
Simulation time 54009233 ps
CPU time 2.07 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 216104 kb
Host smart-87cafaea-716a-447a-8288-ca7f9bc32a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386808519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3386808519
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1618185017
Short name T639
Test name
Test status
Simulation time 665881454 ps
CPU time 2.75 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:28 PM PDT 24
Peak memory 232680 kb
Host smart-dc589a0c-1284-4eba-9bb6-89b4a24d7e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618185017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1618185017
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1460333257
Short name T409
Test name
Test status
Simulation time 588390012 ps
CPU time 3.61 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:29 PM PDT 24
Peak memory 221804 kb
Host smart-3d91176b-0a3a-471e-af86-8ee6d9fc32d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460333257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1460333257
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1091500783
Short name T149
Test name
Test status
Simulation time 18229840422 ps
CPU time 157.68 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:27:04 PM PDT 24
Peak memory 249376 kb
Host smart-caf38ee8-ec3b-4921-a5a3-92f408aacb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091500783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1091500783
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2343295114
Short name T937
Test name
Test status
Simulation time 5098701225 ps
CPU time 27.73 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 216548 kb
Host smart-f6e82f99-1a9d-47fb-8a49-f1622c07d23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343295114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2343295114
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.40658505
Short name T843
Test name
Test status
Simulation time 17804989533 ps
CPU time 13.58 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 216500 kb
Host smart-84b7e599-39b5-484d-89b6-6dc9e54cddff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40658505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.40658505
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2971970869
Short name T598
Test name
Test status
Simulation time 18438484 ps
CPU time 1.29 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 216356 kb
Host smart-6bade1a1-b724-4172-814c-b9b46d80dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971970869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2971970869
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2654910647
Short name T372
Test name
Test status
Simulation time 74689542 ps
CPU time 0.79 seconds
Started May 23 01:24:14 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 205844 kb
Host smart-8653ac89-886b-455f-ab27-96bf243e12bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654910647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2654910647
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3534673075
Short name T170
Test name
Test status
Simulation time 106965050 ps
CPU time 2.75 seconds
Started May 23 01:24:17 PM PDT 24
Finished May 23 01:24:21 PM PDT 24
Peak memory 218484 kb
Host smart-8d19edf9-39e4-443e-b2e5-563850f44807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534673075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3534673075
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1702800241
Short name T647
Test name
Test status
Simulation time 38130963 ps
CPU time 0.69 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 204684 kb
Host smart-7db8aee0-c515-497c-acba-f3c7a9d2abd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702800241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1702800241
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1365212970
Short name T473
Test name
Test status
Simulation time 171683235 ps
CPU time 2.69 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:24 PM PDT 24
Peak memory 233740 kb
Host smart-bc5044f4-c560-4d8f-aa30-15a6cb37069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365212970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1365212970
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3553679793
Short name T535
Test name
Test status
Simulation time 16761259 ps
CPU time 0.74 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 206392 kb
Host smart-e2c20eac-4582-420b-aecc-d3ddc50c4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553679793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3553679793
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1916624902
Short name T405
Test name
Test status
Simulation time 20713625 ps
CPU time 0.8 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:23 PM PDT 24
Peak memory 215892 kb
Host smart-16d7cf49-babf-4d29-b869-b28b62a4d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916624902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1916624902
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2830384311
Short name T960
Test name
Test status
Simulation time 5100292182 ps
CPU time 50.49 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:25:11 PM PDT 24
Peak memory 249312 kb
Host smart-b72e372f-fe90-4357-a0a4-5a6a4901e45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830384311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2830384311
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3039681405
Short name T385
Test name
Test status
Simulation time 8145619185 ps
CPU time 64.33 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 248384 kb
Host smart-85f8480a-0fd6-4057-af9d-9d257ac3194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039681405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3039681405
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2511280511
Short name T606
Test name
Test status
Simulation time 137648420 ps
CPU time 2.82 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 232700 kb
Host smart-652eb725-c2b1-4e08-9b61-bed905352a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511280511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2511280511
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.32589719
Short name T612
Test name
Test status
Simulation time 2564224931 ps
CPU time 9.63 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:32 PM PDT 24
Peak memory 234404 kb
Host smart-8d05a72b-e329-4c71-8087-4c1fe33747cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32589719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.32589719
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.22247360
Short name T683
Test name
Test status
Simulation time 15337933 ps
CPU time 0.98 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 216756 kb
Host smart-b5d5e490-2245-4de0-a937-a3acca9d46b1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22247360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.22247360
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1642273151
Short name T513
Test name
Test status
Simulation time 3876183026 ps
CPU time 9.46 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 217972 kb
Host smart-63b6a3d1-1954-4a4d-a214-c6871c11ae76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642273151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1642273151
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2565360468
Short name T475
Test name
Test status
Simulation time 15954064951 ps
CPU time 18.4 seconds
Started May 23 01:24:17 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 240488 kb
Host smart-5b2522d6-97ed-47e6-a56d-a395c0180a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565360468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2565360468
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.580697009
Short name T610
Test name
Test status
Simulation time 596080797 ps
CPU time 6.24 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:30 PM PDT 24
Peak memory 219932 kb
Host smart-a00d410e-d84c-46ed-96fa-e609e6f43652
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=580697009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.580697009
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2647179401
Short name T67
Test name
Test status
Simulation time 49447783667 ps
CPU time 128.67 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:26:31 PM PDT 24
Peak memory 261816 kb
Host smart-8d6c9236-cce0-44f0-908f-b9cccad8bb8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647179401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2647179401
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2772466210
Short name T161
Test name
Test status
Simulation time 7580750745 ps
CPU time 12.41 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:37 PM PDT 24
Peak memory 216440 kb
Host smart-85a232be-366b-4a15-93a2-b7acd2097650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772466210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2772466210
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3180193820
Short name T803
Test name
Test status
Simulation time 1006092192 ps
CPU time 4.42 seconds
Started May 23 01:24:42 PM PDT 24
Finished May 23 01:24:47 PM PDT 24
Peak memory 216312 kb
Host smart-32a57d5d-c572-4865-a235-3b24d9300740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180193820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3180193820
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2436051416
Short name T674
Test name
Test status
Simulation time 425729290 ps
CPU time 1.98 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 216316 kb
Host smart-c027bb43-df12-4bc7-b34c-e340632310b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436051416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2436051416
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3385294074
Short name T20
Test name
Test status
Simulation time 67144727 ps
CPU time 0.91 seconds
Started May 23 01:24:18 PM PDT 24
Finished May 23 01:24:21 PM PDT 24
Peak memory 206208 kb
Host smart-09c65950-12b1-4565-86ab-31a7b88cdb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385294074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3385294074
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2511405146
Short name T169
Test name
Test status
Simulation time 355766723 ps
CPU time 3.43 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 218572 kb
Host smart-c623b135-5ac4-4917-b833-64bc9cadddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511405146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2511405146
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.61879851
Short name T406
Test name
Test status
Simulation time 14340919 ps
CPU time 0.75 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 205372 kb
Host smart-8c2291ab-61ba-40af-ab25-6ec46e6f00e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61879851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.61879851
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2309648914
Short name T726
Test name
Test status
Simulation time 2440166848 ps
CPU time 13.25 seconds
Started May 23 01:24:39 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 235944 kb
Host smart-451482a0-9923-4c21-94b7-5600e6929bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309648914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2309648914
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2009641326
Short name T595
Test name
Test status
Simulation time 50909520 ps
CPU time 0.76 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 206724 kb
Host smart-40a51db1-788e-4786-885d-38deb6c04711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009641326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2009641326
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3798221539
Short name T548
Test name
Test status
Simulation time 2222228294 ps
CPU time 2.82 seconds
Started May 23 01:24:42 PM PDT 24
Finished May 23 01:24:46 PM PDT 24
Peak memory 217520 kb
Host smart-92f9fd1d-6314-45e4-ab85-6439ca381f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798221539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3798221539
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4212441357
Short name T306
Test name
Test status
Simulation time 3687675032 ps
CPU time 12.58 seconds
Started May 23 01:24:31 PM PDT 24
Finished May 23 01:24:45 PM PDT 24
Peak memory 224636 kb
Host smart-ef5f2f37-c2a6-4e3a-b222-f15f7e6c151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212441357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4212441357
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2973914180
Short name T208
Test name
Test status
Simulation time 87521133 ps
CPU time 2.3 seconds
Started May 23 01:24:31 PM PDT 24
Finished May 23 01:24:34 PM PDT 24
Peak memory 224576 kb
Host smart-38490626-c3b6-442f-9f32-8050e35ba6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973914180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2973914180
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.191224736
Short name T181
Test name
Test status
Simulation time 3122993393 ps
CPU time 9.39 seconds
Started May 23 01:24:26 PM PDT 24
Finished May 23 01:24:37 PM PDT 24
Peak memory 218680 kb
Host smart-70d5850f-c2a0-4ad1-8354-d30e654ac1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191224736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.191224736
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1569726738
Short name T591
Test name
Test status
Simulation time 28038617 ps
CPU time 1.08 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 217928 kb
Host smart-01c44c61-a4da-4fae-8a66-182054c80f3f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569726738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1569726738
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.962558596
Short name T392
Test name
Test status
Simulation time 765733772 ps
CPU time 3.48 seconds
Started May 23 01:24:26 PM PDT 24
Finished May 23 01:24:31 PM PDT 24
Peak memory 218516 kb
Host smart-49191aa4-7870-4c11-8046-59ad46361466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962558596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.962558596
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2532618960
Short name T124
Test name
Test status
Simulation time 147605508 ps
CPU time 2.61 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 233604 kb
Host smart-6151097a-99ae-4980-b0a3-cd9172c32a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532618960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2532618960
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4185049834
Short name T490
Test name
Test status
Simulation time 334497203 ps
CPU time 5.6 seconds
Started May 23 01:24:28 PM PDT 24
Finished May 23 01:24:35 PM PDT 24
Peak memory 220060 kb
Host smart-07d0cfa7-e6e5-4ff2-bc0c-2f378329b3da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185049834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4185049834
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.85729176
Short name T706
Test name
Test status
Simulation time 85756978 ps
CPU time 1.04 seconds
Started May 23 01:24:33 PM PDT 24
Finished May 23 01:24:35 PM PDT 24
Peak memory 207092 kb
Host smart-4c0e8a32-56e7-4aea-ae25-d12988f4673e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85729176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress
_all.85729176
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1675825021
Short name T587
Test name
Test status
Simulation time 3286970593 ps
CPU time 18.87 seconds
Started May 23 01:24:20 PM PDT 24
Finished May 23 01:24:41 PM PDT 24
Peak memory 216476 kb
Host smart-44647e0f-0098-44d5-8161-00d1b3e6b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675825021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1675825021
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2261903483
Short name T696
Test name
Test status
Simulation time 3838653351 ps
CPU time 12.24 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 216456 kb
Host smart-0339686f-215b-4970-a66f-efb3a0194a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261903483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2261903483
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.84200063
Short name T514
Test name
Test status
Simulation time 191844093 ps
CPU time 1.19 seconds
Started May 23 01:24:22 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 207884 kb
Host smart-a9a598db-dc09-462e-aa46-88b1cfa3e0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84200063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.84200063
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1387433801
Short name T156
Test name
Test status
Simulation time 116523173 ps
CPU time 0.78 seconds
Started May 23 01:24:19 PM PDT 24
Finished May 23 01:24:21 PM PDT 24
Peak memory 205776 kb
Host smart-b5bbc8dd-c25d-4654-ab61-0e5eab98349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387433801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1387433801
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2247151862
Short name T677
Test name
Test status
Simulation time 221030441 ps
CPU time 2.43 seconds
Started May 23 01:24:32 PM PDT 24
Finished May 23 01:24:35 PM PDT 24
Peak memory 216340 kb
Host smart-8368f375-5986-4fd5-97e0-2b707318bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247151862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2247151862
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.827926891
Short name T494
Test name
Test status
Simulation time 49465086 ps
CPU time 0.75 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 205352 kb
Host smart-1b745243-135d-49f5-85db-9cbc7d7f1c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827926891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.827926891
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3501853026
Short name T666
Test name
Test status
Simulation time 2254099585 ps
CPU time 5.67 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:55 PM PDT 24
Peak memory 218848 kb
Host smart-661462c2-982e-4247-9959-2b8f48daf51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501853026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3501853026
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1663786058
Short name T21
Test name
Test status
Simulation time 34201700 ps
CPU time 0.78 seconds
Started May 23 01:23:29 PM PDT 24
Finished May 23 01:23:31 PM PDT 24
Peak memory 206380 kb
Host smart-c2b67402-b67e-4ddc-93b8-a669b7f1c704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663786058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1663786058
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.133381967
Short name T233
Test name
Test status
Simulation time 79813955874 ps
CPU time 172.62 seconds
Started May 23 01:23:43 PM PDT 24
Finished May 23 01:26:36 PM PDT 24
Peak memory 256468 kb
Host smart-1b00733a-776d-4ff9-9436-46d727eb0eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133381967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.133381967
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1898700063
Short name T234
Test name
Test status
Simulation time 59788524523 ps
CPU time 269.04 seconds
Started May 23 01:23:55 PM PDT 24
Finished May 23 01:28:26 PM PDT 24
Peak memory 257552 kb
Host smart-ed8b6c84-1d86-4381-9af0-7ef577d46f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898700063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1898700063
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1972134615
Short name T55
Test name
Test status
Simulation time 152681362 ps
CPU time 4.71 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 232724 kb
Host smart-8f0fa9d5-ca5b-4725-b604-0c39d05846a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972134615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1972134615
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2532619641
Short name T438
Test name
Test status
Simulation time 2256172456 ps
CPU time 9.22 seconds
Started May 23 01:23:43 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 224608 kb
Host smart-d753e5c6-b954-4a67-aac2-7d1eff2e5e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532619641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2532619641
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3233421246
Short name T290
Test name
Test status
Simulation time 10838802243 ps
CPU time 34.86 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 239612 kb
Host smart-9475174d-b688-408b-b4d5-a55f8aad3fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233421246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3233421246
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3758991907
Short name T549
Test name
Test status
Simulation time 25584893 ps
CPU time 1.06 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 216744 kb
Host smart-b37998a7-1e1f-4bed-a87b-7755266eab19
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758991907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3758991907
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2857754284
Short name T451
Test name
Test status
Simulation time 6173734450 ps
CPU time 13.34 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:24:01 PM PDT 24
Peak memory 237828 kb
Host smart-b51b490f-5630-4c46-aaff-11540d1860b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857754284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2857754284
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2871433435
Short name T452
Test name
Test status
Simulation time 932688410 ps
CPU time 10.07 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:23:56 PM PDT 24
Peak memory 232576 kb
Host smart-b145a5b8-078f-4ea2-a2d8-232bd25639cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871433435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2871433435
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1678974643
Short name T609
Test name
Test status
Simulation time 135470619 ps
CPU time 3.25 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:24:01 PM PDT 24
Peak memory 220176 kb
Host smart-32d74d6a-5e16-4823-afce-212f54e6c0e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1678974643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1678974643
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2731491469
Short name T660
Test name
Test status
Simulation time 87856646 ps
CPU time 0.98 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:23:57 PM PDT 24
Peak memory 206848 kb
Host smart-03652be0-41aa-4936-8266-9a4b6e4fd923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731491469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2731491469
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3603455479
Short name T865
Test name
Test status
Simulation time 1581614933 ps
CPU time 21.59 seconds
Started May 23 01:23:34 PM PDT 24
Finished May 23 01:23:57 PM PDT 24
Peak memory 216616 kb
Host smart-0d9e8607-e1c8-4300-8416-a59177adcb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603455479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3603455479
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1954917897
Short name T528
Test name
Test status
Simulation time 58107725 ps
CPU time 0.74 seconds
Started May 23 01:23:36 PM PDT 24
Finished May 23 01:23:39 PM PDT 24
Peak memory 205568 kb
Host smart-e2ef7e23-8e56-4dae-bb21-9d428bd93fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954917897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1954917897
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1472591261
Short name T787
Test name
Test status
Simulation time 949618637 ps
CPU time 8.17 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 216252 kb
Host smart-a72efbc0-7203-40d5-866f-b90c0d3bdf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472591261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1472591261
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2240294671
Short name T340
Test name
Test status
Simulation time 22956682 ps
CPU time 0.78 seconds
Started May 23 01:23:35 PM PDT 24
Finished May 23 01:23:37 PM PDT 24
Peak memory 205776 kb
Host smart-95d72290-646d-491e-b193-de128d43f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240294671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2240294671
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2713384385
Short name T378
Test name
Test status
Simulation time 4671052804 ps
CPU time 16.61 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:24:03 PM PDT 24
Peak memory 230160 kb
Host smart-6f84a5ac-901e-45d5-a54b-ff89a90a4b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713384385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2713384385
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2000812313
Short name T443
Test name
Test status
Simulation time 37112628 ps
CPU time 0.74 seconds
Started May 23 01:24:30 PM PDT 24
Finished May 23 01:24:32 PM PDT 24
Peak memory 204768 kb
Host smart-fe8533a3-4349-479d-9b19-4a4b27b3a49b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000812313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2000812313
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.893867115
Short name T384
Test name
Test status
Simulation time 111392971 ps
CPU time 2.84 seconds
Started May 23 01:24:28 PM PDT 24
Finished May 23 01:24:31 PM PDT 24
Peak memory 218556 kb
Host smart-55900a57-7718-4523-8a44-5ed4bae11de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893867115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.893867115
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3322666667
Short name T333
Test name
Test status
Simulation time 25131830 ps
CPU time 0.79 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 206404 kb
Host smart-6ac67f82-06fa-4823-a2cd-ec223ecbbbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322666667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3322666667
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.842547126
Short name T278
Test name
Test status
Simulation time 13619551977 ps
CPU time 115.18 seconds
Started May 23 01:24:29 PM PDT 24
Finished May 23 01:26:25 PM PDT 24
Peak memory 255636 kb
Host smart-05388356-e8d0-4217-baae-2b9fb05f0af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842547126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.842547126
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1324195768
Short name T247
Test name
Test status
Simulation time 14101290316 ps
CPU time 85.49 seconds
Started May 23 01:24:26 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 257288 kb
Host smart-efe6185e-5ce2-4fd6-8473-8a5ed8c99d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324195768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1324195768
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.425963952
Short name T504
Test name
Test status
Simulation time 4398925376 ps
CPU time 20.97 seconds
Started May 23 01:24:28 PM PDT 24
Finished May 23 01:24:49 PM PDT 24
Peak memory 217388 kb
Host smart-1ad6ac89-95cf-447f-ba3e-3f343af56a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425963952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.425963952
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3216314888
Short name T303
Test name
Test status
Simulation time 4628798175 ps
CPU time 17.43 seconds
Started May 23 01:24:31 PM PDT 24
Finished May 23 01:24:49 PM PDT 24
Peak memory 224656 kb
Host smart-c38504bc-50e5-4228-91d6-c622062332c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216314888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3216314888
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1480443680
Short name T551
Test name
Test status
Simulation time 3069260419 ps
CPU time 5.22 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:24:44 PM PDT 24
Peak memory 234300 kb
Host smart-c5831b8d-0e9b-480c-aaa1-885815aa1385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480443680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1480443680
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3565324061
Short name T777
Test name
Test status
Simulation time 3868288711 ps
CPU time 26.87 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:25:07 PM PDT 24
Peak memory 228008 kb
Host smart-7a245878-e053-4b5d-97fb-2a1f48a69d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565324061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3565324061
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.502352193
Short name T297
Test name
Test status
Simulation time 72018895 ps
CPU time 3.07 seconds
Started May 23 01:24:29 PM PDT 24
Finished May 23 01:24:33 PM PDT 24
Peak memory 233760 kb
Host smart-6b63c352-3b68-438b-80c6-389bc4b827f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502352193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.502352193
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2110107427
Short name T128
Test name
Test status
Simulation time 530518004 ps
CPU time 2.87 seconds
Started May 23 01:24:39 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 223828 kb
Host smart-315464ac-348f-4ad9-b678-d40cb2d7b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110107427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2110107427
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1029143564
Short name T651
Test name
Test status
Simulation time 3055691475 ps
CPU time 7.23 seconds
Started May 23 01:24:34 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 219312 kb
Host smart-eca39faf-b63c-4b14-ab2b-2206c35ab44f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1029143564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1029143564
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.4150617389
Short name T251
Test name
Test status
Simulation time 57649005076 ps
CPU time 585.42 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:34:24 PM PDT 24
Peak memory 265496 kb
Host smart-396e05ba-0c1e-48b5-8272-f6ccefa87dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150617389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.4150617389
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3596605229
Short name T418
Test name
Test status
Simulation time 493081792 ps
CPU time 3.38 seconds
Started May 23 01:24:30 PM PDT 24
Finished May 23 01:24:35 PM PDT 24
Peak memory 216340 kb
Host smart-973f6fbc-1b61-4bff-87cc-367b954bdf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596605229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3596605229
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1126572462
Short name T931
Test name
Test status
Simulation time 142535730 ps
CPU time 1.89 seconds
Started May 23 01:24:33 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 216388 kb
Host smart-5ffaacea-cba5-49a4-a8ac-728ad3634b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126572462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1126572462
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.156636538
Short name T746
Test name
Test status
Simulation time 339834811 ps
CPU time 0.96 seconds
Started May 23 01:24:28 PM PDT 24
Finished May 23 01:24:30 PM PDT 24
Peak memory 205868 kb
Host smart-c04492ee-898b-497c-9685-25bbe282247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156636538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.156636538
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3239020510
Short name T281
Test name
Test status
Simulation time 1703434559 ps
CPU time 5.45 seconds
Started May 23 01:24:34 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 234076 kb
Host smart-b31d671a-0c39-4fc7-b542-8d7a91890521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239020510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3239020510
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3880313046
Short name T982
Test name
Test status
Simulation time 15670909 ps
CPU time 0.72 seconds
Started May 23 01:24:40 PM PDT 24
Finished May 23 01:24:42 PM PDT 24
Peak memory 204696 kb
Host smart-55fdb334-8b1f-4e24-ac6c-b52e90348d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880313046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3880313046
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2678729729
Short name T766
Test name
Test status
Simulation time 177254599 ps
CPU time 2.89 seconds
Started May 23 01:24:36 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 234596 kb
Host smart-c7ae0017-fb23-479a-97a4-04469f2f1136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678729729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2678729729
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3009722808
Short name T359
Test name
Test status
Simulation time 60502464 ps
CPU time 0.81 seconds
Started May 23 01:24:34 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 206500 kb
Host smart-5dc45a21-1d8d-4ae4-a687-be319b6d1f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009722808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3009722808
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1300853367
Short name T15
Test name
Test status
Simulation time 54274475039 ps
CPU time 103.45 seconds
Started May 23 01:24:34 PM PDT 24
Finished May 23 01:26:19 PM PDT 24
Peak memory 241096 kb
Host smart-96670055-b519-4857-b00f-d0c86ae6be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300853367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1300853367
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4124055357
Short name T293
Test name
Test status
Simulation time 25178237216 ps
CPU time 237.23 seconds
Started May 23 01:24:32 PM PDT 24
Finished May 23 01:28:30 PM PDT 24
Peak memory 251452 kb
Host smart-7dfd7160-da3f-4496-847b-92803eb7d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124055357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4124055357
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3511659310
Short name T243
Test name
Test status
Simulation time 36787232739 ps
CPU time 344.43 seconds
Started May 23 01:24:33 PM PDT 24
Finished May 23 01:30:19 PM PDT 24
Peak memory 256968 kb
Host smart-36d68a1d-b8e3-4000-b85a-fe7da69ce9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511659310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3511659310
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2805913418
Short name T956
Test name
Test status
Simulation time 340842060 ps
CPU time 5.76 seconds
Started May 23 01:24:25 PM PDT 24
Finished May 23 01:24:33 PM PDT 24
Peak memory 232772 kb
Host smart-f18dbead-e3c7-4936-a04c-00dbf96605ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805913418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2805913418
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2948338057
Short name T923
Test name
Test status
Simulation time 2566219817 ps
CPU time 6.33 seconds
Started May 23 01:24:32 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 233612 kb
Host smart-c9bc2952-5e07-4d5b-b9f0-3f90e01f1557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948338057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2948338057
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1709787702
Short name T964
Test name
Test status
Simulation time 4123253841 ps
CPU time 48.74 seconds
Started May 23 01:24:36 PM PDT 24
Finished May 23 01:25:26 PM PDT 24
Peak memory 227320 kb
Host smart-437da171-abd4-4c6b-8c62-2cf43fcba2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709787702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1709787702
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.95650616
Short name T479
Test name
Test status
Simulation time 319898460 ps
CPU time 2.91 seconds
Started May 23 01:24:33 PM PDT 24
Finished May 23 01:24:37 PM PDT 24
Peak memory 218604 kb
Host smart-47a19bcb-5b30-44f3-b52b-1c390f895e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95650616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.95650616
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.676520817
Short name T539
Test name
Test status
Simulation time 23264710607 ps
CPU time 13.58 seconds
Started May 23 01:24:33 PM PDT 24
Finished May 23 01:24:48 PM PDT 24
Peak memory 218912 kb
Host smart-926fede8-9194-4426-b2f4-651e5c6c6717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676520817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.676520817
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3620812498
Short name T565
Test name
Test status
Simulation time 571927942 ps
CPU time 5.31 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 222824 kb
Host smart-2a944fa4-fbee-41f8-84b0-8fb883966957
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3620812498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3620812498
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2558731556
Short name T961
Test name
Test status
Simulation time 640364735253 ps
CPU time 293.25 seconds
Started May 23 01:24:31 PM PDT 24
Finished May 23 01:29:25 PM PDT 24
Peak memory 250336 kb
Host smart-bb292bac-8870-45d9-9069-12172343c51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558731556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2558731556
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.223415537
Short name T77
Test name
Test status
Simulation time 861296532 ps
CPU time 13.39 seconds
Started May 23 01:24:35 PM PDT 24
Finished May 23 01:24:49 PM PDT 24
Peak memory 216380 kb
Host smart-a0dd9e2f-df88-4801-b944-b51206a83661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223415537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.223415537
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2992504415
Short name T845
Test name
Test status
Simulation time 5768877487 ps
CPU time 9.28 seconds
Started May 23 01:24:25 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 216440 kb
Host smart-291c7680-e61e-4971-868f-19110bd50313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992504415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2992504415
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4173385352
Short name T435
Test name
Test status
Simulation time 605624167 ps
CPU time 5.6 seconds
Started May 23 01:24:32 PM PDT 24
Finished May 23 01:24:39 PM PDT 24
Peak memory 216440 kb
Host smart-a13ffea1-22ac-4184-ad28-b972c1442c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173385352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4173385352
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3322641577
Short name T336
Test name
Test status
Simulation time 30089208 ps
CPU time 0.73 seconds
Started May 23 01:24:24 PM PDT 24
Finished May 23 01:24:27 PM PDT 24
Peak memory 205760 kb
Host smart-751948a1-4d61-4994-9770-8f8ca04e9719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322641577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3322641577
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1628345000
Short name T917
Test name
Test status
Simulation time 14289890 ps
CPU time 0.78 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 204672 kb
Host smart-42f273b0-af86-4c15-8dd0-57198cbb8ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628345000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1628345000
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3705977377
Short name T751
Test name
Test status
Simulation time 1887557823 ps
CPU time 4 seconds
Started May 23 01:24:44 PM PDT 24
Finished May 23 01:24:49 PM PDT 24
Peak memory 218564 kb
Host smart-b4cc950a-ba30-4007-9cc1-19a78b72dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705977377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3705977377
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2362556948
Short name T652
Test name
Test status
Simulation time 53040530 ps
CPU time 0.79 seconds
Started May 23 01:24:34 PM PDT 24
Finished May 23 01:24:36 PM PDT 24
Peak memory 206816 kb
Host smart-a86fbe3d-6e75-4270-ad15-c3f4d74e0ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362556948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2362556948
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2177260554
Short name T563
Test name
Test status
Simulation time 4498764277 ps
CPU time 24.98 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 249220 kb
Host smart-e00ca92c-d949-47f8-88f9-4252ecbb4d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177260554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2177260554
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1429697799
Short name T461
Test name
Test status
Simulation time 68410843411 ps
CPU time 318.82 seconds
Started May 23 01:24:47 PM PDT 24
Finished May 23 01:30:08 PM PDT 24
Peak memory 253880 kb
Host smart-87b5eaa7-23a7-4ac0-96da-df3789086b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429697799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1429697799
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.120063772
Short name T304
Test name
Test status
Simulation time 1877529758 ps
CPU time 11.45 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:24:50 PM PDT 24
Peak memory 240880 kb
Host smart-adc4276c-c674-4877-a22d-2bc974bcd1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120063772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.120063772
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1027074698
Short name T760
Test name
Test status
Simulation time 1857890230 ps
CPU time 19.79 seconds
Started May 23 01:24:39 PM PDT 24
Finished May 23 01:25:01 PM PDT 24
Peak memory 224508 kb
Host smart-c17b666b-343e-4660-8bff-56bda30723da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027074698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1027074698
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2786006993
Short name T531
Test name
Test status
Simulation time 17200572627 ps
CPU time 50.39 seconds
Started May 23 01:24:46 PM PDT 24
Finished May 23 01:25:38 PM PDT 24
Peak memory 250404 kb
Host smart-f7113186-286b-4106-8f78-dad84d55880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786006993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2786006993
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3314054383
Short name T967
Test name
Test status
Simulation time 7073414659 ps
CPU time 6.29 seconds
Started May 23 01:24:43 PM PDT 24
Finished May 23 01:24:51 PM PDT 24
Peak memory 233856 kb
Host smart-72fedb51-e6eb-4d93-b3dd-9d1db431db47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314054383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3314054383
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2116367675
Short name T201
Test name
Test status
Simulation time 940468947 ps
CPU time 4.53 seconds
Started May 23 01:24:47 PM PDT 24
Finished May 23 01:24:53 PM PDT 24
Peak memory 233560 kb
Host smart-383758cb-96bb-4918-9922-54e3c1c1fcd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116367675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2116367675
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2629608868
Short name T428
Test name
Test status
Simulation time 510935119 ps
CPU time 4.75 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 222764 kb
Host smart-3b0bc747-a692-4da6-a324-d5a29f87cdce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2629608868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2629608868
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2183379760
Short name T773
Test name
Test status
Simulation time 288645479 ps
CPU time 1.27 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:24:41 PM PDT 24
Peak memory 207076 kb
Host smart-7bafa7f7-f4f6-4bd7-96d0-c1fb5d57e429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183379760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2183379760
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4205993393
Short name T542
Test name
Test status
Simulation time 8689009617 ps
CPU time 29.26 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 216800 kb
Host smart-c7740a7e-1c45-4289-990f-ef83513208c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205993393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4205993393
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4111355557
Short name T525
Test name
Test status
Simulation time 788599246 ps
CPU time 5.61 seconds
Started May 23 01:24:23 PM PDT 24
Finished May 23 01:24:31 PM PDT 24
Peak memory 216340 kb
Host smart-d4d8fe28-4464-46d9-b0a7-ddb7762c664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111355557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4111355557
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2900926007
Short name T472
Test name
Test status
Simulation time 59782671 ps
CPU time 0.91 seconds
Started May 23 01:24:39 PM PDT 24
Finished May 23 01:24:42 PM PDT 24
Peak memory 207248 kb
Host smart-3bff6bee-9f0f-4cc5-9745-ce07d414f10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900926007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2900926007
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.741623014
Short name T848
Test name
Test status
Simulation time 28289241 ps
CPU time 0.92 seconds
Started May 23 01:24:26 PM PDT 24
Finished May 23 01:24:28 PM PDT 24
Peak memory 205840 kb
Host smart-ba8766ba-5523-4cb5-960b-759ae35b2c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741623014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.741623014
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3733367927
Short name T286
Test name
Test status
Simulation time 26543749632 ps
CPU time 22.4 seconds
Started May 23 01:24:43 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 230464 kb
Host smart-2fe23bf7-bd9b-4b3a-849a-1ed5177f877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733367927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3733367927
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2568272246
Short name T477
Test name
Test status
Simulation time 14990199 ps
CPU time 0.72 seconds
Started May 23 01:24:41 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 205624 kb
Host smart-56a2ea49-c2e3-448c-9550-cc2a7400d6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568272246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2568272246
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2092494218
Short name T357
Test name
Test status
Simulation time 127884464 ps
CPU time 2.53 seconds
Started May 23 01:24:36 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 218512 kb
Host smart-d6f53d09-e251-4f0c-9aba-72b3169e619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092494218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2092494218
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3460636069
Short name T57
Test name
Test status
Simulation time 59781859 ps
CPU time 0.75 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:24:53 PM PDT 24
Peak memory 205404 kb
Host smart-1c86f665-309e-430c-a793-37012c54e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460636069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3460636069
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1568787730
Short name T273
Test name
Test status
Simulation time 6575827938 ps
CPU time 62.21 seconds
Started May 23 01:24:47 PM PDT 24
Finished May 23 01:25:51 PM PDT 24
Peak memory 249208 kb
Host smart-1100104a-5868-46b3-9860-a14134f8475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568787730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1568787730
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2989447097
Short name T781
Test name
Test status
Simulation time 184944250532 ps
CPU time 134.36 seconds
Started May 23 01:24:43 PM PDT 24
Finished May 23 01:26:58 PM PDT 24
Peak memory 256892 kb
Host smart-86048a48-f0d6-400f-86a6-aaf870b9bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989447097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2989447097
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.469333996
Short name T797
Test name
Test status
Simulation time 2149353265 ps
CPU time 21.27 seconds
Started May 23 01:24:39 PM PDT 24
Finished May 23 01:25:01 PM PDT 24
Peak memory 224792 kb
Host smart-0b1b480f-a8cb-4b6a-94c0-b5f378a3c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469333996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.469333996
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.277068358
Short name T884
Test name
Test status
Simulation time 1481413113 ps
CPU time 8.3 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 234448 kb
Host smart-8adf2656-df50-44c0-a87b-40cf6bfa45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277068358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.277068358
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3243219758
Short name T289
Test name
Test status
Simulation time 4608880517 ps
CPU time 23.14 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:25:14 PM PDT 24
Peak memory 234356 kb
Host smart-b52b9edf-4294-4090-97c9-9101f73fd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243219758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3243219758
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4029860787
Short name T944
Test name
Test status
Simulation time 1054079440 ps
CPU time 10.29 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:25:04 PM PDT 24
Peak memory 239572 kb
Host smart-acf90265-f81a-48ec-8c53-0600405da857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029860787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4029860787
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.737969525
Short name T239
Test name
Test status
Simulation time 30969513954 ps
CPU time 21.25 seconds
Started May 23 01:24:44 PM PDT 24
Finished May 23 01:25:07 PM PDT 24
Peak memory 224660 kb
Host smart-aef888be-5abb-4c8d-85a0-f92459075629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737969525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.737969525
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3305948127
Short name T182
Test name
Test status
Simulation time 66053910 ps
CPU time 3.03 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:24:42 PM PDT 24
Peak memory 233500 kb
Host smart-8e8f6dbe-9804-4b35-8d92-f9da98a96935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305948127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3305948127
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.976438387
Short name T882
Test name
Test status
Simulation time 274099751 ps
CPU time 3.84 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 222580 kb
Host smart-36c545b3-d7dc-401b-a0e4-8d3829fb46d0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=976438387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.976438387
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.335152385
Short name T955
Test name
Test status
Simulation time 179818724717 ps
CPU time 452.48 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:32:25 PM PDT 24
Peak memory 264360 kb
Host smart-3136b07b-33fd-4c02-bc05-8295de0797ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335152385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.335152385
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2696476855
Short name T585
Test name
Test status
Simulation time 6900488865 ps
CPU time 40.51 seconds
Started May 23 01:24:41 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 216468 kb
Host smart-f1b4cbea-06f5-4027-8fa1-cb8fc7ce1070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696476855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2696476855
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2102908215
Short name T417
Test name
Test status
Simulation time 4780644327 ps
CPU time 13.79 seconds
Started May 23 01:24:44 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 216584 kb
Host smart-8d02cc35-45f0-4803-b990-59033ae44763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102908215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2102908215
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1933602519
Short name T316
Test name
Test status
Simulation time 143296519 ps
CPU time 1.47 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 216232 kb
Host smart-ee2ef1b8-bff7-4f27-92f4-0d84c3813037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933602519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1933602519
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_upload.1422682010
Short name T189
Test name
Test status
Simulation time 2152038775 ps
CPU time 9.1 seconds
Started May 23 01:24:45 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 234860 kb
Host smart-6a7fd94a-44c6-4a65-9919-a77d97d1a2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422682010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1422682010
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.190340415
Short name T670
Test name
Test status
Simulation time 20564618 ps
CPU time 0.72 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 205352 kb
Host smart-ce1af9c6-e397-4f56-936b-3f69efb2d6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190340415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.190340415
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.4128317631
Short name T715
Test name
Test status
Simulation time 57080836 ps
CPU time 2.16 seconds
Started May 23 01:24:43 PM PDT 24
Finished May 23 01:24:47 PM PDT 24
Peak memory 221632 kb
Host smart-9817b107-22a7-47cf-b051-7670abeed1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128317631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.4128317631
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.568099188
Short name T855
Test name
Test status
Simulation time 59313409 ps
CPU time 0.81 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:24:40 PM PDT 24
Peak memory 206396 kb
Host smart-791971b9-0133-4e1a-92b3-9ec9459daa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568099188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.568099188
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3342994455
Short name T915
Test name
Test status
Simulation time 8593820742 ps
CPU time 11.72 seconds
Started May 23 01:24:44 PM PDT 24
Finished May 23 01:24:57 PM PDT 24
Peak memory 224476 kb
Host smart-eb0d7431-82c3-4bf8-9f11-a67f3ba6ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342994455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3342994455
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1713238251
Short name T287
Test name
Test status
Simulation time 31811491172 ps
CPU time 305.03 seconds
Started May 23 01:24:37 PM PDT 24
Finished May 23 01:29:43 PM PDT 24
Peak memory 249268 kb
Host smart-5bc808c5-4677-4af5-806b-00ed3757adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713238251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1713238251
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1652566380
Short name T735
Test name
Test status
Simulation time 19342464500 ps
CPU time 79.57 seconds
Started May 23 01:24:44 PM PDT 24
Finished May 23 01:26:04 PM PDT 24
Peak memory 252476 kb
Host smart-f3ac23b3-ddab-475e-a969-4d835436551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652566380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1652566380
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.985308576
Short name T352
Test name
Test status
Simulation time 104973728 ps
CPU time 2.82 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:56 PM PDT 24
Peak memory 224464 kb
Host smart-39cac3b3-6e9d-4ca8-8345-9566e6c1db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985308576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.985308576
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2958554813
Short name T276
Test name
Test status
Simulation time 174327141 ps
CPU time 2.96 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:57 PM PDT 24
Peak memory 224484 kb
Host smart-65532abf-5702-46ea-b58a-b4a6d185f6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958554813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2958554813
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3132693353
Short name T325
Test name
Test status
Simulation time 214226396 ps
CPU time 2.48 seconds
Started May 23 01:24:40 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 218524 kb
Host smart-0eaaa40c-5751-4072-af99-4ee4f878246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132693353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3132693353
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.927977487
Short name T945
Test name
Test status
Simulation time 16365031351 ps
CPU time 15.81 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 240352 kb
Host smart-4abe9b56-14ca-4c99-9447-87c235122223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927977487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.927977487
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2051545790
Short name T330
Test name
Test status
Simulation time 32503209 ps
CPU time 2.51 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:24:57 PM PDT 24
Peak memory 221376 kb
Host smart-ca974cae-e3ed-4420-be8d-44c0ee5ec93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051545790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2051545790
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1032550638
Short name T460
Test name
Test status
Simulation time 1205189304 ps
CPU time 3.57 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 218656 kb
Host smart-96bbef87-4ecb-4c25-81d9-df4f9ae0b8ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1032550638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1032550638
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3729858569
Short name T851
Test name
Test status
Simulation time 84775040 ps
CPU time 0.97 seconds
Started May 23 01:24:46 PM PDT 24
Finished May 23 01:24:48 PM PDT 24
Peak memory 206532 kb
Host smart-4c79934b-acfa-4c7f-aa40-07657390acfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729858569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3729858569
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1170813019
Short name T377
Test name
Test status
Simulation time 22636630 ps
CPU time 0.78 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 205452 kb
Host smart-ae1e67ba-eea1-49a1-a83f-e3fcfe5b19bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170813019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1170813019
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1925550866
Short name T830
Test name
Test status
Simulation time 20651143802 ps
CPU time 17.81 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:16 PM PDT 24
Peak memory 217672 kb
Host smart-04752ac3-f0c1-4599-8630-74893a8b09fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925550866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1925550866
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2235689670
Short name T536
Test name
Test status
Simulation time 103462555 ps
CPU time 3.68 seconds
Started May 23 01:24:39 PM PDT 24
Finished May 23 01:24:44 PM PDT 24
Peak memory 216532 kb
Host smart-7d5e2b51-c669-407d-9d6c-bfce7cf00b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235689670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2235689670
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1431216110
Short name T79
Test name
Test status
Simulation time 200483067 ps
CPU time 0.93 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:24:52 PM PDT 24
Peak memory 206720 kb
Host smart-9e540fcd-3442-4140-b10a-b780ce3282c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431216110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1431216110
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.399383268
Short name T493
Test name
Test status
Simulation time 1083023175 ps
CPU time 4.09 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:57 PM PDT 24
Peak memory 217792 kb
Host smart-69a963be-e357-422b-8aec-b72e567f5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399383268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.399383268
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.485404269
Short name T826
Test name
Test status
Simulation time 14200177 ps
CPU time 0.73 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 204772 kb
Host smart-4d0b5456-7019-4d7a-a5e3-5997605ff0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485404269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.485404269
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3157311598
Short name T291
Test name
Test status
Simulation time 727385521 ps
CPU time 4.69 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 218160 kb
Host smart-1e3e76ea-dd22-424e-8d48-e00ad851a3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157311598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3157311598
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1590844894
Short name T888
Test name
Test status
Simulation time 22720208 ps
CPU time 0.79 seconds
Started May 23 01:24:44 PM PDT 24
Finished May 23 01:24:46 PM PDT 24
Peak memory 206432 kb
Host smart-c73b8dbd-a055-4c2e-9b1d-1cb982986672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590844894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1590844894
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.325995510
Short name T576
Test name
Test status
Simulation time 7287634250 ps
CPU time 62.7 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:25:58 PM PDT 24
Peak memory 241096 kb
Host smart-b3d3a0ea-24ed-499a-a9c7-34133c9e972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325995510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.325995510
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.557710056
Short name T134
Test name
Test status
Simulation time 20065358165 ps
CPU time 202.43 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:28:19 PM PDT 24
Peak memory 250684 kb
Host smart-b52f98b2-c4df-442e-9473-1cc5fdfecc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557710056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.557710056
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1735586569
Short name T25
Test name
Test status
Simulation time 7365577315 ps
CPU time 109.41 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:26:46 PM PDT 24
Peak memory 255156 kb
Host smart-60f9fd5d-c1ee-4975-86f7-b963341ca49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735586569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1735586569
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2371198526
Short name T307
Test name
Test status
Simulation time 503306673 ps
CPU time 8.83 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:07 PM PDT 24
Peak memory 232784 kb
Host smart-0ad7d598-704a-4901-9c9a-1becf38671de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371198526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2371198526
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3437715430
Short name T669
Test name
Test status
Simulation time 294400662 ps
CPU time 3.51 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 218500 kb
Host smart-f75ae4ec-c4e7-49e1-9d56-de9fa205ccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437715430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3437715430
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.863593358
Short name T499
Test name
Test status
Simulation time 5349108229 ps
CPU time 12.26 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:11 PM PDT 24
Peak memory 218536 kb
Host smart-2db61c84-4c81-4ff1-9925-c529d43191d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863593358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.863593358
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2778841585
Short name T187
Test name
Test status
Simulation time 2595824382 ps
CPU time 3.42 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 216908 kb
Host smart-742857dd-d9a4-4711-bf84-72b955cef76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778841585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2778841585
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.909035637
Short name T910
Test name
Test status
Simulation time 1457329239 ps
CPU time 11.24 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:25:07 PM PDT 24
Peak memory 220308 kb
Host smart-7cddee98-4fd6-47e4-9214-79fd790654a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=909035637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.909035637
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3302399995
Short name T26
Test name
Test status
Simulation time 37924874990 ps
CPU time 284.86 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:29:45 PM PDT 24
Peak memory 266420 kb
Host smart-bad9e23b-0bec-4c3c-90df-23c9293fdc50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302399995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3302399995
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2827269931
Short name T375
Test name
Test status
Simulation time 1528688468 ps
CPU time 3.98 seconds
Started May 23 01:24:38 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 216468 kb
Host smart-ab136a99-d78c-4685-b500-e0972ab2a3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827269931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2827269931
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3216487169
Short name T545
Test name
Test status
Simulation time 3506465633 ps
CPU time 3.62 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:24:56 PM PDT 24
Peak memory 216448 kb
Host smart-ad5a9078-83ce-458c-b6db-9cab5cfe940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216487169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3216487169
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.299874190
Short name T455
Test name
Test status
Simulation time 1382447782 ps
CPU time 3.12 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:56 PM PDT 24
Peak memory 216424 kb
Host smart-f5164c0b-85d8-4a59-a117-c09c93e5abcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299874190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.299874190
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2675227935
Short name T347
Test name
Test status
Simulation time 114197689 ps
CPU time 0.97 seconds
Started May 23 01:24:49 PM PDT 24
Finished May 23 01:24:54 PM PDT 24
Peak memory 205696 kb
Host smart-29841a4e-994c-4692-9cb0-c603f90372a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675227935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2675227935
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3160824587
Short name T946
Test name
Test status
Simulation time 817337662 ps
CPU time 3.78 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:25:00 PM PDT 24
Peak memory 233884 kb
Host smart-915c7320-8777-427c-b489-6a72c7d1af92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160824587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3160824587
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2129066985
Short name T597
Test name
Test status
Simulation time 12836807 ps
CPU time 0.72 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:24:58 PM PDT 24
Peak memory 205656 kb
Host smart-47e31248-0483-428b-a3c5-9e04dcdeb363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129066985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2129066985
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.201813539
Short name T796
Test name
Test status
Simulation time 86530037 ps
CPU time 2.68 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:24:58 PM PDT 24
Peak memory 234244 kb
Host smart-95834c6c-b542-4e92-9d5b-5b65866db6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201813539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.201813539
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.417740427
Short name T769
Test name
Test status
Simulation time 21830178 ps
CPU time 0.75 seconds
Started May 23 01:24:48 PM PDT 24
Finished May 23 01:24:53 PM PDT 24
Peak memory 205372 kb
Host smart-cbee0c29-99ef-47df-8ce4-8da208eaaac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417740427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.417740427
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1952563476
Short name T245
Test name
Test status
Simulation time 49165619283 ps
CPU time 350.45 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:30:47 PM PDT 24
Peak memory 249292 kb
Host smart-febcff63-6314-4d29-b9d9-8f9cdd92b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952563476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1952563476
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.843354364
Short name T581
Test name
Test status
Simulation time 44342680322 ps
CPU time 101.42 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:26:39 PM PDT 24
Peak memory 249392 kb
Host smart-68ed14a1-e444-4ca6-a93a-3ccba7fef888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843354364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.843354364
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4166607946
Short name T874
Test name
Test status
Simulation time 845816835 ps
CPU time 10.95 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:11 PM PDT 24
Peak memory 238752 kb
Host smart-3f442ff1-6ad3-49c0-8717-955dd1190c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166607946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4166607946
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3131837080
Short name T583
Test name
Test status
Simulation time 682543745 ps
CPU time 7.03 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 234280 kb
Host smart-0688c3ff-5a62-4d64-bac4-22ffd30226b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131837080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3131837080
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.724066501
Short name T205
Test name
Test status
Simulation time 3099092003 ps
CPU time 32.22 seconds
Started May 23 01:25:00 PM PDT 24
Finished May 23 01:25:35 PM PDT 24
Peak memory 218544 kb
Host smart-5e3c0d0c-3efe-460f-9e1f-93eae842aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724066501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.724066501
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.401989359
Short name T625
Test name
Test status
Simulation time 10993184198 ps
CPU time 32.8 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:25:29 PM PDT 24
Peak memory 224228 kb
Host smart-0345369b-3102-4bf7-bae8-c7becb5e9ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401989359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.401989359
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3826705509
Short name T510
Test name
Test status
Simulation time 1981666701 ps
CPU time 9.88 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 233152 kb
Host smart-4ac2524c-c091-4b8b-bc8b-b76cf1bb9517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826705509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3826705509
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.597057661
Short name T489
Test name
Test status
Simulation time 665113974 ps
CPU time 6.93 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:07 PM PDT 24
Peak memory 221604 kb
Host smart-b6e0c29d-7e5a-46d8-8b9e-27fa44dee760
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597057661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.597057661
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2347859195
Short name T745
Test name
Test status
Simulation time 12325947 ps
CPU time 0.74 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:24:58 PM PDT 24
Peak memory 205620 kb
Host smart-57729a8f-6970-455f-9c57-534396b92283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347859195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2347859195
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3967389830
Short name T700
Test name
Test status
Simulation time 614868077 ps
CPU time 1.83 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:00 PM PDT 24
Peak memory 207932 kb
Host smart-03266aeb-12ce-4f5e-aa1d-a4e1301c8821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967389830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3967389830
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3466751539
Short name T350
Test name
Test status
Simulation time 38158960 ps
CPU time 0.77 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:24:58 PM PDT 24
Peak memory 205800 kb
Host smart-510feb79-b6bf-4a15-a400-23d40b570676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466751539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3466751539
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3562243262
Short name T588
Test name
Test status
Simulation time 29589582 ps
CPU time 0.75 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 205816 kb
Host smart-e405fed8-d0bb-40ab-a59b-cd6de8142f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562243262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3562243262
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1004607205
Short name T553
Test name
Test status
Simulation time 6566641916 ps
CPU time 9.78 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 218712 kb
Host smart-f9a7bfd1-150d-4003-9a1c-686689b29399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004607205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1004607205
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.122196025
Short name T596
Test name
Test status
Simulation time 30327383 ps
CPU time 0.73 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:01 PM PDT 24
Peak memory 204700 kb
Host smart-d5daacdd-39a4-4a44-b389-d9ad7760303c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122196025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.122196025
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1055375881
Short name T471
Test name
Test status
Simulation time 62351814 ps
CPU time 2.15 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 216600 kb
Host smart-373298c1-5ca9-41d6-af9c-553d739ac6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055375881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1055375881
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2643479127
Short name T540
Test name
Test status
Simulation time 14613958 ps
CPU time 0.77 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:24:57 PM PDT 24
Peak memory 205780 kb
Host smart-77716ee8-4f34-4c41-893c-6a558a809c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643479127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2643479127
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3177475266
Short name T396
Test name
Test status
Simulation time 66676799536 ps
CPU time 226.45 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:28:45 PM PDT 24
Peak memory 250220 kb
Host smart-a818670a-be16-416e-9b49-94f4e0c1fb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177475266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3177475266
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.299536009
Short name T738
Test name
Test status
Simulation time 4680930191 ps
CPU time 91.86 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:26:30 PM PDT 24
Peak memory 257584 kb
Host smart-ab1f0956-e20c-4450-92d4-8f3cbc23e3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299536009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.299536009
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3889911541
Short name T366
Test name
Test status
Simulation time 1318655697 ps
CPU time 5.79 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 217388 kb
Host smart-aa9bc78f-4919-4788-ad1a-4ffe22537f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889911541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3889911541
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1771061060
Short name T299
Test name
Test status
Simulation time 2084443598 ps
CPU time 9.47 seconds
Started May 23 01:24:56 PM PDT 24
Finished May 23 01:25:09 PM PDT 24
Peak memory 224500 kb
Host smart-bdd88faa-b494-4521-b46a-3a09a322cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771061060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1771061060
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3904994317
Short name T449
Test name
Test status
Simulation time 1280170383 ps
CPU time 8.03 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:05 PM PDT 24
Peak memory 218488 kb
Host smart-4f3cd9eb-ae82-4c3d-9191-7a5e87f29a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904994317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3904994317
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.11252333
Short name T530
Test name
Test status
Simulation time 63494841 ps
CPU time 2.14 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 218612 kb
Host smart-4fb655f8-96d0-443a-a788-83ec0ce038df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11252333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.11252333
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1097650794
Short name T546
Test name
Test status
Simulation time 3325488306 ps
CPU time 14.85 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:13 PM PDT 24
Peak memory 233708 kb
Host smart-d0d61359-7778-4bee-90d0-783775ab5486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097650794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1097650794
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2157347406
Short name T95
Test name
Test status
Simulation time 99842889 ps
CPU time 2.16 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:24:58 PM PDT 24
Peak memory 221608 kb
Host smart-6d71a0e6-8d9b-49cf-aca6-a80d152774b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157347406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2157347406
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3851010974
Short name T840
Test name
Test status
Simulation time 778252555 ps
CPU time 9.23 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 219252 kb
Host smart-fa7b07b0-0967-4f01-91dd-af66a16b5584
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3851010974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3851010974
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3294869844
Short name T153
Test name
Test status
Simulation time 3336569500 ps
CPU time 44.28 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 224700 kb
Host smart-53e58a0c-a2cf-4d7d-9b67-5da447843ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294869844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3294869844
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2923223366
Short name T614
Test name
Test status
Simulation time 7772702363 ps
CPU time 16.56 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:25:13 PM PDT 24
Peak memory 216440 kb
Host smart-128df515-5184-467b-b2a2-752c43f82f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923223366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2923223366
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.487815669
Short name T387
Test name
Test status
Simulation time 7446400152 ps
CPU time 10.65 seconds
Started May 23 01:24:58 PM PDT 24
Finished May 23 01:25:12 PM PDT 24
Peak memory 216412 kb
Host smart-de5dfafd-e2d2-4503-8b76-4fd6ce19e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487815669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.487815669
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3177030967
Short name T433
Test name
Test status
Simulation time 63870314 ps
CPU time 1.14 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:00 PM PDT 24
Peak memory 207716 kb
Host smart-90028c9c-cd0b-4cef-acf5-8c3774d1b578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177030967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3177030967
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1389821963
Short name T80
Test name
Test status
Simulation time 44825139 ps
CPU time 0.77 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 205776 kb
Host smart-cb47c428-520b-427c-9566-00c8a0aae54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389821963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1389821963
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2120258455
Short name T779
Test name
Test status
Simulation time 7073742954 ps
CPU time 21.87 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 233400 kb
Host smart-48d2b1a7-3d0a-47fd-a03a-b705b057c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120258455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2120258455
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3409958727
Short name T423
Test name
Test status
Simulation time 16987778 ps
CPU time 0.78 seconds
Started May 23 01:24:59 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 205392 kb
Host smart-b3e3ac7c-fa97-4183-b80a-c2ac715df52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409958727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3409958727
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3859736477
Short name T575
Test name
Test status
Simulation time 5272313926 ps
CPU time 7.62 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:05 PM PDT 24
Peak memory 224692 kb
Host smart-d9b6c3a2-e57f-4998-a20f-483399c2ea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859736477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3859736477
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1693783459
Short name T58
Test name
Test status
Simulation time 64363198 ps
CPU time 0.77 seconds
Started May 23 01:24:51 PM PDT 24
Finished May 23 01:24:57 PM PDT 24
Peak memory 206792 kb
Host smart-8b5a7051-8d77-4692-9471-5910239bf06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693783459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1693783459
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3761771463
Short name T876
Test name
Test status
Simulation time 217301107787 ps
CPU time 423.61 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:32:01 PM PDT 24
Peak memory 253604 kb
Host smart-bed3496a-6102-48ea-8d11-5f35f54d68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761771463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3761771463
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.843656239
Short name T47
Test name
Test status
Simulation time 74848851453 ps
CPU time 165.63 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:27:42 PM PDT 24
Peak memory 250508 kb
Host smart-031b9369-2a7c-4c41-b186-3ed4f6865701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843656239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.843656239
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3090082011
Short name T285
Test name
Test status
Simulation time 8953358826 ps
CPU time 106.44 seconds
Started May 23 01:25:01 PM PDT 24
Finished May 23 01:26:50 PM PDT 24
Peak memory 249412 kb
Host smart-21be07ff-a135-4373-8f3d-9be37db61e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090082011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3090082011
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3172500386
Short name T707
Test name
Test status
Simulation time 1106281553 ps
CPU time 10.38 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:09 PM PDT 24
Peak memory 224500 kb
Host smart-eb465a84-afa5-418d-b09e-e9fba881e734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172500386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3172500386
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3063000912
Short name T641
Test name
Test status
Simulation time 1049287320 ps
CPU time 11.23 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 234960 kb
Host smart-f14ff39f-60a0-474b-8d13-cbc1740948c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063000912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3063000912
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2424530107
Short name T129
Test name
Test status
Simulation time 5938612473 ps
CPU time 57.36 seconds
Started May 23 01:24:56 PM PDT 24
Finished May 23 01:25:57 PM PDT 24
Peak memory 231056 kb
Host smart-ce13ed10-862f-4b39-857b-ed8f9d9ed8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424530107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2424530107
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.903565583
Short name T214
Test name
Test status
Simulation time 5305523754 ps
CPU time 18.48 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:17 PM PDT 24
Peak memory 233416 kb
Host smart-3bea0693-31b5-4081-953e-df84b1b9beab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903565583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.903565583
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.684609840
Short name T659
Test name
Test status
Simulation time 930998111 ps
CPU time 3.84 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 235264 kb
Host smart-5e7d0a53-cd7b-440b-9882-524b6f122d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684609840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.684609840
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2055628847
Short name T718
Test name
Test status
Simulation time 295730377 ps
CPU time 3.76 seconds
Started May 23 01:24:55 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 219256 kb
Host smart-9e692c9b-2029-4c0f-8fb5-17171fcc0593
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2055628847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2055628847
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1600605662
Short name T675
Test name
Test status
Simulation time 363920301 ps
CPU time 5.88 seconds
Started May 23 01:24:50 PM PDT 24
Finished May 23 01:25:01 PM PDT 24
Peak memory 216356 kb
Host smart-548eddae-569b-4390-a279-7c646193bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600605662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1600605662
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.537829772
Short name T694
Test name
Test status
Simulation time 196787997 ps
CPU time 1.74 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 207696 kb
Host smart-12433224-8e18-4f86-bba7-51afb4e0f26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537829772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.537829772
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.270517892
Short name T386
Test name
Test status
Simulation time 2835566389 ps
CPU time 5.14 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 216584 kb
Host smart-13d4637a-d6ae-4c7a-b44b-e5eca945813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270517892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.270517892
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3929911268
Short name T846
Test name
Test status
Simulation time 104316271 ps
CPU time 0.78 seconds
Started May 23 01:24:58 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 205784 kb
Host smart-0f6aeaa5-5a87-41c4-be2c-e627891a8174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929911268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3929911268
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1272285826
Short name T711
Test name
Test status
Simulation time 56925157 ps
CPU time 2.03 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:24:59 PM PDT 24
Peak memory 207936 kb
Host smart-9ee9d7c3-c847-467e-b2d6-2ebece4fb559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272285826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1272285826
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2190667842
Short name T788
Test name
Test status
Simulation time 31428174 ps
CPU time 0.72 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 204688 kb
Host smart-fac414a9-69b0-4e0f-be8f-0b19a96e180b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190667842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2190667842
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.665835223
Short name T198
Test name
Test status
Simulation time 212318482 ps
CPU time 4.37 seconds
Started May 23 01:24:54 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 219852 kb
Host smart-88c1639b-78f5-4e47-9aa2-a31cb648c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665835223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.665835223
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.331001115
Short name T59
Test name
Test status
Simulation time 12784066 ps
CPU time 0.74 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:00 PM PDT 24
Peak memory 205728 kb
Host smart-1d621f20-7389-416d-aa1c-ee2df2d1af9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331001115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.331001115
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1466452489
Short name T339
Test name
Test status
Simulation time 13608760 ps
CPU time 0.77 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:24:58 PM PDT 24
Peak memory 215892 kb
Host smart-39e0e9b0-687f-4342-bffc-24a48fb1bdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466452489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1466452489
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2871224846
Short name T40
Test name
Test status
Simulation time 29144042418 ps
CPU time 117.27 seconds
Started May 23 01:25:01 PM PDT 24
Finished May 23 01:27:00 PM PDT 24
Peak memory 249392 kb
Host smart-9b0ef6ec-9df7-4f01-a844-506c96bbd225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871224846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2871224846
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1117007558
Short name T509
Test name
Test status
Simulation time 1731079014 ps
CPU time 11.09 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:17 PM PDT 24
Peak memory 217644 kb
Host smart-700d6dd6-bb9d-4e28-a442-3ee595d59b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117007558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1117007558
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.16754949
Short name T393
Test name
Test status
Simulation time 1741364102 ps
CPU time 8.37 seconds
Started May 23 01:24:59 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 232788 kb
Host smart-f1824e7a-1f7c-4006-9202-beab57aa9c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16754949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.16754949
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1040875500
Short name T434
Test name
Test status
Simulation time 2843886292 ps
CPU time 29.12 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:34 PM PDT 24
Peak memory 224592 kb
Host smart-aa67059a-b1f0-4c21-a8e7-987f82dc6260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040875500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1040875500
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.385508082
Short name T608
Test name
Test status
Simulation time 848820827 ps
CPU time 11.17 seconds
Started May 23 01:24:52 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 218572 kb
Host smart-4ca6aef9-d313-4235-b3df-47e435d5d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385508082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.385508082
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2091517358
Short name T586
Test name
Test status
Simulation time 2603202519 ps
CPU time 11.75 seconds
Started May 23 01:24:57 PM PDT 24
Finished May 23 01:25:12 PM PDT 24
Peak memory 218828 kb
Host smart-2fa75696-4624-4ff5-8fcc-68fabd0767d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091517358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2091517358
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.376997188
Short name T790
Test name
Test status
Simulation time 2416456914 ps
CPU time 8.79 seconds
Started May 23 01:24:56 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 224640 kb
Host smart-ccc5c82c-856f-49e1-9892-073f8e769776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376997188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.376997188
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.299164815
Short name T618
Test name
Test status
Simulation time 437745687 ps
CPU time 4.47 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:02 PM PDT 24
Peak memory 219956 kb
Host smart-30fb2e15-1c5e-4351-9813-3f3197a943af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299164815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.299164815
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2043082818
Short name T241
Test name
Test status
Simulation time 532504992416 ps
CPU time 651.85 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:36:02 PM PDT 24
Peak memory 256872 kb
Host smart-3bc5a23b-fafc-4c2f-897e-50daab2501f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043082818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2043082818
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2179139169
Short name T317
Test name
Test status
Simulation time 3520941409 ps
CPU time 29.93 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 216516 kb
Host smart-013e4fe3-6d9a-4df7-922a-10ef2b9eb9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179139169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2179139169
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1529563795
Short name T831
Test name
Test status
Simulation time 41586556960 ps
CPU time 18.78 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:16 PM PDT 24
Peak memory 216552 kb
Host smart-5c3c8729-3177-43c6-8ad1-d621cf271736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529563795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1529563795
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.622929836
Short name T478
Test name
Test status
Simulation time 827221117 ps
CPU time 6.38 seconds
Started May 23 01:24:53 PM PDT 24
Finished May 23 01:25:03 PM PDT 24
Peak memory 216484 kb
Host smart-f360ad1a-077d-4fe8-87e1-046db44f08ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622929836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.622929836
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2112716268
Short name T49
Test name
Test status
Simulation time 219095165 ps
CPU time 0.93 seconds
Started May 23 01:24:56 PM PDT 24
Finished May 23 01:25:00 PM PDT 24
Peak memory 205788 kb
Host smart-e6e92f67-44ea-40d1-a232-6ccd5f8f1b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112716268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2112716268
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1723678688
Short name T763
Test name
Test status
Simulation time 46254328423 ps
CPU time 26.52 seconds
Started May 23 01:24:58 PM PDT 24
Finished May 23 01:25:28 PM PDT 24
Peak memory 239300 kb
Host smart-0f0214ac-4522-454b-bd5e-1f241bcec539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723678688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1723678688
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3044494574
Short name T547
Test name
Test status
Simulation time 23296965 ps
CPU time 0.75 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:23:48 PM PDT 24
Peak memory 204620 kb
Host smart-02dfc947-0522-40c7-9a70-c21d6059559f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044494574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
044494574
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1620305645
Short name T522
Test name
Test status
Simulation time 798592343 ps
CPU time 10.2 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:59 PM PDT 24
Peak memory 233992 kb
Host smart-7ef84f75-072a-482d-a863-52baf310dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620305645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1620305645
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1274516106
Short name T482
Test name
Test status
Simulation time 54808810 ps
CPU time 0.78 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:01 PM PDT 24
Peak memory 206488 kb
Host smart-b758d69f-3cc8-4d85-9dbb-5ea32b370f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274516106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1274516106
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3127850866
Short name T45
Test name
Test status
Simulation time 16918362251 ps
CPU time 68.82 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 249232 kb
Host smart-e70768db-3659-45aa-a9a9-8bb4c7798b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127850866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3127850866
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2729286108
Short name T253
Test name
Test status
Simulation time 9210813467 ps
CPU time 64.3 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:24:50 PM PDT 24
Peak memory 237724 kb
Host smart-ba1399af-bf84-4253-9b8f-5b48e51ef6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729286108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2729286108
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4140874422
Short name T747
Test name
Test status
Simulation time 20262676978 ps
CPU time 158.67 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:26:26 PM PDT 24
Peak memory 256684 kb
Host smart-3e148713-d3a9-4510-86d2-436737a588dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140874422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4140874422
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3410187019
Short name T12
Test name
Test status
Simulation time 2774009412 ps
CPU time 12.11 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 234884 kb
Host smart-bfe8ead5-4d1c-46a2-996b-66d2ef101928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410187019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3410187019
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2299798480
Short name T272
Test name
Test status
Simulation time 233648072 ps
CPU time 4.87 seconds
Started May 23 01:23:43 PM PDT 24
Finished May 23 01:23:49 PM PDT 24
Peak memory 234368 kb
Host smart-0b9f253e-7433-4411-8c5f-083576061b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299798480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2299798480
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2299853798
Short name T870
Test name
Test status
Simulation time 15524856758 ps
CPU time 56.65 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:24:41 PM PDT 24
Peak memory 235644 kb
Host smart-347ee9c1-7c52-4662-8a35-23ec9036ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299853798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2299853798
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3712120984
Short name T761
Test name
Test status
Simulation time 47632980 ps
CPU time 1.03 seconds
Started May 23 01:23:42 PM PDT 24
Finished May 23 01:23:44 PM PDT 24
Peak memory 218008 kb
Host smart-54c99e85-54c8-44ce-8408-a54947990199
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712120984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3712120984
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3445467186
Short name T689
Test name
Test status
Simulation time 13215151871 ps
CPU time 37.14 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:24:33 PM PDT 24
Peak memory 247356 kb
Host smart-4f391fe5-a45b-4f1a-9dec-3f9193045817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445467186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3445467186
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2938466529
Short name T537
Test name
Test status
Simulation time 837772082 ps
CPU time 5.5 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:23:53 PM PDT 24
Peak memory 236532 kb
Host smart-0818e22d-5b3b-4a81-bcf2-6e8b483ef66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938466529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2938466529
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3550013787
Short name T894
Test name
Test status
Simulation time 225418706 ps
CPU time 4.24 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:23:50 PM PDT 24
Peak memory 222932 kb
Host smart-089d00a2-95b4-40c7-a56c-ced1bac13ae0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3550013787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3550013787
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4154229764
Short name T62
Test name
Test status
Simulation time 117707142 ps
CPU time 0.96 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:23:46 PM PDT 24
Peak memory 234704 kb
Host smart-c9c1f638-f545-422d-8144-c2708554d327
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154229764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4154229764
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4098645865
Short name T421
Test name
Test status
Simulation time 88738536 ps
CPU time 1.06 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 206796 kb
Host smart-5b9dd244-ca86-4bbf-8c16-0dad28eea12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098645865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4098645865
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3866532190
Short name T369
Test name
Test status
Simulation time 1348016936 ps
CPU time 2.75 seconds
Started May 23 01:23:43 PM PDT 24
Finished May 23 01:23:47 PM PDT 24
Peak memory 216352 kb
Host smart-d250f517-708a-42ae-b590-5d55bc814a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866532190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3866532190
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.375215759
Short name T857
Test name
Test status
Simulation time 1369884913 ps
CPU time 4.29 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:23:50 PM PDT 24
Peak memory 216380 kb
Host smart-4d19d936-db6b-4c55-b6ad-fe5381ac3ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375215759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.375215759
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.416048473
Short name T355
Test name
Test status
Simulation time 78420579 ps
CPU time 1.66 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:01 PM PDT 24
Peak memory 216312 kb
Host smart-e302d449-a46a-4935-a412-9e93fccc7bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416048473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.416048473
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2643169198
Short name T353
Test name
Test status
Simulation time 11439361 ps
CPU time 0.72 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 205468 kb
Host smart-5f8aabda-1519-4fc6-8a8a-649489da0d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643169198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2643169198
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2245867090
Short name T282
Test name
Test status
Simulation time 11838888522 ps
CPU time 14.63 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:24:03 PM PDT 24
Peak memory 233456 kb
Host smart-a562dad4-45db-438c-afa9-1a601f1f356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245867090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2245867090
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1520264618
Short name T868
Test name
Test status
Simulation time 15114615 ps
CPU time 0.73 seconds
Started May 23 01:25:04 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 205368 kb
Host smart-0f510a68-24c2-409a-a855-26a79cd221d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520264618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1520264618
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3633294644
Short name T216
Test name
Test status
Simulation time 566225519 ps
CPU time 4.35 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 218576 kb
Host smart-dad7a1d4-5d88-4117-9b8d-868e30f0f80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633294644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3633294644
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4041132856
Short name T511
Test name
Test status
Simulation time 60430304 ps
CPU time 0.73 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 205400 kb
Host smart-6ffae1fc-9aa9-4098-9c5a-147a0937c2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041132856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4041132856
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2042063894
Short name T258
Test name
Test status
Simulation time 20046963912 ps
CPU time 166.23 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:27:51 PM PDT 24
Peak memory 252140 kb
Host smart-00a6ba54-8bcc-4d96-8375-c086874a0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042063894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2042063894
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2360841436
Short name T255
Test name
Test status
Simulation time 13744864866 ps
CPU time 81.97 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:26:29 PM PDT 24
Peak memory 249328 kb
Host smart-b894f506-9b22-4106-b127-b73463dabc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360841436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2360841436
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1962616132
Short name T277
Test name
Test status
Simulation time 126152564621 ps
CPU time 305.11 seconds
Started May 23 01:25:02 PM PDT 24
Finished May 23 01:30:09 PM PDT 24
Peak memory 255120 kb
Host smart-3b0ecbd4-4ff1-46db-b2be-f02043057c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962616132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1962616132
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.45880902
Short name T791
Test name
Test status
Simulation time 497553803 ps
CPU time 5.89 seconds
Started May 23 01:25:02 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 232800 kb
Host smart-84d49c9c-d56f-4ddc-979f-4bc5e8d9350f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45880902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.45880902
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2875959413
Short name T577
Test name
Test status
Simulation time 1991716081 ps
CPU time 23.43 seconds
Started May 23 01:24:59 PM PDT 24
Finished May 23 01:25:25 PM PDT 24
Peak memory 218408 kb
Host smart-eb0c2071-ccd6-434f-94cb-a8ac9fe39405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875959413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2875959413
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2847756303
Short name T953
Test name
Test status
Simulation time 22880100795 ps
CPU time 52.86 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:26:02 PM PDT 24
Peak memory 222160 kb
Host smart-a878b240-887f-4da3-8dd9-d9b649ceda04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847756303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2847756303
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2982669817
Short name T555
Test name
Test status
Simulation time 7738753786 ps
CPU time 23.23 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:29 PM PDT 24
Peak memory 233876 kb
Host smart-c0566c30-305c-4ecb-97c1-bc5bc2dc45b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982669817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2982669817
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3655558257
Short name T617
Test name
Test status
Simulation time 372522734 ps
CPU time 2.32 seconds
Started May 23 01:25:02 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 218532 kb
Host smart-cc1a0d1f-9574-48dc-9531-5d6a3d4892be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655558257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3655558257
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2799219541
Short name T42
Test name
Test status
Simulation time 2990374015 ps
CPU time 11.72 seconds
Started May 23 01:25:02 PM PDT 24
Finished May 23 01:25:16 PM PDT 24
Peak memory 223132 kb
Host smart-445dce59-1d59-4a23-9769-700ca614363d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2799219541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2799219541
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4187895592
Short name T971
Test name
Test status
Simulation time 990219240 ps
CPU time 22.51 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:33 PM PDT 24
Peak memory 224524 kb
Host smart-7ced659b-88e3-4f68-8990-faf84a23719f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187895592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4187895592
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.296367967
Short name T782
Test name
Test status
Simulation time 38037910 ps
CPU time 0.72 seconds
Started May 23 01:25:02 PM PDT 24
Finished May 23 01:25:05 PM PDT 24
Peak memory 205448 kb
Host smart-0d65c897-a725-41f4-a099-d3fa1e962931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296367967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.296367967
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2686289826
Short name T721
Test name
Test status
Simulation time 882199016 ps
CPU time 4.98 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 216440 kb
Host smart-ecaa4936-7863-4542-908a-5a27287daf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686289826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2686289826
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4233442122
Short name T259
Test name
Test status
Simulation time 858797288 ps
CPU time 2.85 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 216308 kb
Host smart-f0d6f710-2b16-4846-ae8f-e57b03cbc113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233442122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4233442122
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3171562564
Short name T589
Test name
Test status
Simulation time 247052175 ps
CPU time 0.77 seconds
Started May 23 01:25:04 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 205772 kb
Host smart-5927b296-3390-4fe8-9d61-f40f5648f276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171562564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3171562564
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.932217956
Short name T159
Test name
Test status
Simulation time 2745031830 ps
CPU time 6.68 seconds
Started May 23 01:25:01 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 233584 kb
Host smart-b75fa8ae-fa32-4b33-83dc-f946fa14acd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932217956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.932217956
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3362761192
Short name T94
Test name
Test status
Simulation time 17216186 ps
CPU time 0.82 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 205012 kb
Host smart-0b98e1b7-ff14-4069-9c5d-b253d1358d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362761192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3362761192
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.207708583
Short name T743
Test name
Test status
Simulation time 938573745 ps
CPU time 13.82 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 219540 kb
Host smart-686d77ef-e27e-4fec-948b-472d29889e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207708583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.207708583
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.559940419
Short name T825
Test name
Test status
Simulation time 65761080 ps
CPU time 0.81 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 206392 kb
Host smart-6bf27ccf-e485-4aa4-a246-7b9a3bc9113e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559940419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.559940419
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1906319589
Short name T231
Test name
Test status
Simulation time 6331745713 ps
CPU time 81.86 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:26:30 PM PDT 24
Peak memory 257100 kb
Host smart-78d4ddc2-0916-4603-b08c-9c13235ace84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906319589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1906319589
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2875610577
Short name T131
Test name
Test status
Simulation time 271588441308 ps
CPU time 223.28 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:28:51 PM PDT 24
Peak memory 249376 kb
Host smart-14159ed1-18ba-4c83-9fd4-91955d67dd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875610577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2875610577
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1685273711
Short name T816
Test name
Test status
Simulation time 80905246 ps
CPU time 0.83 seconds
Started May 23 01:25:07 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 217148 kb
Host smart-ca0e0091-67ca-48d5-8d41-47803fe885e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685273711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1685273711
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2630680727
Short name T638
Test name
Test status
Simulation time 78372295 ps
CPU time 4.33 seconds
Started May 23 01:25:07 PM PDT 24
Finished May 23 01:25:13 PM PDT 24
Peak memory 232760 kb
Host smart-20e255e1-9db3-4c6d-a92e-d7e3b0cd2146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630680727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2630680727
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2293360911
Short name T82
Test name
Test status
Simulation time 433591650 ps
CPU time 2.47 seconds
Started May 23 01:25:03 PM PDT 24
Finished May 23 01:25:08 PM PDT 24
Peak memory 218732 kb
Host smart-785ce0f1-b613-4bd3-91f7-02b1a7ed3498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293360911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2293360911
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2464373390
Short name T628
Test name
Test status
Simulation time 37134816699 ps
CPU time 100.77 seconds
Started May 23 01:25:01 PM PDT 24
Finished May 23 01:26:44 PM PDT 24
Peak memory 217916 kb
Host smart-099013f5-5598-4889-b262-3053b6865987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464373390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2464373390
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3574349009
Short name T664
Test name
Test status
Simulation time 24047715171 ps
CPU time 21.57 seconds
Started May 23 01:25:04 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 228876 kb
Host smart-05b86492-40cd-42d7-8b5e-79923caa5880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574349009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3574349009
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1933356904
Short name T963
Test name
Test status
Simulation time 2871188536 ps
CPU time 5.08 seconds
Started May 23 01:25:04 PM PDT 24
Finished May 23 01:25:11 PM PDT 24
Peak memory 233308 kb
Host smart-adc8f999-5bfc-4fb0-9106-15fc5785a785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933356904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1933356904
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4060946333
Short name T749
Test name
Test status
Simulation time 606154923 ps
CPU time 3.92 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:14 PM PDT 24
Peak memory 223092 kb
Host smart-f891da78-221a-4900-90d1-b5883f110b82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4060946333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4060946333
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1368878880
Short name T972
Test name
Test status
Simulation time 15434037279 ps
CPU time 45.29 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 236780 kb
Host smart-21a44a4e-9162-4598-9e71-74a000fd9c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368878880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1368878880
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1814102358
Short name T938
Test name
Test status
Simulation time 24713342661 ps
CPU time 35.17 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 216488 kb
Host smart-4e9c6f89-d504-4a75-ba74-23a3b94763bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814102358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1814102358
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1165342176
Short name T965
Test name
Test status
Simulation time 9839903294 ps
CPU time 26.52 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:25:35 PM PDT 24
Peak memory 216516 kb
Host smart-dfbe525c-cd8c-4fd2-b396-dc2ebfba97c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165342176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1165342176
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3551757011
Short name T416
Test name
Test status
Simulation time 28383863 ps
CPU time 1.14 seconds
Started May 23 01:25:02 PM PDT 24
Finished May 23 01:25:06 PM PDT 24
Peak memory 216428 kb
Host smart-9949c034-202b-4a88-a543-a2e121af5f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551757011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3551757011
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3769199282
Short name T326
Test name
Test status
Simulation time 76152904 ps
CPU time 0.79 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:25:09 PM PDT 24
Peak memory 205764 kb
Host smart-3c50c944-ff99-4a1c-a0ac-8768d63a5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769199282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3769199282
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1370987002
Short name T861
Test name
Test status
Simulation time 1255385294 ps
CPU time 11.03 seconds
Started May 23 01:25:04 PM PDT 24
Finished May 23 01:25:17 PM PDT 24
Peak memory 232056 kb
Host smart-68f92915-0b1d-426d-9d75-ef20cf552a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370987002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1370987002
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.534167480
Short name T415
Test name
Test status
Simulation time 28584041 ps
CPU time 0.72 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:12 PM PDT 24
Peak memory 205364 kb
Host smart-5e03bfe2-12c7-4736-94be-a91a653fd5c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534167480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.534167480
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1228031132
Short name T958
Test name
Test status
Simulation time 843014249 ps
CPU time 4.93 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:12 PM PDT 24
Peak memory 233848 kb
Host smart-4c86022d-bf18-48d1-bd85-c40f1462e9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228031132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1228031132
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1502978597
Short name T897
Test name
Test status
Simulation time 16391200 ps
CPU time 0.77 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:11 PM PDT 24
Peak memory 205328 kb
Host smart-d3418d68-e6ed-4da1-82e8-134fee116b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502978597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1502978597
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3764954978
Short name T930
Test name
Test status
Simulation time 52626844222 ps
CPU time 415.02 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:32:07 PM PDT 24
Peak memory 271960 kb
Host smart-5b3d7873-fbc0-4b64-8ae7-dcaeb82b9a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764954978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3764954978
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3630453682
Short name T35
Test name
Test status
Simulation time 48538447985 ps
CPU time 464.62 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:32:57 PM PDT 24
Peak memory 268152 kb
Host smart-c9944b11-485d-4824-9f6a-ccaafb2be8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630453682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3630453682
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4116629830
Short name T526
Test name
Test status
Simulation time 5624201392 ps
CPU time 12.01 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 232960 kb
Host smart-ef620026-9502-47e5-a1f1-5b45852035e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116629830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4116629830
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2488433509
Short name T523
Test name
Test status
Simulation time 336365985 ps
CPU time 3.53 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:15 PM PDT 24
Peak memory 232692 kb
Host smart-8129da3b-58a1-42ad-b5b4-088d09393cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488433509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2488433509
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1502877760
Short name T778
Test name
Test status
Simulation time 1181017288 ps
CPU time 6.45 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:14 PM PDT 24
Peak memory 233372 kb
Host smart-3c464d59-37f7-49c0-acea-2f591620dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502877760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1502877760
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.942299099
Short name T765
Test name
Test status
Simulation time 480378277 ps
CPU time 2.74 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 224548 kb
Host smart-9aaf865f-f799-4794-889a-35ab3066302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942299099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.942299099
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2310170962
Short name T593
Test name
Test status
Simulation time 2322650495 ps
CPU time 9.65 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:20 PM PDT 24
Peak memory 233868 kb
Host smart-d875a655-66ac-42a1-a092-3c6b85f4dac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310170962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2310170962
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2582846929
Short name T976
Test name
Test status
Simulation time 8942437568 ps
CPU time 14.17 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 237528 kb
Host smart-da97bfe4-d39e-4696-828f-e57c2bdad186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582846929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2582846929
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2832836872
Short name T361
Test name
Test status
Simulation time 1029138534 ps
CPU time 6.75 seconds
Started May 23 01:25:09 PM PDT 24
Finished May 23 01:25:18 PM PDT 24
Peak memory 219080 kb
Host smart-9648c788-0128-4435-b0e3-84dfadc7b67b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2832836872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2832836872
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2653502638
Short name T164
Test name
Test status
Simulation time 2699405243 ps
CPU time 35.04 seconds
Started May 23 01:25:09 PM PDT 24
Finished May 23 01:25:46 PM PDT 24
Peak memory 232932 kb
Host smart-70b12922-b5d2-4f90-8f83-94bf552c3913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653502638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2653502638
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1763973523
Short name T592
Test name
Test status
Simulation time 4115292878 ps
CPU time 18.49 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 216568 kb
Host smart-f67fa087-c090-46a7-9464-b5b1f243cdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763973523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1763973523
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2842672141
Short name T521
Test name
Test status
Simulation time 1365800770 ps
CPU time 5.45 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:16 PM PDT 24
Peak memory 216336 kb
Host smart-531a0628-29d4-461e-8897-e02cf9981d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842672141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2842672141
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3439906388
Short name T942
Test name
Test status
Simulation time 20476625 ps
CPU time 0.69 seconds
Started May 23 01:25:06 PM PDT 24
Finished May 23 01:25:09 PM PDT 24
Peak memory 205424 kb
Host smart-b36754cf-cc0c-45d4-9a6c-fecb27d2c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439906388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3439906388
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3091101048
Short name T635
Test name
Test status
Simulation time 58956644 ps
CPU time 0.8 seconds
Started May 23 01:25:07 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 205772 kb
Host smart-83e71dec-ada2-4e57-93a4-24e7e227b3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091101048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3091101048
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.293894404
Short name T512
Test name
Test status
Simulation time 2875037290 ps
CPU time 7.04 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:17 PM PDT 24
Peak memory 224160 kb
Host smart-f07d0f0d-5042-403c-bc11-3dc8ea2a7ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293894404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.293894404
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1693714341
Short name T342
Test name
Test status
Simulation time 10919405 ps
CPU time 0.69 seconds
Started May 23 01:25:16 PM PDT 24
Finished May 23 01:25:18 PM PDT 24
Peak memory 204620 kb
Host smart-ae18a981-0f12-496f-8bde-3841fd6a00f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693714341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1693714341
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2121508613
Short name T204
Test name
Test status
Simulation time 787607886 ps
CPU time 5.82 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:18 PM PDT 24
Peak memory 235396 kb
Host smart-f576ff0d-712a-4fd5-860d-e41fb960686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121508613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2121508613
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4119596792
Short name T681
Test name
Test status
Simulation time 20644177 ps
CPU time 0.79 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:13 PM PDT 24
Peak memory 206484 kb
Host smart-588a56ee-c017-4ce6-812b-c16839418414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119596792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4119596792
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3413549631
Short name T174
Test name
Test status
Simulation time 1849604674 ps
CPU time 38.97 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:51 PM PDT 24
Peak memory 250372 kb
Host smart-a1d1e554-95fe-400c-a2ab-0ae18042920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413549631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3413549631
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1162317071
Short name T256
Test name
Test status
Simulation time 1081157040 ps
CPU time 27.42 seconds
Started May 23 01:25:07 PM PDT 24
Finished May 23 01:25:37 PM PDT 24
Peak memory 249276 kb
Host smart-6ed50366-048c-4a4a-b6e9-f7126ba242cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162317071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1162317071
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3737489692
Short name T631
Test name
Test status
Simulation time 648716897 ps
CPU time 6.65 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:18 PM PDT 24
Peak memory 219164 kb
Host smart-1cc99996-baa7-4d42-bb67-d1f8d806c906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737489692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3737489692
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3373279918
Short name T288
Test name
Test status
Simulation time 3839226763 ps
CPU time 33.51 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:45 PM PDT 24
Peak memory 232832 kb
Host smart-c6793bae-7774-4cf6-8354-2deac6273fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373279918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3373279918
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3202998600
Short name T881
Test name
Test status
Simulation time 1183800874 ps
CPU time 11.49 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:23 PM PDT 24
Peak memory 237472 kb
Host smart-a5bc52d2-91d3-4ad3-b68d-e7a4abe468dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202998600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3202998600
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.451569637
Short name T488
Test name
Test status
Simulation time 7232297064 ps
CPU time 22.8 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:34 PM PDT 24
Peak memory 241024 kb
Host smart-515ed7e1-90b4-4374-b76b-47a79e03160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451569637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.451569637
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.378666005
Short name T2
Test name
Test status
Simulation time 8086480143 ps
CPU time 15.56 seconds
Started May 23 01:25:05 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 227132 kb
Host smart-68a78701-2e2e-46dc-9377-3c9ceb7d8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378666005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.378666005
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.67083619
Short name T970
Test name
Test status
Simulation time 814198958 ps
CPU time 4.54 seconds
Started May 23 01:25:07 PM PDT 24
Finished May 23 01:25:14 PM PDT 24
Peak memory 233720 kb
Host smart-a8a35027-eb80-4a86-966b-f62c6262141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67083619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.67083619
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3761436536
Short name T827
Test name
Test status
Simulation time 747438548 ps
CPU time 11.43 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:23 PM PDT 24
Peak memory 222864 kb
Host smart-fc6c7164-e122-4621-92d2-5ad311fcd22e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3761436536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3761436536
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3940313886
Short name T148
Test name
Test status
Simulation time 74880058 ps
CPU time 1.11 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:13 PM PDT 24
Peak memory 206840 kb
Host smart-8c55c2dd-d596-496a-8395-e0b241883ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940313886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3940313886
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2366823141
Short name T427
Test name
Test status
Simulation time 1322190291 ps
CPU time 6 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:16 PM PDT 24
Peak memory 216304 kb
Host smart-63ca8470-70eb-4004-8346-7595eeb68f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366823141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2366823141
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1427775320
Short name T78
Test name
Test status
Simulation time 16969344053 ps
CPU time 14.29 seconds
Started May 23 01:25:10 PM PDT 24
Finished May 23 01:25:26 PM PDT 24
Peak memory 216528 kb
Host smart-67294a28-7702-4660-8fcf-881887fda18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427775320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1427775320
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3500182072
Short name T679
Test name
Test status
Simulation time 332233567 ps
CPU time 1.93 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:12 PM PDT 24
Peak memory 215772 kb
Host smart-c9d2087b-50fc-4a83-9d77-5d50f8e7fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500182072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3500182072
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3929058380
Short name T502
Test name
Test status
Simulation time 12459854 ps
CPU time 0.68 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 205440 kb
Host smart-bcfcfa2a-7ec8-4c80-b63c-011888192612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929058380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3929058380
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.4248839926
Short name T604
Test name
Test status
Simulation time 4009535305 ps
CPU time 5.12 seconds
Started May 23 01:25:08 PM PDT 24
Finished May 23 01:25:15 PM PDT 24
Peak memory 216708 kb
Host smart-bac5f9bc-b30e-4262-b8f6-5106462cb6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248839926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.4248839926
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1098672176
Short name T600
Test name
Test status
Simulation time 27438146 ps
CPU time 0.78 seconds
Started May 23 01:25:22 PM PDT 24
Finished May 23 01:25:26 PM PDT 24
Peak memory 205304 kb
Host smart-a6e9751e-8293-4383-ad92-13de7e30c511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098672176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1098672176
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.831728714
Short name T445
Test name
Test status
Simulation time 1790487541 ps
CPU time 8.82 seconds
Started May 23 01:25:16 PM PDT 24
Finished May 23 01:25:25 PM PDT 24
Peak memory 217748 kb
Host smart-c31afdfc-fe43-4813-92f8-7a1ed5af89be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831728714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.831728714
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3466005352
Short name T922
Test name
Test status
Simulation time 54311750 ps
CPU time 0.77 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 206716 kb
Host smart-9b457c10-53eb-4a69-b9c0-453d565605f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466005352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3466005352
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.928106138
Short name T601
Test name
Test status
Simulation time 123228406160 ps
CPU time 234.48 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:29:15 PM PDT 24
Peak memory 249884 kb
Host smart-33c74e97-4942-498d-b9d4-efb21e679326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928106138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.928106138
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.15992940
Short name T311
Test name
Test status
Simulation time 24125140401 ps
CPU time 81.22 seconds
Started May 23 01:25:22 PM PDT 24
Finished May 23 01:26:47 PM PDT 24
Peak memory 224716 kb
Host smart-bfdcd875-1d43-4806-9963-5761b1dc281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15992940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.15992940
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.438027100
Short name T171
Test name
Test status
Simulation time 318890558571 ps
CPU time 541.53 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:34:21 PM PDT 24
Peak memory 255248 kb
Host smart-3d4af4ff-e45b-48b1-a508-3022b5b2db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438027100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.438027100
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3542648333
Short name T362
Test name
Test status
Simulation time 244789475 ps
CPU time 6.69 seconds
Started May 23 01:25:16 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 224544 kb
Host smart-a2d25e58-7959-47b4-969e-2172de496e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542648333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3542648333
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1303820072
Short name T160
Test name
Test status
Simulation time 353424432 ps
CPU time 2.15 seconds
Started May 23 01:25:17 PM PDT 24
Finished May 23 01:25:20 PM PDT 24
Peak memory 216140 kb
Host smart-dd85df36-0363-4d4a-be7b-7d469802d5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303820072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1303820072
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.820456049
Short name T940
Test name
Test status
Simulation time 1021760908 ps
CPU time 11.89 seconds
Started May 23 01:25:21 PM PDT 24
Finished May 23 01:25:37 PM PDT 24
Peak memory 219504 kb
Host smart-1ad943e0-9eef-4269-a7e0-cbb5f77766cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820456049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.820456049
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1812236614
Short name T903
Test name
Test status
Simulation time 79349896 ps
CPU time 2.23 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 216128 kb
Host smart-9fd0148e-7bf5-4360-bdcb-e7fc633bf104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812236614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1812236614
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1902585731
Short name T447
Test name
Test status
Simulation time 462242319 ps
CPU time 2.85 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 233192 kb
Host smart-b5ff4861-4222-449a-a840-b19b4c334e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902585731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1902585731
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.926882122
Short name T360
Test name
Test status
Simulation time 246764183 ps
CPU time 3.74 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 218736 kb
Host smart-591b1aa9-2fdd-4966-a4da-ab56e39c3b1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=926882122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.926882122
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3657652494
Short name T912
Test name
Test status
Simulation time 1530923597 ps
CPU time 38.92 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:26:02 PM PDT 24
Peak memory 249276 kb
Host smart-39ed8b02-a9e1-4da7-8b2f-e3294a4195df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657652494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3657652494
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3152786522
Short name T4
Test name
Test status
Simulation time 12517161875 ps
CPU time 19.03 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:42 PM PDT 24
Peak memory 216516 kb
Host smart-2142b6c7-53c5-4726-873d-6ebc8fb152c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152786522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3152786522
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1549906466
Short name T349
Test name
Test status
Simulation time 2817483160 ps
CPU time 5.77 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:26 PM PDT 24
Peak memory 216512 kb
Host smart-bb57e9ae-6454-4c8e-b6e8-ba9c40eedb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549906466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1549906466
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3230724444
Short name T685
Test name
Test status
Simulation time 34614493 ps
CPU time 0.97 seconds
Started May 23 01:25:17 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 206960 kb
Host smart-89f15ee3-3124-4d4d-af8c-d69093d0a839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230724444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3230724444
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.918969069
Short name T904
Test name
Test status
Simulation time 498535144 ps
CPU time 0.86 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 205852 kb
Host smart-1352ad52-4f77-4b3f-bd36-8309eea04565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918969069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.918969069
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.955606924
Short name T294
Test name
Test status
Simulation time 278016346 ps
CPU time 4.38 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 236404 kb
Host smart-aef4ed14-75af-4c76-9753-e1e5a01a81ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955606924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.955606924
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3371638626
Short name T327
Test name
Test status
Simulation time 40098388 ps
CPU time 0.75 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:23 PM PDT 24
Peak memory 205380 kb
Host smart-c0ae990e-3b0a-4d8b-ace4-8ea278679307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371638626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3371638626
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1208581175
Short name T969
Test name
Test status
Simulation time 735581916 ps
CPU time 9.55 seconds
Started May 23 01:25:24 PM PDT 24
Finished May 23 01:25:36 PM PDT 24
Peak memory 224420 kb
Host smart-7fde774a-5ddc-4197-b6c7-3cfe2e8aa5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208581175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1208581175
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.966474108
Short name T158
Test name
Test status
Simulation time 33832289 ps
CPU time 0.76 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 205444 kb
Host smart-9fe12edc-aef6-4d5b-8cf8-0dfe6efa8ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966474108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.966474108
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.819978813
Short name T688
Test name
Test status
Simulation time 142931053086 ps
CPU time 264.9 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:29:48 PM PDT 24
Peak memory 248300 kb
Host smart-14d3a96e-cb17-45dd-8f09-5c4066880e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819978813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.819978813
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.330006775
Short name T197
Test name
Test status
Simulation time 4661293836 ps
CPU time 105.6 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:27:08 PM PDT 24
Peak memory 250468 kb
Host smart-e30cd1ad-3f89-40c3-9a3c-4681b116cefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330006775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.330006775
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2779138575
Short name T662
Test name
Test status
Simulation time 7706795055 ps
CPU time 18.56 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 224712 kb
Host smart-e317d31a-676c-43bf-b7cd-179b78f1674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779138575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2779138575
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3439861810
Short name T737
Test name
Test status
Simulation time 90692861 ps
CPU time 2.17 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 216132 kb
Host smart-1e85d8fd-1a1a-4283-993f-b23a2f3efb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439861810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3439861810
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1271225305
Short name T275
Test name
Test status
Simulation time 19549733350 ps
CPU time 132.94 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:27:32 PM PDT 24
Peak memory 218460 kb
Host smart-8331eea6-4727-4de4-bc92-f9baad770576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271225305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1271225305
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1037451990
Short name T935
Test name
Test status
Simulation time 16357361972 ps
CPU time 13.25 seconds
Started May 23 01:25:24 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 224680 kb
Host smart-3569a720-d9bd-4a50-a55b-474d1ca06025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037451990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1037451990
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1396917488
Short name T789
Test name
Test status
Simulation time 76369572 ps
CPU time 2.32 seconds
Started May 23 01:25:16 PM PDT 24
Finished May 23 01:25:19 PM PDT 24
Peak memory 218592 kb
Host smart-939c227e-74dc-4aef-b34b-2e480ad4b219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396917488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1396917488
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2599602336
Short name T404
Test name
Test status
Simulation time 1425249036 ps
CPU time 6.24 seconds
Started May 23 01:25:21 PM PDT 24
Finished May 23 01:25:31 PM PDT 24
Peak memory 220084 kb
Host smart-133e687f-f350-42e4-be98-04659587820b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2599602336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2599602336
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4293921522
Short name T431
Test name
Test status
Simulation time 158046360 ps
CPU time 0.95 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 217480 kb
Host smart-ff6898f3-69bb-495b-8e65-e9e83ee6461a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293921522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4293921522
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3177687351
Short name T724
Test name
Test status
Simulation time 4328164451 ps
CPU time 4.98 seconds
Started May 23 01:25:21 PM PDT 24
Finished May 23 01:25:30 PM PDT 24
Peak memory 216440 kb
Host smart-815cdbc3-bacb-440c-a21c-c22d1579a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177687351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3177687351
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2058571670
Short name T391
Test name
Test status
Simulation time 2416414902 ps
CPU time 5.37 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:25 PM PDT 24
Peak memory 216388 kb
Host smart-7208d1c7-4ed5-494b-9c1a-23d2f2bdd0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058571670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2058571670
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.305161745
Short name T318
Test name
Test status
Simulation time 64908916 ps
CPU time 1.14 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 216436 kb
Host smart-2694395e-4f4d-4841-9d9e-38a7a2ac1e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305161745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.305161745
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.539556083
Short name T408
Test name
Test status
Simulation time 13924642 ps
CPU time 0.73 seconds
Started May 23 01:25:22 PM PDT 24
Finished May 23 01:25:26 PM PDT 24
Peak memory 205412 kb
Host smart-59a6ec0b-8da8-457c-9561-747f1772fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539556083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.539556083
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3719598323
Short name T458
Test name
Test status
Simulation time 1608484001 ps
CPU time 8.71 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:30 PM PDT 24
Peak memory 233948 kb
Host smart-27e7ee13-7b36-44bc-907a-eebf414ec1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719598323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3719598323
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1296036368
Short name T31
Test name
Test status
Simulation time 25366976 ps
CPU time 0.72 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 205316 kb
Host smart-8b6d05e0-5551-4133-adbb-4befe445ace1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296036368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1296036368
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2646849468
Short name T702
Test name
Test status
Simulation time 947208846 ps
CPU time 5.18 seconds
Started May 23 01:25:21 PM PDT 24
Finished May 23 01:25:30 PM PDT 24
Peak memory 217764 kb
Host smart-c26ffcc9-cbfa-4196-824b-35dfb9df6f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646849468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2646849468
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.552227223
Short name T835
Test name
Test status
Simulation time 19035328 ps
CPU time 0.8 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:25 PM PDT 24
Peak memory 206452 kb
Host smart-6021d0b3-5339-45f1-a5df-5e7cd1360d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552227223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.552227223
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3964276029
Short name T123
Test name
Test status
Simulation time 81462194376 ps
CPU time 304.2 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:30:25 PM PDT 24
Peak memory 249220 kb
Host smart-cd4c82bf-95c7-4cff-bcad-12e13ffd4829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964276029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3964276029
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1028012310
Short name T309
Test name
Test status
Simulation time 17561280909 ps
CPU time 173.37 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:28:17 PM PDT 24
Peak memory 255488 kb
Host smart-d43dbad4-52be-4d2e-9559-f3a4c9e6077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028012310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1028012310
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.452227340
Short name T924
Test name
Test status
Simulation time 14435982584 ps
CPU time 53.13 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:26:16 PM PDT 24
Peak memory 252536 kb
Host smart-a10d9cdc-0884-45ee-8adc-776991caedfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452227340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.452227340
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2705738953
Short name T110
Test name
Test status
Simulation time 149602928 ps
CPU time 7.13 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:29 PM PDT 24
Peak memory 232784 kb
Host smart-4cf0b1e4-e21c-4d6d-891e-c358cc98dd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705738953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2705738953
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1511734089
Short name T194
Test name
Test status
Simulation time 1443742034 ps
CPU time 5.26 seconds
Started May 23 01:25:21 PM PDT 24
Finished May 23 01:25:30 PM PDT 24
Peak memory 236136 kb
Host smart-88428143-586d-4a54-a691-48946dec0241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511734089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1511734089
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3924558092
Short name T813
Test name
Test status
Simulation time 4921342340 ps
CPU time 19.25 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 233076 kb
Host smart-f6ea0b53-baaa-49ba-883f-e959a0c12a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924558092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3924558092
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3089822542
Short name T484
Test name
Test status
Simulation time 268094280 ps
CPU time 3.93 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 233848 kb
Host smart-5b89735d-d17a-4372-aab6-ff6581da8024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089822542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3089822542
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.160151691
Short name T491
Test name
Test status
Simulation time 2399282672 ps
CPU time 10.63 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:30 PM PDT 24
Peak memory 233536 kb
Host smart-ccb4c609-d3b8-4169-8dea-8492710ec236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160151691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.160151691
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2286815796
Short name T811
Test name
Test status
Simulation time 2141514857 ps
CPU time 13.25 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:33 PM PDT 24
Peak memory 220268 kb
Host smart-5471f502-62df-4e29-8baf-d7723f20d90a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2286815796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2286815796
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.590528754
Short name T952
Test name
Test status
Simulation time 45053639 ps
CPU time 0.96 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 205560 kb
Host smart-fd3e80dd-083c-46ee-8be2-4e68d91a9c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590528754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.590528754
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2512920499
Short name T314
Test name
Test status
Simulation time 4614290936 ps
CPU time 25.71 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 216500 kb
Host smart-d90c7f7b-311c-4d3a-8334-7699aa247a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512920499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2512920499
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3224007172
Short name T564
Test name
Test status
Simulation time 2294592116 ps
CPU time 11.31 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:34 PM PDT 24
Peak memory 216548 kb
Host smart-31d41ff1-8176-42ec-b192-d42dd8aec7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224007172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3224007172
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3954846829
Short name T365
Test name
Test status
Simulation time 65770052 ps
CPU time 1.09 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 207152 kb
Host smart-106c6d14-475b-49db-9556-58581e6e7a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954846829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3954846829
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3287425361
Short name T663
Test name
Test status
Simulation time 21739669 ps
CPU time 0.68 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:20 PM PDT 24
Peak memory 205492 kb
Host smart-a61b1678-75f8-4c8f-9c65-af3b27e523ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287425361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3287425361
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4134511611
Short name T467
Test name
Test status
Simulation time 3861433028 ps
CPU time 4.71 seconds
Started May 23 01:25:17 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 219032 kb
Host smart-7344fdc4-0612-4d0a-8abf-c75b13a218de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134511611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4134511611
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1183826474
Short name T824
Test name
Test status
Simulation time 14772523 ps
CPU time 0.72 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 204672 kb
Host smart-cba476c3-4df3-4521-b873-92eb716bb290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183826474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1183826474
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.176332235
Short name T419
Test name
Test status
Simulation time 489666100 ps
CPU time 2.17 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:25:28 PM PDT 24
Peak memory 218816 kb
Host smart-e4051831-d628-4b34-8293-cdd3e121bb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176332235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.176332235
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1938469653
Short name T341
Test name
Test status
Simulation time 39612534 ps
CPU time 0.81 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:25:27 PM PDT 24
Peak memory 206680 kb
Host smart-be42d62e-e3c6-4a7c-a118-fcf617106fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938469653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1938469653
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3901885860
Short name T808
Test name
Test status
Simulation time 7028633377 ps
CPU time 93.18 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:26:59 PM PDT 24
Peak memory 240988 kb
Host smart-4702fa93-cb77-4317-8b38-bd548f99f657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901885860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3901885860
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3953428919
Short name T800
Test name
Test status
Simulation time 3823917120 ps
CPU time 57.79 seconds
Started May 23 01:25:24 PM PDT 24
Finished May 23 01:26:25 PM PDT 24
Peak memory 253960 kb
Host smart-ddb2457d-27b2-4ebd-9fd7-0a6b55a5feb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953428919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3953428919
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3819885753
Short name T38
Test name
Test status
Simulation time 185409417219 ps
CPU time 388.86 seconds
Started May 23 01:25:24 PM PDT 24
Finished May 23 01:31:56 PM PDT 24
Peak memory 255148 kb
Host smart-d2a60f3c-9deb-40f4-bc57-ad26ae30f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819885753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3819885753
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1540724599
Short name T344
Test name
Test status
Simulation time 37511092480 ps
CPU time 32.55 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:25:59 PM PDT 24
Peak memory 249256 kb
Host smart-caf88070-c083-42ab-b8e3-29be5b0c733d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540724599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1540724599
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1785256703
Short name T849
Test name
Test status
Simulation time 131963337 ps
CPU time 2.81 seconds
Started May 23 01:25:19 PM PDT 24
Finished May 23 01:25:24 PM PDT 24
Peak memory 232708 kb
Host smart-d7ed217f-212c-4394-b009-863d99fb7521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785256703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1785256703
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3791820739
Short name T775
Test name
Test status
Simulation time 4597442463 ps
CPU time 40.77 seconds
Started May 23 01:25:22 PM PDT 24
Finished May 23 01:26:06 PM PDT 24
Peak memory 240328 kb
Host smart-a9b19cd4-bbc2-4e49-b133-b863cb24f207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791820739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3791820739
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4175161953
Short name T783
Test name
Test status
Simulation time 258712002 ps
CPU time 3.86 seconds
Started May 23 01:25:24 PM PDT 24
Finished May 23 01:25:31 PM PDT 24
Peak memory 233208 kb
Host smart-f76dddbc-eeba-4a45-a229-c8451447d563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175161953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4175161953
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1444299345
Short name T178
Test name
Test status
Simulation time 12593057563 ps
CPU time 22.13 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 233828 kb
Host smart-5a2d7478-a290-4165-b18e-6ddd0a1cd038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444299345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1444299345
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3203071861
Short name T899
Test name
Test status
Simulation time 113001952 ps
CPU time 4.22 seconds
Started May 23 01:25:24 PM PDT 24
Finished May 23 01:25:31 PM PDT 24
Peak memory 222376 kb
Host smart-7f0e9f08-d026-42ac-b2aa-fa5ad6b72550
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3203071861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3203071861
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2692313864
Short name T866
Test name
Test status
Simulation time 75608341928 ps
CPU time 364.04 seconds
Started May 23 01:25:21 PM PDT 24
Finished May 23 01:31:28 PM PDT 24
Peak memory 254808 kb
Host smart-c40b815d-145a-4e34-9946-1e9ee3fc6165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692313864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2692313864
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.792038131
Short name T615
Test name
Test status
Simulation time 6290101469 ps
CPU time 22.24 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:45 PM PDT 24
Peak memory 216428 kb
Host smart-4e4e53e0-c1d6-4bcf-b658-2862afc0b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792038131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.792038131
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1496027232
Short name T371
Test name
Test status
Simulation time 652827698 ps
CPU time 5.04 seconds
Started May 23 01:25:23 PM PDT 24
Finished May 23 01:25:31 PM PDT 24
Peak memory 216392 kb
Host smart-7f8f61b7-6207-447f-a93f-8a23b4ff181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496027232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1496027232
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.909765528
Short name T501
Test name
Test status
Simulation time 72111626 ps
CPU time 1.43 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:22 PM PDT 24
Peak memory 216344 kb
Host smart-07110da9-c517-4043-b06a-aa2453074af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909765528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.909765528
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1936313447
Short name T338
Test name
Test status
Simulation time 188497968 ps
CPU time 0.8 seconds
Started May 23 01:25:18 PM PDT 24
Finished May 23 01:25:21 PM PDT 24
Peak memory 205864 kb
Host smart-a72f53ae-ecd6-4762-888f-1a114beca293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936313447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1936313447
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3960604572
Short name T177
Test name
Test status
Simulation time 768604602 ps
CPU time 9.65 seconds
Started May 23 01:25:20 PM PDT 24
Finished May 23 01:25:33 PM PDT 24
Peak memory 239348 kb
Host smart-b00bb30a-2b33-4966-a0ea-ecc74f002306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960604572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3960604572
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1206227914
Short name T5
Test name
Test status
Simulation time 12025754 ps
CPU time 0.78 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 205660 kb
Host smart-3a2df0c5-c285-47de-aee9-cc16d0e6d899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206227914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1206227914
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2509147898
Short name T3
Test name
Test status
Simulation time 964070387 ps
CPU time 9.56 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:49 PM PDT 24
Peak memory 233560 kb
Host smart-c6e1bcbc-9db4-4d3b-8cad-e9e5a65efc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509147898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2509147898
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1508164575
Short name T320
Test name
Test status
Simulation time 73034413 ps
CPU time 0.77 seconds
Started May 23 01:25:17 PM PDT 24
Finished May 23 01:25:18 PM PDT 24
Peak memory 206460 kb
Host smart-97356dff-a26f-4e04-a144-4afd4a1e01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508164575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1508164575
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.593196991
Short name T640
Test name
Test status
Simulation time 7732072448 ps
CPU time 55.8 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:26:30 PM PDT 24
Peak memory 241092 kb
Host smart-892cf987-c61b-4e43-bf78-a32b5d35aff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593196991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.593196991
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3071467110
Short name T252
Test name
Test status
Simulation time 8976609532 ps
CPU time 57.78 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:26:33 PM PDT 24
Peak memory 250416 kb
Host smart-92dacfda-4451-4390-9689-0f06c0bab22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071467110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3071467110
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.949799743
Short name T833
Test name
Test status
Simulation time 4085305692 ps
CPU time 53.23 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:31 PM PDT 24
Peak memory 249444 kb
Host smart-19639621-c266-4ea3-a83f-548468921be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949799743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.949799743
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2264696608
Short name T697
Test name
Test status
Simulation time 3708524343 ps
CPU time 21.23 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:00 PM PDT 24
Peak memory 232804 kb
Host smart-e61cd104-30e3-4810-aed8-d0293721d621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264696608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2264696608
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1157504609
Short name T852
Test name
Test status
Simulation time 257763210 ps
CPU time 6.18 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:42 PM PDT 24
Peak memory 233508 kb
Host smart-eb74f866-222b-485d-aeb7-bf60ef5eccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157504609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1157504609
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1761407620
Short name T889
Test name
Test status
Simulation time 11885454864 ps
CPU time 53.98 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:26:29 PM PDT 24
Peak memory 224544 kb
Host smart-3237f16b-a9f6-43a8-b876-494eaccff8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761407620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1761407620
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1911131915
Short name T720
Test name
Test status
Simulation time 2609379596 ps
CPU time 10.87 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:49 PM PDT 24
Peak memory 227716 kb
Host smart-e91a55e4-b777-4c79-b361-805b94d0249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911131915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1911131915
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2745174259
Short name T829
Test name
Test status
Simulation time 449144869 ps
CPU time 3.83 seconds
Started May 23 01:25:37 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 218348 kb
Host smart-867efbd7-4c7b-4dfd-b41d-41b62a61a42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745174259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2745174259
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2607315665
Short name T83
Test name
Test status
Simulation time 735727669 ps
CPU time 7.65 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:25:41 PM PDT 24
Peak memory 222000 kb
Host smart-bcad12bb-f17b-4c72-87d3-d369847fdc53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2607315665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2607315665
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2660878826
Short name T841
Test name
Test status
Simulation time 6980697029 ps
CPU time 30.39 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 216512 kb
Host smart-d7b35c76-75a7-4b94-a160-1d86521af3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660878826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2660878826
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3546108142
Short name T820
Test name
Test status
Simulation time 1398631906 ps
CPU time 4.82 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:42 PM PDT 24
Peak memory 216232 kb
Host smart-2be69e7e-8734-435c-bb95-f726b3f89fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546108142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3546108142
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2099577083
Short name T508
Test name
Test status
Simulation time 23441085 ps
CPU time 0.79 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:36 PM PDT 24
Peak memory 206664 kb
Host smart-b523ef64-0964-4189-900f-ecbaebabd869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099577083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2099577083
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.866845151
Short name T708
Test name
Test status
Simulation time 405128357 ps
CPU time 0.97 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:38 PM PDT 24
Peak memory 205796 kb
Host smart-a8805dab-da39-41da-91ae-8448eae80d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866845151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.866845151
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4083281321
Short name T480
Test name
Test status
Simulation time 376480770 ps
CPU time 6.36 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:45 PM PDT 24
Peak memory 232680 kb
Host smart-6d731edb-2006-4200-b088-811af1e09765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083281321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4083281321
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3658545271
Short name T319
Test name
Test status
Simulation time 34475346 ps
CPU time 0.73 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:25:35 PM PDT 24
Peak memory 204692 kb
Host smart-34bcc039-2623-404d-8425-e9b318142153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658545271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3658545271
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1502321439
Short name T462
Test name
Test status
Simulation time 1019083370 ps
CPU time 11.14 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 219628 kb
Host smart-e135bdc7-5f43-4f5f-a26d-795cda92c3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502321439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1502321439
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1219174596
Short name T335
Test name
Test status
Simulation time 27887940 ps
CPU time 0.8 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:38 PM PDT 24
Peak memory 206728 kb
Host smart-98e520e6-6882-4d0a-8049-03cbc0a9d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219174596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1219174596
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2016051141
Short name T225
Test name
Test status
Simulation time 63676031936 ps
CPU time 419.42 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:32:35 PM PDT 24
Peak memory 255108 kb
Host smart-3abcf2cc-66db-4e29-b7b6-a06ef1bf27d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016051141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2016051141
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4030641754
Short name T481
Test name
Test status
Simulation time 3149277660 ps
CPU time 73.3 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:51 PM PDT 24
Peak memory 249332 kb
Host smart-d56dac80-5239-4381-a183-a089740dc3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030641754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4030641754
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.634728781
Short name T41
Test name
Test status
Simulation time 15025627477 ps
CPU time 73.43 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:52 PM PDT 24
Peak memory 251712 kb
Host smart-96be81a6-879d-4a09-8d85-9864574152c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634728781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.634728781
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2481966774
Short name T869
Test name
Test status
Simulation time 604723658 ps
CPU time 2.83 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:42 PM PDT 24
Peak memory 229376 kb
Host smart-a82ca262-4d90-43c1-adf0-cf77e8dba90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481966774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2481966774
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3422357722
Short name T495
Test name
Test status
Simulation time 6090607598 ps
CPU time 11.66 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:50 PM PDT 24
Peak memory 233916 kb
Host smart-ea805eb7-ede3-488d-825e-767dd082400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422357722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3422357722
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1364716084
Short name T626
Test name
Test status
Simulation time 10557994336 ps
CPU time 76 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:54 PM PDT 24
Peak memory 234204 kb
Host smart-65b6e452-5b8c-49a4-89e9-5a76f39d7a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364716084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1364716084
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3186687474
Short name T571
Test name
Test status
Simulation time 1518070727 ps
CPU time 4.28 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:25:38 PM PDT 24
Peak memory 219660 kb
Host smart-ca2ffccd-8198-46d9-8299-5ef6da056028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186687474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3186687474
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3586878459
Short name T529
Test name
Test status
Simulation time 2238386340 ps
CPU time 4.83 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:42 PM PDT 24
Peak memory 218904 kb
Host smart-257de08b-e231-4735-bbbc-848b7917c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586878459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3586878459
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2081025732
Short name T649
Test name
Test status
Simulation time 151647460 ps
CPU time 3.91 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 222964 kb
Host smart-8cb7ae55-bcab-45f5-a9f6-092c1322b0da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2081025732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2081025732
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3085823305
Short name T207
Test name
Test status
Simulation time 66021461616 ps
CPU time 569.68 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:35:04 PM PDT 24
Peak memory 254032 kb
Host smart-448fd5cc-f9e5-4cf7-a72d-b685cb08a333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085823305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3085823305
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.166062601
Short name T17
Test name
Test status
Simulation time 3515377005 ps
CPU time 20.31 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 216572 kb
Host smart-8a59ada7-b193-4bc7-bc26-a428198a27b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166062601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.166062601
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2035036120
Short name T485
Test name
Test status
Simulation time 25099573510 ps
CPU time 17.42 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:56 PM PDT 24
Peak memory 216432 kb
Host smart-a524a907-cc8a-4f6f-bb47-93448be784e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035036120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2035036120
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1965819039
Short name T656
Test name
Test status
Simulation time 68377887 ps
CPU time 1.27 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:37 PM PDT 24
Peak memory 208012 kb
Host smart-b3143327-0e8d-413c-87fa-4822c3ec4ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965819039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1965819039
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2524396137
Short name T887
Test name
Test status
Simulation time 82889202 ps
CPU time 0.85 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 205744 kb
Host smart-98eeca2d-d9eb-45dd-b719-d81d1599c102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524396137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2524396137
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3111442941
Short name T162
Test name
Test status
Simulation time 551320545 ps
CPU time 3.84 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:41 PM PDT 24
Peak memory 217392 kb
Host smart-23a6b713-803b-4b80-b6ac-eca6fc276944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111442941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3111442941
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2108183288
Short name T629
Test name
Test status
Simulation time 15181952 ps
CPU time 0.75 seconds
Started May 23 01:23:50 PM PDT 24
Finished May 23 01:23:53 PM PDT 24
Peak memory 205400 kb
Host smart-f932fe32-1f19-4e11-a7d1-cf0188faecb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108183288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
108183288
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1552931816
Short name T906
Test name
Test status
Simulation time 89770287 ps
CPU time 2.43 seconds
Started May 23 01:23:42 PM PDT 24
Finished May 23 01:23:45 PM PDT 24
Peak memory 218632 kb
Host smart-09cab83b-7bfb-4fa0-86ab-ac0f470cf5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552931816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1552931816
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2485827223
Short name T487
Test name
Test status
Simulation time 31023899 ps
CPU time 0.82 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:23:46 PM PDT 24
Peak memory 206464 kb
Host smart-6e4637a6-e5a3-416b-90b1-bab10824247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485827223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2485827223
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.612117982
Short name T951
Test name
Test status
Simulation time 22943001 ps
CPU time 0.77 seconds
Started May 23 01:23:47 PM PDT 24
Finished May 23 01:23:49 PM PDT 24
Peak memory 215868 kb
Host smart-5aa1c45b-4e70-4e42-9d79-d12c2787384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612117982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.612117982
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2569764643
Short name T860
Test name
Test status
Simulation time 29964115641 ps
CPU time 102.43 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:25:28 PM PDT 24
Peak memory 249388 kb
Host smart-8bb8e47f-bd28-4458-b2c1-d9a21a98aaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569764643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2569764643
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1247672448
Short name T444
Test name
Test status
Simulation time 817267159 ps
CPU time 7.04 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 234032 kb
Host smart-60dc35da-0d83-44a2-9c0e-8b8fbc691dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247672448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1247672448
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3338315022
Short name T891
Test name
Test status
Simulation time 411381971 ps
CPU time 4.58 seconds
Started May 23 01:23:57 PM PDT 24
Finished May 23 01:24:03 PM PDT 24
Peak memory 232816 kb
Host smart-835be5da-1538-4939-a8d8-a14d91ccc330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338315022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3338315022
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.693043182
Short name T517
Test name
Test status
Simulation time 2535949547 ps
CPU time 26.66 seconds
Started May 23 01:23:57 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 236732 kb
Host smart-e250acb8-20c7-45ef-9cf4-e168f3ec741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693043182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.693043182
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3790213152
Short name T411
Test name
Test status
Simulation time 69170559 ps
CPU time 1.02 seconds
Started May 23 01:23:41 PM PDT 24
Finished May 23 01:23:43 PM PDT 24
Peak memory 216688 kb
Host smart-8151f6d7-1af8-46e0-847b-df3c20225755
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790213152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3790213152
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2229808888
Short name T719
Test name
Test status
Simulation time 19683162314 ps
CPU time 18.11 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 248356 kb
Host smart-ccec6930-e213-4db4-a441-ecc0157c91f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229808888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2229808888
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3503121736
Short name T213
Test name
Test status
Simulation time 469168864 ps
CPU time 2.86 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 232652 kb
Host smart-e3df91cd-f4e6-4515-b28b-5ec77454990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503121736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3503121736
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3216414784
Short name T345
Test name
Test status
Simulation time 127993899 ps
CPU time 4.16 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:03 PM PDT 24
Peak memory 223052 kb
Host smart-d813074f-1957-4510-9126-7a7e59ef7fab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3216414784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3216414784
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1150337045
Short name T65
Test name
Test status
Simulation time 31527647 ps
CPU time 0.99 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:23:46 PM PDT 24
Peak memory 234804 kb
Host smart-b872d68f-8026-4a90-a295-09425da4731d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150337045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1150337045
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2009448214
Short name T32
Test name
Test status
Simulation time 99493991173 ps
CPU time 293.26 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:28:43 PM PDT 24
Peak memory 264656 kb
Host smart-49b16935-7f29-4151-b5c8-a54d495225b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009448214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2009448214
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4197829969
Short name T776
Test name
Test status
Simulation time 11942555 ps
CPU time 0.82 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:50 PM PDT 24
Peak memory 205488 kb
Host smart-7e72e30e-9897-4885-ae19-e58ae4882cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197829969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4197829969
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2814944085
Short name T729
Test name
Test status
Simulation time 96225758 ps
CPU time 1.22 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:00 PM PDT 24
Peak memory 206920 kb
Host smart-2df3798d-987a-4a3f-abd8-50885ddbc09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814944085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2814944085
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2854949079
Short name T313
Test name
Test status
Simulation time 102109831 ps
CPU time 2.03 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:23:49 PM PDT 24
Peak memory 216532 kb
Host smart-715854bc-e0b0-441f-b48b-31c09d326d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854949079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2854949079
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2353273250
Short name T436
Test name
Test status
Simulation time 56837619 ps
CPU time 0.85 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 205820 kb
Host smart-2505d698-4877-4d36-9af4-990f8da7be95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353273250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2353273250
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.65586474
Short name T218
Test name
Test status
Simulation time 890325795 ps
CPU time 4.38 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:23:56 PM PDT 24
Peak memory 235040 kb
Host smart-3089a2ac-48b9-477f-ae47-1e11daab69e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65586474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.65586474
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.332973618
Short name T395
Test name
Test status
Simulation time 13028285 ps
CPU time 0.72 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:37 PM PDT 24
Peak memory 205704 kb
Host smart-5f3d175e-3f49-451b-80b2-3d8bc452bdb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332973618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.332973618
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.80079515
Short name T191
Test name
Test status
Simulation time 586699200 ps
CPU time 9.16 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 224400 kb
Host smart-680f4e14-bdf8-4f68-9226-a23b0b7e00f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80079515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.80079515
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.56021017
Short name T875
Test name
Test status
Simulation time 51570333 ps
CPU time 0.75 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 205344 kb
Host smart-1c99d3b6-44b4-4141-a5ef-c3200143f8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56021017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.56021017
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2069187475
Short name T424
Test name
Test status
Simulation time 987318082 ps
CPU time 5.36 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:44 PM PDT 24
Peak memory 234668 kb
Host smart-d8d33451-7ca8-4fcd-9505-ff48e112db49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069187475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2069187475
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3869818667
Short name T978
Test name
Test status
Simulation time 69481621865 ps
CPU time 304.22 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:30:43 PM PDT 24
Peak memory 249312 kb
Host smart-409a2249-fbc3-433c-a789-3c031e06d8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869818667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3869818667
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3525433037
Short name T853
Test name
Test status
Simulation time 72283913331 ps
CPU time 143.06 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:28:01 PM PDT 24
Peak memory 249388 kb
Host smart-0fbf43c8-d45d-4bc0-a391-d28b35e1b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525433037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3525433037
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.520636816
Short name T370
Test name
Test status
Simulation time 602920698 ps
CPU time 7.45 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:46 PM PDT 24
Peak memory 224568 kb
Host smart-482e9d61-b8ed-4f40-a1b8-bcafd2b17a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520636816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.520636816
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2012516912
Short name T802
Test name
Test status
Simulation time 82368019 ps
CPU time 2.86 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 235208 kb
Host smart-d1cdfdbc-ea03-4470-9a33-7b9c75c4f4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012516912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2012516912
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3317549287
Short name T474
Test name
Test status
Simulation time 1359259468 ps
CPU time 4.11 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 217632 kb
Host smart-0e6817d0-982f-42b0-9bf5-7402910b6105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317549287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3317549287
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1984921311
Short name T905
Test name
Test status
Simulation time 3160400872 ps
CPU time 6.61 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 233872 kb
Host smart-23d0617c-863e-42ff-97c5-de8553bc42b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984921311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1984921311
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3636503493
Short name T210
Test name
Test status
Simulation time 501499138 ps
CPU time 2.62 seconds
Started May 23 01:25:34 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 218392 kb
Host smart-5ddfc82c-2986-4784-bab7-97c888e5a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636503493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3636503493
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.884381407
Short name T50
Test name
Test status
Simulation time 205601557 ps
CPU time 5.04 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:43 PM PDT 24
Peak memory 222844 kb
Host smart-0ce0a35e-9af8-4a15-b6d3-02507bb9828c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=884381407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.884381407
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3479426837
Short name T932
Test name
Test status
Simulation time 3549476647 ps
CPU time 45.04 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:26:24 PM PDT 24
Peak memory 232968 kb
Host smart-4c47be06-a2c6-46d8-91b1-27def561fc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479426837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3479426837
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3773347574
Short name T772
Test name
Test status
Simulation time 4481206971 ps
CPU time 18.42 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 220528 kb
Host smart-09aa55fb-e119-443c-939c-2961c6bffe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773347574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3773347574
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2691302149
Short name T908
Test name
Test status
Simulation time 997722378 ps
CPU time 5.02 seconds
Started May 23 01:25:33 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 216400 kb
Host smart-376a41e5-d2f4-42c5-8b8a-7395de53cd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691302149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2691302149
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3365047148
Short name T363
Test name
Test status
Simulation time 151393658 ps
CPU time 2.06 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 216236 kb
Host smart-830751b7-dbf6-4678-8650-411d6225a05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365047148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3365047148
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2546461246
Short name T367
Test name
Test status
Simulation time 25934304 ps
CPU time 0.85 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 205740 kb
Host smart-08591cf8-9602-4117-b21a-22f7ae4f62d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546461246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2546461246
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3631398711
Short name T947
Test name
Test status
Simulation time 50114516900 ps
CPU time 21.45 seconds
Started May 23 01:25:37 PM PDT 24
Finished May 23 01:26:01 PM PDT 24
Peak memory 226876 kb
Host smart-83de2419-904d-474f-9302-80f9d83e6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631398711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3631398711
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1604575762
Short name T943
Test name
Test status
Simulation time 24267017 ps
CPU time 0.76 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 205296 kb
Host smart-86614abb-f9ed-470a-a54d-545647c07b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604575762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1604575762
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1184237892
Short name T620
Test name
Test status
Simulation time 429068702 ps
CPU time 3.49 seconds
Started May 23 01:25:45 PM PDT 24
Finished May 23 01:25:50 PM PDT 24
Peak memory 218632 kb
Host smart-f94da68d-fb22-4cb0-9eb8-8961c11ff2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184237892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1184237892
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2552343283
Short name T764
Test name
Test status
Simulation time 203345580 ps
CPU time 0.84 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:40 PM PDT 24
Peak memory 206456 kb
Host smart-44ec7285-18d4-42da-b1b0-91966d81cd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552343283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2552343283
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3761057674
Short name T248
Test name
Test status
Simulation time 194584416695 ps
CPU time 192.19 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:29:02 PM PDT 24
Peak memory 254008 kb
Host smart-bbbde3d8-68c2-4187-bebb-f8ab8a08cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761057674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3761057674
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2037305872
Short name T742
Test name
Test status
Simulation time 56238045736 ps
CPU time 127.16 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:28:01 PM PDT 24
Peak memory 252564 kb
Host smart-1f5c68bf-2b6b-450d-926f-60809d3663ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037305872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2037305872
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2079713285
Short name T221
Test name
Test status
Simulation time 23027630310 ps
CPU time 154.71 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:28:26 PM PDT 24
Peak memory 264920 kb
Host smart-9ccc36d0-98fb-4e17-a892-15859d90c36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079713285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2079713285
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3835055376
Short name T298
Test name
Test status
Simulation time 3909135755 ps
CPU time 18.1 seconds
Started May 23 01:25:45 PM PDT 24
Finished May 23 01:26:04 PM PDT 24
Peak memory 232896 kb
Host smart-39a392fc-8be6-49ec-8247-979ce3ce4468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835055376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3835055376
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1842082112
Short name T334
Test name
Test status
Simulation time 422215649 ps
CPU time 2.21 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:41 PM PDT 24
Peak memory 220960 kb
Host smart-c5267059-4900-4665-ac2f-05a12c143ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842082112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1842082112
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4136112861
Short name T793
Test name
Test status
Simulation time 27884645600 ps
CPU time 59.45 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:26:38 PM PDT 24
Peak memory 231992 kb
Host smart-7d52d990-7c37-4375-95dd-352e35a7fe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136112861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4136112861
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4248942148
Short name T821
Test name
Test status
Simulation time 10724296200 ps
CPU time 29.73 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:26:08 PM PDT 24
Peak memory 234304 kb
Host smart-711dd4d7-16a5-40e0-a582-2e14300193d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248942148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4248942148
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3166788752
Short name T562
Test name
Test status
Simulation time 25674863466 ps
CPU time 10.22 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 219412 kb
Host smart-2002f162-71e6-4824-b57e-0ca99c807d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166788752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3166788752
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.626902616
Short name T139
Test name
Test status
Simulation time 5122286359 ps
CPU time 14.94 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 222624 kb
Host smart-3caf0034-ccdb-4d55-9500-0baaca145639
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=626902616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.626902616
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2033356450
Short name T632
Test name
Test status
Simulation time 1910978826 ps
CPU time 3.5 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:42 PM PDT 24
Peak memory 216428 kb
Host smart-82874f00-869d-4985-aaff-962eefbfae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033356450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2033356450
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1532769101
Short name T710
Test name
Test status
Simulation time 6001368473 ps
CPU time 8.26 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:46 PM PDT 24
Peak memory 216472 kb
Host smart-73614ff6-03b5-4862-8a96-52a893951ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532769101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1532769101
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2257878472
Short name T807
Test name
Test status
Simulation time 350695764 ps
CPU time 2.05 seconds
Started May 23 01:25:36 PM PDT 24
Finished May 23 01:25:41 PM PDT 24
Peak memory 216372 kb
Host smart-c02abee5-c7ca-45f8-bebd-f1780d9c2760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257878472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2257878472
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1638348922
Short name T383
Test name
Test status
Simulation time 39618945 ps
CPU time 0.8 seconds
Started May 23 01:25:35 PM PDT 24
Finished May 23 01:25:39 PM PDT 24
Peak memory 205868 kb
Host smart-e3398ec5-cb28-4250-8e47-9b9efd6d2f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638348922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1638348922
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1445243052
Short name T661
Test name
Test status
Simulation time 210303779 ps
CPU time 2.47 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 207872 kb
Host smart-6b19d792-a64c-411d-9e7a-91e7b0f80adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445243052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1445243052
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4273737621
Short name T496
Test name
Test status
Simulation time 21423458 ps
CPU time 0.82 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:25:51 PM PDT 24
Peak memory 205412 kb
Host smart-0cddff30-1275-4d88-b13a-7726cb3147a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273737621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4273737621
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.825051315
Short name T770
Test name
Test status
Simulation time 3750793978 ps
CPU time 8.45 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:00 PM PDT 24
Peak memory 218972 kb
Host smart-fa54a1ad-5270-4339-af6e-75eff966bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825051315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.825051315
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1659825633
Short name T784
Test name
Test status
Simulation time 93734446 ps
CPU time 0.77 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 205440 kb
Host smart-cc1cf824-a372-4adb-bf5f-f93b9d570d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659825633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1659825633
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2826932909
Short name T39
Test name
Test status
Simulation time 5176673214 ps
CPU time 31.78 seconds
Started May 23 01:25:46 PM PDT 24
Finished May 23 01:26:19 PM PDT 24
Peak memory 241208 kb
Host smart-ae55a9e5-d36d-4961-9b37-52820b37375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826932909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2826932909
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1647544810
Short name T948
Test name
Test status
Simulation time 398144228825 ps
CPU time 543.93 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:34:56 PM PDT 24
Peak memory 256316 kb
Host smart-326621d3-3199-457b-b480-890f2ff885c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647544810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1647544810
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3480698511
Short name T902
Test name
Test status
Simulation time 3387094084 ps
CPU time 60.29 seconds
Started May 23 01:25:52 PM PDT 24
Finished May 23 01:26:55 PM PDT 24
Peak memory 249400 kb
Host smart-043ad501-b421-4905-98a4-9470f806551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480698511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3480698511
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.625173908
Short name T466
Test name
Test status
Simulation time 1132248627 ps
CPU time 6.41 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:26:00 PM PDT 24
Peak memory 240860 kb
Host smart-da62e509-cb79-4e64-b8c7-9d1530007873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625173908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.625173908
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2993834582
Short name T794
Test name
Test status
Simulation time 4180971100 ps
CPU time 11.19 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:03 PM PDT 24
Peak memory 238016 kb
Host smart-d84e8f00-f131-4a6a-a41b-cbc04243e252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993834582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2993834582
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3950956075
Short name T756
Test name
Test status
Simulation time 5366739893 ps
CPU time 26.74 seconds
Started May 23 01:25:45 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 233572 kb
Host smart-6c3c3e22-bbbd-4b48-afac-55e17b32ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950956075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3950956075
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.106296898
Short name T222
Test name
Test status
Simulation time 7770854356 ps
CPU time 21.41 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:13 PM PDT 24
Peak memory 230036 kb
Host smart-eac3690b-ce08-4044-9db5-924666c4c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106296898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.106296898
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.4200431907
Short name T402
Test name
Test status
Simulation time 42164151564 ps
CPU time 17.7 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:26:11 PM PDT 24
Peak memory 233592 kb
Host smart-ef6196a2-6394-4cc1-804c-55a40c290e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200431907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.4200431907
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1130288120
Short name T498
Test name
Test status
Simulation time 866583261 ps
CPU time 11.69 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:26:01 PM PDT 24
Peak memory 222908 kb
Host smart-b02c9687-cc6a-4c5c-bed4-e4a913523609
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1130288120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1130288120
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3798380494
Short name T878
Test name
Test status
Simulation time 1593849471 ps
CPU time 17.03 seconds
Started May 23 01:25:46 PM PDT 24
Finished May 23 01:26:04 PM PDT 24
Peak memory 216360 kb
Host smart-75c78225-bb2c-49c3-aaad-20b6d17bf452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798380494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3798380494
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.192936436
Short name T839
Test name
Test status
Simulation time 8520221573 ps
CPU time 24.61 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:17 PM PDT 24
Peak memory 216508 kb
Host smart-bba94357-11ae-4430-ac4d-8e163f10c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192936436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.192936436
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3967495267
Short name T890
Test name
Test status
Simulation time 30810238 ps
CPU time 1.7 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:25:56 PM PDT 24
Peak memory 216384 kb
Host smart-ad09fb82-1ee0-4dba-8cda-43a02c1c6dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967495267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3967495267
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2573264641
Short name T752
Test name
Test status
Simulation time 38100264 ps
CPU time 0.81 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:25:50 PM PDT 24
Peak memory 205840 kb
Host smart-daea0291-c51e-458f-99e5-b124b3f4913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573264641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2573264641
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.76813955
Short name T203
Test name
Test status
Simulation time 6070729773 ps
CPU time 20.15 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:13 PM PDT 24
Peak memory 237916 kb
Host smart-c22ec01a-5107-4339-aba6-f0f8c20b595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76813955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.76813955
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4099740877
Short name T60
Test name
Test status
Simulation time 121683426 ps
CPU time 0.71 seconds
Started May 23 01:25:45 PM PDT 24
Finished May 23 01:25:47 PM PDT 24
Peak memory 205368 kb
Host smart-352267ea-ddd0-49c7-bb5f-93e01cb24ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099740877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4099740877
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3627755262
Short name T722
Test name
Test status
Simulation time 4308234301 ps
CPU time 12.89 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:26:05 PM PDT 24
Peak memory 219804 kb
Host smart-d8594c06-d7a2-45ce-9769-2db0470b9ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627755262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3627755262
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2440770448
Short name T329
Test name
Test status
Simulation time 46619417 ps
CPU time 0.76 seconds
Started May 23 01:25:46 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 206468 kb
Host smart-6637ec27-ef37-45f3-98f1-8594db3a607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440770448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2440770448
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4046068241
Short name T643
Test name
Test status
Simulation time 4043835409 ps
CPU time 37.44 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:29 PM PDT 24
Peak memory 241004 kb
Host smart-e4619a93-df61-4b30-8590-36859712edd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046068241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4046068241
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2430701311
Short name T767
Test name
Test status
Simulation time 3127609757 ps
CPU time 67.22 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:26:56 PM PDT 24
Peak memory 240428 kb
Host smart-e374354c-7dad-4512-be2b-79bc85c221a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430701311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2430701311
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.987754713
Short name T301
Test name
Test status
Simulation time 401642679 ps
CPU time 7.14 seconds
Started May 23 01:25:46 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 242336 kb
Host smart-5120b732-2ce0-4684-aeac-4bc4bee8ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987754713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.987754713
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.161297635
Short name T623
Test name
Test status
Simulation time 889759719 ps
CPU time 4.04 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 218364 kb
Host smart-810248f5-18a6-4c70-bc85-21d8fc4d39d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161297635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.161297635
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3909985789
Short name T410
Test name
Test status
Simulation time 108325998 ps
CPU time 2.35 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 216056 kb
Host smart-af2c061d-0431-4b14-af78-964ffbda150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909985789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3909985789
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.614443798
Short name T14
Test name
Test status
Simulation time 49142527255 ps
CPU time 9.45 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:02 PM PDT 24
Peak memory 229360 kb
Host smart-87933060-5006-4bca-87f9-102dbe64c2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614443798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.614443798
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.4189512459
Short name T980
Test name
Test status
Simulation time 2023585911 ps
CPU time 2.31 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 216128 kb
Host smart-5b271df4-9ccd-4a86-a066-f36cfd8e3d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189512459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4189512459
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.123605265
Short name T936
Test name
Test status
Simulation time 258507827 ps
CPU time 3.53 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 219160 kb
Host smart-231a2ccf-e99f-4cbb-a9a1-5dd4d8fabf42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=123605265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.123605265
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3940637944
Short name T468
Test name
Test status
Simulation time 4036568598 ps
CPU time 3.51 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:25:56 PM PDT 24
Peak memory 216532 kb
Host smart-d104f241-6f50-4f56-af3b-d52cd5bcbfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940637944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3940637944
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.808655414
Short name T810
Test name
Test status
Simulation time 2118948508 ps
CPU time 6.85 seconds
Started May 23 01:25:53 PM PDT 24
Finished May 23 01:26:03 PM PDT 24
Peak memory 216384 kb
Host smart-fb41847b-91fb-4a4b-be42-f9b0b0b34483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808655414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.808655414
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1186719643
Short name T315
Test name
Test status
Simulation time 115416842 ps
CPU time 1.26 seconds
Started May 23 01:25:46 PM PDT 24
Finished May 23 01:25:48 PM PDT 24
Peak memory 208232 kb
Host smart-17565681-270b-4911-83e1-eb6263d1e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186719643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1186719643
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2704098227
Short name T755
Test name
Test status
Simulation time 52046343 ps
CPU time 0.85 seconds
Started May 23 01:25:46 PM PDT 24
Finished May 23 01:25:49 PM PDT 24
Peak memory 205828 kb
Host smart-930838c5-6180-4f25-9aac-75525d09a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704098227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2704098227
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1681665249
Short name T560
Test name
Test status
Simulation time 4523900810 ps
CPU time 16.18 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:09 PM PDT 24
Peak memory 217920 kb
Host smart-fd36423d-cdc8-448d-993b-8e07c4427aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681665249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1681665249
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.32381854
Short name T520
Test name
Test status
Simulation time 45414352 ps
CPU time 0.77 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 205304 kb
Host smart-d7dfb45a-a100-43cc-b767-10570762559a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32381854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.32381854
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3437969648
Short name T295
Test name
Test status
Simulation time 611760399 ps
CPU time 2.22 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:25:56 PM PDT 24
Peak memory 218808 kb
Host smart-c8a9e205-fa5c-4133-b65c-65e3299cbf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437969648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3437969648
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2455720020
Short name T483
Test name
Test status
Simulation time 59922756 ps
CPU time 0.73 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 206300 kb
Host smart-16a6a9f5-dbf8-4aa0-b784-fe1d71679732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455720020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2455720020
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2049729155
Short name T503
Test name
Test status
Simulation time 6965981528 ps
CPU time 53.22 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:45 PM PDT 24
Peak memory 224708 kb
Host smart-c46b3727-e5d5-4528-b6a9-c202f6660743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049729155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2049729155
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1063520071
Short name T678
Test name
Test status
Simulation time 6763598054 ps
CPU time 56.36 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:26:46 PM PDT 24
Peak memory 239796 kb
Host smart-dfabef8a-4e75-46dd-9e60-3e520811e095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063520071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1063520071
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3183868947
Short name T556
Test name
Test status
Simulation time 2406863147 ps
CPU time 36.51 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:28 PM PDT 24
Peak memory 249148 kb
Host smart-ce255126-4d6e-4509-8f62-df33f9b99a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183868947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3183868947
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.599972570
Short name T690
Test name
Test status
Simulation time 10316903929 ps
CPU time 20.51 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:26:15 PM PDT 24
Peak memory 224636 kb
Host smart-afecb923-717f-4b43-81b3-a3345d17850c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599972570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.599972570
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.359172081
Short name T750
Test name
Test status
Simulation time 1727794894 ps
CPU time 8.13 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:01 PM PDT 24
Peak memory 233300 kb
Host smart-19c01a9d-f8c5-43f6-ac09-e9e3d106ab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359172081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.359172081
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1342300489
Short name T188
Test name
Test status
Simulation time 2037452309 ps
CPU time 6.91 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:25:59 PM PDT 24
Peak memory 238508 kb
Host smart-c38d8204-f985-4a91-b44d-d0cfcc0b8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342300489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1342300489
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1755377447
Short name T127
Test name
Test status
Simulation time 1046117548 ps
CPU time 2.89 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:25:51 PM PDT 24
Peak memory 233084 kb
Host smart-ad0d6fb7-b1be-4643-ba52-3c713d8df3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755377447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1755377447
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2358772388
Short name T925
Test name
Test status
Simulation time 1013339339 ps
CPU time 13.34 seconds
Started May 23 01:25:53 PM PDT 24
Finished May 23 01:26:09 PM PDT 24
Peak memory 219952 kb
Host smart-f6a03fdb-eb33-4d31-a385-9e3b2c1a05a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2358772388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2358772388
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2289984956
Short name T150
Test name
Test status
Simulation time 10220566347 ps
CPU time 38.23 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:26:32 PM PDT 24
Peak memory 249300 kb
Host smart-e9be1495-469d-4b16-ab72-1ef74a222ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289984956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2289984956
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2071178271
Short name T698
Test name
Test status
Simulation time 1546410652 ps
CPU time 4.33 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:25:58 PM PDT 24
Peak memory 216420 kb
Host smart-f3286a9b-e07b-47f0-925b-6ccdafd2cfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071178271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2071178271
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3710164881
Short name T613
Test name
Test status
Simulation time 245799923 ps
CPU time 1.04 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:25:50 PM PDT 24
Peak memory 206856 kb
Host smart-5c17de8b-364a-47df-9afa-5f3b11aebba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710164881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3710164881
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1341213978
Short name T580
Test name
Test status
Simulation time 88986191 ps
CPU time 0.91 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 205852 kb
Host smart-84aeef97-f0f2-4a52-9f95-ee34a8057972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341213978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1341213978
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.851143577
Short name T665
Test name
Test status
Simulation time 22439343054 ps
CPU time 24.18 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:16 PM PDT 24
Peak memory 236688 kb
Host smart-2c9517d1-0533-4740-bd67-2a213ba0d99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851143577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.851143577
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.222215592
Short name T519
Test name
Test status
Simulation time 26843138 ps
CPU time 0.73 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 204692 kb
Host smart-eab87bc7-b8db-4101-9417-a3ed205a0cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222215592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.222215592
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2765829137
Short name T202
Test name
Test status
Simulation time 993680681 ps
CPU time 2.72 seconds
Started May 23 01:25:54 PM PDT 24
Finished May 23 01:25:59 PM PDT 24
Peak memory 218660 kb
Host smart-618e6737-ed84-41a7-9d81-d2db77c5a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765829137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2765829137
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1623820410
Short name T590
Test name
Test status
Simulation time 15632506 ps
CPU time 0.8 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 206728 kb
Host smart-8fea9a74-8611-4380-9a96-eb2408c3a8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623820410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1623820410
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3996930968
Short name T703
Test name
Test status
Simulation time 3503382752 ps
CPU time 38.39 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:31 PM PDT 24
Peak memory 249204 kb
Host smart-b1bc0dc7-3d3a-471e-98a8-a26904f3e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996930968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3996930968
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3044341340
Short name T48
Test name
Test status
Simulation time 60500328273 ps
CPU time 562.91 seconds
Started May 23 01:25:52 PM PDT 24
Finished May 23 01:35:18 PM PDT 24
Peak memory 249400 kb
Host smart-3d54b5a2-5fdd-4124-a5fa-f6e3efc678d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044341340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3044341340
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.764050074
Short name T133
Test name
Test status
Simulation time 12873082199 ps
CPU time 116.71 seconds
Started May 23 01:25:53 PM PDT 24
Finished May 23 01:27:52 PM PDT 24
Peak memory 249296 kb
Host smart-a7b18595-43ff-45d8-bddb-6abf64ae3809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764050074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.764050074
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2096479027
Short name T657
Test name
Test status
Simulation time 1826495534 ps
CPU time 21.8 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:14 PM PDT 24
Peak memory 241016 kb
Host smart-9891a25e-c73c-4575-918b-13d4620ca392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096479027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2096479027
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.386662690
Short name T185
Test name
Test status
Simulation time 649964030 ps
CPU time 8.66 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:26:01 PM PDT 24
Peak memory 233268 kb
Host smart-0b247e45-2b35-49f5-ad65-84ed4d842f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386662690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.386662690
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1313553009
Short name T768
Test name
Test status
Simulation time 6169766327 ps
CPU time 19.05 seconds
Started May 23 01:25:53 PM PDT 24
Finished May 23 01:26:15 PM PDT 24
Peak memory 218848 kb
Host smart-d956f42a-cb48-40ad-b43b-ab0001f57216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313553009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1313553009
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1829359285
Short name T254
Test name
Test status
Simulation time 13739075086 ps
CPU time 20.63 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 233624 kb
Host smart-5b9d91bf-bfc4-4bb4-b9b4-16f8ec78b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829359285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1829359285
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3518075877
Short name T557
Test name
Test status
Simulation time 35202107985 ps
CPU time 16.5 seconds
Started May 23 01:25:53 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 224668 kb
Host smart-e587854e-e557-42f3-a612-7ccb9094a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518075877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3518075877
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4043296676
Short name T141
Test name
Test status
Simulation time 1930546002 ps
CPU time 8.03 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:26:01 PM PDT 24
Peak memory 220148 kb
Host smart-7af5aa04-a260-41a7-bafb-9e01a39484e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4043296676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4043296676
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2011585871
Short name T627
Test name
Test status
Simulation time 10650907286 ps
CPU time 111.09 seconds
Started May 23 01:25:54 PM PDT 24
Finished May 23 01:27:47 PM PDT 24
Peak memory 249392 kb
Host smart-e98a19b1-2aa6-4486-8d95-6c3b11c5669e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011585871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2011585871
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4109167320
Short name T390
Test name
Test status
Simulation time 19892239 ps
CPU time 0.74 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:25:52 PM PDT 24
Peak memory 205556 kb
Host smart-44986b10-29d5-4ccf-8245-cfcb9ded4e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109167320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4109167320
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.636413189
Short name T785
Test name
Test status
Simulation time 2342911105 ps
CPU time 4.75 seconds
Started May 23 01:25:53 PM PDT 24
Finished May 23 01:26:00 PM PDT 24
Peak memory 216472 kb
Host smart-5017bfa0-12c8-4e92-8875-0919e2102917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636413189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.636413189
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3921923169
Short name T653
Test name
Test status
Simulation time 165116232 ps
CPU time 0.97 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:25:51 PM PDT 24
Peak memory 207372 kb
Host smart-aa4919df-ae84-402a-8d24-cd3e41685a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921923169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3921923169
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3911725681
Short name T51
Test name
Test status
Simulation time 16896427 ps
CPU time 0.71 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 205428 kb
Host smart-f2ebc5d5-b4d0-4149-a141-0c5c157ec8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911725681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3911725681
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.388851047
Short name T567
Test name
Test status
Simulation time 1159303217 ps
CPU time 6.12 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:58 PM PDT 24
Peak memory 219668 kb
Host smart-ff55a3f9-23fd-4569-9ad7-0e3ad0e5ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388851047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.388851047
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1604006667
Short name T599
Test name
Test status
Simulation time 16649489 ps
CPU time 0.77 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:06 PM PDT 24
Peak memory 204664 kb
Host smart-b01e0aeb-9cff-4046-bbe4-6df5f70b24e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604006667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1604006667
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2807605607
Short name T380
Test name
Test status
Simulation time 4874577836 ps
CPU time 16.17 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:26:05 PM PDT 24
Peak memory 224616 kb
Host smart-d37efd7e-9156-4cf5-8454-5bfc7e746c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807605607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2807605607
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3469386621
Short name T883
Test name
Test status
Simulation time 29928451 ps
CPU time 0.81 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:25:54 PM PDT 24
Peak memory 206416 kb
Host smart-641a9aa0-a86d-4a6f-9c71-8b3f3bb291c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469386621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3469386621
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3696424307
Short name T786
Test name
Test status
Simulation time 5443495340 ps
CPU time 26.39 seconds
Started May 23 01:26:01 PM PDT 24
Finished May 23 01:26:29 PM PDT 24
Peak memory 249336 kb
Host smart-c5a3d0da-3420-4c04-9f49-4279584983ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696424307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3696424307
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.515331144
Short name T543
Test name
Test status
Simulation time 127671203082 ps
CPU time 325.37 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:31:31 PM PDT 24
Peak memory 256896 kb
Host smart-97796f46-b725-404e-adcf-7b6cbea54737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515331144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.515331144
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1453198903
Short name T224
Test name
Test status
Simulation time 24549545881 ps
CPU time 205.17 seconds
Started May 23 01:26:06 PM PDT 24
Finished May 23 01:29:32 PM PDT 24
Peak memory 253864 kb
Host smart-51115baf-9590-4878-a273-c5e298015dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453198903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1453198903
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4251264452
Short name T374
Test name
Test status
Simulation time 1258574361 ps
CPU time 6.49 seconds
Started May 23 01:25:52 PM PDT 24
Finished May 23 01:26:01 PM PDT 24
Peak memory 232700 kb
Host smart-5c74a27c-09cd-452b-a48b-cc16db553d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251264452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4251264452
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1023474511
Short name T582
Test name
Test status
Simulation time 1768261488 ps
CPU time 16.81 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:26:11 PM PDT 24
Peak memory 234376 kb
Host smart-363859b6-0079-4d08-9685-667aa2d8a8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023474511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1023474511
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2249900857
Short name T867
Test name
Test status
Simulation time 1859437605 ps
CPU time 22.01 seconds
Started May 23 01:25:47 PM PDT 24
Finished May 23 01:26:11 PM PDT 24
Peak memory 224420 kb
Host smart-928fb3ce-76da-4e07-81ea-50e42330873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249900857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2249900857
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1607132697
Short name T561
Test name
Test status
Simulation time 1535359281 ps
CPU time 6.76 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:59 PM PDT 24
Peak memory 233612 kb
Host smart-b16ffc01-58c7-4348-a364-f149adf451b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607132697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1607132697
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3334032618
Short name T817
Test name
Test status
Simulation time 4638348129 ps
CPU time 7.29 seconds
Started May 23 01:25:50 PM PDT 24
Finished May 23 01:26:00 PM PDT 24
Peak memory 216960 kb
Host smart-230416ce-fa3e-4d95-afba-d2ee33b1fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334032618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3334032618
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1753424030
Short name T622
Test name
Test status
Simulation time 119071439 ps
CPU time 3.93 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 221716 kb
Host smart-431a9b74-7d1a-48d8-9f48-bac997be2965
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753424030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1753424030
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.643816932
Short name T28
Test name
Test status
Simulation time 3276348473 ps
CPU time 2.93 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:25:57 PM PDT 24
Peak memory 216856 kb
Host smart-80bd0a7e-a3f8-4587-af62-2eaa69b75e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643816932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.643816932
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1029546938
Short name T621
Test name
Test status
Simulation time 2691715870 ps
CPU time 9.1 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:26:00 PM PDT 24
Peak memory 216572 kb
Host smart-e4a37fb5-1dff-469a-b6bf-01b22ff2a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029546938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1029546938
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4005000862
Short name T16
Test name
Test status
Simulation time 123765217 ps
CPU time 1.09 seconds
Started May 23 01:25:51 PM PDT 24
Finished May 23 01:25:55 PM PDT 24
Peak memory 207848 kb
Host smart-00718a3f-c806-43ff-86ad-ba19595ab8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005000862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4005000862
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1601176434
Short name T407
Test name
Test status
Simulation time 25797312 ps
CPU time 0.75 seconds
Started May 23 01:25:49 PM PDT 24
Finished May 23 01:25:53 PM PDT 24
Peak memory 205804 kb
Host smart-72c46ff7-4d22-44d0-971d-e034ad646827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601176434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1601176434
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3465960985
Short name T858
Test name
Test status
Simulation time 118689305312 ps
CPU time 42.98 seconds
Started May 23 01:25:48 PM PDT 24
Finished May 23 01:26:33 PM PDT 24
Peak memory 233492 kb
Host smart-56c63f72-281b-436c-976b-85344488bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465960985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3465960985
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.132261489
Short name T966
Test name
Test status
Simulation time 50739049 ps
CPU time 0.75 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:04 PM PDT 24
Peak memory 205700 kb
Host smart-e002623f-cdb6-4b76-bb96-754e8ab1afdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132261489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.132261489
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3156204206
Short name T977
Test name
Test status
Simulation time 89821963 ps
CPU time 2.35 seconds
Started May 23 01:26:08 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 233812 kb
Host smart-75d97f7f-9356-4f2e-b8b0-1ee3852b1904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156204206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3156204206
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1979048784
Short name T413
Test name
Test status
Simulation time 22173620 ps
CPU time 0.79 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:04 PM PDT 24
Peak memory 206500 kb
Host smart-0386521c-275a-495d-9c37-4aa53ddb7f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979048784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1979048784
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2898812429
Short name T183
Test name
Test status
Simulation time 70388948283 ps
CPU time 217.18 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:29:43 PM PDT 24
Peak memory 249192 kb
Host smart-fc066df1-c86c-4eab-a23f-fc124c8af7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898812429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2898812429
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.773770030
Short name T126
Test name
Test status
Simulation time 25036358577 ps
CPU time 201.26 seconds
Started May 23 01:26:09 PM PDT 24
Finished May 23 01:29:31 PM PDT 24
Peak memory 240548 kb
Host smart-1b726977-0fb9-4389-a989-d210656dd893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773770030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.773770030
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3606491521
Short name T911
Test name
Test status
Simulation time 23707276393 ps
CPU time 118.89 seconds
Started May 23 01:26:00 PM PDT 24
Finished May 23 01:28:00 PM PDT 24
Peak memory 254952 kb
Host smart-660a480a-1c53-4489-9d55-ae468121eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606491521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3606491521
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1310797242
Short name T734
Test name
Test status
Simulation time 384447420 ps
CPU time 3.57 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:10 PM PDT 24
Peak memory 232660 kb
Host smart-55b2c4b2-f26c-43e0-819b-5f51506e9a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310797242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1310797242
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1869874104
Short name T8
Test name
Test status
Simulation time 423685512 ps
CPU time 5 seconds
Started May 23 01:26:07 PM PDT 24
Finished May 23 01:26:13 PM PDT 24
Peak memory 233052 kb
Host smart-a957d17c-6e14-4b7a-b370-479cbd0deb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869874104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1869874104
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3922434887
Short name T215
Test name
Test status
Simulation time 904680100 ps
CPU time 13.77 seconds
Started May 23 01:26:00 PM PDT 24
Finished May 23 01:26:15 PM PDT 24
Peak memory 223512 kb
Host smart-6bceb0c2-a73d-44f4-98d9-16ae0f616cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922434887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3922434887
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.790096358
Short name T453
Test name
Test status
Simulation time 412532788 ps
CPU time 6.44 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:13 PM PDT 24
Peak memory 234656 kb
Host smart-39b6747f-4aea-4261-8283-0f689a50247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790096358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.790096358
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1152372936
Short name T900
Test name
Test status
Simulation time 367903482 ps
CPU time 3.23 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 233684 kb
Host smart-dd2f1205-893d-4ca0-812c-4501551cef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152372936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1152372936
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2639419326
Short name T574
Test name
Test status
Simulation time 153851408 ps
CPU time 3.56 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:08 PM PDT 24
Peak memory 219228 kb
Host smart-d4232ed9-b86b-4014-b03c-27bc2c54fb90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2639419326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2639419326
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2101108776
Short name T10
Test name
Test status
Simulation time 5635552545 ps
CPU time 11.6 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:16 PM PDT 24
Peak memory 216588 kb
Host smart-2607082f-c65b-461f-b9fe-3d28f0737ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101108776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2101108776
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1054970730
Short name T426
Test name
Test status
Simulation time 887076907 ps
CPU time 3.19 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:08 PM PDT 24
Peak memory 207964 kb
Host smart-4be8ed20-c3ad-4708-9b05-237269138faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054970730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1054970730
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.736169413
Short name T847
Test name
Test status
Simulation time 26361097 ps
CPU time 1.06 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:06 PM PDT 24
Peak memory 207920 kb
Host smart-086d43e3-75a0-42eb-879f-0f2608986f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736169413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.736169413
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1685680400
Short name T459
Test name
Test status
Simulation time 63372810 ps
CPU time 0.81 seconds
Started May 23 01:26:11 PM PDT 24
Finished May 23 01:26:13 PM PDT 24
Peak memory 205776 kb
Host smart-a5527b96-8163-4f0e-a5a9-7d733f99ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685680400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1685680400
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.557645176
Short name T795
Test name
Test status
Simulation time 5258435974 ps
CPU time 17.28 seconds
Started May 23 01:26:08 PM PDT 24
Finished May 23 01:26:27 PM PDT 24
Peak memory 233468 kb
Host smart-bc60489b-d547-427e-949b-7f8da90e744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557645176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.557645176
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1146915741
Short name T973
Test name
Test status
Simulation time 130820518 ps
CPU time 0.79 seconds
Started May 23 01:26:07 PM PDT 24
Finished May 23 01:26:09 PM PDT 24
Peak memory 205424 kb
Host smart-b67e3789-209a-47b2-8ca7-76981d2a7362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146915741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1146915741
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.880028743
Short name T873
Test name
Test status
Simulation time 2008276620 ps
CPU time 19.62 seconds
Started May 23 01:26:01 PM PDT 24
Finished May 23 01:26:22 PM PDT 24
Peak memory 218792 kb
Host smart-74e0d54d-8c53-4b2f-b35b-e1acdae76072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880028743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.880028743
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1448199637
Short name T607
Test name
Test status
Simulation time 29818411 ps
CPU time 0.79 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:05 PM PDT 24
Peak memory 206480 kb
Host smart-bf9afdc3-e10d-4f56-9414-e9eb48cdba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448199637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1448199637
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2145754651
Short name T725
Test name
Test status
Simulation time 19668630 ps
CPU time 0.79 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 215980 kb
Host smart-2c62363c-1bc7-4747-88e2-56eeff835fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145754651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2145754651
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3134545420
Short name T913
Test name
Test status
Simulation time 342516471090 ps
CPU time 802.76 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:39:26 PM PDT 24
Peak memory 272800 kb
Host smart-ffcf70e8-266e-4201-ae99-f4850835a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134545420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3134545420
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3844596041
Short name T381
Test name
Test status
Simulation time 15582067637 ps
CPU time 75.88 seconds
Started May 23 01:26:09 PM PDT 24
Finished May 23 01:27:26 PM PDT 24
Peak memory 256752 kb
Host smart-1a052eea-919d-4f98-b54b-0a4f879672c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844596041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3844596041
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1340242791
Short name T941
Test name
Test status
Simulation time 310422456 ps
CPU time 4.61 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:09 PM PDT 24
Peak memory 232784 kb
Host smart-295c563f-bbb6-4670-8dcc-38407e85e6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340242791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1340242791
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.9079515
Short name T892
Test name
Test status
Simulation time 4267479103 ps
CPU time 10.18 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:13 PM PDT 24
Peak memory 219588 kb
Host smart-1e57c04d-3204-44ba-b28b-65cdc5fb9525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9079515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.9079515
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3244994951
Short name T516
Test name
Test status
Simulation time 22854941630 ps
CPU time 43.15 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:48 PM PDT 24
Peak memory 246464 kb
Host smart-4c0b5a99-6aa8-4779-8d00-e802964b85d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244994951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3244994951
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1261219344
Short name T168
Test name
Test status
Simulation time 602306714 ps
CPU time 2.06 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:09 PM PDT 24
Peak memory 218516 kb
Host smart-2c7652cc-75e3-4c57-ac0e-21ae38c4ddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261219344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1261219344
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1746513511
Short name T780
Test name
Test status
Simulation time 1876995364 ps
CPU time 4.23 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:11 PM PDT 24
Peak memory 233200 kb
Host smart-a709405e-e218-4f21-8b3a-cd050e90c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746513511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1746513511
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3547376880
Short name T140
Test name
Test status
Simulation time 1116866596 ps
CPU time 8.42 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:15 PM PDT 24
Peak memory 219420 kb
Host smart-9902d57e-c8dd-4e5e-ad8a-8467270c8f49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3547376880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3547376880
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3424390213
Short name T497
Test name
Test status
Simulation time 34126380328 ps
CPU time 377.76 seconds
Started May 23 01:26:08 PM PDT 24
Finished May 23 01:32:27 PM PDT 24
Peak memory 254972 kb
Host smart-ab270a67-b9e6-4083-8e0d-a9ce428df832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424390213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3424390213
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.961699277
Short name T886
Test name
Test status
Simulation time 294182545 ps
CPU time 3.47 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:26:09 PM PDT 24
Peak memory 216356 kb
Host smart-dd6dd107-2fa0-4aa1-8586-f3eb821abc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961699277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.961699277
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.903110785
Short name T927
Test name
Test status
Simulation time 43699064 ps
CPU time 0.71 seconds
Started May 23 01:26:01 PM PDT 24
Finished May 23 01:26:03 PM PDT 24
Peak memory 205580 kb
Host smart-234ba3a1-899b-4dd1-b068-13de3eff01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903110785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.903110785
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3886583990
Short name T759
Test name
Test status
Simulation time 46889336 ps
CPU time 0.93 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 206572 kb
Host smart-afa344d1-cf49-48fd-812b-60a0b578ee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886583990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3886583990
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2807196440
Short name T469
Test name
Test status
Simulation time 36689168 ps
CPU time 0.76 seconds
Started May 23 01:26:10 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 205820 kb
Host smart-e0e66d7a-2b14-4c7a-a9e3-b3849b243916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807196440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2807196440
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.465598693
Short name T454
Test name
Test status
Simulation time 1320706855 ps
CPU time 8.02 seconds
Started May 23 01:26:11 PM PDT 24
Finished May 23 01:26:21 PM PDT 24
Peak memory 222436 kb
Host smart-11a4d6d1-08f9-4b8d-901c-45a9e541e010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465598693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.465598693
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.913258941
Short name T440
Test name
Test status
Simulation time 12490501 ps
CPU time 0.76 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:03 PM PDT 24
Peak memory 204744 kb
Host smart-9161a87b-03b1-4ac2-91f3-a237707a9be0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913258941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.913258941
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3206529730
Short name T441
Test name
Test status
Simulation time 1224352853 ps
CPU time 9.85 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:26:16 PM PDT 24
Peak memory 234648 kb
Host smart-d3a99521-c941-4aeb-a48a-e5978603c2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206529730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3206529730
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3661727712
Short name T500
Test name
Test status
Simulation time 29751076 ps
CPU time 0.75 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 206732 kb
Host smart-d63462e8-7fd2-4444-b25d-94eaf270b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661727712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3661727712
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1965246252
Short name T893
Test name
Test status
Simulation time 53692401927 ps
CPU time 65.85 seconds
Started May 23 01:26:11 PM PDT 24
Finished May 23 01:27:18 PM PDT 24
Peak memory 241084 kb
Host smart-f277f7b6-1167-4982-a567-dc26d14709f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965246252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1965246252
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3320713910
Short name T798
Test name
Test status
Simulation time 7943627885 ps
CPU time 40.56 seconds
Started May 23 01:26:09 PM PDT 24
Finished May 23 01:26:51 PM PDT 24
Peak memory 237188 kb
Host smart-981ded41-ab85-4323-8eba-2bf2a0fedd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320713910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3320713910
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3371462179
Short name T211
Test name
Test status
Simulation time 28467921077 ps
CPU time 222.52 seconds
Started May 23 01:26:08 PM PDT 24
Finished May 23 01:29:52 PM PDT 24
Peak memory 233832 kb
Host smart-24a091c2-80f2-4419-9cbd-5d73909c2ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371462179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3371462179
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2564527385
Short name T346
Test name
Test status
Simulation time 864725039 ps
CPU time 15.85 seconds
Started May 23 01:26:08 PM PDT 24
Finished May 23 01:26:25 PM PDT 24
Peak memory 232804 kb
Host smart-9fa99303-b956-470e-815f-957f6b7d4ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564527385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2564527385
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.343747721
Short name T534
Test name
Test status
Simulation time 133685316 ps
CPU time 2.34 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:06 PM PDT 24
Peak memory 232772 kb
Host smart-9e644a79-df94-4371-a18f-0700db8d3170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343747721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.343747721
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4106753153
Short name T446
Test name
Test status
Simulation time 1398346641 ps
CPU time 20.83 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:24 PM PDT 24
Peak memory 240644 kb
Host smart-a9b9d81a-776a-488d-bd10-8980df895b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106753153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4106753153
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2410371480
Short name T192
Test name
Test status
Simulation time 3199930467 ps
CPU time 8.3 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:12 PM PDT 24
Peak memory 233668 kb
Host smart-000ca966-1dc7-43ff-96ed-b6d09bde4ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410371480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2410371480
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4133519722
Short name T771
Test name
Test status
Simulation time 49671214911 ps
CPU time 26.09 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:31 PM PDT 24
Peak memory 228744 kb
Host smart-d86c9894-85a7-42e3-99b3-64dc7425f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133519722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4133519722
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.598093671
Short name T125
Test name
Test status
Simulation time 4003536012 ps
CPU time 9.48 seconds
Started May 23 01:26:11 PM PDT 24
Finished May 23 01:26:22 PM PDT 24
Peak memory 219212 kb
Host smart-93661020-a8b6-43c3-b892-21ed07dd6e84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598093671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.598093671
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.90010611
Short name T712
Test name
Test status
Simulation time 118472080 ps
CPU time 1.07 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:05 PM PDT 24
Peak memory 206776 kb
Host smart-36fdf0f6-2240-4c22-bfbd-4df1dd5c0e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90010611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.90010611
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1749533173
Short name T524
Test name
Test status
Simulation time 40045207 ps
CPU time 0.78 seconds
Started May 23 01:26:02 PM PDT 24
Finished May 23 01:26:04 PM PDT 24
Peak memory 205588 kb
Host smart-99fc49f5-e470-4014-be82-fd7b8e9534b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749533173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1749533173
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1950906850
Short name T804
Test name
Test status
Simulation time 5325904263 ps
CPU time 15.78 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:21 PM PDT 24
Peak memory 216484 kb
Host smart-c48cfddd-7a2f-42e0-a78c-9283531d74ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950906850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1950906850
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1758228378
Short name T754
Test name
Test status
Simulation time 65621716 ps
CPU time 1.24 seconds
Started May 23 01:26:05 PM PDT 24
Finished May 23 01:26:08 PM PDT 24
Peak memory 216472 kb
Host smart-1f27a6dc-e9cc-421a-8eaa-a0429525f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758228378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1758228378
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.477084704
Short name T22
Test name
Test status
Simulation time 253470576 ps
CPU time 0.88 seconds
Started May 23 01:26:04 PM PDT 24
Finished May 23 01:26:07 PM PDT 24
Peak memory 205528 kb
Host smart-bba34c06-ae40-4c30-9cd4-20258de2ff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477084704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.477084704
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2610599477
Short name T492
Test name
Test status
Simulation time 3865343929 ps
CPU time 15.98 seconds
Started May 23 01:26:03 PM PDT 24
Finished May 23 01:26:21 PM PDT 24
Peak memory 242940 kb
Host smart-fe4644ee-68d1-412b-a25e-d0f2f0fb056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610599477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2610599477
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3490503889
Short name T476
Test name
Test status
Simulation time 14518908 ps
CPU time 0.81 seconds
Started May 23 01:23:52 PM PDT 24
Finished May 23 01:23:55 PM PDT 24
Peak memory 205728 kb
Host smart-d3a7d6ef-469a-44f5-953f-10510b56fec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490503889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
490503889
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2546640972
Short name T968
Test name
Test status
Simulation time 45018867 ps
CPU time 2.82 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:53 PM PDT 24
Peak memory 234428 kb
Host smart-9d7c56b3-4b7b-4c8e-8857-623eb7e1ea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546640972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2546640972
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.19612757
Short name T348
Test name
Test status
Simulation time 21248350 ps
CPU time 0.83 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:23:52 PM PDT 24
Peak memory 206372 kb
Host smart-752abeb1-12c2-4ab9-8d62-c33de5636369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19612757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.19612757
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2507490660
Short name T284
Test name
Test status
Simulation time 3080561096 ps
CPU time 20.57 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:24:12 PM PDT 24
Peak memory 224620 kb
Host smart-e991b6c6-0a31-4bf7-b139-3df6f6ea4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507490660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2507490660
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3594479949
Short name T806
Test name
Test status
Simulation time 4887176206 ps
CPU time 70.55 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:25:12 PM PDT 24
Peak memory 249416 kb
Host smart-e1313793-6197-4353-a6be-697faf318282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594479949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3594479949
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.449370139
Short name T235
Test name
Test status
Simulation time 21366522674 ps
CPU time 126.75 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:25:58 PM PDT 24
Peak memory 272380 kb
Host smart-fe105dab-9665-4f99-a722-a6daf179697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449370139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
449370139
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1329244685
Short name T305
Test name
Test status
Simulation time 752998860 ps
CPU time 17.64 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 249172 kb
Host smart-146d1416-7bd1-403a-a1b9-beeead4e8443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329244685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1329244685
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3882685587
Short name T648
Test name
Test status
Simulation time 11960761329 ps
CPU time 14.36 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 218028 kb
Host smart-4b4368a2-94a0-4449-89e4-c07ef64a7c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882685587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3882685587
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1638954718
Short name T538
Test name
Test status
Simulation time 3892366001 ps
CPU time 40.17 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:43 PM PDT 24
Peak memory 218572 kb
Host smart-8118d074-e81b-4038-a0de-3c3aebe4c280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638954718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1638954718
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2385568785
Short name T739
Test name
Test status
Simulation time 110940902 ps
CPU time 1.09 seconds
Started May 23 01:23:55 PM PDT 24
Finished May 23 01:23:57 PM PDT 24
Peak memory 216752 kb
Host smart-946843d7-418a-4bd0-ba1a-49d638e571ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385568785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2385568785
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.814453924
Short name T950
Test name
Test status
Simulation time 758599698 ps
CPU time 3.81 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:23:57 PM PDT 24
Peak memory 233292 kb
Host smart-40febabc-69d8-41d3-a83b-3dff6f9c5677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814453924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
814453924
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.74182870
Short name T279
Test name
Test status
Simulation time 2410832448 ps
CPU time 5.94 seconds
Started May 23 01:23:50 PM PDT 24
Finished May 23 01:23:58 PM PDT 24
Peak memory 219092 kb
Host smart-33699a64-02e7-4d5a-b899-4cc375ba6687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74182870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.74182870
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3401130990
Short name T872
Test name
Test status
Simulation time 2866913120 ps
CPU time 12.04 seconds
Started May 23 01:23:52 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 223036 kb
Host smart-58e02945-8a9c-4d72-8d39-ee1a4e1d309b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3401130990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3401130990
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3166402412
Short name T815
Test name
Test status
Simulation time 2078372965 ps
CPU time 44.66 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:24:38 PM PDT 24
Peak memory 252460 kb
Host smart-fcde05df-b18d-4022-83a8-1a99c2acbf37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166402412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3166402412
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2520528296
Short name T308
Test name
Test status
Simulation time 6085303176 ps
CPU time 21.22 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 216480 kb
Host smart-dd7f4b1d-1ae8-46de-bd28-43783823eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520528296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2520528296
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.179822395
Short name T388
Test name
Test status
Simulation time 8898962315 ps
CPU time 13.51 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:24:07 PM PDT 24
Peak memory 216524 kb
Host smart-bbf418bf-6c9a-47c8-80a8-5251715d777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179822395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.179822395
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3752637093
Short name T399
Test name
Test status
Simulation time 42148337 ps
CPU time 0.86 seconds
Started May 23 01:23:47 PM PDT 24
Finished May 23 01:23:50 PM PDT 24
Peak memory 205868 kb
Host smart-f6d0942b-af44-4af9-9bf9-56be31f9512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752637093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3752637093
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1064109294
Short name T570
Test name
Test status
Simulation time 162252518 ps
CPU time 0.84 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 205820 kb
Host smart-54dec12c-892d-4234-aff7-e535e814020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064109294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1064109294
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2410762142
Short name T957
Test name
Test status
Simulation time 14478541560 ps
CPU time 8.41 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 233488 kb
Host smart-bef13077-0b98-40ae-9cf5-01daebba0602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410762142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2410762142
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3111116891
Short name T854
Test name
Test status
Simulation time 16570008 ps
CPU time 0.8 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 205280 kb
Host smart-34321229-f6a5-46fb-adb5-5897200d5162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111116891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
111116891
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1630743096
Short name T981
Test name
Test status
Simulation time 38748162 ps
CPU time 2.28 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 218752 kb
Host smart-4885b622-6ed1-4518-ad5c-d61da01ed386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630743096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1630743096
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.945039933
Short name T337
Test name
Test status
Simulation time 48091653 ps
CPU time 0.78 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:03 PM PDT 24
Peak memory 206788 kb
Host smart-1cda7e8c-f41f-4335-9d7a-c48e5fbd3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945039933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.945039933
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2701641529
Short name T671
Test name
Test status
Simulation time 499638797 ps
CPU time 8.33 seconds
Started May 23 01:24:04 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 239444 kb
Host smart-6448bfd4-d660-484f-9677-e261d0b7ad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701641529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2701641529
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4043000817
Short name T801
Test name
Test status
Simulation time 16469983253 ps
CPU time 169.56 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:26:37 PM PDT 24
Peak memory 250676 kb
Host smart-4ab8c106-6c98-408d-95d9-7b67b6e34fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043000817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4043000817
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.682666757
Short name T673
Test name
Test status
Simulation time 112259513661 ps
CPU time 132.77 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:26:11 PM PDT 24
Peak memory 253556 kb
Host smart-a77bb1d2-7b24-4e2b-a09e-8f00ad7eeb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682666757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
682666757
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.299844337
Short name T844
Test name
Test status
Simulation time 8558342436 ps
CPU time 43.3 seconds
Started May 23 01:24:01 PM PDT 24
Finished May 23 01:24:47 PM PDT 24
Peak memory 250616 kb
Host smart-a20fbf0a-f2f7-430d-8880-4e1997b474db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299844337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.299844337
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2908034697
Short name T430
Test name
Test status
Simulation time 514721196 ps
CPU time 3.35 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 233888 kb
Host smart-1c1b8a9f-e3c9-4b20-b9d3-e0e88d5aba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908034697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2908034697
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2850603585
Short name T432
Test name
Test status
Simulation time 1710247660 ps
CPU time 14.07 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:14 PM PDT 24
Peak memory 216780 kb
Host smart-a2fcb4b5-7b84-4af1-a8ae-ca61ee15b8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850603585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2850603585
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3830547513
Short name T324
Test name
Test status
Simulation time 103260698 ps
CPU time 1.11 seconds
Started May 23 01:23:57 PM PDT 24
Finished May 23 01:23:59 PM PDT 24
Peak memory 216752 kb
Host smart-f45657e9-8f46-4ac0-aab5-6b27a4a12ed8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830547513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3830547513
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.583827289
Short name T636
Test name
Test status
Simulation time 418003728 ps
CPU time 4.02 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 217888 kb
Host smart-15a822e9-ca35-4e24-a255-eaa233304170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583827289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
583827289
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3652911757
Short name T954
Test name
Test status
Simulation time 223457485 ps
CPU time 3.46 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:24:00 PM PDT 24
Peak memory 233764 kb
Host smart-1d9c6c5a-008f-4c24-8121-b436f10ccd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652911757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3652911757
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1327912195
Short name T463
Test name
Test status
Simulation time 2388732069 ps
CPU time 11.27 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 221688 kb
Host smart-0e9cc668-d478-4294-b329-a0388cb3b072
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1327912195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1327912195
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1751705305
Short name T716
Test name
Test status
Simulation time 1666814405 ps
CPU time 20.47 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 216492 kb
Host smart-7a8b8eeb-63fa-46e1-bba4-c256f841a6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751705305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1751705305
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1068326745
Short name T879
Test name
Test status
Simulation time 3230587686 ps
CPU time 4.25 seconds
Started May 23 01:23:55 PM PDT 24
Finished May 23 01:24:01 PM PDT 24
Peak memory 216564 kb
Host smart-0ed26a00-5c13-4f3d-8dbe-1d6f4cc4f771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068326745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1068326745
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.4283154563
Short name T579
Test name
Test status
Simulation time 92274866 ps
CPU time 0.79 seconds
Started May 23 01:23:47 PM PDT 24
Finished May 23 01:23:49 PM PDT 24
Peak memory 205760 kb
Host smart-723dd1c0-0f81-423e-8914-31ba761c3d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283154563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.4283154563
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1870461429
Short name T684
Test name
Test status
Simulation time 110249055 ps
CPU time 0.84 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:23:59 PM PDT 24
Peak memory 205840 kb
Host smart-ec90bff6-9f60-45c2-bff9-930a8addab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870461429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1870461429
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3442039580
Short name T271
Test name
Test status
Simulation time 38432484685 ps
CPU time 14.86 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 219036 kb
Host smart-6ca3ac9a-df8c-466f-9243-d64192c0a3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442039580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3442039580
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1685661856
Short name T322
Test name
Test status
Simulation time 33397010 ps
CPU time 0.72 seconds
Started May 23 01:23:53 PM PDT 24
Finished May 23 01:23:55 PM PDT 24
Peak memory 204764 kb
Host smart-2a0ccf81-18c3-41eb-9c70-a848fb4750cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685661856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
685661856
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.472037446
Short name T296
Test name
Test status
Simulation time 249757982 ps
CPU time 2.64 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 219808 kb
Host smart-77dfa3fa-6bbe-4f21-93d9-7bd35e44ede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472037446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.472037446
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2082564850
Short name T321
Test name
Test status
Simulation time 167524483 ps
CPU time 0.79 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:23:52 PM PDT 24
Peak memory 206380 kb
Host smart-f74bec46-ff1c-4300-aa1f-651b57378d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082564850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2082564850
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2793832052
Short name T740
Test name
Test status
Simulation time 31387990237 ps
CPU time 78.05 seconds
Started May 23 01:23:50 PM PDT 24
Finished May 23 01:25:10 PM PDT 24
Peak memory 253016 kb
Host smart-50bbb255-f8c7-417f-bb4d-8ee719095eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793832052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2793832052
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1981261305
Short name T246
Test name
Test status
Simulation time 165839877770 ps
CPU time 502.14 seconds
Started May 23 01:23:41 PM PDT 24
Finished May 23 01:32:04 PM PDT 24
Peak memory 257528 kb
Host smart-1b866b04-8822-4abf-ae4f-a8bcaecb875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981261305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1981261305
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3826338121
Short name T799
Test name
Test status
Simulation time 477597612 ps
CPU time 8.48 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:08 PM PDT 24
Peak memory 217392 kb
Host smart-5327ae50-b533-48aa-927c-835e4e4bfe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826338121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3826338121
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2440151611
Short name T379
Test name
Test status
Simulation time 813527396 ps
CPU time 7.09 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:23:54 PM PDT 24
Peak memory 232600 kb
Host smart-2d9bdd09-6ceb-4ca2-9b4d-8d593ff9ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440151611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2440151611
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1386014385
Short name T292
Test name
Test status
Simulation time 3554823916 ps
CPU time 17.56 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:24:13 PM PDT 24
Peak memory 233656 kb
Host smart-dad82e3c-15f9-428f-a984-47e6a746a511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386014385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1386014385
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3693560020
Short name T209
Test name
Test status
Simulation time 969908031 ps
CPU time 3.83 seconds
Started May 23 01:23:45 PM PDT 24
Finished May 23 01:23:50 PM PDT 24
Peak memory 224540 kb
Host smart-67bb2d5b-263a-4789-8300-9192e84617d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693560020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3693560020
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.15523839
Short name T654
Test name
Test status
Simulation time 31036133400 ps
CPU time 7.25 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 218640 kb
Host smart-6d9956c8-5435-43c8-b0c0-10eb3b233f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15523839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.15523839
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3612468643
Short name T828
Test name
Test status
Simulation time 2590971470 ps
CPU time 7.98 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 226692 kb
Host smart-10748128-f552-442f-ae9a-94c534be2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612468643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3612468643
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3978035736
Short name T687
Test name
Test status
Simulation time 1900769635 ps
CPU time 7.49 seconds
Started May 23 01:23:44 PM PDT 24
Finished May 23 01:23:53 PM PDT 24
Peak memory 223100 kb
Host smart-3d8271ff-5830-487a-a526-f493be1e2fbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3978035736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3978035736
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3540581258
Short name T244
Test name
Test status
Simulation time 30284818953 ps
CPU time 327.79 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:29:19 PM PDT 24
Peak memory 264764 kb
Host smart-368f4ee9-3d6d-4b87-a099-055f83d1c1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540581258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3540581258
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2493264917
Short name T312
Test name
Test status
Simulation time 7874913031 ps
CPU time 21.49 seconds
Started May 23 01:23:56 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 216500 kb
Host smart-b729d806-a10e-4d01-9b01-be85adcfd942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493264917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2493264917
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1907680633
Short name T667
Test name
Test status
Simulation time 1225725679 ps
CPU time 6.91 seconds
Started May 23 01:23:54 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 216440 kb
Host smart-a8e001a2-d696-4fb7-9c50-8e87c4adcef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907680633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1907680633
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2756181629
Short name T505
Test name
Test status
Simulation time 198936426 ps
CPU time 1.17 seconds
Started May 23 01:23:46 PM PDT 24
Finished May 23 01:23:49 PM PDT 24
Peak memory 207908 kb
Host smart-742fdca4-bb99-43d9-baac-6ad419658c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756181629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2756181629
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2549959024
Short name T733
Test name
Test status
Simulation time 12163577 ps
CPU time 0.75 seconds
Started May 23 01:23:53 PM PDT 24
Finished May 23 01:23:55 PM PDT 24
Peak memory 205752 kb
Host smart-ccd2c312-2a01-4567-8f57-1cffd3923eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549959024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2549959024
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4084082885
Short name T429
Test name
Test status
Simulation time 3659348854 ps
CPU time 8.77 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:58 PM PDT 24
Peak memory 217516 kb
Host smart-4ffc570d-7d9c-4726-af69-512699982de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084082885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4084082885
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3195179589
Short name T645
Test name
Test status
Simulation time 12289967 ps
CPU time 0.72 seconds
Started May 23 01:24:01 PM PDT 24
Finished May 23 01:24:04 PM PDT 24
Peak memory 205368 kb
Host smart-318a1779-656d-4129-b80f-c24480258901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195179589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
195179589
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4027658501
Short name T130
Test name
Test status
Simulation time 635503153 ps
CPU time 2.37 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:02 PM PDT 24
Peak memory 234256 kb
Host smart-417790fe-ecfe-40a8-b89e-12078ec3b320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027658501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4027658501
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.264856552
Short name T323
Test name
Test status
Simulation time 109005410 ps
CPU time 0.76 seconds
Started May 23 01:23:53 PM PDT 24
Finished May 23 01:23:56 PM PDT 24
Peak memory 206788 kb
Host smart-83a37940-3494-41ed-9034-356e89147eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264856552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.264856552
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1580700332
Short name T356
Test name
Test status
Simulation time 3366007517 ps
CPU time 25.04 seconds
Started May 23 01:24:10 PM PDT 24
Finished May 23 01:24:37 PM PDT 24
Peak memory 220856 kb
Host smart-a2bba30c-d8d5-432b-b518-b7dd8f25ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580700332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1580700332
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.820060745
Short name T236
Test name
Test status
Simulation time 28624782402 ps
CPU time 267.77 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:28:32 PM PDT 24
Peak memory 263128 kb
Host smart-13a67521-cdb1-4053-bc25-6635b9916131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820060745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.820060745
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1522031918
Short name T624
Test name
Test status
Simulation time 217437364 ps
CPU time 3.22 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 224472 kb
Host smart-58c83c73-b34a-452f-b614-a9b8e8c63a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522031918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1522031918
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3379254207
Short name T554
Test name
Test status
Simulation time 488435768 ps
CPU time 6.61 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 218780 kb
Host smart-e5236422-d815-407f-a008-7cc1be98d8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379254207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3379254207
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1749483263
Short name T762
Test name
Test status
Simulation time 87182956130 ps
CPU time 47.96 seconds
Started May 23 01:24:01 PM PDT 24
Finished May 23 01:24:51 PM PDT 24
Peak memory 234940 kb
Host smart-7541925f-a3ea-44ef-a4c0-3ff119c34638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749483263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1749483263
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.24203993
Short name T331
Test name
Test status
Simulation time 108877415 ps
CPU time 1.09 seconds
Started May 23 01:23:50 PM PDT 24
Finished May 23 01:23:53 PM PDT 24
Peak memory 216784 kb
Host smart-97ed24d6-10a7-433d-aa4e-a76dd6e62478
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.24203993
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.338545764
Short name T507
Test name
Test status
Simulation time 1592472188 ps
CPU time 2.66 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:05 PM PDT 24
Peak memory 223680 kb
Host smart-97a83bb4-944d-4927-a89a-dc2e56fbbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338545764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
338545764
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.164703107
Short name T382
Test name
Test status
Simulation time 354774589 ps
CPU time 2.94 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:24:07 PM PDT 24
Peak memory 218652 kb
Host smart-d918b6fe-7160-4d4a-a865-78c8ef4c0b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164703107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.164703107
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2707315439
Short name T823
Test name
Test status
Simulation time 1609643509 ps
CPU time 6.92 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:09 PM PDT 24
Peak memory 220300 kb
Host smart-bd0c2c4d-3556-4650-a066-0e23b35d3e37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2707315439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2707315439
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.179721808
Short name T227
Test name
Test status
Simulation time 9017539064 ps
CPU time 169.48 seconds
Started May 23 01:24:01 PM PDT 24
Finished May 23 01:26:53 PM PDT 24
Peak memory 267456 kb
Host smart-429ab84c-3b37-4d51-b7d9-d1bc47b495e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179721808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.179721808
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.346005784
Short name T420
Test name
Test status
Simulation time 17557871498 ps
CPU time 22.98 seconds
Started May 23 01:23:51 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 216508 kb
Host smart-baeb9a0e-e578-4938-a6b8-a1bb5e03de0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346005784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.346005784
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1038089676
Short name T389
Test name
Test status
Simulation time 7204045135 ps
CPU time 4.74 seconds
Started May 23 01:23:49 PM PDT 24
Finished May 23 01:23:57 PM PDT 24
Peak memory 216468 kb
Host smart-8e61788f-855d-420e-8a53-856b1c700e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038089676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1038089676
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.204084874
Short name T533
Test name
Test status
Simulation time 45999881 ps
CPU time 1.09 seconds
Started May 23 01:23:53 PM PDT 24
Finished May 23 01:23:56 PM PDT 24
Peak memory 206860 kb
Host smart-ee7c1824-3242-4ece-86bc-e4cb5f0d2a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204084874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.204084874
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2050953959
Short name T691
Test name
Test status
Simulation time 68507975 ps
CPU time 0.87 seconds
Started May 23 01:23:48 PM PDT 24
Finished May 23 01:23:51 PM PDT 24
Peak memory 205784 kb
Host smart-c61212f7-363d-4040-9898-52a52735b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050953959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2050953959
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2160769783
Short name T200
Test name
Test status
Simulation time 9450454264 ps
CPU time 30.99 seconds
Started May 23 01:23:58 PM PDT 24
Finished May 23 01:24:30 PM PDT 24
Peak memory 234496 kb
Host smart-9109e6b6-0fa7-45a5-bd7b-6cfdc9b6341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160769783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2160769783
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3700095082
Short name T717
Test name
Test status
Simulation time 44759476 ps
CPU time 0.75 seconds
Started May 23 01:24:01 PM PDT 24
Finished May 23 01:24:04 PM PDT 24
Peak memory 205376 kb
Host smart-626c5729-585f-4a58-ace6-151c18deabc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700095082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
700095082
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2112088850
Short name T165
Test name
Test status
Simulation time 478877637 ps
CPU time 2.22 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:04 PM PDT 24
Peak memory 218576 kb
Host smart-4694103e-1928-43f8-bc47-c5aad178004d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112088850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2112088850
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.288035598
Short name T974
Test name
Test status
Simulation time 16018796 ps
CPU time 0.76 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:06 PM PDT 24
Peak memory 205448 kb
Host smart-ec09d42f-37c2-43b7-8090-3a4e8558d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288035598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.288035598
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2511344187
Short name T619
Test name
Test status
Simulation time 93477393611 ps
CPU time 183.92 seconds
Started May 23 01:24:02 PM PDT 24
Finished May 23 01:27:08 PM PDT 24
Peak memory 249492 kb
Host smart-56a62580-9e8c-4ef7-bd51-b7f548ebc979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511344187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2511344187
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.16048855
Short name T223
Test name
Test status
Simulation time 11853780314 ps
CPU time 181.03 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:27:06 PM PDT 24
Peak memory 271808 kb
Host smart-1dede22a-4904-4309-9d96-e58e45d7fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16048855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.16048855
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2116093743
Short name T457
Test name
Test status
Simulation time 7312654757 ps
CPU time 39.47 seconds
Started May 23 01:24:14 PM PDT 24
Finished May 23 01:24:55 PM PDT 24
Peak memory 238076 kb
Host smart-aaffbfa3-3111-4fb6-a712-dc6cb64de5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116093743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2116093743
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3189381139
Short name T602
Test name
Test status
Simulation time 88775170 ps
CPU time 3.7 seconds
Started May 23 01:24:15 PM PDT 24
Finished May 23 01:24:20 PM PDT 24
Peak memory 232640 kb
Host smart-0b09fb89-330d-4bef-b8f2-914032e65cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189381139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3189381139
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2025025784
Short name T695
Test name
Test status
Simulation time 998258050 ps
CPU time 4.83 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 234004 kb
Host smart-27e44ea7-f105-4a25-a44f-6d90abca2c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025025784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2025025784
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.5429922
Short name T732
Test name
Test status
Simulation time 30434809 ps
CPU time 2.54 seconds
Started May 23 01:24:13 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 221452 kb
Host smart-23f63c1e-9d21-4759-b99f-79b3085c1b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5429922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.5429922
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1451346271
Short name T155
Test name
Test status
Simulation time 24263233 ps
CPU time 1.06 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:24:04 PM PDT 24
Peak memory 217996 kb
Host smart-db3c8426-9c4f-4ec1-8d58-39f358934e11
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451346271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1451346271
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4098337435
Short name T465
Test name
Test status
Simulation time 45293234238 ps
CPU time 9.31 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:32 PM PDT 24
Peak memory 232864 kb
Host smart-6f00def3-6713-4593-950b-2b8f8268e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098337435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4098337435
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3933011244
Short name T837
Test name
Test status
Simulation time 16229804484 ps
CPU time 13.98 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:16 PM PDT 24
Peak memory 236132 kb
Host smart-8364ed78-333a-4ed9-b700-1f2ee885fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933011244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3933011244
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1397658856
Short name T43
Test name
Test status
Simulation time 2778044907 ps
CPU time 5.73 seconds
Started May 23 01:24:05 PM PDT 24
Finished May 23 01:24:13 PM PDT 24
Peak memory 222764 kb
Host smart-b7b7e266-ba28-480a-b632-90f3c6386f56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1397658856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1397658856
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3635563304
Short name T152
Test name
Test status
Simulation time 285697976575 ps
CPU time 684.43 seconds
Started May 23 01:24:00 PM PDT 24
Finished May 23 01:35:28 PM PDT 24
Peak memory 268100 kb
Host smart-9eb646f0-1763-40af-892b-c016b3a44616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635563304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3635563304
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.891391773
Short name T723
Test name
Test status
Simulation time 19462335524 ps
CPU time 24.33 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:26 PM PDT 24
Peak memory 216548 kb
Host smart-b1769abd-6ed7-47f2-ba7f-745cdbfcf319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891391773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.891391773
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3162786728
Short name T686
Test name
Test status
Simulation time 1655494218 ps
CPU time 4 seconds
Started May 23 01:24:03 PM PDT 24
Finished May 23 01:24:10 PM PDT 24
Peak memory 216324 kb
Host smart-cc416c88-062b-40c5-8eea-7c798ee59333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162786728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3162786728
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1974853565
Short name T54
Test name
Test status
Simulation time 136491289 ps
CPU time 1.09 seconds
Started May 23 01:24:13 PM PDT 24
Finished May 23 01:24:15 PM PDT 24
Peak memory 207164 kb
Host smart-598460bb-16dc-4952-a762-2cadf6d25183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974853565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1974853565
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2751124191
Short name T713
Test name
Test status
Simulation time 48291280 ps
CPU time 0.86 seconds
Started May 23 01:24:21 PM PDT 24
Finished May 23 01:24:25 PM PDT 24
Peak memory 205856 kb
Host smart-3ea1049f-5b4c-435d-a5a8-c442315d0f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751124191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2751124191
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2608447734
Short name T206
Test name
Test status
Simulation time 20855966642 ps
CPU time 15.93 seconds
Started May 23 01:23:59 PM PDT 24
Finished May 23 01:24:17 PM PDT 24
Peak memory 234528 kb
Host smart-a87c453e-4c13-40f4-87a8-f02a527fcb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608447734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2608447734
Directory /workspace/9.spi_device_upload/latest
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