Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3643408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3997321

1

T1

22

T2

7915

T3

239

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4283573	1			T1	1		T2	1534		T3	1
values[0x0]	1677997	1			T1	14		T2	3515		T3	129
values[0x1]	1679159	1			T1	17		T2	3541		T3	169

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2577299	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5063430

1

T1

24

T2

8068

T3

255

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27017	1			T2	10		T5	60		T6	12
valid_sources[0x01]	28492	1			T2	42		T5	6		T6	11
valid_sources[0x02]	27197	1			T2	9		T5	27		T6	21
valid_sources[0x03]	27675	1			T1	1		T2	52		T3	1
valid_sources[0x04]	28900	1			T2	32		T5	35		T6	11
valid_sources[0x05]	28635	1			T1	1		T2	38		T5	13
valid_sources[0x06]	27576	1			T2	32		T3	1		T5	11
valid_sources[0x07]	27830	1			T1	2		T2	56		T5	2
valid_sources[0x08]	28104	1			T2	18		T3	2		T5	14
valid_sources[0x09]	27230	1			T2	66		T5	21		T6	10
valid_sources[0x0a]	29705	1			T2	34		T3	2		T5	27
valid_sources[0x0b]	28504	1			T2	26		T5	45		T6	30
valid_sources[0x0c]	30449	1			T2	62		T3	1		T5	21
valid_sources[0x0d]	35297	1			T3	1		T5	9		T6	20
valid_sources[0x0e]	28464	1			T2	59		T3	3		T5	24
valid_sources[0x0f]	28258	1			T2	31		T3	2		T5	33
valid_sources[0x10]	26657	1			T2	70		T3	2		T5	27
valid_sources[0x11]	29150	1			T2	1		T3	2		T5	18
valid_sources[0x12]	28772	1			T2	18		T3	3		T5	35
valid_sources[0x13]	28621	1			T2	66		T3	3		T5	51
valid_sources[0x14]	29637	1			T2	10		T5	18		T6	15
valid_sources[0x15]	30776	1			T2	44		T5	31		T6	15
valid_sources[0x16]	27659	1			T1	1		T2	62		T3	2
valid_sources[0x17]	26986	1			T3	1		T5	1		T6	20
valid_sources[0x18]	29757	1			T2	32		T5	5		T6	21
valid_sources[0x19]	27383	1			T2	53		T3	1		T5	31
valid_sources[0x1a]	29826	1			T2	41		T5	6		T6	20
valid_sources[0x1b]	30697	1			T2	18		T3	1		T5	14
valid_sources[0x1c]	27897	1			T1	1		T2	51		T5	7
valid_sources[0x1d]	26468	1			T2	8		T5	23		T6	15
valid_sources[0x1e]	28309	1			T2	61		T3	2		T5	4
valid_sources[0x1f]	34090	1			T2	17		T3	3		T5	6
valid_sources[0x20]	27189	1			T1	1		T2	12		T3	1
valid_sources[0x21]	30004	1			T1	1		T2	1		T5	19
valid_sources[0x22]	29427	1			T2	1		T3	2		T5	40
valid_sources[0x23]	27495	1			T5	43		T6	22		T7	1
valid_sources[0x24]	28670	1			T2	18		T5	37		T6	29
valid_sources[0x25]	30573	1			T2	27		T3	6		T5	50
valid_sources[0x26]	25712	1			T2	84		T3	3		T5	11
valid_sources[0x27]	30559	1			T2	83		T5	6		T6	12
valid_sources[0x28]	28281	1			T2	33		T3	3		T5	12
valid_sources[0x29]	30332	1			T2	87		T3	2		T5	20
valid_sources[0x2a]	27775	1			T2	27		T5	32		T6	27
valid_sources[0x2b]	30241	1			T2	43		T3	2		T5	31
valid_sources[0x2c]	31038	1			T1	1		T2	8		T5	26
valid_sources[0x2d]	29847	1			T2	44		T3	2		T5	9
valid_sources[0x2e]	33166	1			T2	11		T5	7		T6	29
valid_sources[0x2f]	29386	1			T3	1		T5	25		T6	20
valid_sources[0x30]	27939	1			T2	34		T3	2		T5	16
valid_sources[0x31]	27392	1			T3	2		T5	11		T6	26
valid_sources[0x32]	28647	1			T2	5		T5	40		T6	15
valid_sources[0x33]	28024	1			T2	25		T3	1		T5	9
valid_sources[0x34]	26807	1			T2	15		T3	2		T5	19
valid_sources[0x35]	27871	1			T2	12		T3	4		T5	5
valid_sources[0x36]	26933	1			T2	11		T3	3		T5	15
valid_sources[0x37]	29106	1			T3	3		T5	33		T6	21
valid_sources[0x38]	28209	1			T2	63		T3	2		T5	42
valid_sources[0x39]	27143	1			T1	1		T2	4		T3	1
valid_sources[0x3a]	28425	1			T2	3		T5	23		T6	10
valid_sources[0x3b]	35409	1			T2	61		T3	1		T5	12
valid_sources[0x3c]	28714	1			T2	35		T3	7		T5	45
valid_sources[0x3d]	27907	1			T2	26		T3	3		T5	29
valid_sources[0x3e]	27258	1			T2	23		T5	12		T6	53
valid_sources[0x3f]	30965	1			T2	5		T5	8		T6	24
valid_sources[0x40]	29256	1			T2	24		T3	2		T5	4
valid_sources[0x41]	29878	1			T2	60		T5	44		T6	17
valid_sources[0x42]	28250	1			T2	59		T5	12		T6	24
valid_sources[0x43]	32109	1			T2	36		T5	3		T6	26
valid_sources[0x44]	28023	1			T2	24		T3	2		T4	1088
valid_sources[0x45]	29536	1			T2	68		T3	6		T5	36
valid_sources[0x46]	28005	1			T2	26		T5	16		T6	20
valid_sources[0x47]	26220	1			T2	13		T3	1		T5	18
valid_sources[0x48]	28670	1			T2	8		T3	3		T5	17
valid_sources[0x49]	30611	1			T2	21		T3	4		T5	8
valid_sources[0x4a]	27249	1			T2	14		T5	22		T6	20
valid_sources[0x4b]	30988	1			T2	30		T3	1		T5	16
valid_sources[0x4c]	27309	1			T2	54		T3	1		T5	26
valid_sources[0x4d]	59669	1			T2	29		T5	20		T6	15
valid_sources[0x4e]	28667	1			T2	32		T3	1		T5	12
valid_sources[0x4f]	27328	1			T2	27		T5	19		T6	23
valid_sources[0x50]	30546	1			T2	44		T3	2		T5	27
valid_sources[0x51]	30564	1			T2	11		T3	1		T5	33
valid_sources[0x52]	33331	1			T2	39		T3	1		T5	14
valid_sources[0x53]	30897	1			T2	18		T3	3		T5	16
valid_sources[0x54]	31358	1			T2	48		T5	14		T6	21
valid_sources[0x55]	31567	1			T1	1		T2	6		T5	15
valid_sources[0x56]	26730	1			T1	1		T2	16		T3	1
valid_sources[0x57]	30534	1			T2	27		T3	2		T5	2
valid_sources[0x58]	27643	1			T2	21		T3	1		T5	23
valid_sources[0x59]	31328	1			T2	25		T6	19		T8	4
valid_sources[0x5a]	30687	1			T2	49		T3	1		T5	8
valid_sources[0x5b]	31558	1			T2	2		T3	3		T5	12
valid_sources[0x5c]	28156	1			T2	42		T3	1		T5	19
valid_sources[0x5d]	27876	1			T2	47		T5	28		T6	18
valid_sources[0x5e]	27749	1			T2	1		T5	19		T6	17
valid_sources[0x5f]	28605	1			T2	92		T3	1		T5	33
valid_sources[0x60]	28386	1			T2	123		T3	1		T5	15
valid_sources[0x61]	30099	1			T2	54		T3	1		T5	11
valid_sources[0x62]	27643	1			T2	24		T3	1		T5	18
valid_sources[0x63]	30857	1			T1	1		T2	23		T3	1
valid_sources[0x64]	28026	1			T1	1		T2	23		T5	34
valid_sources[0x65]	29206	1			T2	56		T3	1		T5	24
valid_sources[0x66]	30070	1			T2	49		T3	1		T5	38
valid_sources[0x67]	29038	1			T2	36		T3	3		T5	32
valid_sources[0x68]	29569	1			T2	51		T3	1		T5	21
valid_sources[0x69]	34844	1			T2	107		T5	36		T6	24
valid_sources[0x6a]	29540	1			T3	1		T5	6		T6	8
valid_sources[0x6b]	28777	1			T2	50		T5	12		T6	15
valid_sources[0x6c]	31564	1			T2	7		T5	42		T6	19
valid_sources[0x6d]	29230	1			T3	1		T5	21		T6	22
valid_sources[0x6e]	28530	1			T1	1		T2	5		T3	2
valid_sources[0x6f]	28472	1			T2	92		T5	12		T6	25
valid_sources[0x70]	29383	1			T2	35		T3	3		T5	18
valid_sources[0x71]	28790	1			T2	26		T3	3		T5	14
valid_sources[0x72]	30050	1			T2	1		T5	16		T6	18
valid_sources[0x73]	28901	1			T2	21		T3	3		T5	15
valid_sources[0x74]	28547	1			T2	7		T3	3		T5	56
valid_sources[0x75]	27908	1			T2	11		T3	1		T5	8
valid_sources[0x76]	28541	1			T2	22		T3	2		T5	41
valid_sources[0x77]	29168	1			T2	28		T3	1		T5	14
valid_sources[0x78]	28434	1			T2	30		T3	1		T5	48
valid_sources[0x79]	28381	1			T5	8		T6	23		T8	11
valid_sources[0x7a]	29646	1			T1	1		T2	2		T5	27
valid_sources[0x7b]	28540	1			T2	12		T5	2		T6	33
valid_sources[0x7c]	29900	1			T2	64		T3	7		T5	17
valid_sources[0x7d]	30972	1			T2	9		T3	1		T5	29
valid_sources[0x7e]	27855	1			T2	23		T5	20		T6	11
valid_sources[0x7f]	27975	1			T1	1		T2	20		T5	6
valid_sources[0x80]	29870	1			T2	7		T5	12		T6	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

976018

1

T1

1

T2

901

T3

1

values[0x0]

all_enables

biggest_size

1522128

1

T1

10

T2

3503

T3

108

values[0x1]

all_enables

biggest_size

1499175

1

T1

11

T2

3511

T3

130