Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3662943

1

T1

10

T2

675

T3

60

full_word

3996318

1

T1

22

T2

7915

T3

239

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7658861	1			T1	32		T2	8590		T3	299
auto[TlIntgErrCmd]	126	1			T99	7		T103	6		T104	4
auto[TlIntgErrData]	147	1			T99	6		T103	6		T104	4
auto[TlIntgErrBoth]	127	1			T99	7		T103	8		T104	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4285079

1

T1

1

T2

1534

T3

1

auto[1]

3374182

1

T1

31

T2

7056

T3

298

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3308807	1			T2	633		T4	103		T5	3306
auto[TlIntgErrNone]	partial	auto[1]	353759	1			T1	10		T2	42		T3	60
auto[TlIntgErrNone]	full_word	auto[0]	976103	1			T1	1		T2	901		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3020192	1			T1	21		T2	7014		T3	238
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T99	2		T104	1		T113	2
auto[TlIntgErrCmd]	partial	auto[1]	77	1			T99	5		T103	6		T104	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T165	1		T166	1		-	-
auto[TlIntgErrData]	partial	auto[0]	60	1			T99	2		T103	1		T104	1
auto[TlIntgErrData]	partial	auto[1]	70	1			T99	4		T103	4		T104	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T112	1		T150	1		T167	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T103	1		T112	1		T165	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T99	2		T103	3		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T99	5		T103	5		T113	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T104	1		T168	1		T169	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T150	1		-	-		-	-