Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.62	93.89	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14
1	1	Covered	T2,T12,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14
1	1	Covered	T2,T12,T14

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1165817883	2317	0	0
SrcPulseCheck_M	403577781	2317	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1165817883	2317	0	0
T2	745777	13	0	0
T3	70777	0	0	0
T4	183520	0	0	0
T5	284770	0	0	0
T6	150515	0	0	0
T7	1594	0	0	0
T8	364032	0	0	0
T9	142610	0	0	0
T10	873	0	0	0
T11	212903	0	0	0
T12	0	9	0	0
T14	0	2	0	0
T15	1151420	10	0	0
T16	235130	18	0	0
T17	8274	0	0	0
T19	2126	0	0	0
T25	4348	0	0	0
T27	358504	11	0	0
T28	0	2	0	0
T30	0	3	0	0
T41	121838	7	0	0
T42	2462	0	0	0
T43	0	2	0	0
T45	165058	7	0	0
T48	0	2	0	0
T49	620672	4	0	0
T86	0	11	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	7	0	0
T143	0	7	0	0
T144	0	7	0	0
T145	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	403577781	2317	0	0
T2	340883	13	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	9	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	1907580	10	0	0
T16	1071968	18	0	0
T17	5484	0	0	0
T18	58630	0	0	0
T19	144	0	0	0
T27	687720	11	0	0
T28	0	2	0	0
T30	0	3	0	0
T41	38402	7	0	0
T42	144	0	0	0
T43	0	2	0	0
T45	30004	7	0	0
T48	0	2	0	0
T49	191332	4	0	0
T86	0	11	0	0
T140	0	7	0	0
T141	0	7	0	0
T142	0	7	0	0
T143	0	7	0	0
T144	0	7	0	0
T145	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T41,T48
1	0	Covered	T45,T41,T48
1	1	Covered	T45,T41,T140

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T41,T48
1	0	Covered	T45,T41,T140
1	1	Covered	T45,T41,T48

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	388605961	178	0	0
SrcPulseCheck_M	134525927	178	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	178	0	0
T15	575710	0	0	0
T16	117565	0	0	0
T17	4137	0	0	0
T19	1063	0	0	0
T25	2174	0	0	0
T27	179252	0	0	0
T41	60919	2	0	0
T42	1231	0	0	0
T45	82529	2	0	0
T48	0	1	0	0
T49	310336	0	0	0
T86	0	6	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	178	0	0
T15	953790	0	0	0
T16	535984	0	0	0
T17	2742	0	0	0
T18	29315	0	0	0
T19	72	0	0	0
T27	343860	0	0	0
T41	19201	2	0	0
T42	72	0	0	0
T45	15002	2	0	0
T48	0	1	0	0
T49	95666	0	0	0
T86	0	6	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	2	0	0
T145	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T41,T48
1	0	Covered	T45,T41,T48
1	1	Covered	T45,T41,T140

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T41,T48
1	0	Covered	T45,T41,T140
1	1	Covered	T45,T41,T48

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	388605961	322	0	0
SrcPulseCheck_M	134525927	322	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	322	0	0
T15	575710	0	0	0
T16	117565	0	0	0
T17	4137	0	0	0
T19	1063	0	0	0
T25	2174	0	0	0
T27	179252	0	0	0
T41	60919	5	0	0
T42	1231	0	0	0
T45	82529	5	0	0
T48	0	1	0	0
T49	310336	0	0	0
T86	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	0	5	0	0
T144	0	5	0	0
T145	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	322	0	0
T15	953790	0	0	0
T16	535984	0	0	0
T17	2742	0	0	0
T18	29315	0	0	0
T19	72	0	0	0
T27	343860	0	0	0
T41	19201	5	0	0
T42	72	0	0	0
T45	15002	5	0	0
T48	0	1	0	0
T49	95666	0	0	0
T86	0	5	0	0
T140	0	5	0	0
T141	0	5	0	0
T142	0	5	0	0
T143	0	5	0	0
T144	0	5	0	0
T145	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14
1	1	Covered	T2,T12,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T14
1	0	Covered	T2,T12,T14
1	1	Covered	T2,T12,T14

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	388605961	1817	0	0
SrcPulseCheck_M	134525927	1817	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388605961	1817	0	0
T2	745777	13	0	0
T3	70777	0	0	0
T4	183520	0	0	0
T5	284770	0	0	0
T6	150515	0	0	0
T7	1594	0	0	0
T8	364032	0	0	0
T9	142610	0	0	0
T10	873	0	0	0
T11	212903	0	0	0
T12	0	9	0	0
T14	0	2	0	0
T15	0	10	0	0
T16	0	18	0	0
T27	0	11	0	0
T28	0	2	0	0
T30	0	3	0	0
T43	0	2	0	0
T49	0	4	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	134525927	1817	0	0
T2	340883	13	0	0
T3	106047	0	0	0
T4	43958	0	0	0
T5	65717	0	0	0
T6	144213	0	0	0
T8	50617	0	0	0
T9	139094	0	0	0
T11	52316	0	0	0
T12	481483	9	0	0
T13	8208	0	0	0
T14	0	2	0	0
T15	0	10	0	0
T16	0	18	0	0
T27	0	11	0	0
T28	0	2	0	0
T30	0	3	0	0
T43	0	2	0	0
T49	0	4	0	0